Semiconductor device and manufacturing method for the same

Abstract

To provide a semiconductor device in which the decrease in source / drain breakdown voltage is suppressed.SOLUTION: A semiconductor device 100 includes a semiconductor substrate 10, a well region 12 with a first conductivity type, a source region 20 with a second conductivity type, a drain region 22 with the second conductivity type, a gate oxide film 24 provided on the semiconductor substrate between the source region and the drain region, an element separation oxide film 28a provided between the gate oxide film and the drain region, a gate electrode 26, a first diffusion region 16 of the second conductivity type provided in a well region under the drain region, a second diffusion region 14 of the second conductivity type provided in the well region between the first diffusion region and the gate oxide film, and a third diffusion region 18 of the first conductivity type provided in the well region under the first diffusion region, in which an end on the source region side exists closer to the drain region side than an end of the second diffusion region and the impurity concentration is higher than that in the well region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In a high-voltage MOS (Metal Oxide Semiconductor) transistor, a first diffusion region of the same conductivity type as the drain region is provided in a well region below the drain region and in the well region between the drain region and the gate electrode. It is known to provide a second diffusion region below the first diffusion region, which has a higher impurity concentration than the well region and is of the same conductivity type as the well region (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-157848 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the electric field strength between the first diffusion region and the second diffusion region increases, which may reduce the source-drain breakdown voltage.

[0005] The present disclosure provides a semiconductor device that suppresses a decrease in source-drain breakdown voltage, and a method for manufacturing the same. [Means for solving the problem]

[0006] According to an embodiment of the present disclosure, a semiconductor device includes a semiconductor substrate, a well region of a first conductivity type provided in the semiconductor substrate, a source region of a second conductivity type different from the first conductivity type provided in an upper portion of the well region, a drain region of the second conductivity type provided in an upper portion of the well region, a gate oxide film provided on the semiconductor substrate between the source region and the drain region, an element isolation oxide film provided on the semiconductor substrate between the gate oxide film and the drain region, a gate electrode provided on the gate oxide film, a first diffusion region of the second conductivity type provided in the well region below the drain region, a second diffusion region of the second conductivity type provided in the well region between the first diffusion region and the gate oxide film, and a third diffusion region of the first conductivity type provided in the well region below the first diffusion region, the end of the source region side being located closer to the drain region than the end of the second diffusion region, and having a higher impurity concentration than the well region.

[0007] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: a well region of a first conductivity type provided in a semiconductor substrate; a source region of a second conductivity type different from the first conductivity type provided in an upper portion of the well region; a drain region of the second conductivity type provided in an upper portion of the well region; a gate oxide film provided on the semiconductor substrate between the source region and the drain region; an element isolation oxide film provided on the semiconductor substrate between the gate oxide film and the drain region; and a gate electrode provided on the gate oxide film. The method includes the steps of: forming a first diffusion region of the second conductivity type by implanting ions into a first range that is below the drain region when viewed in the thickness direction of the semiconductor substrate; forming a second diffusion region of the second conductivity type by implanting ions into a second range that includes a side of the first range that will become the gate oxide film; and forming a third diffusion region of the first conductivity type that overlaps with the first range, has an end on the side of the region that will become the source region located closer to the region that will become the drain region than an end of the second range that will become the source region, and has an impurity concentration higher than that of the well region. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to suppress a decrease in the source-drain breakdown voltage. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing the simulation results showing the impurity concentration versus depth in the BB cross section, CC cross section, and DD cross section of FIG. [Figure 3] FIG. 3 is a schematic diagram showing the P-type impurity concentration with respect to the position in the cross section AA of FIG. [Figure 4] 4(a) and 4(b) are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 5(a) and 5(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] 6(a) and 6(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] 7(a) and 7(b) are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 8(a) and 8(b) are cross-sectional views showing methods for manufacturing semiconductor devices according to first and second comparative examples, respectively. [Figure 9] FIG. 9(a) is a diagram showing the substrate current versus gate voltage Vg of semiconductor devices 100 and 110, and FIGS. 9(b) and 9(c) are diagrams showing the drain current Id versus drain voltage Vd of semiconductor devices 110 and 100, respectively. [Figure 10] FIG. 10(a) is a diagram showing leakage current versus substrate voltage in the first embodiment, and FIG. 10(b) is a diagram showing threshold voltage versus dose amount. [Figure 11] FIG. 11 is a cross-sectional view of the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the drawings. The following embodiments are examples for embodying the technical ideas of the invention, and the present invention is not limited to the described configurations and numerical values. In each drawing, the same components are given the same reference numerals, and duplicated explanations may be omitted as appropriate. The size, positional relationship, etc. of each component shown in each drawing may be exaggerated to facilitate understanding of the invention.

[0011] Fig. 1 is a cross-sectional view of a semiconductor device according to the first embodiment. As shown in Fig. 1, the semiconductor device 100 according to the first embodiment includes a semiconductor substrate 10, well regions 11 and 12, diffusion regions 14, 16, and 18, a source region 20, a drain region 22, a gate oxide film 24, a gate electrode 26, an element isolation oxide film 28, a contact region 30, and a diffusion region 31.

[0012] The semiconductor substrate 10 is of N-type. Well regions 11 and 12 are provided in the semiconductor substrate 10 and are an N-type well region and a P-type well region, respectively. The well region 11 is a region for element isolation, and the well region 12 is a region for forming a transistor. An element isolation oxide film 28 is provided on the surface of the semiconductor substrate 10. The element isolation oxide film 28 is, for example, a LOCOS (Local Oxidation of Silicon) film. The element isolation oxide film 28 may also be an STI (Shallow Trench Isolation) film.

[0013] A source region 20 and a drain region 22 are provided between element isolation oxide films 28 in the upper part of the well region 12. The source region 20 and the drain region 22 are N-type diffusion regions. The impurity concentrations in the source region 20 and the drain region 22 are higher than the impurity concentration in the semiconductor substrate 10.

[0014] A gate oxide film 24 is provided on the semiconductor substrate 10 between the source region 20 and the drain region 22. An element isolation oxide film 28a is provided on the semiconductor substrate 10 between the gate oxide film 24 and the drain region 22. A gate electrode 26 is provided over the gate oxide film 24 and the element isolation oxide film 28a. The upper part of the well region 12 below the gate oxide film 24 is a channel region 25 through which carriers travel.

[0015] An N-type diffusion region 16 is provided in the well region 12 below the drain region 22. An end E2 of the diffusion region 16 on the source region 20 side is located closer to the drain region 22 than an end E4 of the element isolation oxide film 28a on the source region 20 side, and is located closer to the source region 20 than an end E5 of the element isolation oxide film 28a on the drain region 22 side.

[0016] An N-type diffusion region 14 is provided in the well region 12 below the element isolation oxide film 28a between the diffusion region 16 and the channel region 25. An end E1 of the diffusion region 14 on the source region 20 side is located closer to the source region 20 than an end E4 of the element isolation oxide film 28a on the source region 20 side and an end E2 of the diffusion region 16. The bottom surface of the diffusion region 16 is located below the bottom surface of the diffusion region 14. The impurity concentration of the diffusion region 16 is lower than the impurity concentration of the drain region 22. The impurity concentration of the diffusion region 14 is lower than the impurity concentration of the diffusion region 16.

[0017] A P-type diffusion region 18 is provided below the diffusion region 16. The diffusion region 18 is not provided in at least the region on the source region 20 side below the diffusion region 14. An end E3 of the diffusion region 18 on the source region 20 side is located closer to the drain region 22 than an end E1 of the diffusion region 14 and an end E4 of the element isolation oxide film 28a, and is located closer to the source region 20 than an end E2 of the diffusion region 16 and an end E5 of the element isolation oxide film 28a on the drain region 22 side. The end E3 of the diffusion region 18 may be located closer to the drain region 22 than the end E2 of the diffusion region 16. The lower surface of the diffusion region 18 is located below the lower surface of the well region 12 below the source region 20. The impurity concentration of the diffusion region 18 is higher than that of the well region 12.

[0018] A P-type contact region 30 is provided between the element isolation oxide films 28 in the upper part of the well region 12. A P-type diffusion region 31 is provided to surround the contact region 30. The diffusion region 31 does not necessarily have to be provided. The contact region 30 is a region that supplies a potential to the well region 12.

[0019] The semiconductor substrate 10 is, for example, a silicon (Si) substrate. The impurities in the N-type region of the semiconductor substrate 10 are donor elements such as phosphorus (P) or arsenic (As). The impurities in the P-type region of the semiconductor substrate 10 are acceptor elements such as boron (B) or aluminum (Al). The gate oxide film 24 and the element isolation oxide films 28 and 28a are, for example, silicon oxide (SiO2) films. The element isolation oxide film 28a is provided to improve the source-drain breakdown voltage and is thicker than the gate oxide film 24. The thickness of the element isolation oxide film 28a is, for example, at least twice the thickness of the gate oxide film 24. The gate electrode 26 is, for example, a metal layer such as aluminum.

[0020] FIG. 2 shows the results of a simulation showing the impurity concentration versus depth in the BB, CC, and DD cross sections of FIG. 1. The BB cross section is a cross section of the channel region 25. The CC cross section is a cross section of a region where the diffusion region 16 is not provided but the diffusion region 14 is provided. The DD cross section is a cross section of the drain region 22. PB, PC, and PD indicate the P-type impurity concentrations in the BB, CC, and DD cross sections, respectively. NC and ND indicate the N-type impurity concentrations in the CC and DD cross sections, respectively. A depth of 0 μm corresponds to the bottom surface of the element isolation oxide film 28. The simulation conditions are the ion implantation conditions and heat treatment conditions shown in an example of the manufacturing method described below.

[0021] As shown in Figure 2, PC is slightly larger than PB. PC is about 1.5 times larger than PB. PD is larger than PC. PD is about twice larger than PC. The depth at which PD is almost 0 is larger than the depth at which PC is almost 0. The BB cross section contains almost no N-type impurities. NC is larger than PC, about three times larger. ND is larger than NC, about three times larger. The depth at which ND is almost 0 is larger than the depth at which NC is almost 0.

[0022] 3 is a schematic diagram showing the P-type impurity concentration versus position on the AA cross section in FIG. 1. Positions B, C, and D indicate positions on the BB cross section, the CC cross section, and the DD cross section, respectively. As shown in FIG. 3, the P-type impurity concentration is maximum at position D. The impurity concentration at position C is lower than the impurity concentration at position D. The impurity concentration at position B is lower than the impurity concentration at position C.

[0023] (Manufacturing method) 4(a) to 7(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. As shown in FIG. 4(a), element isolation oxide films 28 and 28a are formed on the surface of a semiconductor substrate 10 using the LOCOS method.

[0024] Next, as shown in FIG. 4(b), a mask layer 50 having an opening 51 is formed on the semiconductor substrate 10. The mask layer 50 is, for example, a photoresist, and is formed using photolithography. The opening 51 is formed in an area 41 that will become the well region 12 in FIG. 1. As indicated by arrow 60, impurities that will become acceptors are ion-implanted into the area 41 of the semiconductor substrate 10 using the mask layer 50 as a mask. As an example, boron is ion-implanted at an implantation energy of 240 KeV and a concentration of 2×10 12 cm -3 The impurity is implanted into the semiconductor substrate 10 in a region 40 above the semiconductor substrate 10.

[0025] Next, as shown in FIG. 5(a), after removing the mask layer 50, a mask layer 52 having an opening 53 is formed on the semiconductor substrate 10. The mask layer 52 is, for example, a photoresist, and is formed using photolithography. The opening 53 is formed in the area 43 that will become the diffusion region 18 in FIG. 1. As indicated by arrow 62, using the mask layer 52 as a mask, an impurity that will become an acceptor is ion-implanted into the area 43 of the semiconductor substrate 10. As an example, boron is implanted at an implantation energy of 240 KeV and a concentration of 4×10 12 cm -3 The impurity is implanted into the semiconductor substrate 10 in a region 42 in the upper part of the semiconductor substrate 10.

[0026] Next, as shown in FIG. 5(b), after removing the mask layer 52, a mask layer 54 having an opening 55 is formed on the semiconductor substrate 10. The mask layer 54 is, for example, a photoresist, and is formed using photolithography. The opening 55 is formed in an area 49 that will become the well region 11 in FIG. 1. As indicated by arrow 64, using the mask layer 54 as a mask, an impurity that will become a donor is ion-implanted into the area 49 of the semiconductor substrate 10. As an example, phosphorus is ion-implanted at an implantation energy of 480 KeV and a concentration of 2×10 12 cm -3 The impurity is implanted into the semiconductor substrate 10 in a region 48 in the upper part of the semiconductor substrate 10.

[0027] 6(a), after removing the mask layer 54, the impurities in the regions 48, 40, and 42 are diffused by a thermal diffusion process to form the well regions 11, 12 and the diffusion region 18 in the semiconductor substrate 10. As an example, the impurities are thermally diffused by performing a heat treatment at a temperature of 1200°C for 9 hours.

[0028] Next, as shown in FIG. 6(b), a mask layer 56 having an opening 57 is formed on the semiconductor substrate 10. The mask layer 56 is, for example, a photoresist, and is formed using photolithography. The opening 57 is formed in the area 47 that will become the diffusion region 16 in FIG. 1. As indicated by arrow 66, using the mask layer 56 as a mask, an impurity to be a donor is ion-implanted into the area 47 of the semiconductor substrate 10. As an example, phosphorus is ion-implanted at an implantation energy of 480 KeV and a concentration of 1×10 13 cm -3 The impurity is implanted into the semiconductor substrate 10 in a region 46 in the upper part of the semiconductor substrate 10.

[0029] Next, as shown in FIG. 7(a), after removing the mask layer 56, a mask layer 58 having an opening 59 is formed on the semiconductor substrate 10. The mask layer 58 is, for example, a photoresist, and is formed using photolithography. The opening 59 is formed in the area 45 that will become the diffusion region 14 in FIG. 1. As indicated by arrow 64, using the mask layer 54 as a mask, an impurity that will become a donor is ion-implanted into the semiconductor substrate 10. As an example, phosphorus is ion-implanted at an implantation energy of 480 KeV and a concentration of 4×10 12 cm -3 The impurity is implanted into the semiconductor substrate 10 in a region 44 in the upper part of the semiconductor substrate 10.

[0030] Next, as shown in FIG. 7(b), after removing the mask layer 58, the impurities in the regions 44 and 46 are diffused by a thermal diffusion process to form the diffusion regions 14 and 16 in the semiconductor substrate 10. As an example, the impurities are thermally diffused by a heat treatment at a temperature of 1200° C. for 30 minutes. In FIG. 7(a), the edge of the region 46 is located under the element isolation oxide film 28a, but the thermal diffusion of the impurities may position the edge of the diffusion region 14 outside the element isolation oxide film 28a.

[0031] 1, a source region 20, a drain region 22, a contact region 30, and a diffusion region 31 are formed in the semiconductor substrate 10. A gate electrode 26 is formed on the semiconductor substrate 10 via a gate oxide film 24. An interlayer insulating film and wiring are formed on the semiconductor substrate 10. In this manner, the semiconductor device 100 is manufactured.

[0032] Although an example of forming a deep diffusion region by ion implantation with an implantation energy of 1 MeV or less and thermal diffusion for a long time has been described, ion implantation with a high implantation energy of 1 MeV to 5 MeV and thermal treatment for a shorter time may also be performed.

[0033] (First Comparative Example) 8(a) is a cross-sectional view of a semiconductor device according to a first comparative example. As shown in FIG. 8(a), a semiconductor device 110 according to the first comparative example has a diffusion region 14. Diffusion regions 16 and 18 are not provided. The other configurations are the same as those of the first embodiment shown in FIG. 1.

[0034] (Second Comparative Example) FIG. 8(b) is a cross-sectional view of a semiconductor device according to a second comparative example. The second comparative example is an example considered with reference to FIG. 1 of Patent Document 1. As shown in FIG. 8(b), a semiconductor device 112 of the second comparative example has a diffusion region 14. Diffusion regions 16 and 18 are not provided. A P-type diffusion region 17 is provided in the well region 12 below the diffusion region 14. The impurity concentration of the diffusion region 17 is higher than the impurity concentration of the well region 12. The other configurations are the same as those of FIG. 1 of the first embodiment.

[0035] (Comparison with the first comparative example) The semiconductor device 100 of the first embodiment and the semiconductor device 110 of the first comparative example were fabricated under the same fabrication conditions as those shown in the manufacturing method of the semiconductor device 100. The gate length was 5 μm and the gate width was approximately 20 μm.

[0036] FIG. 9(a) is a graph showing the substrate current versus gate voltage Vg for the semiconductor devices 100 and 110. The graph shows the current flowing through the contact region 30 when the drain voltage Vd is set to 40 V and the gate voltage Vg is swept from 0 V to 40 V. When the speed of carriers traveling through the channel region 25 increases, impact ionization occurs on the drain region 22 side of the channel region 25, generating electrons and holes. The generated electrons flow into the drain region 22. The generated holes are injected into the well region 12 and flow into the contact region 30. This increases the substrate current. As shown in FIG. 9(a), the semiconductor device 110 has a large substrate current and a large hot carrier effect. The semiconductor device 100 has a small substrate current and a small hot carrier effect.

[0037] 9(b) and 9(c) are diagrams showing the drain current Id versus the drain voltage Vd of the semiconductor devices 110 and 100, respectively. As shown by the dashed circle in FIG. 9(b), in the semiconductor device 110, when Vd is 30 V or higher, the drain current Id increases and the source-drain breakdown voltage in the on state decreases. This is thought to be due to an increase in substrate current caused by the hot carrier effect.

[0038] 9(c), no decrease in the source-drain breakdown voltage is observed in the semiconductor device 100. This is thought to be because, in the semiconductor device 100, the provision of the diffusion region 16 gradually increases the impurity concentration between the channel region 25 and the drain region 22, thereby mitigating the concentration of the electric field and suppressing the hot carrier effect.

[0039] Furthermore, in the semiconductor device 100, the impurity concentration increases stepwise between the channel region 25 and the drain region 22, which alleviates the concentration of the electric field between the channel region 25 and the drain region 22 even when the device is off. This improves the source-drain breakdown voltage when the device is off. In addition, the drain resistance can be reduced, which improves the current driving capability.

[0040] If the diffusion regions 14 and 16 are provided, there is a concern that the punch-through breakdown voltage may decrease. Therefore, the diffusion region 18 is provided in the semiconductor device 100. The semiconductor device 100 was fabricated with different doses in FIG. 5(a) for forming the diffusion region 18. The fabrication conditions for the diffusion region and other factors are the example conditions shown in the fabrication method for the semiconductor device 100.

[0041] 10(a) is a diagram showing the leakage current versus substrate voltage in the first embodiment. The substrate voltage is the voltage between the semiconductor substrate 10 and the drain region 22, and the leakage current is the current flowing between the semiconductor substrate 10 and the drain region 22. As shown in FIG. 10(a), increasing the dose when forming the diffusion region 18 increases the punch-through breakdown voltage. The target breakdown voltage of 42 V (vertical dashed line) is cleared at all doses. Increasing the dose provides a larger margin relative to the target.

[0042] FIG. 10(b) is a graph showing the threshold voltage versus dose. The horizontal axis of FIG. 10(b) represents the dose when forming the diffusion region 18, and the vertical axis represents the threshold voltage of the semiconductor device. Multiple points at the same dose represent the threshold voltages of different transistors. A dose of 0 represents a semiconductor device in which the diffusion region 18 is not formed. As shown in FIG. 10(b), the threshold voltage hardly changes even when the diffusion region 18 is formed. This is because the diffusion region 18 is formed below the diffusion region 16 and not near the channel region 25, so the diffusion region 18 is thought to have little effect on the threshold voltage.

[0043] In the semiconductor device 110 of the first comparative example, increasing the impurity concentration of the well region 12 or deepening the well region 12 is considered as a method for improving the punch-through breakdown voltage. However, if the impurity concentration of the well region 12 is increased, the concentration of impurities that become acceptors in the channel region 25 will increase, causing a change in the threshold voltage. Furthermore, the source-drain breakdown voltage will decrease. Deepening the well region 12 requires a longer heat treatment time for thermal diffusion, which increases the number of manufacturing steps. In the semiconductor device 100 of the first embodiment, the punch-through breakdown voltage can be improved without affecting the threshold voltage by providing the diffusion region 18, even without deepening the well region 12.

[0044] (Comparison with the second comparative example) In the semiconductor device 112 of the second comparative example shown in FIG. 8(b), a diffusion region 17 is provided below the diffusion region 14. This, as described in Patent Document 1, can alleviate the electric field concentration in the lateral direction 68 near the end of the channel region 25 on the drain region 22 side. However, the gradient of the electric field in the vertical direction 69 between the diffusion regions 14 and 17 becomes steep. Therefore, referring to FIG. 4 of Patent Document 1, it is also possible to provide an N-type diffusion region with a lower impurity concentration than the diffusion region 14 between the diffusion regions 14 and 17. However, since the N-type diffusion region becomes deeper, punch-through between the diffusion region and the semiconductor substrate becomes more likely.

[0045] In the first embodiment, the end E3 of the P-type diffusion region 18 is located closer to the drain region 22 than the end E1 of the diffusion region 14. This makes it possible to prevent vertical electric field concentration near the end of the channel region 25.

[0046] According to the first embodiment, as shown in FIG. 1 , an N-type diffusion region 16 (first diffusion region) is provided in the well region 12 below the drain region 22. An N-type diffusion region 14 (second diffusion region) is provided in the well region 12 between the diffusion region 16 and the gate oxide film 24. A diffusion region 18 (third diffusion region) is provided in the well region 12 below the diffusion region 16. The end E3 of the diffusion region 14 on the source region 20 side is located closer to the drain region 22 than the end E1 of the diffusion region 14, and has a higher impurity concentration (dopant concentration) than the well region 12. By positioning the end E3 closer to the drain region 22 than the end E1, vertical electric field concentration at the end of the channel region 25 on the drain region 22 side, as in the semiconductor device 112 of the second comparative example, can be suppressed. This improves the source-drain breakdown voltage. Furthermore, the diffusion region 18 can suppress punch-through.

[0047] The position of the end E3 of the diffusion region 18 is preferably located closer to the drain region 22 than the end E4 of the element isolation oxide film 28a, and more preferably closer to the drain region 22 than the midpoint between the ends E4 and E5 of the element isolation oxide film 28a. This improves the source-drain breakdown voltage. The position of the end E3 of the diffusion region 18 can be determined as follows. When the peak impurity concentration in FIG. 3 is P1 (the impurity concentration at position D) and the impurity concentration of the channel region 25 is P2, the position of the end E3 is (P1-P2) / 2.

[0048] The impurity concentration of the diffusion region 16 is higher than that of the diffusion region 14. This allows the impurity concentration to increase stepwise from the channel region 25 toward the drain region 22. This improves the source-drain breakdown voltage. Furthermore, the drain resistance can be reduced, improving the driving capability. The impurity concentration of the diffusion region 16 and the impurity concentration of the diffusion region 14 are compared at the peak positions in FIG. 2. The impurity concentration of the diffusion region 16 is preferably at least twice as high as the impurity concentration of the diffusion region 14, and more preferably at least three times as high.

[0049] The bottom surface of the diffusion region 16 is deeper than the bottom surface of the diffusion region 14. This reduces electric field concentration from the channel region 25 toward the drain region 22, thereby improving the source-drain breakdown voltage. The bottom surface of the diffusion region 16 is located at a position where the donor impurity concentration and the acceptor impurity concentration are the same (the depth at the intersection of ND and PD in FIG. 2). The bottom surface of the diffusion region 14 is located at a position where the donor impurity concentration and the acceptor impurity concentration are the same (the depth at the intersection of NC and PC in FIG. 2). For example, the bottom surface is located at a depth where the impurity concentration is half the peak impurity concentration in the diffusion region 14. The depth of the bottom surface of the diffusion region 16 is preferably 1.2 times or more, and more preferably 1.5 times or more, of the depth of the bottom surface of the diffusion region 14.

[0050] If the diffusion region 16 is provided at a deep position with a high impurity concentration, the position near the bottom surface of the diffusion region 16 where the electric field concentrates in the vertical direction becomes deep, thereby improving the resistance to static electricity.

[0051] The end E1 of the diffusion region 14 on the source region 20 side is located closer to the source region 20 than the end E4 of the element isolation oxide film 28a on the source region 20 side. This improves the source-drain breakdown voltage. The end E1 of the diffusion region 14 is the position where the concentration of impurities that become donors and the concentration of impurities that become acceptors are the same.

[0052] The end E2 of the diffusion region 16 on the source region 20 side is preferably located closer to the drain region 22 than the end E4 of the element isolation oxide film 28a on the source region 20 side, and is preferably located closer to the drain region 22 than the midpoint between the ends E4 and E5 of the element isolation oxide film 28a. This allows the electric field concentration from the channel region 25 toward the drain region 22 to be alleviated, thereby improving the source-drain breakdown voltage.

[0053] As shown in Figures 6(b) and 7(b), ions are implanted into a range 47 (first range) that is below the drain region 22 when viewed in the thickness direction of the semiconductor substrate 10, thereby forming a diffusion region 16. As shown in Figures 7(a) and 7(b), ions are implanted into a range 45 (second range) that includes the side of range 47 that will become the gate oxide film 24, thereby forming a diffusion region 14. As shown in Figures 5(a) and 6(a), a diffusion region 18 is formed that overlaps with range 47, and whose end on the source region 20 side is located closer to the drain region 22 than the end of range 45 on the source region 20 side. By performing these steps, the semiconductor device 100 of Figure 1 can be manufactured.

[0054] (Second embodiment) The second embodiment is an example of a triple-well CMOS transistor. FIG. 11 is a cross-sectional view of a semiconductor device according to the second embodiment. As shown in FIG. 11, in a semiconductor device 102 according to the second embodiment, a well region 12 is P-type and is provided in an N-type semiconductor substrate 10. Well regions 13a and 13b are provided in the well region 12. The well regions 13a and 13b are P-type and N-type, respectively. The impurity concentrations of the well regions 13a and 13b are higher than the impurity concentration of the well region 12. The upper part of the well region 13a is P-type, but is provided with a diffusion region 13c in which donor impurities are diffused so that the carrier concentration is lower than that of the well region 13a. The upper part of the well region 13b is N-type, but is provided with a diffusion region 13d in which acceptor impurities are diffused so that the carrier concentration is lower than that of the well region 13b.

[0055] A source region 20a, a drain region 22a, and a contact region 30a are provided in the diffusion region 13c. The source region 20a and the drain region 22a are N-type, and the contact region 30a is P-type. A gate electrode 26a is provided on the semiconductor substrate 10 between the source region 20a and the drain region 22a via a gate oxide film. Insulator sidewalls 27a are provided on both sides of the gate electrode 26a. An LDD (Lightly Doped Drain) region 21a is provided below the sidewalls 27a. The LDD region 21a is N-type with a lower impurity concentration than the source region 20a and the drain region 22a.

[0056] A source region 20b, a drain region 22b, and a contact region 30b are provided in the diffusion region 13d. The source region 20b and the drain region 22b are P-type, and the contact region 30b is N-type. A gate electrode 26b is provided on the semiconductor substrate 10 between the source region 20b and the drain region 22b, with a gate oxide film interposed therebetween. Insulator sidewalls 27b are provided on both sides of the gate electrode 26b. An LDD region 21b is provided below the sidewalls 27b. The LDD region 21b is P-type with a lower impurity concentration than the source region 20b and the drain region 22b.

[0057] In the triple well structure, an N-type well region 13b is provided within a P-type well region 12. This tends to reduce the punch-through breakdown voltage between the well region 13b and the semiconductor substrate 10 via the well region 12. Therefore, a P-type diffusion region 18 with a higher impurity concentration than the well region 12 is provided below the well region 13b. This improves the punch-through breakdown voltage.

[0058] In the first and second embodiments, the first conductivity type is described as P type and the second conductivity type is described as N type, but the first conductivity type may be N type and the second conductivity type may be P type. For example, in the first embodiment, the well region 12, diffusion regions 18, 31, and contact region 30 may be N type, and the semiconductor substrate 10, diffusion regions 14, 16, source region 20, and drain region 22 may be P type.

[0059] Although the embodiments have been described above, they are presented as examples and the present invention is not limited to the above embodiments. The above embodiments can be implemented in various other forms, and various combinations, omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as set forth in the claims. [Explanation of symbols]

[0060] 10: Semiconductor substrate 11, 12: Well area 14, 16, 17, 18: Diffusion area 20: Source area 22: Drain region 24: Gate oxide film 25: Channel region 26: Gate electrode 28, 28a: Element isolation oxide film 40, 42, 44, 46, 48: area 41, 43, 45, 47, 49: Range

Claims

1. a semiconductor substrate; a well region of a first conductivity type provided in the semiconductor substrate; a source region of a second conductivity type different from the first conductivity type, the source region being provided above the well region; a drain region of the second conductivity type provided above the well region; a gate oxide film provided on the semiconductor substrate between the source region and the drain region; an element isolation oxide film provided on the semiconductor substrate between the gate oxide film and the drain region; a gate electrode provided on the gate oxide film; a first diffusion region of the second conductivity type provided in the well region below the drain region; a second diffusion region of the second conductivity type provided in the well region between the first diffusion region and the gate oxide film; a third diffusion region of the first conductivity type provided in the well region below the first diffusion region, the end of the third diffusion region on the source region side being located closer to the drain region than the end of the second diffusion region, and having a higher impurity concentration than the well region; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the impurity concentration of the first diffusion region is higher than the impurity concentration of the second diffusion region.

3. an end of the first diffusion region on the source region side is located closer to the drain region than an end of the element isolation oxide film on the source region side; 3. The semiconductor device according to claim 2, wherein an end of the second diffusion region on the source region side is located closer to the source region than an end of the element isolation oxide film on the source region side.

4. 4. The semiconductor device according to claim 3, wherein an end of the third diffusion region on the side of the source region is located closer to the drain region than an end of the element isolation oxide film on the side of the source region.

5. 4. The semiconductor device according to claim 3, wherein the end of the third diffusion region on the source region side is located closer to the drain region than the midpoint between the end of the element isolation oxide film on the source region side and the end of the element isolation oxide film on the drain region side.

6. 6. The semiconductor device according to claim 2, wherein a bottom surface of the first diffusion region is deeper than a bottom surface of the second diffusion region.

7. 6. The semiconductor device according to claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.

8. A method for manufacturing a semiconductor device comprising: a well region of a first conductivity type provided in a semiconductor substrate; a source region of a second conductivity type different from the first conductivity type provided in an upper portion of the well region; a drain region of the second conductivity type provided in an upper portion of the well region; a gate oxide film provided on the semiconductor substrate between the source region and the drain region; an element isolation oxide film provided on the semiconductor substrate between the gate oxide film and the drain region; and a gate electrode provided on the gate oxide film, forming a first diffusion region of the second conductivity type by implanting ions into a first range that is below the drain region when viewed in a thickness direction of the semiconductor substrate; forming a second diffusion region of the second conductivity type by implanting ions into a second region including a region of the first region that will become the gate oxide film; forming a third diffusion region of the first conductivity type that overlaps with the first region, an end of which is located closer to the region that will become the source region than the end of the second region that is located closer to the region that will become the drain region, and that has an impurity concentration higher than that of the well region; A method for manufacturing a semiconductor device comprising:

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