Semiconductor device and control method for semiconductor device

Abstract

To provide a semiconductor device whose surge current tolerance is improved.SOLUTION: A semiconductor device according to an embodiment includes: a transistor including a first electrode, a second electrode, an n-type first semiconductor region provided between the first electrode and the second electrode, a p-type second semiconductor region provided between the first semiconductor region and the first electrode, an n-type third semiconductor region provided between the second semiconductor region and the first electrode, and a gate electrode; a detector that detects the voltage of the first electrode or the current flowing from the first electrode to the second electrode when the voltage of the first electrode is a positive voltage that is higher than the voltage of the second electrode; a comparison circuit that compares the measurement value measured by the detector and a first threshold; and a gate driver circuit that applies a first positive voltage, which is higher than the threshold voltage of the transistor, to the gate electrode and when the measurement value is more than the first threshold as a result of the comparison in the comparison circuit, applies a first negative voltage to the gate electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a method for controlling the semiconductor device. [Background technology]

[0002] Silicon carbide is one example of a material for next-generation semiconductor devices. Compared to silicon, silicon carbide has excellent physical properties, such as a band gap three times larger, a breakdown field strength approximately ten times larger, and a thermal conductivity approximately three times larger. Utilizing these properties, for example, can realize MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) that have high breakdown voltage, low loss, and can operate at high temperatures.

[0003] Vertical MOSFETs using silicon carbide have a built-in pn junction diode. For example, MOSFETs are used as switching elements connected to inductive loads. In this case, the built-in diode allows a freewheeling current to flow even when the MOSFET is off.

[0004] A large surge current may flow through a MOSFET momentarily, exceeding the steady state. When a large surge current flows, the MOSFET heats up and is destroyed. The maximum allowable peak current (I FSM ) is called surge current capability. It is desirable to improve the surge current capability of MOSFETs. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2020-178312 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a semiconductor device with improved surge current resistance. [Means for solving the problem]

[0007] a gate electrode facing the second semiconductor region; a detector that detects the voltage of the first electrode or a current flowing from the first electrode to the second electrode when the voltage of the first electrode is a positive voltage higher than the voltage of the second electrode; a comparison circuit that compares a measurement value measured by the detector with a first threshold value when the voltage of the first electrode is a positive voltage higher than the voltage of the second electrode; and a gate driver circuit that applies a first positive voltage higher than a threshold voltage of the transistor to the gate electrode when the measurement value exceeds the first threshold value as a result of comparison by the comparison circuit. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of a semiconductor device according to a first embodiment. [Figure 2] FIG. 1 is a schematic cross-sectional view of a transistor according to a first embodiment. [Figure 3] FIG. 2 is a diagram showing a specific example of the semiconductor device according to the first embodiment. [Figure 4] FIG. 2 is an explanatory diagram of a control method for the semiconductor device according to the first embodiment. [Figure 5] FIG. 2 is an explanatory diagram of a control method for the semiconductor device according to the first embodiment. [Figure 6] FIG. 10 is a block diagram of a semiconductor device of a comparative example. [Figure 7] FIG. 10 is an explanatory diagram of a control method for a semiconductor device according to a comparative example. [Figure 8] FIG. 10 is an explanatory diagram of a control method for a semiconductor device according to a comparative example. [Figure 9] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 10] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 11] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 12] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 13] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 14] FIG. 10 is a block diagram of a semiconductor device according to a modified example of the first embodiment. [Figure 15] FIG. 10 is an explanatory diagram of a control method of a semiconductor device according to a modified example of the first embodiment. [Figure 16] FIG. 10 is a block diagram of a semiconductor device according to a second embodiment. [Figure 17] FIG. 5 is a schematic cross-sectional view of a transistor according to a second embodiment. [Figure 18] FIG. 10 is a block diagram of a semiconductor device according to a modified example of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described may be omitted as appropriate.

[0010] In the following description, n + , n, n - and p + , p, p - The notation indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, -indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The type is simply n-type, p + type, p - The type is sometimes simply referred to as p-type.

[0011] The impurity concentration can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined from the level of the carrier concentration determined, for example, by SCM (Scanning Capacitance Microscopy). Distances such as the depth and thickness of the impurity region can be determined, for example, by SIMS. Distances such as the depth, thickness, width, and spacing of the impurity region can also be determined, for example, from a composite image of an SCM image and an AFM (Atomic Force Microscope) image.

[0012] In this specification, the impurity concentration of a semiconductor region means the maximum impurity concentration of the semiconductor region, unless otherwise specified.

[0013] (First embodiment) A semiconductor device according to a first embodiment includes a transistor including a first electrode, a second electrode, an n-type first semiconductor region provided between the first electrode and the second electrode and electrically connected to the second electrode, a p-type second semiconductor region provided between the first semiconductor region and the first electrode and electrically connected to the first electrode, an n-type third semiconductor region provided between the second semiconductor region and the first electrode and electrically connected to the first electrode, and a gate electrode facing the second semiconductor region; a detector configured to detect a current flowing from the first electrode to the second electrode when the voltage of the first electrode is a positive voltage higher than that of the second electrode; a comparison circuit configured to compare a measurement value measured by the detector with a first threshold value in the above state; and a gate driver circuit configured to apply a first positive voltage higher than a threshold voltage of the transistor to the gate electrode in the above state, and to apply a first negative voltage to the gate electrode when the measurement value in the comparison circuit exceeds the first threshold value.

[0014] 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention, which is a semiconductor module 100 including a transistor 100a made of silicon carbide.

[0015] The semiconductor module 100 includes a transistor 100a, an ammeter 100b, a comparison circuit 100c, and a gate driver circuit 100d.

[0016] 2 is a schematic cross-sectional view of the transistor 100a according to the first embodiment.

[0017] The transistor 100a is a planar-gate vertical MOSFET using silicon carbide. The transistor 100a is, for example, a double implantation MOSFET (DIMOSFET) in which the body region and the source region are formed by ion implantation. The transistor 100a is a vertical n-channel MOSFET that uses electrons as carriers.

[0018] The transistor 100a includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20.

[0019] In the silicon carbide layer 10, n + n-type drain region 26 - a p-type drift region 28 (first semiconductor region), a p-type body region 30 (second semiconductor region), and an n-type + A source region 34 (third semiconductor region) of the type is included.

[0020] The silicon carbide layer 10 is provided between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is provided between the gate electrode 18 and the drain electrode 14. The silicon carbide layer 10 is single-crystal SiC. The silicon carbide layer 10 is, for example, 4H—SiC.

[0021] Silicon carbide layer 10 has a first surface ("P1" in FIG. 2) and a second surface ("P2" in FIG. 2). First surface P1 and second surface P2 are opposed to each other. Hereinafter, the first surface may be referred to as the front surface, and the second surface may be referred to as the back surface. Hereinafter, "depth" refers to the depth relative to the first surface.

[0022] The first plane P1 is, for example, a plane tilted at an angle of 0 to 8 degrees with respect to the (0001) plane. The second plane P2 is, for example, a plane tilted at an angle of 0 to 8 degrees with respect to the (000-1) plane. The (0001) plane is called a silicon plane. The (000-1) plane is called a carbon plane.

[0023] n + A drain region 26 of the n-type is provided between the source electrode 12 and the drain electrode 14. + The n-type drain region 26 is provided on the back surface side of the silicon carbide layer 10. The drain region 26 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 26 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0024] The drain region 26 is electrically connected to the drain electrode 14. The drain region 26 contacts the drain electrode 14.

[0025] n - A drift region 28 of the type is provided between the drain region 26 and the first plane P1. The drift region 28 is provided between the source electrode 12 and the drain electrode 14. The drift region 28 is provided between the gate electrode 18 and the drain electrode 14.

[0026] The drift region 28 functions as a current path when the transistor 100a is in the on state. When the transistor 100a is in the off state, a thick depletion layer is formed in the drift region 28, thereby increasing the breakdown voltage of the transistor 100a. The drift region 28 also functions as an n-type semiconductor region of a pn junction diode.

[0027] The drift region 28 is provided on the drain region 26. The drift region 28 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 28 is lower than the n-type impurity concentration of the drain region 26. The n-type impurity concentration of the drift region 28 is, for example, 4×10 14 cm -3 More than 1×10 17 cm -3 The following is the result.

[0028] The thickness of the drift region 28 in the direction from the source electrode 12 to the drain electrode 14 is, for example, 5 μm or more and 150 μm or less. The thickness of the drift region 28 in the direction from the source electrode 12 to the drain electrode 14 is, for example, thicker than the thickness of the body region 30 in the direction from the source electrode 12 to the drain electrode 14. The thickness of the drift region 28 in the direction from the source electrode 12 to the drain electrode 14 is, for example, 10 times or more the thickness of the body region 30 in the direction from the source electrode 12 to the drain electrode 14.

[0029] The drift region 28 is electrically connected to the drain electrode 14 .

[0030] The p-type body region 30 is provided between the drift region 28 and the first plane P1. The body region 30 is provided between the drift region 28 and the source electrode 12. A portion of the body region 30 functions as a channel region of the transistor 100a. The body region 30 functions as a p-type semiconductor region of the pn junction diode.

[0031] The body region 30 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the body region 30 is, for example, 1×10 16 cm -3 More than 1×10 21 cm -3 The following is the result.

[0032] The depth of the body region 30 is, for example, not less than 0.3 μm and not more than 1.0 μm.

[0033] The body region 30 is electrically connected to the source electrode 12. The body region 30 contacts the source electrode 12.

[0034] n + The source region 34 is provided between the body region 30 and the first plane P1. The source region 34 is provided between the body region 30 and the source electrode 12.

[0035] The source region 34 contains, for example, phosphorus (P) as an n-type impurity. The n-type impurity concentration of the source region 34 is higher than the n-type impurity concentration of the drift region 28. The n-type impurity concentration of the source region 34 is, for example, 10 times or more the n-type impurity concentration of the drift region 28.

[0036] The n-type impurity concentration of the source region 34 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The depth of the source region 34 is shallower than the depth of the body region 30. The depth of the source region 34 is, for example, not less than 0.1 μm and not more than 0.3 μm.

[0037] The source region 34 is electrically connected to the source electrode 12. The source region 34 contacts the source electrode 12.

[0038] The gate electrode 18 is provided on the first face P1 side of the silicon carbide layer 10. The gate electrode 18 is provided on the silicon carbide layer 10. The gate electrode 18 has, for example, a stripe shape.

[0039] The gate electrode 18 is a conductive layer, and is, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

[0040] The gate electrode 18 faces, for example, a portion of the body region 30 that contacts the first face P1. The gate electrode 18 faces, for example, a portion of the drift region 28 that contacts the first face P1.

[0041] The gate insulating layer 16 is provided between the gate electrode 18 and the body region 30. The gate insulating layer 16 is provided between the gate electrode 18 and the drift region .

[0042] The gate insulating layer 16 is made of, for example, silicon oxide. For example, a high-k insulating material (high dielectric constant insulating material) can be used for the gate insulating layer 16.

[0043] The interlayer insulating layer 20 is provided on the gate electrode 18 and the silicon carbide layer 10. The interlayer insulating layer 20 is provided between the gate electrode 18 and the source electrode 12. The interlayer insulating layer 20 is made of, for example, silicon oxide.

[0044] The source electrode 12 is provided on the first face P1 side of the silicon carbide layer 10. The source electrode 12 is in contact with the first face P1.

[0045] The source electrode 12 contacts the body region 30 and the source region 34 .

[0046] The source electrode 12 includes a metal, and the metal forming the source electrode 12 has a laminated structure of, for example, titanium (Ti) and aluminum (Al).

[0047] The portion of the source electrode 12 in contact with the body region 30 and the source region 34 is made of, for example, a metal silicide. The metal silicide is, for example, titanium silicide or nickel silicide.

[0048] The contact between the body region 30 and the source electrode 12 and the contact between the source region 34 and the source electrode 12 are, for example, ohmic contacts.

[0049] The drain electrode 14 is provided on the second face P2 side of the silicon carbide layer 10. The drain electrode 14 is in contact with the second face P2. The drain electrode 14 is in contact with the drain region 26.

[0050] The drain electrode 14 is, for example, a metal or a metal-semiconductor compound, and includes at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0051] The contact between the drain region 26 and the drain electrode 14 is, for example, an ohmic contact.

[0052] As shown in FIG. 1, a pn junction diode is connected as a built-in diode between the source electrode 12 and the drain electrode 14 of the transistor 100a.

[0053] For example, consider a case where transistor 100a is used as a switching element connected to an inductive load. When transistor 100a is in the off state, a load current caused by the inductive load may apply a positive voltage higher than the voltage at drain electrode 14 to source electrode 12. In this case, a forward current flows through the built-in diode of transistor 100a. This state is also called a reverse conduction state.

[0054] When the voltage between the source electrode 12 and the drain electrode 14 exceeds the forward voltage (Vf) of the pn junction diode, a forward current flows through the pn junction diode.

[0055] The ammeter 100b is provided, for example, between the source electrode 12 and the channel region of the transistor 100a. The ammeter 100b is an example of a detector. The ammeter 100b detects the current flowing from the source electrode 12 to the drain electrode 14 when the voltage of the source electrode 12 is a higher positive voltage than the drain electrode 14.

[0056] The comparison circuit 100c is electrically connected to the ammeter 100b. When the voltage of the source electrode 12 is a positive voltage higher than that of the drain electrode 14, the comparison circuit 100c compares the measurement value measured by the ammeter 100b with a first threshold value.

[0057] The measured value measured by the ammeter 100b is a current value, and the first threshold is a preset threshold current.

[0058] The first threshold value is, for example, the maximum allowable peak current value (I FSM In this case, the maximum allowable peak current value (I FSM ) is the maximum allowable peak current value (I) of the transistor 100a under the operating condition that the gate voltage Vg of +15 V is continuously applied to the gate electrode 18 while the voltage of the source electrode 12 is a positive voltage higher than that of the drain electrode 14. FSM )

[0059] The comparison circuit 100c is, for example, an electronic circuit, and includes, for example, hardware and software.

[0060] The comparison circuit 100c includes, for example, a Central Processing Unit (CPU). The comparison circuit 100c includes, for example, a storage device. The storage device included in the comparison circuit 100c is, for example, a semiconductor memory. For example, a first threshold value is stored in the storage device.

[0061] The gate driver circuit 100d is electrically connected to the comparison circuit 100c and the gate electrode 18.

[0062] The gate driver circuit 100d applies a first positive voltage higher than the threshold voltage of the transistor 100a to the gate electrode 18 when the voltage of the source electrode 12 is a higher positive voltage than the drain electrode 14. Furthermore, the gate driver circuit 100d applies a first negative voltage to the gate electrode 18 when the value measured by the comparison circuit 100c exceeds the first threshold.

[0063] The gate driver circuit 100d is, for example, an electronic circuit, and the comparison circuit 100c includes, for example, hardware and software.

[0064] When the comparator circuit 100c detects the current flowing from the source electrode 12 to the drain electrode 14, the delay time from when the measured value in the comparator circuit 100c exceeds the first threshold to when the first negative voltage is applied to the gate electrode 18 is, for example, less than 2 ms (2000 μs). For example, the delay time from when the measured value in the comparator circuit 100c exceeds the first threshold to when the gate driver circuit 100d outputs the first negative voltage to the gate electrode 18 is, for example, less than 2 ms.

[0065] FIG. 3 is a diagram showing a specific example of the semiconductor device according to the first embodiment.

[0066] The semiconductor module 100 includes a transistor 100a, a Rogowski coil ammeter 100ax, a comparator 100cx, a pulse generator 100e, and a gate driver circuit 100d.

[0067] The Rogowski coil ammeter 100ax is an example of a detector, and the comparator 100cx is an example of a comparison circuit.

[0068] The comparator 100cx compares the value measured by the Rogowski coil ammeter 100ax with the first threshold value to determine whether they are larger or smaller. The pulse generator 100e generates a pulse based on the comparison result by the comparator 100cx and transmits it to the gate driver circuit 100d.

[0069] Next, a method for controlling the semiconductor device of the first embodiment will be described.

[0070] A first embodiment of a control method for a semiconductor device includes a transistor including a first electrode, a second electrode, an n-type first semiconductor region provided between the first electrode and the second electrode and electrically connected to the second electrode, a p-type second semiconductor region provided between the first semiconductor region and the first electrode and electrically connected to the first electrode, an n-type third semiconductor region provided between the second semiconductor region and the first electrode and electrically connected to the first electrode, and a gate electrode facing the second semiconductor region, the control method comprising: applying a positive voltage to the first electrode that is higher than that to the second electrode; applying a first positive voltage to the gate electrode that is higher than a threshold voltage of the transistor; detecting a current flowing from the first electrode to the second electrode; comparing the detected measured value with a first threshold; and applying a first negative voltage to the gate electrode if the measured value exceeds the first threshold.

[0071] 4, 5(a), 5(b), 5(c), 5(d), 5(e), and 5(f) are explanatory diagrams of a control method for a semiconductor device according to the first embodiment.

[0072] 4 is a diagram showing the change over time of the current and gate voltage of the transistor 100a of the first embodiment. Fig. 4 shows the change over time of the current and gate voltage when the voltage of the source electrode 12 is a higher positive voltage than the drain electrode 14. Fig. 4 also shows the voltage of the source electrode 12.

[0073] In the upper diagram of Figure 4, the horizontal axis represents time and the vertical axis represents current and voltage. The current is the current flowing from the source electrode 12 to the drain electrode 14. The voltage is the voltage of the source electrode 12. The voltage of the source electrode 12 is, for example, the potential difference between the potential of the source electrode 12 and a reference potential. The reference potential is, for example, 0 V. In the upper diagram of Figure 4, the current is indicated by a solid line and the voltage by a dotted line.

[0074] 4, the horizontal axis represents time and the vertical axis represents gate voltage. The gate voltage is the voltage applied to the gate electrode 18. The gate voltage is, for example, the potential difference between the potential of the gate electrode 18 and a reference potential. The reference potential is, for example, 0 V.

[0075] Figures 5(a), 5(b), 5(c), 5(d), 5(e), and 5(f) are schematic diagrams showing the current flowing through the transistor 100a during each time period shown in Figure 4. In the diagrams, solid arrows indicate unipolar currents, and dotted arrows indicate bipolar currents.

[0076] In the following description, we will consider a case where the transistor 100a is a high-side transistor provided in one arm of a three-phase inverter circuit that performs synchronous rectification. In particular, we will consider a case where, when the transistor 100a is in an off state, a load current caused by an inductive load applies a voltage to the source electrode 12 that is positive with respect to the drain electrode 14. In other words, we will consider a case where the source voltage of the source electrode 12 is a positive voltage that is higher than the drain voltage of the drain electrode 14.

[0077] Between time t0 and time t1, a gate voltage Vg lower than the threshold voltage of the transistor 100a is applied to the gate electrode 18. Between time t0 and time t1, for example, a negative gate voltage Vg is applied to the gate electrode 18. Between time t0 and time t1, a negative voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, −15 V.

[0078] A gate voltage Vg is applied to the gate electrode 18 by a gate driver circuit 100d.

[0079] Between time t0 and time t1, the gate voltage Vg is lower than the threshold voltage of the transistor 100a. Therefore, between time t0 and time t1, as shown in FIG. 5(a), no inversion layer is formed in the channel region of the transistor 100a, and no current flows through the channel region. Also, between time t0 and time t1, for example, the voltage between the source electrode 12 and the drain electrode 14 is lower than the forward voltage (Vf) of the pn junction diode built into the transistor 100a, so no current flows through the pn junction diode either.

[0080] In a three-phase inverter circuit that performs synchronous rectification, it is necessary to prevent a shoot-through current from flowing through one arm. For example, it is necessary to prevent a shoot-through current from flowing when both the low-side transistor and the high-side transistor 100a, both of which are provided in the same arm as the transistor 100a, are turned on. For this reason, a dead time is provided in synchronous rectification, during which both the low-side transistor and the high-side transistor 100a are turned off. The period from time t0 to time t1 is part of the dead time.

[0081] Between time t1 and time t2, a positive gate voltage Vg is applied to the gate electrode 18. Between time t1 and time t2, a positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15 V. The gate voltage Vg applied to the gate electrode 18 between time t1 and time t2 is an example of a first positive voltage.

[0082] 5(b), an inversion layer is formed in the channel region of the transistor 100a, and a unipolar current flows through the channel region. Also, between the time t1 and the time t2, for example, the voltage between the source electrode 12 and the drain electrode 14 is lower than the forward voltage (Vf) of the pn junction diode built into the transistor 100a, so no current flows through the pn junction diode.

[0083] For example, from time t2 to time t6, a large surge current that exceeds the steady state flows through the transistor 100a. For example, the surge current reaches its maximum at time t4. Between time t0 to time t2 and between time t6 and time t7, the transistor 100a is in the steady state.

[0084] Between time t2 and time t3, a positive gate voltage Vg is applied to the gate electrode 18. Between time t2 and time t3, a positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15 V. The gate voltage Vg applied to the gate electrode 18 between time t2 and time t3 is an example of a first positive voltage.

[0085] Between time t2 and time t3, as shown in Figure 5(c), an inversion layer is formed in the channel region of transistor 100a, and a unipolar current flows through the channel region. Also, between time t2 and time t3, for example, the voltage between source electrode 12 and drain electrode 14 becomes higher than the forward voltage (Vf) of the pn junction diode built into transistor 100a, and a bipolar current flows through the pn junction diode. Between time t2 and time t3, for example, a unipolar current and a bipolar current flow through transistor 100a.

[0086] At time t3, the current flowing from the source electrode 12 to the drain electrode 14 of the transistor 100a exceeds a first threshold current. The first threshold current is a predetermined current value. The first threshold current is an example of a first threshold. The current flowing from the source electrode 12 to the drain electrode 14 is measured by the ammeter 100b.

[0087] The first threshold current is, for example, the maximum allowable peak current value (I FSM In this case, the maximum allowable peak current value (I FSM ) is the maximum allowable peak current value (I) of the transistor 100a under the operating condition that the gate voltage Vg of +15 V is continuously applied to the gate electrode 18 while the voltage of the source electrode 12 is a positive voltage higher than that of the drain electrode 14. FSM )

[0088] At time t3, the comparison circuit 100c determines that the current flowing from the source electrode 12 to the drain electrode 14 of the transistor 100a has exceeded the first threshold current. The comparison circuit 100c makes this determination by comparing the value measured by the ammeter 100b with the first threshold current.

[0089] At time t3, a negative gate voltage Vg lower than the threshold voltage of transistor 100a is applied to gate electrode 18. At time t3, the negative voltage is applied to gate electrode 18. The gate voltage Vg is, for example, −15 V. The gate voltage Vg applied to gate electrode 18 at time t3 is an example of a first negative voltage.

[0090] If the comparison result in the comparator circuit 100c indicates that the measured current exceeds the first threshold current, a first negative voltage is applied to the gate electrode 18 by the gate driver circuit 100d.

[0091] The delay time from when the measured value in the comparison circuit 100c exceeds the first threshold current to when the negative voltage is applied to the gate electrode 18 is, for example, 2 ms or less. For example, the delay time from when the measured value in the comparison circuit 100c exceeds the first threshold current to when the gate driver circuit 100d outputs the first negative voltage to the gate electrode 18 is, for example, 2 ms or less.

[0092] Between time t3 and time t5, a negative gate voltage Vg is applied to the gate electrode 18. Between time t3 and time t5, a negative voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, −15 V. The gate voltage Vg applied to the gate electrode 18 between time t3 and time t5 is an example of a first negative voltage.

[0093] Between time t3 and time t5, the gate voltage Vg becomes a first negative voltage, causing the body region 30 facing the gate electrode 18 to enter an accumulation state. Between time t3 and time t5, an accumulation layer is formed in the channel region of the transistor 100a, and no channel is formed in the channel region. Therefore, as shown in FIG. 5(d), no current flows in the channel region.

[0094] Furthermore, between time t3 and time t5, for example, the voltage between the source electrode 12 and the drain electrode 14 becomes higher than the forward voltage (Vf) of the pn junction diode built into the transistor 100a, and a bipolar current flows through the pn junction diode. Between time t3 and time t5, for example, no unipolar current flows, and only a bipolar current flows.

[0095] At time t5, the current flowing from the source electrode 12 to the drain electrode 14 of the transistor 100a falls below the second threshold current. The second threshold current is an example of a second threshold. The second threshold current may be equal to the first threshold current. Alternatively, the second threshold current may be different from the first threshold current.

[0096] At time t5, the comparison circuit 100c determines that the current flowing from the source electrode 12 to the drain electrode 14 of the transistor 100a has fallen below the second threshold current. The comparison circuit 100c makes this determination by comparing the value measured by the ammeter 100b with the second threshold current.

[0097] At time t5, a positive gate voltage Vg higher than the threshold voltage of transistor 100a is applied to gate electrode 18. At time t5, a positive voltage is applied to gate electrode 18. The gate voltage Vg is, for example, +15 V. The gate voltage Vg applied to gate electrode 18 at time t5 is an example of a second positive voltage.

[0098] If the comparison result in the comparator circuit 100c indicates that the measured current is below the second threshold current, a second positive voltage is applied to the gate electrode 18 by the gate driver circuit 100d.

[0099] Between time t5 and time t6, a positive gate voltage Vg is applied to the gate electrode 18. Between time t5 and time t6, a positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15 V. The gate voltage Vg applied to the gate electrode 18 between time t5 and time t6 is an example of a second positive voltage.

[0100] Between time t5 and time t6, an inversion layer is formed in the channel region of the transistor 100a. Therefore, as shown in FIG. 5(e), a unipolar current flows in the channel region of the transistor 100a. Also, between time t5 and time t6, for example, the voltage between the source electrode 12 and the drain electrode 14 becomes higher than the forward voltage (Vf) of the pn junction diode built into the transistor 100a. Therefore, a bipolar current flows in the pn junction diode. Between time t5 and time t6, for example, a unipolar current and a bipolar current flow in the transistor 100a.

[0101] Between time t6 and time t7, a positive gate voltage Vg is applied to the gate electrode 18. Between time t6 and time t7, a positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15 V. The gate voltage Vg applied to the gate electrode 18 between time t6 and time t7 is an example of a second positive voltage.

[0102] Between time t6 and time t7, an inversion layer is formed in the channel region of transistor 100a. Therefore, as shown in Figure 5(f), a unipolar current flows in the channel region of transistor 100a. Also, between time t6 and time t7, for example, the voltage between source electrode 12 and drain electrode 14 is lower than the forward voltage (Vf) of the pn junction diode built into transistor 100a, so no current flows through the pn junction diode.

[0103] Next, the operation and effects of the semiconductor device of the first embodiment will be described.

[0104] Vertical MOSFETs using silicon carbide have a built-in pn junction diode. For example, MOSFETs are used as switching elements connected to inductive loads. In this case, the built-in diode allows a freewheeling current to flow even when the MOSFET is off.

[0105] A large surge current may flow through a MOSFET momentarily, exceeding the steady state. When a large surge current flows, the MOSFET heats up and is destroyed. The maximum allowable peak current value (I FSM ) is called surge current capability. It is desirable to improve the surge current capability of MOSFETs.

[0106] In the semiconductor module 100 of the first embodiment, when a surge current flows through the transistor 100a included in the semiconductor module 100, a negative voltage is applied to the gate electrode 18, thereby improving the surge current resistance. This will be described in detail below.

[0107] 6 is a block diagram of a semiconductor device of a comparative example, which is a semiconductor module 900 including a transistor 100a using silicon carbide.

[0108] The semiconductor module 900 includes a transistor 100a and a gate driver circuit 100d. The semiconductor module 900 differs from the semiconductor module 100 of the first embodiment in that it does not include an ammeter 100b and a comparator circuit 100c.

[0109] 7, 8(a), 8(b), 8(c), and 8(d) are explanatory diagrams of a control method for a semiconductor device of a comparative example.

[0110] 7 is a diagram showing changes over time in the current and gate voltage of the transistor 100a of the comparative example, and corresponds to FIG. 4 of the first embodiment.

[0111] Figures 8(a), 8(b), 8(c), and 8(d) are schematic diagrams showing the current flowing through the transistor 100a during each time period shown in Figure 7. In the diagrams, solid arrows indicate unipolar currents, and dotted arrows indicate bipolar currents.

[0112] Between time t0 and time t1, a gate voltage Vg lower than the threshold voltage of the transistor 100a is applied to the gate electrode 18. Between time t0 and time t1, no current flows in the channel region, as shown in FIG. 8(a). Also, between time t0 and time t1, no current flows in, for example, the pn junction diode.

[0113] Between time t1 and time t2, a positive gate voltage Vg higher than the threshold voltage of the transistor 100a is applied to the gate electrode 18. Between time t1 and time t2, as shown in FIG. 8(b), a unipolar current flows in the channel region. Also, between time t1 and time t2, no current flows in the pn junction diode.

[0114] For example, between time t2 and time t6, a large surge current exceeding the steady state is applied to the transistor 100a as shown in the upper diagram of Fig. 7. For example, the surge current reaches its maximum at time t4.

[0115] 7, a positive gate voltage Vg higher than the threshold voltage of the transistor 100a is applied to the gate electrode 18. From time t2 to time t6, a positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15 V.

[0116] Between time t2 and time t6, an inversion layer is formed in the channel region of the transistor 100a. Therefore, as shown in FIG. 8(c), a unipolar current flows in the channel region of the transistor 100a. Also, between time t2 and time t6, for example, the voltage between the source electrode 12 and the drain electrode 14 becomes higher than the forward voltage (Vf) of the pn junction diode built into the transistor 100a. Therefore, a bipolar current flows in the pn junction diode. Between time t2 and time t6, for example, a unipolar current and a bipolar current flow in the transistor 100a.

[0117] Between time t6 and time t7, a positive gate voltage Vg is applied to the gate electrode 18. Between time t1 and time t2, an inversion layer is formed in the channel region of the transistor 100a. Therefore, as shown in FIG. 8(d), a unipolar current flows in the channel region. Also, between time t6 and time t7, for example, the voltage between the source electrode 12 and the drain electrode 14 is lower than the forward voltage (Vf) of the pn junction diode built into the transistor 100a, so no current flows through the pn junction diode.

[0118] The control method of the semiconductor module 900 of the comparative example differs from that of the semiconductor module 100 of the first embodiment in that, particularly when a large surge current flows through the transistor 100a, a negative voltage is not applied to the gate electrode 18. In other words, the control method of the semiconductor module 900 of the comparative example differs from that of the semiconductor module 100 of the first embodiment in that, particularly when a large surge current flows through the transistor 100a, a positive voltage is continuously applied to the gate electrode 18.

[0119] 9 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment. FIG. 9 shows the relationship between the source voltage of transistor 100a and the current flowing through transistor 100a. The current flows when the source voltage of source electrode 12 is a positive voltage higher than the drain voltage of drain electrode 14. The solid line in FIG. 9 represents the case where gate voltage Vg is +15V, and the dotted line represents the case where gate voltage Vg is -15V.

[0120] 9, when the gate voltage Vg is +15 V, a unipolar current flows in the channel region of the transistor 100a, causing the current to rise from a source voltage of 0 V. On the other hand, when the gate voltage Vg is −15 V, no current flows in the channel region of the transistor 100a, and the current rises when the source voltage exceeds the forward voltage (Vf) of the pn junction diode.

[0121] When a freewheeling current is passed through the transistor 100a, the power loss of the semiconductor module can be reduced by passing a unipolar current through the channel region with the gate voltage Vg set to +15 V. Therefore, when a freewheeling current is passed through the transistor 100a, it is preferable to apply a positive voltage exceeding the threshold voltage of the transistor 100a to the gate voltage Vg.

[0122] In the semiconductor module 900 of the comparative example, during steady-state periods when no surge current flows, for example, between time t1 and time t2 and between time t6 and time t7, a positive voltage exceeding the threshold voltage of the transistor 100a is applied to the gate voltage Vg, thereby reducing power loss in the semiconductor module 900.

[0123] Similarly, in the semiconductor module 100 of the first embodiment, during steady-state periods when no surge current flows, for example, between time t1 and time t2 and between time t6 and time t7, a positive voltage exceeding the threshold voltage of the transistor 100a is applied to the gate voltage Vg, thereby reducing power loss in the semiconductor module 100.

[0124] 10 is a diagram illustrating the operation and effect of the semiconductor device of the first embodiment. FIG. 10 shows the maximum allowable peak current value (I FSM ) of the semiconductor module of the first embodiment. FSM ) is 100%, the maximum allowable peak current value (I FSM ) indicates the ratio.

[0125] As shown in FIG. 10, the maximum allowable peak current value (I FSM ) is 29%, and the maximum allowable peak current value (I FSM ) is lower than that of the semiconductor module of the comparative example. In other words, the semiconductor module of the first embodiment has an improved surge current resistance compared to the semiconductor module of the comparative example.

[0126] 11 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment. FIG. 11 shows the relationship between the source voltage of a transistor 100a and the current flowing through the transistor 100a. The current flows when the source voltage of the source electrode 12 is a positive voltage higher than the drain voltage of the drain electrode 14. The solid line in FIG. 11 represents the case where the gate voltage Vg is +15V, and the dotted line represents the case where the gate voltage Vg is -15V. FIG. 11 includes a region where the source voltage is higher than that in FIG. 9.

[0127] 11, in the region where the current flowing through the transistor 100a is low, the source voltage is lower when the gate voltage Vg is +15 V than when the gate voltage Vg is −15 V. Therefore, the amount of heat generated, which is proportional to the product of the current and voltage, is lower when the gate voltage Vg is +15 V.

[0128] 11, in a region where the current flowing through transistor 100a is high, specifically in a region where the current is higher than the current reversal point in Fig. 11, the source voltage is higher when gate voltage Vg is +15 V than when gate voltage Vg is -15 V. Therefore, in a region where the current is higher than the current reversal point in Fig. 11, the amount of heat generated, which is proportional to the product of the current and voltage, is higher when gate voltage Vg is +15 V than when gate voltage Vg is -15 V.

[0129] 7, in the semiconductor module 900 of the comparative example, the gate voltage Vg is maintained at +15 V from time t2 to time t6 when the surge current flows. Therefore, the amount of heat generated when the surge current flows is higher than when the gate voltage Vg is maintained at -15 V, for example. This is thought to result in a decrease in surge current resistance.

[0130] On the other hand, in the semiconductor module 100 of the first embodiment, as shown in Fig. 4, the gate voltage Vg is maintained at -15V during the period from time t3 to time t5 when a high surge current flows. Therefore, the amount of heat generated when a surge current flows is lower than when the gate voltage Vg is maintained at +15V, for example. This is thought to improve surge current resistance.

[0131] In the semiconductor module 100 of the first embodiment, in order to prevent current from flowing in the channel region of the transistor 100a, the first negative voltage applied to the gate electrode 18 between time t3 and time t5 is preferably −5V or less, more preferably −10V or less, and even more preferably −15V or less.

[0132] In the semiconductor module 100 of the first embodiment, from the viewpoint of flowing current through the channel region of the transistor 100a, the first negative voltage applied to the gate electrode 18 between time t1 and time t2 and between time t6 and time t7 is preferably +5V or more, more preferably +10V or more, and even more preferably +15V or more.

[0133] 12(a) and 12(b) are explanatory diagrams of the operation and effect of the semiconductor device of the first embodiment, and are diagrams showing simulation results.

[0134] Fig. 12(a) is a diagram showing the change over time in surge current when a positive gate voltage Vg of +15 V, which is higher than the threshold voltage of the transistor 100a, is applied to the gate electrode 18 in the structure of the transistor 100a shown in Fig. 2. As shown in Fig. 12(a), a current peak of 34 A is observed at 4.0 ms (milliseconds).

[0135] 12(b) is a diagram showing the maximum temperature in the transistor 100a when a surge current flows in the structure of the transistor 100a shown in FIG. 2. The solid line represents the case where +15 V is continuously applied as the gate voltage Vg, as in the comparative example. The dotted line represents the case where the positive gate voltage Vg of +15 V is switched to the negative gate voltage Vg of −15 V at the time (4.0 ms) when the current peak is observed. The dotted line corresponds to the first embodiment.

[0136] As shown in Figure 12(b), there is a delay of 2 ms (milliseconds) between the time when the current peak is observed and the time when the maximum temperature is reached. It is believed that the heat propagation delay inside the transistor 100a is one of the causes of this delay.

[0137] Because of the delay time, even if the gate voltage Vg is switched from a positive voltage to a negative voltage at the same time as the current peak is observed, the internal temperature of the transistor 100a is kept sufficiently low, as shown by the dotted line in Figure 12(b). Because of the delay time, by switching the gate voltage Vg from a positive voltage to a negative voltage within 2 ms from the time the current peak is observed, the internal temperature of the transistor 100a can be prevented from reaching the maximum temperature.

[0138] 13 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment, and is a diagram showing the results of an experiment using the transistor 100a shown in FIG.

[0139] The maximum allowable peak current value of the transistor 100a (I FSM ) was evaluated using the gate voltage Vg, the first threshold current (Isw), and the delay time (Tdelay) from when the first threshold current (Isw) is detected until the first negative voltage, which is the negative gate voltage Vg, is applied to the gate electrode 18 as parameters.

[0140] The first threshold current (Isw) is calculated as the maximum allowable peak current value (I FSM ), the maximum allowable peak current value (I FSM ) from the maximum allowable peak current (I FSM ) is not observed. Also, up to the delay time of 2000 μs (2 ms), the maximum allowable peak current value (I FSM) or more than the maximum allowable peak current value (I FSM ) can be achieved.

[0141] When the comparator circuit 100c detects the current flowing from the source electrode 12 to the drain electrode 14, the delay time from when the measured value in the comparator circuit 100c exceeds the first threshold current to when the first negative voltage is applied to the gate electrode 18 is preferably less than 2 ms, more preferably less than 500 μs, and even more preferably less than 200 μs. For example, the delay time from when the measured value in the comparator circuit 100c exceeds the first threshold current to when the gate driver circuit 100d outputs the first negative voltage to the gate electrode 18 is preferably less than 2 ms, more preferably less than 500 μs, and even more preferably less than 200 μs. By satisfying the upper limit of the delay time, the maximum allowable peak current value (I FSM ) is suppressed, and surge current resistance is improved.

[0142] The first threshold current is the maximum allowable peak current value (I FSM ) is preferably 0.6 times or more and 1.0 times or less, and more preferably 0.8 times or more and 1.0 times or less. In this case, the maximum allowable peak current value (I FSM ) is the maximum allowable peak current value (I) of the transistor 100a under the operating condition in which a gate voltage Vg of +15 V is continuously applied to the gate electrode 18 when the voltage of the source electrode 12 is a positive voltage higher than that of the drain electrode 14 (the operating condition of the comparative example). FSM )

[0143] When the first threshold current satisfies the upper limit, the maximum allowable peak current value (I FSM ) is suppressed. Furthermore, by making the first threshold current satisfy the above-mentioned lower limit, reduction in power loss of the semiconductor module 100 is promoted.

[0144] (Variation) The semiconductor device of the modified example of the first embodiment differs from the first embodiment in that it includes a detector that detects the voltage of the first electrode when the voltage of the first electrode is a positive voltage higher than the voltage of the second electrode.

[0145] 14 is a block diagram of a semiconductor device according to a modification of the first embodiment. The semiconductor device according to the modification of the first embodiment is a semiconductor module 101 including a transistor 100a using silicon carbide.

[0146] The semiconductor module 101 includes a transistor 100a, a voltmeter 100f, a comparator circuit 100c, and a gate driver circuit 100d.

[0147] The voltmeter 100f is provided, for example, between the source electrode 12 and the drain electrode 14 of the transistor 100a. The voltmeter 100f can detect the voltage of the source electrode 12, that is, the source voltage.

[0148] The voltmeter 100f is an example of a detector. The voltmeter 100f detects the voltage of the source electrode 12 when the voltage of the source electrode 12 is a positive voltage higher than the voltage of the drain electrode 14.

[0149] The comparison circuit 100c is electrically connected to the voltmeter 100f. When the voltage of the source electrode 12 is a positive voltage higher than that of the drain electrode 14, the comparison circuit 100c compares the measurement value measured by the voltmeter 100f with a first threshold value.

[0150] The measured value measured by the voltmeter 100f is a voltage value. The first threshold is a preset threshold voltage. The first threshold is, for example, 5V or more and 15V or less.

[0151] The gate driver circuit 100d is electrically connected to the comparison circuit 100c and the gate electrode 18.

[0152] The gate driver circuit 100d applies a first positive voltage higher than the threshold voltage of the transistor 100a to the gate electrode 18 when the voltage of the source electrode 12 is a higher positive voltage than the drain electrode 14. Furthermore, the gate driver circuit 100d applies a first negative voltage to the gate electrode 18 when the value measured by the comparison circuit 100c exceeds the first threshold.

[0153] Next, a method for controlling a semiconductor device according to a modification of the first embodiment will be described.

[0154] The method for controlling a semiconductor device according to the first embodiment differs from the method for controlling a semiconductor device according to the first embodiment in that the voltage of the first electrode is detected.

[0155] Fig. 15 is an explanatory diagram of a control method for a semiconductor device according to a modified example of the first embodiment, and corresponds to Fig. 4 of the first embodiment.

[0156] Fig. 15 is a diagram showing the change over time in the voltage and gate voltage of the transistor 100a according to the modification of the first embodiment. Fig. 15 shows the change over time in the voltage and gate voltage when the voltage of the source electrode 12 is a higher positive voltage than the voltage of the drain electrode 14. Fig. 15 also shows the current of the source electrode 12.

[0157] In the upper diagram of Figure 15, the horizontal axis represents time and the vertical axis represents current and voltage. The current is a current that flows from the source electrode 12 to the drain electrode 14. The voltage is the voltage of the source electrode 12. The reference potential is, for example, 0 V. In the upper diagram of Figure 15, the current is represented by a dotted line and the voltage is represented by a solid line.

[0158] 15, the horizontal axis represents time and the vertical axis represents gate voltage. The gate voltage is the voltage applied to the gate electrode 18.

[0159] Between time t0 and time t1, as in the first embodiment, a gate voltage Vg lower than the threshold voltage of the transistor 100a is applied to the gate electrode 18. Between time t0 and time t1, for example, a negative gate voltage Vg is applied to the gate electrode 18.

[0160] Between time t1 and time t2, as in the first embodiment, a positive gate voltage Vg is applied to the gate electrode 18. Between time t1 and time t2, a positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15 V. The gate voltage Vg applied to the gate electrode 18 between time t1 and time t2 is an example of a first positive voltage.

[0161] For example, a large surge current exceeding the steady state current flows through the transistor 100a from time t2 to time t6. For example, the surge current reaches its maximum at time t4.

[0162] Between time t2 and time t3, as in the first embodiment, a positive gate voltage Vg is applied to the gate electrode 18. Between time t2 and time t3, a positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15 V. The gate voltage Vg applied to the gate electrode 18 between time t2 and time t3 is an example of a first positive voltage.

[0163] At time t3, the voltage of the source electrode 12 of the transistor 100a exceeds a first threshold voltage. The first threshold voltage is a predetermined voltage value. The first threshold voltage is an example of a first threshold. The voltage of the source electrode 12 is measured by a voltmeter 100f.

[0164] At time t3, the comparator circuit 100c determines that the current flowing from the source electrode 12 to the drain electrode 14 of the transistor 100a has exceeded the first threshold voltage. The comparator circuit 100c makes this determination by comparing the value measured by the voltmeter 100f with the first threshold voltage.

[0165] At time t3, a negative gate voltage Vg lower than the threshold voltage of transistor 100a is applied to gate electrode 18. At time t3, the negative voltage is applied to gate electrode 18. The gate voltage Vg is, for example, −15 V. The gate voltage Vg applied to gate electrode 18 at time t3 is an example of a first negative voltage.

[0166] If the comparison result in the comparator circuit 100c indicates that the measured voltage of the source electrode 12 exceeds the first threshold voltage, a first negative voltage is applied to the gate electrode 18 by the gate driver circuit 100d.

[0167] Between time t3 and time t5, as in the first embodiment, a negative gate voltage Vg is applied to the gate electrode 18. Between time t3 and time t5, a negative voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, −15 V. The gate voltage Vg applied to the gate electrode 18 between time t3 and time t5 is an example of a first negative voltage.

[0168] At time t5, the voltage of the source electrode 12 of the transistor 100a falls below the second threshold voltage. The second threshold voltage is an example of a second threshold. The second threshold voltage may be equal to the first threshold voltage, for example. The second threshold voltage may also be lower than the first threshold voltage, for example.

[0169] At time t5, the comparison circuit 100c determines that the voltage at the source electrode 12 of the transistor 100a has fallen below the second threshold voltage by comparing the value measured by the voltmeter 100f with the second threshold voltage.

[0170] At time t5, a positive gate voltage Vg higher than the threshold voltage of transistor 100a is applied to gate electrode 18. At time t5, a positive voltage is applied to gate electrode 18. The gate voltage Vg is, for example, +15 V. The gate voltage Vg applied to gate electrode 18 at time t5 is an example of a second positive voltage.

[0171] If the comparison result in the comparator circuit 100c indicates that the measured voltage of the source electrode 12 is lower than the second threshold voltage, a second positive voltage is applied to the gate electrode 18 by the gate driver circuit 100d.

[0172] Between time t5 and time t6, as in the first embodiment, a positive gate voltage Vg is applied to the gate electrode 18. Between time t5 and time t6, a positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15 V. The gate voltage Vg applied to the gate electrode 18 between time t5 and time t6 is an example of a second positive voltage.

[0173] Between time t6 and time t7, as in the first embodiment, a positive gate voltage Vg is applied to the gate electrode 18. Between time t6 and time t7, a positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15 V. The gate voltage Vg applied to the gate electrode 18 between time t6 and time t7 is an example of a second positive voltage.

[0174] According to the semiconductor module 101 of the modified example of the first embodiment, similarly to the semiconductor module 100 of the first embodiment, when a surge current flows through the transistor 100a included in the semiconductor module 101, a negative voltage is applied to the gate electrode 18. Therefore, it is possible to improve the surge current resistance.

[0175] In the semiconductor module 101 according to the modification of the first embodiment, the second threshold voltage is preferably lower than the first threshold voltage as shown in FIG. 15 in order to improve the surge current resistance.

[0176] 15, for example, the voltage of source electrode 12 of transistor 100a peaks when the surge current begins to flow and then decreases. Therefore, if the second threshold voltage is equal to the first threshold voltage, the current flowing through transistor 100a at time t5 may be larger than the current flowing through transistor 100a at time t3. In this case, if a positive voltage is applied to gate electrode 18 at time t5, the current flowing through transistor 100a may exceed the maximum allowable peak current value.

[0177] By setting the second threshold voltage lower than the first threshold voltage, the current flowing through transistor 100a at time t5 can be made equal to or less than the current flowing through transistor 100a at time t3. Therefore, applying a positive voltage to gate electrode 18 at time t5 eliminates the risk of exceeding the maximum allowable peak current value, thereby improving the surge current resistance of semiconductor module 101.

[0178] As described above, according to the first embodiment and its modifications, a semiconductor device with improved surge current resistance is realized. Also, according to the first embodiment and its modifications, a semiconductor device with reduced power loss is realized.

[0179] (Second embodiment) The semiconductor device and the method for controlling the semiconductor device of the second embodiment differ from the semiconductor device of the first embodiment in that the first electrode is in contact with the first semiconductor region. That is, the semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the transistor includes a Schottky diode as a built-in diode. Hereinafter, some of the content overlapping with the first embodiment may be omitted.

[0180] 16 is a block diagram of a semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is a semiconductor module 200 including a transistor 200a using silicon carbide.

[0181] The semiconductor module 200 includes a transistor 200a, an ammeter 100b, a comparison circuit 100c, and a gate driver circuit 100d.

[0182] 17 is a schematic cross-sectional view of a transistor 200a according to the second embodiment.

[0183] The transistor 200a is a planar-gate vertical MOSFET using silicon carbide. The transistor 200a is, for example, a double implantation MOSFET (DIMOSFET) in which the body region and the source region are formed by ion implantation. The transistor 100a is a vertical n-channel MOSFET that uses electrons as carriers.

[0184] The transistor 200a includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20.

[0185] In the silicon carbide layer 10, n + n-type drain region 26 - a p-type drift region 28 (first semiconductor region), a p-type body region 30 (second semiconductor region), and an n-type + A source region 34 (third semiconductor region) of the type is included.

[0186] The source electrode 12 is provided on the first face P1 side of the silicon carbide layer 10. The source electrode 12 is in contact with the first face P1.

[0187] The source electrode 12 contacts the drift region 28, the body region 30, and the source region 34. The source electrode 12 contacts the drift region 28 at a first plane P1.

[0188] The source electrode 12 includes a metal, and the metal forming the source electrode 12 has a laminated structure of, for example, titanium (Ti) and aluminum (Al).

[0189] The portion of the source electrode 12 in contact with the body region 30 and the source region 34 is made of, for example, a metal silicide. The metal silicide is, for example, titanium silicide or nickel silicide.

[0190] The contact between the body region 30 and the source electrode 12 and the contact between the source region 34 and the source electrode 12 are, for example, ohmic contacts.

[0191] The contact between the drift region 28 and the source electrode 12 is, for example, a Schottky contact.

[0192] As shown in FIG. 16, a transistor 200a has a pn junction diode and a Schottky junction diode connected between a source electrode 12 and a drain electrode 14 as built-in diodes.

[0193] For example, consider a case where transistor 200a is used as a switching element connected to an inductive load. When transistor 200a is off, a load current caused by the inductive load may apply a voltage to source electrode 12 that is positive with respect to drain electrode 14. In this case, a forward current flows through the built-in diode. This state is also called a reverse conduction state.

[0194] When the voltage between the source electrode 12 and the drain electrode 14 exceeds the forward voltage (Vf) of the Schottky junction diode, a forward current flows through the Schottky junction diode. Also, when the voltage between the source electrode 12 and the drain electrode 14 exceeds the forward voltage (Vf) of the pn junction diode, a forward current flows through the pn junction diode. The forward voltage (Vf) of the Schottky junction diode is lower than the forward voltage (Vf) of the pn junction diode.

[0195] According to the semiconductor module 200 of the second embodiment, similar to the semiconductor module 100 of the first embodiment, when a surge current flows through the transistor 200a included in the semiconductor module 200, the surge current tolerance can be improved by applying a negative voltage to the gate electrode 18.

[0196] Furthermore, the transistor 200a includes a built-in Schottky junction diode having a forward voltage (Vf) lower than the forward voltage (Vf) of the pn junction diode. Therefore, for example, if the voltage between the source electrode 12 and the drain electrode 14 becomes higher than the forward voltage (Vf) of the Schottky junction diode built into the transistor 200a between time t0 and time t1 in FIG. 4, a current can flow through the Schottky junction diode. Therefore, the semiconductor module 200 of the second embodiment can start to flow a return current earlier than the semiconductor module 100 of the first embodiment, thereby further reducing power loss.

[0197] (Variation) The semiconductor device of the modified example of the second embodiment differs from the second embodiment in that it includes a detector that detects the voltage of the first electrode when the voltage of the first electrode is a positive voltage higher than the voltage of the second electrode. The semiconductor device of the modified example of the second embodiment also differs from the semiconductor device of the modified example of the first embodiment in that the transistor includes a Schottky junction diode as a built-in diode.

[0198] 18 is a block diagram of a semiconductor device according to a modification of the second embodiment. The semiconductor device according to the modification of the second embodiment is a semiconductor module 201 including a transistor 200a using silicon carbide.

[0199] The semiconductor module 201 includes a transistor 200a, a voltmeter 100f, a comparator circuit 100c, and a gate driver circuit 100d.

[0200] According to the semiconductor module 201 of the modified example of the second embodiment, similarly to the semiconductor module 200 of the second embodiment, when a surge current flows through the transistor 200a included in the semiconductor module 201, the surge current tolerance can be improved by applying a negative voltage to the gate electrode 18.

[0201] As described above, the second embodiment and its modifications provide a semiconductor device with improved surge current resistance. Also, the second embodiment and its modifications provide a semiconductor device with further reduced power loss.

[0202] In the first and second embodiments, the semiconductor region is made of silicon carbide (SiC), but the semiconductor region may be made of silicon (Si) or a nitride semiconductor, for example.

[0203] In the first and second embodiments, the crystalline structure of SiC has been described as 4H—SiC, but the present invention can also be applied to devices using SiC with other crystalline structures such as 6H—SiC, 3C—SiC, etc. Furthermore, a plane other than the (0001) plane can also be applied to the surface of the silicon carbide layer 10.

[0204] In the first and second embodiments, aluminum (Al) is used as an example of a p-type impurity, but boron (B) can also be used. Furthermore, nitrogen (N) and phosphorus (P) are used as examples of n-type impurities, but arsenic (As), antimony (Sb), etc. can also be used.

[0205] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0206] 12 Source electrode (first electrode) 14 Drain electrode (second electrode) 18 gate electrode 28 drift region (first semiconductor region) 30 body region (second semiconductor region) 34 source region (third semiconductor region) 100 Semiconductor module (semiconductor device) 100a transistor 100b Ammeter (detector) 100c comparison circuit 100d Gate driver circuit 100f voltmeter (detector) 101 Semiconductor modules (semiconductor devices) 200 Semiconductor modules (semiconductor devices) 200a transistor 201 Semiconductor modules (semiconductor equipment)

Claims

1. a first electrode; a second electrode; and a transistor including: an n-type first semiconductor region provided between the first electrode and the second electrode and electrically connected to the second electrode; a p-type second semiconductor region provided between the first semiconductor region and the first electrode and electrically connected to the first electrode; an n-type third semiconductor region provided between the second semiconductor region and the first electrode and electrically connected to the first electrode; and a gate electrode facing the second semiconductor region; a detector that detects the voltage of the first electrode or the current flowing from the first electrode to the second electrode when the voltage of the first electrode is a positive voltage higher than the voltage of the second electrode; a comparison circuit that compares the measurement value measured by the detector with a first threshold value in the state; a gate driver circuit that applies a first positive voltage higher than a threshold voltage of the transistor to the gate electrode in the state, and applies a first negative voltage to the gate electrode when the measured value exceeds the first threshold as a result of comparison in the comparator circuit; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein said first electrode is in contact with said first semiconductor region.

3. 3. The semiconductor device according to claim 2, wherein the contact between said first electrode and said first semiconductor region is a Schottky contact.

4. 2. The semiconductor device according to claim 1, wherein said second semiconductor region facing said gate electrode is in an accumulation state when said first negative voltage is applied to said gate electrode.

5. After applying the first negative voltage to the gate electrode, in the state, the comparator circuit compares the measurement value measured by the detector with a second threshold value; 2. The semiconductor device according to claim 1, wherein, in said state, when said measured value in said comparison circuit falls below said second threshold voltage, said gate driver circuit applies to said gate electrode a second positive voltage higher than said threshold voltage.

6. 6. The semiconductor device according to claim 5, wherein when said detector detects the voltage of said first electrode, said second threshold value is a voltage lower than said first threshold value.

7. 2. The semiconductor device according to claim 1, wherein said first semiconductor region, said second semiconductor region, and said third semiconductor region are silicon carbide.

8. When the detector detects a current flowing from the first electrode to the second electrode, the first threshold is a current value, and the first threshold is a maximum allowable peak current value (I ＦＳＭ 2. The semiconductor device according to claim 1, wherein the value of the surface roughness is 0.6 to 1.0 times the surface roughness.

9. When the detector detects a current flowing from the first electrode to the second electrode, the first threshold is a current value, and the first threshold is a maximum allowable peak current value (I ＦＳＭ 2. The semiconductor device according to claim 1, wherein the value of the surface roughness is 0.8 times or more and 1.0 times or less.

10. 2. The semiconductor device according to claim 1, wherein when the detector detects a current flowing from the first electrode to the second electrode, a delay time from when the measured value exceeds the first threshold to when the first negative voltage is applied to the gate electrode is less than 2 ms.

11. 2. The semiconductor device according to claim 1, wherein, when the detector detects a current flowing from the first electrode to the second electrode, a delay time from when the measured value exceeds the first threshold to when the first negative voltage is applied to the gate electrode is less than 200 μs.

12. a first electrode; a second electrode; and A method for controlling a semiconductor device including a transistor including: an n-type first semiconductor region provided between the first electrode and the second electrode and electrically connected to the second electrode; a p-type second semiconductor region provided between the first semiconductor region and the first electrode and electrically connected to the first electrode; an n-type third semiconductor region provided between the second semiconductor region and the first electrode and electrically connected to the first electrode; and a gate electrode facing the second semiconductor region, applying a higher positive voltage to the first electrode than to the second electrode; applying a first positive voltage to the gate electrode, the first positive voltage being higher than a threshold voltage of the transistor; Detecting a voltage of the first electrode or a current flowing from the first electrode to the second electrode; A method for controlling a semiconductor device, comprising: comparing the detected measurement value with a first threshold; and applying a first negative voltage to the gate electrode when the measurement value exceeds the first threshold.

13. The method for controlling a semiconductor device according to claim 12 , wherein the first electrode contacts the first semiconductor region.

14. 14. The method for controlling a semiconductor device according to claim 13, wherein the contact between the first electrode and the first semiconductor region is a Schottky contact.

15. 13. The method for controlling a semiconductor device according to claim 12, wherein when the first negative voltage is applied to the gate electrode, the second semiconductor region facing the gate electrode is in an accumulation state.

16. applying the first negative voltage to the gate electrode, and then comparing the measured value with a second threshold value; 13. The method for controlling a semiconductor device according to claim 12, further comprising the step of applying a second positive voltage higher than the threshold voltage to the gate electrode when the measured value exceeds the second threshold voltage.

17. 17. The method for controlling a semiconductor device according to claim 16, wherein, when detecting the voltage of the first electrode, the second threshold value is a voltage lower than the first threshold value.

18. 13. The method for controlling a semiconductor device according to claim 12, wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are made of silicon carbide.

19. When detecting a current flowing from the first electrode to the second electrode, the first threshold is a current value, and the first threshold is a maximum allowable peak current value (I ＦＳＭ 13. The method for controlling a semiconductor device according to claim 12, wherein the voltage Vcc is 0.6 to 1.0 times the voltage Vcc.

20. When detecting a current flowing from the first electrode to the second electrode, the first threshold is a current value, and the first threshold is a maximum allowable peak current value (I ＦＳＭ 13. The method for controlling a semiconductor device according to claim 12, wherein the voltage Vcc is 0.8 to 1.0 times the voltage Vcc.

21. 13. The method for controlling a semiconductor device according to claim 12, wherein, when detecting a current flowing from the first electrode to the second electrode, a delay time from when the measured value exceeds the first threshold to when the first negative voltage is applied to the gate electrode is less than 2 ms.

22. 13. The method for controlling a semiconductor device according to claim 12, wherein, when detecting a current flowing from the first electrode to the second electrode, a delay time from when the measured value exceeds the first threshold to when the first negative voltage is applied to the gate electrode is less than 200 μs.

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