Regulator circuit, circuit arrangement and oscillator

Abstract

To provide a regulator circuit and the like that can achieve both a smaller circuit area and a lower noise level.SOLUTION: A regulator circuit 30 includes: an N-type output transistor provided between a first power supply node and an output node of a regulated voltage VREG; an operational amplifier OP in which a reference voltage is input to a first input terminal and a feedback voltage VFB, based on the regulated voltage VREG, is input to a second input terminal; and a low-pass filter circuit 40 that outputs a filtered drive voltage VD obtained by filtering the output voltage of the operational amplifier OP to a gate of the output transistor TRQ. The low-pass filter circuit 40 includes a MOS capacitor which is located between the gate of the output transistor TRQ and a second power supply node, and is configured using a transistor with a lower withstanding voltage than the output transistor TRQ.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a regulator circuit, a circuit device, an oscillator, and the like. [Background technology]

[0002] Regulator circuits that step down a power supply voltage to generate a regulated voltage have been known for some time. For example, Patent Document 1 discloses a regulator circuit that includes an operational amplifier having a reference voltage input to one input terminal and a feedback voltage input to the other input terminal, and a source-follower-connected output transistor that has an output signal from the operational amplifier input to its gate and is provided between a power supply node and an output node. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2014 / 207969 Summary of the Invention [Problem to be solved by the invention]

[0004] In a regulator circuit such as that described in Patent Document 1, it is conceivable to provide a low-pass filter circuit having a capacitor to reduce noise. However, if a MOS capacitor made of a MOS transistor is used as this capacitor, increasing the breakdown voltage requires a larger gate oxide film thickness for the MOS capacitor, which reduces the capacitance value per unit area. This poses a problem in that a capacitor with a large circuit area is required to ensure the required capacitance value. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a regulator circuit including: an N-type output transistor provided between a first power supply node and an output node of a regulated voltage; an operational amplifier having a first input terminal to which a reference voltage is input and a second input terminal to which a feedback voltage based on the regulated voltage is input; and a low-pass filter circuit that outputs a drive voltage obtained by filtering the output voltage of the operational amplifier to a gate of the output transistor, wherein the low-pass filter circuit is provided between the gate of the output transistor and a second power supply node and includes a MOS capacitor formed by a transistor having a lower withstand voltage than the output transistor.

[0006] Another aspect of the present disclosure relates to a circuit device including a power supply circuit including the regulator circuit described above, an oscillation circuit that causes an oscillator to oscillate, and a clock signal generation circuit that generates a clock signal based on an oscillation clock signal from the oscillation circuit.

[0007] Another aspect of the present disclosure relates to an oscillator including the circuit device described above and the resonator. [Brief explanation of the drawings]

[0008] [Figure 1] 1 shows an example of the configuration of a regulator circuit according to the present embodiment. [Figure 2] An example of a regulator circuit configuration with an analog switch. [Figure 3] An example of an analog switch configuration. [Figure 4] An example of a feedback circuit configuration. [Figure 5] An example of the characteristics of the current flowing through the output transistor and the drive voltage input to the gate. [Figure 6] Example of PSRR characteristics of a regulator circuit. [Figure 7] 10 shows another example of a regulator circuit configuration. [Figure 8] 1 shows an example of a circuit device including a regulator circuit and an example of an oscillator including the circuit device. [Figure 9]1 shows an example of the configuration of a PLL circuit, which is an example of a clock signal generation circuit. DETAILED DESCRIPTION OF THE INVENTION

[0009] The present embodiment will be described below. Note that the present embodiment described below does not unduly limit the content of the claims. Furthermore, not all of the configurations described in the present embodiment are necessarily essential components.

[0010] 1. Regulator circuit FIG. 1 shows an example configuration of a regulator circuit 30 according to this embodiment. The regulator circuit 30 includes an output transistor TRQ, an operational amplifier OP, and a low-pass filter circuit 40. The regulator circuit 30 may also include a feedback circuit 50. The regulator circuit 30 is a circuit that steps down a power supply voltage VDD to generate a regulated voltage VREG. The regulator circuit 30 is not limited to the configuration shown in FIG. 1, and various modifications are possible, such as omitting some of the components, adding other components, or replacing some of the components with other components.

[0011] The output transistor TRQ is, for example, an N-type transistor, specifically an N-type MOS (Metal Oxide Semiconductor) transistor. The N-type output transistor TRQ is provided between a first power supply node ND and an output node NQ of a regulated voltage VREG. The first power supply node ND is a node to which VDD is supplied, for example, a high-potential power supply node. The output node NQ is a node from which the regulated voltage VREG is output. For example, the drain of the output transistor TRQ is connected to the first power supply node ND, and the source is connected to the output node NQ of the regulated voltage VREG. A drive voltage VD is input to the gate of the output transistor TRQ. The drive voltage VD is a voltage obtained by filtering the output voltage VQ of the operational amplifier OP by a low-pass filter circuit 40. In this way, the output transistor TRQ is a source-follower-connected N-type transistor, and the regulated voltage VREG changes to follow the drive voltage VD. For example, if the drive voltage VD rises, the regulated voltage VREG also rises, and if the drive voltage VD falls, the regulated voltage VREG also falls.

[0012] In this embodiment, the output transistor TRQ is, for example, a depletion-type N-type transistor with a negative threshold voltage, although an enhancement-type N-type transistor with a positive threshold voltage may also be used.

[0013] The operational amplifier OP receives a reference voltage VRF at its first input terminal and a feedback voltage VFB based on the regulated voltage VREG at its second input terminal. The first input terminal is, for example, a non-inverting input terminal of the operational amplifier OP, and the second input terminal is, for example, an inverting input terminal of the operational amplifier OP. The reference voltage VRF input to the first input terminal of the operational amplifier OP is generated by a reference voltage generation circuit (not shown). The reference voltage generation circuit is realized by, for example, a bandgap reference circuit. The feedback voltage VFB input to the second input terminal of the operational amplifier OP is generated by a feedback circuit 50. In this way, the operational amplifier OP operating as an error amplifier receives the reference voltage VRF at its first input terminal and the feedback voltage VFB at its second input terminal, and outputs an output voltage VQ at its output terminal.

[0014] The low-pass filter circuit 40 is a circuit that performs low-pass filtering on the output voltage VQ of the operational amplifier OP. For example, the low-pass filter circuit 40 filters the output voltage VQ of the operational amplifier OP to output a drive voltage VD to the gate of the output transistor TRQ. The low-pass filter circuit 40 includes a resistor RF and a MOS capacitor CM. In this way, the low-pass filter circuit 40 is an RC filter configured by the resistor RF and the MOS capacitor CM.

[0015] The resistor RF is provided between the output terminal of the operational amplifier OP and the gate of the output transistor TRQ. For example, one end of the resistor RF is connected to a node N1 of the output terminal of the operational amplifier OP, and the other end is connected to a node N2 of the gate of the output transistor TRQ.

[0016] The MOS capacitor CM is a capacitor composed of a MOS (Metal Oxide Semiconductor) transistor, and the capacitance of the MOS capacitor CM is the gate capacitance of the MOS transistor. The MOS capacitor CM is provided between the gate of the output transistor TRQ and a second power supply node NS. For example, the gate of the transistor constituting the MOS capacitor CM is connected to node N1 of the gate of the output transistor TRQ, and the source and drain are connected to the second power supply node NS. The second power supply node NS is a node to which, for example, VSS is supplied, and is, for example, a power supply node on the low potential side. VSS can also be referred to as GND, which is ground. The second power supply node NS may be a power supply node other than VSS, as long as it is a node of a predetermined potential.

[0017] The feedback circuit 50 is provided between an output node NQ of the regulated voltage VREG and a second power supply node NS, and outputs a feedback voltage VFB. The feedback circuit 50 is, for example, a voltage divider circuit, and outputs a voltage obtained by voltage-dividing the regulated voltage VREG as the feedback voltage VFB. For example, the feedback circuit 50 includes a ladder resistor circuit having a plurality of resistors connected in series between the output node NQ and the second power supply node NS, and outputs the voltage of a given voltage-divided node of the ladder resistor circuit as the feedback voltage VFB.

[0018] In this embodiment, the low-pass filter circuit 40 includes a MOS capacitor CM provided between the gate of the output transistor TRQ and a second power supply node NS and configured with a transistor having a lower breakdown voltage than the output transistor TRQ. For example, the output transistor TRQ is a transistor with a first breakdown voltage, while the MOS capacitor CM is configured with a transistor with a second breakdown voltage lower than the first breakdown voltage. The first breakdown voltage, which is a high breakdown voltage, is, for example, approximately 4V to 7V, and is, for example, approximately 5.5V. The second breakdown voltage, which is a low breakdown voltage, is, for example, approximately 1.5V to 2V, and is, for example, approximately 1.8V. The breakdown voltage is, for example, the rated voltage of the transistor. For example, the gate oxide film of the transistor configuring the MOS capacitor CM is thinner than the gate oxide film of the output transistor TRQ.

[0019] In this embodiment, in order to reduce noise in the regulated voltage VREG generated by the regulator circuit 30, an RC low-pass filter circuit 40 is provided in the regulator circuit 30. This regulator circuit 30 includes an operational amplifier OP, which is an error amplifier that compares a constant reference voltage VRF with a feedback voltage VFB, the low-pass filter circuit 40 for reducing noise, and an output transistor TRQ, which is, for example, a depletion-type N-type MOSFET, for resistance to external noise.

[0020] In this case, the comparative example uses, for example, an MIM (Metal-Insulator-Metal) capacitor or a MOS capacitor with a breakdown voltage equivalent to the maximum power supply voltage for the RC low-pass filter circuit 40. However, generally, the higher the breakdown voltage, the thicker the gate oxide film of the MOS capacitor becomes, and the smaller the capacitance value per unit area becomes. Therefore, to ensure the required capacitance value, a MOS capacitor with a large size (circuit area) must be prepared. For example, the gate width W and gate length L of the MOS transistor that constitutes the MOS capacitor must be increased, which creates the problem of a larger circuit layout area.

[0021] In this regard, in this embodiment, a low-voltage MOS capacitor CM is used as the capacitor of the low-pass filter circuit 40. Such a low-voltage MOS capacitor CM has a smaller gate oxide film thickness than a high-voltage MOS capacitor, and therefore has a larger capacitance value per unit area. Therefore, even if the size of the MOS transistor that constitutes the MOS capacitor CM is reduced, it is possible to ensure the necessary capacitance value, thereby realizing a reduction in the circuit area of ​​the regulator circuit 30. Therefore, it is possible to achieve both low noise and a small circuit area.

[0022] On the other hand, when such a low-voltage MOS capacitor CM is used, a situation may arise in which a voltage exceeding the withstand voltage of the MOS capacitor CM is applied to the gate of the transistor in the MOS capacitor CM. Therefore, to protect the low-voltage MOS capacitor CM in such a situation, the configuration example in Figure 2 provides an analog switch SW in series with the MOS capacitor CM.

[0023] 2, the low-pass filter circuit 40 includes an analog switch SW disposed between the gate of the output transistor TRQ and the gate of the MOS capacitor CM. For example, one end of the analog switch SW is connected to node N2, which is the gate of the output transistor TRQ, and the other end is connected to node N3, which is the gate of the MOS capacitor CM. The analog switch SW is turned on and off by a control signal CS. The control signal CS is generated, for example, by a control circuit of a circuit device including the regulator circuit 30. For example, in a situation where a voltage exceeding the gate breakdown voltage is applied to the gate of the low-voltage MOS capacitor CM, the control signal CS turns off the analog switch SW. This prevents the high voltage at node N2 from being applied to the gate of the MOS capacitor CM, thereby protecting the MOS capacitor CM.

[0024] For example, the regulator circuit 30 of this embodiment has a normal operation mode and a test mode. In the normal operation mode, a circuit device including the regulator circuit 30 operates normally. In this normal operation mode, the analog switch SW is turned on. This enables an RC low-pass filter circuit 40 consisting of the resistor RF and the MOS capacitor CM, which performs low-pass filtering on the output voltage VQ of the operational amplifier OP, thereby reducing noise in the regulated voltage VREG. The test mode is an inspection mode that is set, for example, during the manufacturing or shipping inspection of a circuit device including the regulator circuit 30. In this test mode, the analog switch SW is turned off. This prevents the MOS capacitor CM from functioning as a capacitor in the low-pass filter circuit 40, but turning the analog switch SW off also blocks the drive voltage VD at node N2 from being transmitted to the gate of the MOS capacitor CM, protecting the MOS capacitor CM from high voltages. The test mode will be described in detail later.

[0025] If it can be guaranteed that there will be no situation in which the withstand voltage of the MOS capacitor CM is exceeded, then such an analog switch SW need not be provided and the configuration of FIG. 1 can be adopted.

[0026] Also, in Figure 2, the analog switch SW is realized by a P-type transistor TRP. For example, the source of the P-type transistor TRP, which is the analog switch SW, is connected to node N2 of the drive voltage VD, and the drain is connected to node N3 of the gate of the MOS capacitor CM. A control signal CS for turning the analog switch SW on or off is input to the gate of the P-type transistor TRP. By using a P-type transistor TRP as the analog switch SW in this way, it is possible to suppress deterioration of the operating point and noise, as well as to suppress deterioration of the phase margin and PSRR (Power Supply Rejection Ratio).

[0027] For example, various configuration examples of analog switch SW are shown in Figure 3. As the analog switch SW, a P-type transistor TRP shown in A1, an N-type transistor TRN shown in A2, or a transmission gate TFG shown in A3 can be used. The transmission gate TFG is composed of a P-type transistor TRP and an N-type transistor TRN connected in parallel.

[0028] 2, for example, if the on-resistance of the analog switch SW increases, the phase margin of the regulator circuit 30 deteriorates. If the phase margin of the regulator circuit 30 deteriorates, the regulated voltage VREG, which is the output voltage of the regulator circuit 30, becomes unstable. In other words, if the phase margin disappears, it takes a long time for the regulated voltage VREG to converge, and it becomes unstable, and in some cases it may even oscillate.

[0029] On the other hand, if the W / L ratio of the analog switch SW transistor is increased to reduce the on-resistance of the analog switch SW, the gate area (L x W) increases, resulting in a larger leakage current flowing to the back gate. If this large amount of leakage current to the back gate draws charge from node N2, which supplies the drive voltage VD, the voltage at node N2 drops, leading to a deterioration in the operating point and increased noise. This means that the output transistor TRQ no longer operates in its saturation region, and the operational amplifier OP does not operate within its proper operating range, resulting in a deterioration in the operating point and increased noise in the regulated voltage VREG.

[0030] If a transmission gate TFG such as that shown in A3 in Figure 3 is used as the analog switch SW, the leakage current will have two paths, increasing the amount of leakage current. Therefore, in order to prevent the operating point and noise from deteriorating due to leakage current, it is desirable to use a P-type or N-type single-channel transistor as the analog switch SW, as shown in A1 and A2.

[0031] Furthermore, shorting the transistor's back gate to its source reduces leakage current. This reduces the leakage current flowing from the drive voltage VD node N2 to the substrate, thereby reducing the operating point and noise degradation caused by leakage current. In this case, if a P-type substrate is used as the substrate on which the transistors are formed, a triple-well structure is required to connect the back gate of the N-type transistor TRN (A2 in Figure 3) to a source other than the power supply. For example, without a triple-well structure, leakage current flows from the N-type impurity region of the drain of the N-type transistor TRN to the P-type substrate set to VSS. However, such a triple-well structure increases the circuit area and manufacturing costs. Therefore, it is desirable to use a P-type transistor TRP (A1 in Figure 3) as the analog switch SW. It is also desirable to connect the back gate of the P-type transistor TRP to its source (A4 in Figure 3).

[0032] In this way, by using a P-type transistor TRP or an N-type transistor TRN as shown in A1 or A2 as the analog switch SW, rather than a transmission gate TFG as shown in A3 in FIG. 3, the leakage current path is limited to one point, the leakage current can be reduced, and deterioration of the operating point and noise caused by the leakage current can be suppressed.

[0033] Furthermore, by using a P-type transistor TRP as shown in A1 of FIG. 3 as the analog switch SW, leakage current can be prevented from flowing to the substrate via the backgate, even without using a triple-well structure. For example, as shown in A4 of FIG. 3, the backgate of the P-type transistor TRP is connected to the source. For example, the backgate of the P-type transistor TRP is connected to node N2, which is the source node of the P-type transistor TRP. This reduces the leakage current of the P-type transistor TRP and suppresses fluctuations in the drive voltage VD due to the leakage current. This makes it possible to suppress deterioration of the operating point and noise of the regulator circuit 30 caused by fluctuations in the drive voltage VD. Note that, for example, when a triple-well structure is adopted or the substrate polarity is different, a modification using an N-type transistor TRN as the analog switch SW is also possible. In this case, the backgate of the N-type transistor TRN can be connected to the source, for example.

[0034] FIG. 4 shows an example of the configuration of a feedback circuit 50. The feedback circuit 50 includes a ladder resistor circuit 52 and a selection circuit 54. The ladder resistor circuit 52 includes multiple resistors R1 to Rn connected in series between the node of the regulated voltage VREG and the node of the VSS. The selection circuit 54 selects one of multiple divided voltages from multiple voltage division nodes (resistance division nodes) formed by the multiple resistors R1 to Rn of the ladder resistor circuit 52 and outputs the selected voltage as the feedback voltage VFB. For example, as shown in FIG. 4, the selection circuit 54 includes multiple selectors, and outputs the divided voltage selected by these selectors in a tournament fashion as the feedback voltage VFB. Control signals for these selectors are output by a control circuit of the circuit device. For example, in the ladder resistor circuit 52, let RA be the resistance value from the voltage division node of the divided voltage selected by the selection circuit 54 to the VSS node, and RB be the resistance value from the node of the regulated voltage VREG to the voltage division node. The regulated voltage can then be expressed as VREG = VRF × {(RA + RB) / RB}. As will be described later, in test mode, the regulator circuit 30 outputs a regulated voltage VREG for test mode that is higher than the regulated voltage VREG for normal operation mode. For example, the regulator circuit 30 outputs a regulated voltage VREG of, for example, 1.5 V in normal operation mode, and outputs a regulated voltage VREG of, for example, 3 V or 2.5 V in test mode. This voltage of 3 V or 2.5 V is higher than the withstand voltage of, for example, the MOS capacitor CM. The feedback circuit 50 in FIG. 4 is configured to output the regulated voltage VREG for normal operation mode in normal operation mode and the regulated voltage VREG for test mode in test mode, by controlling the switching of the selector in the selection circuit 54.

[0035] In this embodiment, a small circuit area is achieved by using a low-voltage MOS capacitor CM in the low-pass filter circuit 40 of the regulator circuit 30. In this case, the drive voltage VD of the node of the gate of the output transistor TRQ is expressed by the following equation (1):

[0036]

number

[0037] In other words, because the N-type output transistor TRQ is connected in a source-follower configuration, the drive voltage VD is the voltage obtained by adding the regulated voltage VREG to the gate-source voltage VGS of the output transistor TRQ. The gate-source voltage VGS of the output transistor TRQ is expressed as the following equation (2), using the equation for a MOS transistor in the saturation region.

[0038]

number

[0039] In the above equation (2), ID is the drain current flowing through the output transistor TRQ, and μ is the carrier movement amount of the output transistor TRQ. C is the gate oxide capacitance of the output transistor TRQ, and VTH is the threshold voltage of the output transistor TRQ. W and L are the gate width and gate length of the output transistor TRQ. Therefore, the drive voltage VD is expressed as the following equation (3) based on the above equations (1) and (2).

[0040]

number

[0041] For example, if a depletion-type N-type transistor is used as the output transistor TRQ, the threshold voltage VTH will be a negative voltage. Therefore, if VREG = 1.5V and VTH = -0.4V, then from the above equation (3), the drive voltage VD at node N2 will be a voltage that gradually increases from approximately 1.5V - 0.4V = 1.1V according to the current ID flowing through the load.

[0042] For example, as a comparative example to this embodiment, there is a method of using a P-type transistor as the output transistor TRQ, but in this comparative example, the drive voltage VD of node N2 becomes close to VDD, which is the high-potential power supply voltage, so that a low-voltage MOS capacitor CM cannot be used in the low-pass filter circuit 40, and the circuit area increases.

[0043] In this embodiment, since a source-follower-connected N-type transistor is used as the output transistor TRQ, the drive voltage VD is the sum of the regulated voltage VREG and the gate-source voltage VGS, as shown in equation (1) above. Therefore, compared to the case where a P-type transistor is used as in the comparative example, the drive voltage VD can be set to a lower voltage. This allows the use of a low-voltage MOS capacitor CM, thereby achieving a smaller circuit area. In particular, if a depletion-mode N-type transistor is used as the output transistor TRQ, the threshold voltage VTH becomes a negative voltage. Therefore, as is clear from equation (3) above, the drive voltage VD can be further lowered compared to the case where an enhancement-mode N-type transistor is used, making it easier to use a low-voltage MOS capacitor CM in the low-pass filter circuit 40.

[0044] In this embodiment, the regulator circuit 30 has a test mode in addition to a normal operation mode in which the circuit device operates normally. For example, in the normal operation mode, the regulated voltage VREG is set to, for example, 1.5 V, but in the test mode, which is a mode for inspection, the regulated voltage VREG is set to, for example, 3 V or 2.5 V. For this test mode, an analog switch SW as shown in FIG. 2 is provided, and in the test mode, the analog switch SW is turned off to prevent a high voltage from being applied to the gate of the low-voltage MOS capacitor.

[0045] For example, the regulated voltage VREG from the regulator circuit 30 is supplied to each circuit of the circuit device, and these circuits operate using the regulated voltage VREG as their power supply voltage. These circuits are composed of low-voltage transistors to enable high-speed operation and low power consumption. Therefore, to eliminate initial defects and improve reliability, a test is performed by applying a voltage such as 3V to the low-voltage transistors of these circuits. Such an application test, typically referred to as a screening test, is a test to eliminate initial defects. Because a long application test can cause product degradation, and a short application can overlook defective products, test conditions such as voltage and temperature are set for each product. For example, in this embodiment, a 3V application test is performed, but the application is not long enough to cause quality degradation or destruction, but is set to ensure that initial defects are properly eliminated. In this case, in addition to applying a 3V voltage, a high temperature of, for example, 100°C or higher is set to maximize the load current, and the load is applied at maximum operation. Therefore, the drive voltage VD at node N2 may exceed the allowable voltage of 3V. For this reason, in this embodiment, an analog switch SW is provided in the low-pass filter circuit 40, and the analog switch SW is turned off during testing to prevent a voltage of 3 V or more from being applied to the low-voltage MOS capacitor CM. The 2.5 V application mode is used in reliability testing.

[0046] Figure 5 shows an example of the characteristics of the current ID flowing through the output transistor TRQ and the drive voltage VD. B1 in Figure 5 shows an example of the characteristics when the regulated voltage VREG is 1.5V and the power supply voltage VDD is 5.5V. B2 shows an example of the characteristics when the regulated voltage VREG is 1.5V and the power supply voltage VDD is 2.25V. B3 shows the voltage characteristics when the regulated voltage VREG is 3V and the power supply voltage VDD is 5.5V. As shown in equation (3) above, the drive voltage VD gradually increases in response to the current ID, which is the load current of the circuit to which the regulated voltage VREG is supplied, from the output transistor TRQ. The load current of the circuit to which the regulated voltage VREG is supplied is known from the design stage. Therefore, in B1 and B2 in Figure 5, the W / L of the output transistor TRQ in equation (3) above is set so that the withstand voltage of the MOS capacitor CM is not exceeded even when this load current reaches its maximum. This prevents a voltage exceeding the breakdown voltage of the low-voltage MOS capacitor CM from being applied when the analog switch SW is turned on in the normal operation mode.

[0047] On the other hand, in test mode, the drive voltage VD exceeds 3V (as shown by B3 in Figure 5), causing the voltage applied to the gate of the MOS capacitor CM to exceed the tolerance range for screening tests. Therefore, Figure 2 includes an analog switch SW. By turning off the analog switch SW in test mode, this voltage exceeding the tolerance range is prevented from being applied to the low-voltage MOS capacitor CM. This prevents the application of a voltage exceeding the MOS capacitor CM's tolerance while achieving higher speeds and lower power consumption in the circuit supplied with the regulated voltage VREG. Furthermore, using a low-voltage MOS capacitor CM allows for a smaller circuit area than using a high-voltage MOS capacitor. For example, a high-voltage MOS capacitor has a gate area of ​​7μm x 900μm (L = 7μm, W = 900μm), while a low-voltage MOS capacitor CM has a gate area of ​​4μm x 600μm (L = 4μm, W = 600μm). The film thickness of the low-voltage MOS capacitor CM is, for example, about 1 / 3 to 1 / 4 of the film thickness of the high-voltage MOS capacitor. Therefore, even if the gate area of ​​the low-voltage MOS capacitor is reduced to 4 μm × 600 μm, which is about 40% of that of the high-voltage MOS capacitor, the capacitance required for low-pass filtering of the low-pass filter circuit 40 can be ensured. This makes it possible to achieve both low noise in the regulated voltage VREG and a small circuit area.

[0048] For example, let the regulated voltage be VREG, the gate-source voltage of the output transistor TRQ be VGS, the breakdown voltage of the MOS capacitor CM be VMOS, and the breakdown voltage of the analog switch SW be VSW. In this case, in the normal operation mode of the regulator circuit 30, the analog switch SW is turned on. And the relationship VREG + VGS < VMOS holds. For example, in B1 and B2 of FIG. 5, the drive voltage VD = VREG + VGS is smaller than the breakdown voltage VMOS of the MOS capacitor CM. Thereby, it is possible to prevent a voltage exceeding the breakdown voltage from being applied to the gate of the MOS capacitor CM. On the other hand, in the test mode, the analog switch SW is turned off. And the relationship VMOS < VREG + VGS < VSW holds. For example, in B3 of FIG. 5, VD = VREG + VGS is larger than the breakdown voltage VMOS of the MOS capacitor CM, but since the analog switch SW is turned off, it is possible to prevent a voltage exceeding the breakdown voltage from being applied to the gate of the MOS capacitor CM. And the drive voltage VD = VREG + VGS is smaller than the breakdown voltage VSW of the analog switch SW. Therefore, it is possible to prevent a voltage exceeding the breakdown voltage from being applied to the analog switch SW.

[0049] Also, when such an analog switch SW is provided, in the normal operation mode, the characteristics of the regulator circuit 30 may deteriorate due to the leakage current and on-resistance of the analog switch SW. In this regard, in FIG. 2, a P-type transistor TRP is used as the analog switch SW. By using such a P-type transistor TRP, the leakage current can be reduced, and the deterioration of the operating point, noise, and PSRR can be suppressed. For example, C1 in FIG. 6 is an example of the PSRR characteristics when the P-type transistor TRP in A1 and A4 of FIG. 3 is used as the analog switch SW, and C2 in FIG. 6 is an example of the PSRR characteristics when the transmission gate TFG in A3 of FIG. 3 is used. As shown in FIG. 6, when a P-type transistor TRP is used as the analog switch SW, the characteristics regarding PSRR are better, for example, on the high-frequency side of 10 MHz or more.

[0050] FIG. 7 shows another example of the configuration of the regulator circuit 30. In FIG. 7, a phase compensation capacitor CC is further provided in the low-pass filter circuit 40. For example, the low-pass filter circuit 40 includes a phase compensation capacitor CC provided in parallel with the MOS capacitor CM between the gate of the output transistor TRQ and the second power supply node NS of VSS. For example, one end of the phase compensation capacitor CC is connected to a node N2 of the drive voltage VD, and the other end is connected to the second power supply node NS. The phase compensation capacitor CC is a capacitor with a high breakdown voltage. For example, the breakdown voltage of the phase compensation capacitor CC is higher than the breakdown voltage of the MOS capacitor CM.

[0051] The phase compensation capacitor CC can be, for example, a metal-insulator-metal (MIM) capacitor or a high-voltage MOS capacitor. For example, in modes such as a test mode in which the analog switch SW is turned off, the analog switch SW is turned off, disconnecting the MOS capacitor CM from the node N2, potentially resulting in a loss of phase margin. In this regard, by providing a phase compensation capacitor CC between the node N2 and the second power supply node NS as shown in Figure 7, the phase compensation capacitor CC can be used to ensure phase margin in modes such as a test mode in which the drive voltage VD is high. Furthermore, because the withstand voltage of the phase compensation capacitor CC is higher than that of the MOS capacitor CM, even if the drive voltage VD at the node N2 becomes high in a test mode, a voltage exceeding the withstand voltage is prevented from being applied to the phase compensation capacitor CC, thereby protecting the phase compensation capacitor CC.

[0052] As described above, the regulator circuit 30 of this embodiment includes an output transistor TRQ, an operational amplifier OP, and a low-pass filter circuit 40, as shown in FIG. 1 . The N-type output transistor TRQ is disposed between a first power supply node ND and an output node NQ of the regulated voltage VREG. The operational amplifier OP receives a reference voltage VRF at its first input terminal and a feedback voltage VFB based on the regulated voltage VREG at its second input terminal. The low-pass filter circuit 40 filters the output voltage VQ of the operational amplifier OP to generate a drive voltage VD, which is output to the gate of the output transistor TRQ. In this embodiment, the low-pass filter circuit 40 includes a MOS capacitor CM disposed between the gate of the output transistor TRQ and the second power supply node NS. The MOS capacitor CM is a low-voltage transistor with a lower breakdown voltage than the high-voltage output transistor TRQ. The low-pass filter circuit 40 reduces noise in the regulated voltage VREG, and the use of a low-voltage MOS capacitor CM as the capacitor of the low-pass filter circuit 40 allows for a smaller circuit area. That is, it is possible to achieve both low noise and a small circuit area. For example, a high-voltage transistor is used for the output transistor TRQ because a high voltage VDD is applied to the drain, etc. On the other hand, because the N-type output transistor TRQ is connected as a source follower, the relationship VD = VREG + VTH holds as shown in the above equation (1), and the drive voltage VD of node N2 can be made lower than when a P-type output transistor is used. Taking advantage of this, in this embodiment, a low-voltage MOS capacitor CM is used as the capacitor of the low-pass filter circuit 40, thereby achieving a smaller circuit area than when a high-voltage MOS capacitor CM is used.

[0053] 2, the low-pass filter circuit 40 also includes an analog switch SW provided between the gate of the output transistor TRQ and the gate of the MOS capacitor CM. By providing such an analog switch SW, even in a situation where the drive voltage VD at node N2 becomes high voltage, the analog switch SW turns off, preventing this high voltage from being applied to the low-voltage MOS capacitor CM. This improves the reliability of the regulator circuit 30.

[0054] In this case, the analog switch SW is, for example, a P-type transistor TRP, as shown at A1 and A4 in FIG. 3. For example, instead of an N-type transistor TRN or a transmission gate TFG, a P-type transistor TRP is used as the analog switch SW. This makes it possible to prevent the operating point and noise of the regulator circuit 30 from deteriorating, as well as the PSRR and other characteristics, due to leakage current and the like in the analog switch SW. For example, in the transmission gate TFG, leakage current occurs through two paths, increasing the leakage current, but using a single-channel transistor such as a P-type transistor TRP can reduce the leakage current.

[0055] Furthermore, as shown by A4 in Figure 3, the back gate of the P-type transistor TRP is connected to the source. This configuration reduces the leakage current in the analog switch SW. For example, it reduces the leakage current that flows from the node N2 of the drive voltage VD to the substrate. This makes it possible to prevent the performance of the regulator circuit 30 from deteriorating due to the leakage current.

[0056] Also, the regulator circuit 30 has a normal operation mode and a test mode. The analog switch SW is turned on in the normal operation mode and turned off in the test mode. By doing so, it becomes possible to achieve both low noise of the regulated voltage VREG and protection of the low breakdown voltage MOS capacitor CM. For example, when the analog switch SW is turned on in the normal operation mode, the node N2 of the drive voltage VD and the MOS capacitor CM are electrically connected, and an RC low-pass filter circuit 40 composed of the resistor RF and the MOS capacitor CM is realized. Thereby, low noise of the regulated voltage VREG can be achieved. On the other hand, when the analog switch SW is turned off in the test mode, the connection between the node N2 of the drive voltage VD and the MOS capacitor CM is electrically interrupted. Thereby, even in a situation where the node N2 of the drive voltage VD becomes a high voltage, the high voltage can be prevented from being applied to the MOS capacitor CM, and the MOS capacitor CM can be protected.

[0057] Also, assume that the regulated voltage is VREG, the gate-source voltage of the output transistor TRQ is VGS, the breakdown voltage of the MOS capacitor CM is VMOS, and the breakdown voltage of the analog switch is VSW. In this case, in the normal operation mode, the analog switch SW is turned on and VREG + VGS < VMOS is satisfied. Also, in the test mode, the analog switch is turned off and VMOS < VREG + VGS < VSW is satisfied. Thus, in the normal operation mode where the analog switch SW is turned on, since the drive voltage VD = VREG + VGS is smaller than the breakdown voltage VMOS of the MOS capacitor CM, it is possible to prevent a voltage exceeding the breakdown voltage from being applied to the gate of the MOS capacitor CM, and the MOS capacitor CM can be protected. Also, in the test mode, when the analog switch SW is turned off, application of a high voltage to the MOS capacitor CM is prevented, and since VMOS < VREG + VGS < VSW holds, it is possible to prevent a drive voltage VD = VREG + VGS exceeding the breakdown voltage VSW from being applied to the analog switch SW.

[0058] The low-pass filter circuit 40 also includes a phase compensation capacitor CC that is connected in parallel to the MOS capacitor CM between the gate of the output transistor TRQ and the second power supply node NS. In this way, even when the drive voltage VD becomes high and the analog switch SW is turned off, cutting off the electrical connection between the node N2 of the drive voltage VD and the MOS capacitor CM, it is possible to ensure a phase margin using the phase compensation capacitor CC.

[0059] Furthermore, the breakdown voltage of the phase compensation capacitor CC is set higher than that of the MOS capacitor CM, so that even if the drive voltage VD at node N2 becomes high, a voltage exceeding the breakdown voltage is prevented from being applied to the phase compensation capacitor CC, thereby protecting the phase compensation capacitor CC.

[0060] The low-pass filter circuit 40 also includes a resistor RF provided between the output terminal of the operational amplifier OP and the gate of the output transistor TRQ. By providing such a resistor RF, an RC low-pass filter circuit 40 can be realized using the resistor RF and the MOS capacitor CM, thereby achieving low noise in the regulated voltage VREG.

[0061] The regulator circuit 30 also includes a feedback circuit 50 that is provided between the output node NQ of the regulated voltage VREG and the second power supply node NS and outputs a feedback voltage VFB. In this configuration, the operational amplifier OP compares the feedback voltage VFB with the reference voltage VRF and controls the gate of the output transistor TRQ, for example, so that the feedback voltage VFB approaches the reference voltage VRF. This allows the regulator circuit 30 to output the regulated voltage VREG at the desired voltage.

[0062] Furthermore, the operational amplifier OP is constructed using transistors with a higher breakdown voltage than the MOS capacitor CM, so that even if the drive voltage VD at node N2 becomes high, the breakdown voltage of the operational amplifier OP is prevented from being exceeded, making it possible to protect the operational amplifier OP.

[0063] 2. Circuit devices, oscillators 8 shows a configuration example of a circuit device 20 of this embodiment and an oscillator 4 including the circuit device 20. The circuit device 20 includes the regulator circuit 30 of this embodiment. For example, the circuit device 20 includes a power supply circuit 140, and the regulator circuit 30 is provided in the power supply circuit 140. The oscillator 4 of this embodiment also includes the circuit device 20 and a resonator 10. For example, in FIG. 8, the resonator 10 is electrically connected to the circuit device 20. For example, the resonator 10 and the circuit device 20 are electrically connected using internal wiring, bonding wires, metal bumps, or the like of a package that houses the resonator 10 and the circuit device 20.

[0064] The vibrator 10 is an element that generates mechanical vibrations in response to an electrical signal. The vibrator 10 can be realized by a vibrating piece such as a quartz crystal vibrating piece. For example, the vibrator 10 can be realized by a quartz crystal vibrating piece that vibrates in a thickness-shear mode, such as an AT-cut or SC-cut cut angle, a tuning-fork type quartz crystal vibrating piece, or a double-ended tuning-fork type quartz crystal vibrating piece. For example, the vibrator 10 may be a vibrator built into an SPXO (Simple Packaged Crystal Oscillator), a vibrator built into a temperature-compensated crystal oscillator (TCXO) that does not have a thermostatic oven, or a vibrator built into an oven-controlled crystal oscillator (OCXO) that has a thermostatic oven. Note that the vibrator 10 of this embodiment can also be realized by various vibrating pieces, such as a vibrating piece other than a thickness-shear type, tuning-fork type, or double-ended tuning-fork type, or a piezoelectric vibrating piece made of a material other than quartz. For example, as the vibrator 10, a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro Electro Mechanical Systems) vibrator as a silicon vibrator formed using a silicon substrate can be used.

[0065] The circuit device 20 includes an oscillator circuit 130, a power supply circuit 140, a clock signal generating circuit 150, a control circuit 160, and an output circuit 180. Each pad, which is a terminal of the circuit device 20, is electrically connected to an external connection terminal of the oscillator 4. For example, the VDD, GND, and CKQ pads are electrically connected to the corresponding external connection terminals. Note that the circuit device 20 is not limited to the configuration shown in FIG. 8, and various modifications are possible, such as omitting some of its components, adding other components, or replacing the components with other types of components.

[0066] The oscillator circuit 130 is a circuit that oscillates the resonator 10. For example, the oscillator circuit 130 generates an oscillation signal by oscillating the resonator 10. For example, the oscillator circuit 130 can be realized by an oscillation drive circuit electrically connected to one end and the other end of the resonator 10, and passive elements such as capacitors and resistors. The drive circuit can be realized by, for example, a CMOS inverter circuit or a bipolar transistor. The drive circuit is the core circuit of the oscillator circuit 130, and the drive circuit drives the resonator 10 with voltage or current, causing it to oscillate. Various types of oscillator circuits, such as inverter type, Pierce type, Colpitts type, or Hartley type, can be used as the oscillator circuit 130. Note that the connection in this embodiment is an electrical connection. An electrical connection is a connection that allows an electrical signal to be transmitted, and is a connection that enables information to be transmitted by the electrical signal. The electrical connection may be a connection via a passive element, etc.

[0067] The power supply circuit 140 receives the power supply voltages VDD and VSS (GND) and generates various power supply voltages for the internal circuits of the circuit device 20, supplying them to each circuit. For example, the power supply circuit 140 generates various regulated voltages by stepping down the power supply voltage VDD and supplies them to each circuit of the circuit device 20. The power supply circuit 140 also includes a reference voltage generation circuit, such as a bandgap reference circuit, which generates the reference voltage VRF described with reference to FIGS. 1 and 2 . The power supply circuit 140 also includes a regulator circuit 30, which supplies a regulated voltage VREG to, for example, the clock signal generation circuit 150. The power supply circuit 140 may also include regulator circuits other than the regulator circuit 30, which may generate regulated voltages that serve as power supply voltages for, for example, the oscillator circuit 130 and the control circuit 160.

[0068] The clock signal generation circuit 150 generates a clock signal CK based on the oscillation clock signal OSCK from the oscillation circuit 130. For example, the clock signal generation circuit 150 generates the clock signal CK using the oscillation clock signal OSCK as a reference clock signal. The clock signal CK is, for example, a clock signal with a frequency obtained by multiplying the frequency of the oscillation clock signal OSCK. The clock signal CK is, for example, a clock signal phase-synchronized with the oscillation clock signal OSCK. In this way, the clock signal generation circuit 150 can generate the clock signal CK based on the oscillation clock signal OSCK with high frequency accuracy from the oscillation circuit 130. The circuit device 20 and the oscillator 4 can then output an output clock signal CKQ based on this clock signal CK.

[0069] Specifically, the clock signal generation circuit 150 operates based on the regulated voltage VREG from the regulator circuit 30 and generates a clock signal CK having a frequency that is a multiple of the frequency of the oscillation clock signal OSCK. For example, the clock signal generation circuit 150 operates using the regulated voltage VREG as a power supply voltage and generates a clock signal CK based on the oscillation clock signal OSCK. For example, a circuit such as a voltage-controlled oscillator circuit of the clock signal generation circuit 150 operates using the regulated voltage VREG as a power supply voltage. In this manner, the clock signal generation circuit 150 operates based on the low-noise regulated voltage VREG generated by the regulator circuit 30 of this embodiment and can generate the clock signal CK. This allows the clock signal generation circuit 150 to generate a low-noise clock signal CK, thereby enabling the clock signal generation circuit 150 to generate a clock signal CK with reduced phase jitter, for example.

[0070] The clock signal generation circuit 150 also includes a circuit configured with transistors having a lower breakdown voltage than the output transistor TRQ of the regulator circuit 30 and operating based on the regulated voltage VREG. For example, circuits such as the voltage-controlled oscillator circuit of the clock signal generation circuit 150 are configured with transistors having a lower breakdown voltage than the output transistor TRQ. For example, the output transistor TRQ is a transistor with a first breakdown voltage, while the circuit of the clock signal generation circuit 150 is configured with transistors having a second breakdown voltage that is lower than the first breakdown voltage. In this way, circuits in the clock signal generation circuit 150 that operate when supplied with the regulated voltage VREG are configured with transistors having a low breakdown voltage, thereby enabling, for example, high-speed operation and reducing power consumption. Furthermore, since the circuit of the clock signal generation circuit 150 operates based on the low-noise regulated voltage VREG, noise in the generated clock signal CK can also be reduced.

[0071] The control circuit 160 is a logic circuit that performs various control processes and arithmetic processes. For example, the control circuit 160 controls the entire circuit device 20 and the operation sequence of the circuit device 20. The control circuit 160 also performs various processes for controlling the oscillation circuit 130. The control circuit 160 can be realized, for example, by an ASIC (Application Specific Integrated Circuit) circuit that uses automatic placement and routing, such as a gate array. The control circuit 160 may also perform temperature compensation processing. For example, the control circuit 160 performs temperature compensation processing based on the temperature detection result of a temperature sensor. This makes it possible to realize an oscillator 4 such as a TCXO. In this case, a variable capacitance circuit whose capacitance is controlled based on the result of the temperature compensation processing may be provided in the oscillation circuit 130.

[0072] The output circuit 180 buffers the clock signal CK from the clock signal generation circuit 150 and outputs the output clock signal CKQ. This output clock signal CKQ becomes the external output clock signal of the oscillator 4. The output circuit 180 also outputs the output clock signal CKQ when, for example, an output enable signal is active. This output enable signal can be input from the outside via an external connection terminal, for example.

[0073] 9 shows an example of the configuration of a PLL circuit 152, which is an example of a clock signal generation circuit 150. The PLL circuit 152 includes a phase comparison circuit 153, a charge pump circuit 154, a loop filter circuit 155, a voltage controlled oscillation circuit 156, and a frequency divider circuit 157. The charge pump circuit 154 and the loop filter circuit 155 form a control voltage generation circuit. Note that the PLL circuit 152 is not limited to this configuration, and various modifications are possible, such as omitting some of the components, adding other components, or replacing some of the components with other components.

[0074] The phase comparator circuit 153 performs a phase comparison between the reference clock signal RFCK and the feedback clock signal FBCK. The reference clock signal RFCK is, for example, an oscillation clock signal OSCK. For example, the phase comparator circuit 153 compares the phases of the reference clock signal RFCK and the feedback clock signal FBCK and outputs a signal corresponding to the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK as a phase comparison result signal. For example, an up signal or a down signal is output as the phase comparison result signal. The charge pump circuit 154 performs a charge pump operation based on the phase comparison result signal from the phase comparator circuit 153, and the loop filter circuit 155 filters the output signal QCP of the charge pump circuit 154. This generates a control voltage VC that controls the oscillation of the voltage-controlled oscillator circuit 156. The voltage-controlled oscillator circuit 156, which is a VCO (Voltage Controlled Oscillator), generates a clock signal CK with a frequency corresponding to the control voltage VC. For example, the voltage-controlled oscillator circuit 156 oscillates based on the control voltage VC to generate the clock signal CK. For example, the voltage-controlled oscillator circuit 156 may be an LC oscillator circuit using an inductor.

[0075] The frequency divider circuit 157 divides the clock signal CK and outputs a feedback clock signal FBCK. For example, the frequency divider circuit 157 divides the frequency of the clock signal CK by a division ratio set by a division ratio setting value, and outputs the resulting signal as the feedback clock signal FBCK. Note that the frequency divider circuit 157 may be realized as a fractional frequency division circuit by using, for example, digital sigma modulation. For example, if the oscillation frequency of the voltage-controlled oscillator circuit 156 is fVCO and the division ratio of the frequency division operation of the frequency divider circuit 157 is DIV, the frequency of the feedback clock signal FBCK will be fVCO / DIV. The phase comparator circuit 153 compares the phase of the reference clock signal RFCK with that of the feedback clock signal FBCK from the frequency divider circuit 157.

[0076] For example, the PLL circuit 152 in FIG. 9 uses an LC oscillator circuit or the like as the voltage-controlled oscillator circuit 156 to generate a clock signal CK with a high frequency of, for example, 1 GHz or more. Because the voltage-controlled oscillator circuit 156 and other circuits of the PLL circuit 152 must operate at high frequencies, they are configured with low-voltage transistors capable of high-speed operation. Therefore, the regulator circuit 30 generates a regulated voltage VREG by stepping down the power supply voltage VDD, and circuits such as the voltage-controlled oscillator circuit 156 of the PLL circuit 152 operate using the regulated voltage VREG, which is lower than VDD, as their power supply voltage. Meanwhile, during test mode, for example, a voltage exceeding the breakdown voltage of a low-voltage transistor may be applied to each circuit of the PLL circuit 152 for a screening test or the like. In this case, the drive voltage VD also becomes high, and this high voltage is input to the gate of the MOS capacitor CM. In this case, for example, an analog switch SW is provided in FIGS. 2 and 7, and by turning off the analog switch SW in test mode, a situation in which a high voltage is applied to the gate of the MOS capacitor CM is prevented.

[0077] As described above, the regulator circuit of this embodiment includes an N-type output transistor provided between a first power supply node and an output node for a regulated voltage, an operational amplifier having a first input terminal to which a reference voltage is input and a second input terminal to which a feedback voltage based on the regulated voltage is input, and a low-pass filter circuit that outputs a drive voltage obtained by filtering the output voltage of the operational amplifier to the gate of the output transistor. The low-pass filter circuit includes a MOS capacitor provided between the gate of the output transistor and the second power supply node, and configured by a transistor with a lower withstand voltage than the output transistor.

[0078] In this way, the provision of a low-pass filter circuit can reduce noise in the regulated voltage, and by using a MOS capacitor with a low breakdown voltage as the capacitor for the low-pass filter circuit, the circuit area can be made smaller.

[0079] In this embodiment, the low-pass filter circuit may also include an analog switch provided between the gate of the output transistor and the gate of the MOS capacitor.

[0080] By providing such an analog switch, even in a situation where the drive voltage node is at a high voltage, the analog switch will be turned off, preventing a situation in which a high voltage is applied to the MOS capacitor.

[0081] In this embodiment, the analog switch may be a P-type transistor.

[0082] This makes it possible to prevent the performance of the regulator circuit from deteriorating due to leakage current in the analog switch or the like.

[0083] In this embodiment, the back gate of the P-type transistor may be connected to the source.

[0084] In this way, the leakage current in the analog switch can be reduced, and deterioration of the performance of the regulator circuit due to the leakage current can be suppressed.

[0085] In this embodiment, the regulator circuit may have a normal operation mode and a test mode, and the analog switch may be turned on in the normal operation mode and turned off in the test mode.

[0086] In this way, it is possible to achieve both low noise in the regulated voltage in the normal operation mode and protection of the MOS capacitor in the test mode.

[0087] Also, in this embodiment, the regulator circuit has a normal operation mode and a test mode. Let the regulated voltage be VREG, the gate-source voltage of the output transistor be VGS, the breakdown voltage of the MOS capacitor be VMOS, and the breakdown voltage of the analog switch be VSW. At this time, in the normal operation mode, the analog switch is turned on, and VREG + VGS < VMOS is satisfied. In the test mode, the analog switch is turned off, and VMOS < VREG + VGS < VSW may be satisfied.

[0088] In this way, in the normal operation mode, the driving voltage is smaller than the breakdown voltage of the MOS capacitor, so the MOS capacitor can be protected. Also, in the test mode, when the analog switch is turned off, the application of a high voltage to the MOS capacitor is prevented, and the application of a driving voltage exceeding the breakdown voltage to the analog switch can also be prevented.

[0089] Also, in this embodiment, the low-pass filter circuit may include a capacitor for phase compensation provided in parallel with the MOS capacitor between the gate of the output transistor and the second power supply node.

[0090] In this way, even when the analog switch is turned off and the electrical connection between the driving voltage node and the MOS capacitor is interrupted, it becomes possible to ensure the phase margin and the like using the capacitor for phase compensation.

[0091] Also, in this embodiment, the breakdown voltage of the capacitor for phase compensation may be higher than the breakdown voltage of the MOS capacitor.

[0092] [ [ In this way, even when the driving voltage node becomes a high voltage, it becomes possible to prevent a voltage exceeding the breakdown voltage from being applied to the capacitor for phase compensation.

[0093] Also, in this embodiment, the low-pass filter circuit may include a resistor provided between the output terminal of the operational amplifier and the gate of the output transistor.

[0094] By providing such a resistor, it becomes possible to realize an RC low-pass filter circuit using a resistor and a MOS capacitor.

[0095] In addition, this embodiment may include a feedback circuit that is provided between the output node of the regulated voltage and the second power supply node and outputs a feedback voltage.

[0096] In this way, the operational amplifier compares the reference voltage with the feedback voltage and controls the gate of the output transistor so that the feedback voltage approaches the reference voltage, thereby making it possible to output a regulated voltage of the desired voltage.

[0097] In this embodiment, the operational amplifier may be configured with a transistor having a higher withstand voltage than the withstand voltage of the MOS capacitor.

[0098] In this way, even if the drive voltage node becomes a high voltage, the voltage will not exceed the breakdown voltage of the operational amplifier, making it possible to protect the operational amplifier.

[0099] This embodiment also relates to a circuit device including a power supply circuit including the regulator circuit described above, an oscillation circuit that causes an oscillator to oscillate, and a clock signal generation circuit that generates a clock signal based on an oscillation clock signal from the oscillation circuit.

[0100] This allows the clock signal generation circuit to generate a clock signal based on the oscillation clock signal with high frequency accuracy from the oscillation circuit.

[0101] In this embodiment, the clock signal generating circuit may operate based on a regulated voltage from a regulator circuit, and generate a clock signal having a frequency that is a multiple of the frequency of the oscillation clock signal.

[0102] In this way, the clock signal generating circuit operates based on the low-noise regulated voltage generated by the regulator circuit, and can generate a clock signal.

[0103] In this embodiment, the clock signal generating circuit may include a circuit that is configured with a transistor having a lower breakdown voltage than the breakdown voltage of the output transistor and operates based on a regulated voltage.

[0104] In this way, the circuits in the clock signal generating circuit that operate when supplied with a regulated voltage can be configured using transistors with low withstand voltages, which enables, for example, high-speed operation and reduced power consumption.

[0105] The present embodiment also relates to an oscillator including the circuit device described above and a resonator.

[0106] Although the present embodiment has been described in detail above, those skilled in the art will readily understand that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader or equivalent meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also included within the scope of the present disclosure. Furthermore, the configurations and operations of the regulator circuit, circuit device, and oscillator are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0107] 4...oscillator, 10...resonator, 20...circuit device, 30...regulator circuit, 40...low-pass filter circuit, 50...feedback circuit, 52...ladder resistor circuit, 54...selection circuit, 130...oscillation circuit, 140...power supply circuit, 150...clock signal generation circuit, 152...PLL circuit, 153...phase comparison circuit, 154...charge pump circuit, 155...loop filter circuit, 156...voltage controlled oscillator circuit, 157...frequency divider circuit, 160...control circuit, 180...output circuit, CC...capacitor for phase compensation, CK...clock signal, CKQ...output clock Signal, CM...MOS capacitor, CS...control signal, FBCK...feedback clock signal, ND...first power supply node, NQ...output node, NS...second power supply node, OP...operational amplifier, OSCK...oscillation clock signal, RF...resistor, RFCK...reference clock signal, SW...analog switch, TFG...transmission gate, TRN, TRP...transistor, TRQ...output transistor, VD...drive voltage, VFB...feedback voltage, VMOS, VSW...breakdown voltage, VQ...output voltage, VREG...regulated voltage, VRF...reference voltage

Claims

1. an N-type output transistor provided between a first power supply node and an output node of a regulated voltage; an operational amplifier having a first input terminal to which a reference voltage is input and a second input terminal to which a feedback voltage based on the regulated voltage is input; a low-pass filter circuit that filters the output voltage of the operational amplifier to output a driving voltage to the gate of the output transistor; Including, The low-pass filter circuit a MOS capacitor provided between the gate of the output transistor and a second power supply node, the MOS capacitor being configured by a transistor having a lower breakdown voltage than the output transistor;

2. 2. The regulator circuit according to claim 1, The low-pass filter circuit a regulator circuit including an analog switch provided between the gate of the output transistor and the gate of the MOS capacitor;

3. 3. The regulator circuit according to claim 2, The regulator circuit is characterized in that the analog switch is a P-type transistor.

4. 4. The regulator circuit according to claim 3, A regulator circuit, wherein the back gate of the P-type transistor is connected to the source.

5. 3. The regulator circuit according to claim 2, It has a normal operation mode and a test mode, The regulator circuit is characterized in that the analog switch is turned on in the normal operation mode and turned off in the test mode.

6. 3. The regulator circuit according to claim 2, It has a normal operation mode and a test mode, When the regulated voltage is VREG, the gate-source voltage of the output transistor is VGS, the withstand voltage of the MOS capacitor is VMOS, and the withstand voltage of the analog switch is VSW, In the normal operation mode, the analog switch is turned on and VREG+VGS<VMOS is satisfied; In the test mode, the analog switch is turned off and VMOS<VREG+VGS<VSW is satisfied.

7. 2. The regulator circuit according to claim 1, The low-pass filter circuit a phase compensation capacitor provided in parallel with the MOS capacitor between the gate of the output transistor and the second power supply node;

8. 8. The regulator circuit according to claim 7, The regulator circuit is characterized in that the withstand voltage of the phase compensation capacitor is higher than the withstand voltage of the MOS capacitor.

9. 2. The regulator circuit according to claim 1, The low-pass filter circuit A regulator circuit comprising a resistor provided between the output terminal of the operational amplifier and the gate of the output transistor.

10. 2. The regulator circuit according to claim 1, a feedback circuit provided between the output node of the regulated voltage and the second power supply node, the feedback circuit outputting the feedback voltage;

11. 2. The regulator circuit according to claim 1, 10. A regulator circuit, wherein the operational amplifier is configured with a transistor having a withstand voltage higher than that of the MOS capacitor.

12. a power supply circuit including the regulator circuit according to any one of claims 1 to 11; an oscillation circuit that causes the oscillator to oscillate; a clock signal generating circuit that generates a clock signal based on the oscillation clock signal from the oscillation circuit; A circuit device comprising:

13. 13. The circuit arrangement according to claim 12, The clock signal generating circuit A circuit device that operates based on the regulated voltage from the regulator circuit and generates a clock signal having a frequency that is multiplied by the frequency of the oscillation clock signal.

14. 13. The circuit arrangement according to claim 12, The clock signal generating circuit A circuit device comprising a circuit configured with a transistor having a breakdown voltage lower than that of the output transistor, the circuit operating based on the regulated voltage.

15. a circuit arrangement according to claim 12; The vibrator; An oscillator comprising:

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