Member for semiconductor manufacturing apparatus

Abstract

To provide a member for semiconductor manufacturing apparatus with improved cooling capacity for wafers.SOLUTION: In a member for semiconductor manufacturing apparatus having a ceramic substrate with an upper surface and a lower surface capable of supporting a wafer and incorporating electrodes, and a cooling plate with an upper surface and a lower surface, and an internal refrigerant flow path, the lower surface of the ceramic substrate and the upper surface of the cooling plate are bonded via an amorphous layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a member for a semiconductor manufacturing device. [Background technology]

[0002] Conventionally, semiconductor manufacturing equipment components have been known that are used for wafer holding, temperature control, transport, etc. These types of semiconductor manufacturing equipment components are also called wafer mounting tables, electrostatic chucks, susceptors, etc., and generally have the function of applying electrostatic attraction power to a built-in electrode to attract a wafer by electrostatic force.

[0003] The semiconductor manufacturing equipment component includes, for example, a ceramic substrate having an upper surface on which a wafer can be placed and a lower surface and incorporating electrodes, and a cooling plate located on the lower surface side of the ceramic substrate and incorporating a refrigerant flow path. In such a semiconductor manufacturing equipment component, when a refrigerant flows through the refrigerant flow path, heat from the wafer is absorbed by the refrigerant flowing through the refrigerant flow path through the ceramic substrate, thereby cooling the wafer placed on the upper surface of the ceramic substrate.

[0004] Thermal Compression Bonding (TCB), for example, is known as a method for bonding a ceramic substrate and a cooling plate (Patent Document 1). TCB is a known method in which a metal bonding material is sandwiched between two components to be bonded, and the two components are pressure-bonded while heated to a temperature below the solidus temperature of the metal bonding material. Another known method is to bond a ceramic substrate and a cooling plate using a resin adhesive, such as a silicone resin adhesive, an epoxy resin adhesive, or an acrylic resin adhesive (Patent Document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2023-70861 [Patent Document 2] Patent No. 7356620 Summary of the Invention [Problem to be solved by the invention]

[0006] However, with conventional methods using TCB or resin-based adhesives, the bonding layer formed between the ceramic substrate and the cooling plate tends to become thick. As the bonding layer becomes thicker, the heat transfer efficiency decreases, making it more difficult for the wafer's heat to be transferred to the refrigerant flowing through the cooling plate's coolant channels, resulting in a problem of reduced cooling capacity. With TCB, the bonding layer is made of metal, so cooling efficiency is higher than when using resin-based adhesives, but a metal bonding material must be sandwiched between the two to form the bonding layer. This means there is a limit to how thin the bonding layer can be. Furthermore, with TCB, the bonding layer is formed by sandwiching a metal bonding material and heating it at high temperatures, which tends to increase manufacturing costs.

[0007] In view of the above circumstances, an object of one embodiment of the present invention is to provide a semiconductor manufacturing equipment member having improved cooling capacity for wafers. [Means for solving the problem]

[0008] The present inventors have conducted extensive research to solve the above problems and have created the present invention, which is exemplified below.

[0009] [Aspect 1] A semiconductor manufacturing equipment component comprising: a ceramic substrate having upper and lower surfaces on which a wafer can be placed and incorporating electrodes; and a cooling plate having upper and lower surfaces and incorporating a refrigerant flow path, the lower surface of the ceramic substrate and the upper surface of the cooling plate are joined via an amorphous layer; Components for semiconductor manufacturing equipment. [Aspect 2] 2. The semiconductor manufacturing equipment member according to aspect 1, wherein the amorphous layer contains at least one element constituting the ceramic substrate and at least one element constituting the cooling plate. [Aspect 3] 3. A semiconductor manufacturing equipment member according to claim 1, wherein the side surfaces of the ceramic substrate and the cooling plate have portions covered with a continuous corrosion-resistant material, including the outer periphery of the amorphous layer that forms the boundary between the ceramic substrate and the cooling plate. [Aspect 4] A semiconductor manufacturing equipment member according to any one of aspects 1 to 3, having one or more selected from a flow path defined by a recess provided on the lower surface of the ceramic substrate and the upper surface of the cooling plate, a flow path defined by a recess provided on the upper surface of the cooling plate and the lower surface of the ceramic substrate, and a flow path defined by a recess provided on the lower surface of the ceramic substrate and a recess provided on the upper surface of the cooling plate. [Aspect 5] The thermal resistance between the ceramic substrate and the cooling plate is 7000m 2 5. A member for a semiconductor manufacturing equipment according to any one of aspects 1 to 4, wherein the elongation coefficient is 0.05K / W or less. [Aspect 6] When the linear expansion coefficient of the material constituting the ceramic substrate measured in accordance with JIS Z2285:2003 during a temperature change from room temperature to 550°C is C1 ( / K), and when the linear expansion coefficient of the material constituting the cooling plate measured in accordance with JIS Z2285:2003 during a temperature change from room temperature to 550°C is C2 ( / K), 0≦|C1-C2|≦5×10 -6 6. A member for a semiconductor manufacturing equipment according to any one of Aspects 1 to 5, wherein the above holds true. [Aspect 7] 7. A semiconductor manufacturing equipment member according to any one of Aspects 1 to 6, wherein the cooling plate is made of one or more materials selected from the group consisting of metals, ceramics, and metal-ceramic composites. [Aspect 8] A semiconductor manufacturing equipment member according to any one of Aspects 1 to 7, wherein the ceramic substrate contains aluminum oxide, and the cooling plate contains one or more selected from the group consisting of Ti, Mo, and W. [Aspect 9] 9. A member for a semiconductor manufacturing equipment according to any one of aspects 1 to 8, wherein the bonding strength between the ceramic substrate and the cooling plate is 50 MPa or more. [Effects of the Invention]

[0010] According to one embodiment of the present invention, a semiconductor manufacturing equipment component is provided that has improved cooling capacity for wafers. This allows wafers to be cooled quickly to a desired temperature, making the semiconductor manufacturing equipment component suitable for use, for example, when performing rapid and complex temperature control on wafers. Furthermore, the amount of cooling fluid required to achieve the same cooling capacity can be reduced, contributing to energy conservation. Furthermore, because the semiconductor manufacturing equipment component does not require the formation of a bonding layer through high-temperature heating, it can be manufactured at low manufacturing costs. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a schematic longitudinal cross-sectional view of a semiconductor manufacturing equipment member according to one embodiment of the present invention (a cross-sectional view taken along a plane including the central axis of the semiconductor manufacturing equipment member 10). [Figure 2] 1A to 1C are diagrams showing a manufacturing process of a semiconductor manufacturing equipment member according to an embodiment of the present invention. [Figure 3] FIG. 1 is a schematic perspective view of a polishing apparatus for performing lapping. [Figure 4] FIG. 1 is an explanatory diagram of a shear peel test device. DETAILED DESCRIPTION OF THE INVENTION

[0012] Next, embodiments of the present invention will be described in detail with reference to the drawings. It should be understood that the present invention is not limited to the following embodiments, and that appropriate design changes, improvements, and the like may be made based on the common knowledge of those skilled in the art without departing from the spirit of the present invention. Furthermore, in this specification, "upper" and "lower" are used for convenience to represent the relative positional relationship when the semiconductor manufacturing equipment component is placed on a horizontal surface with the cooling plate facing downward, and do not represent absolute positional relationships. Therefore, depending on the orientation of the semiconductor manufacturing equipment component, "upper" and "lower" may become "lower" and "upper," "left" and "right," or "front" and "rear."

[0013] <1. Composition of semiconductor manufacturing equipment components> 1, a semiconductor manufacturing equipment member 10 according to one embodiment of the present invention can be used when performing processes such as CVD and etching on a wafer W using plasma, and can be fixed to a mounting plate provided inside a semiconductor process chamber. The semiconductor manufacturing equipment member 10 includes a ceramic substrate 20 having an upper surface 21 on which the wafer W can be placed, and a lower surface 23, and incorporating an electrode 26. The semiconductor manufacturing equipment member 10 also includes a cooling plate 30 located on the lower surface 23 of the ceramic substrate 20, and incorporating a refrigerant flow path 32.

[0014] The ceramic substrate 20 includes a central portion 20a having a circular upper surface 21 in a planar view, and an outer peripheral portion 20b having an annular upper surface 27 in a planar view around the central portion 20a. A wafer W can be placed on the upper surface 21, and a focus ring 78 can be placed on the upper surface 27. The ceramic substrate 20 can be formed from a ceramic material such as alumina or aluminum nitride. The upper surface 27 of the outer peripheral portion 20b is one step lower than the upper surface 21 of the central portion 20a. The central portion 20a and the lower surface 23 of the outer peripheral portion 20b may be flush with each other. The ceramic substrate 20 may have the central portion 20a but not the outer peripheral portion 20b, i.e., it may not have the one-step lower upper surface 27.

[0015] In the embodiment shown in FIG. 1 , the focus ring 78 and the wafer W are flush with each other on the top surface, but the top surface of the focus ring 78 may be located higher than the wafer W. In the embodiment shown in FIG. 1 , the outer diameter of the focus ring 78 and the outer diameter of the outer peripheral portion 20b of the ceramic substrate 20 are the same, but the two outer diameters do not have to be the same. The focus ring 78 may have a step along the inner periphery of its upper end to prevent interference with the wafer W.

[0016] The upper surface 21 of the central portion 20a is provided with a plurality of protrusions 22 for placing the wafer W thereon. A seal band 25 may also be formed along the outer edge of the upper surface 21. In this case, the wafer W may be supported by the upper end surface 21c of the seal band 25 and the upper end surfaces 21a of the plurality of protrusions 22. It is preferable that the seal band 25 and the plurality of protrusions 22 have the same height. In one embodiment, a ring-shaped seal band 25 is formed along the outer edge of the upper surface 21 of the ceramic substrate 20, and a plurality of protrusions 22 are formed over the entire inner surface of the seal band 25.

[0017] The shape of the protrusions 22 is not limited, but may be, for example, a columnar shape such as a cylinder or a rectangular pillar. The height h of the protrusions 22 is, for example, 5 to 100 μm, and typically 10 to 30 μm. The circle-equivalent diameter of the protrusions 22 in a plan view may be 100 μm to 3000 μm. Note that the portion of the upper surface 21 of the central portion 20a of the ceramic substrate 20 on which the seal band 25 and the protrusions 22 are not provided is referred to as the reference surface 21b.

[0018] The central portion 20a of the ceramic substrate 20 may have a diameter of 190 to 450 mm and a thickness of 1 to 5 mm, for example. The electrode 26 is a planar electrode used as an electrostatic electrode and is connected to an external DC power supply via a power supply member (not shown). The electrode 26 is formed of a material containing, for example, W, Mo, WC, or MoC. A low-pass filter may be disposed midway along the power supply member. The power supply member is electrically insulated from the cooling plate 30. When a DC voltage is applied to the electrode 26, the wafer W is attracted and fixed to the wafer mounting surface, specifically, the upper end surface 21c of the seal band 25 and the upper end surface 21a of the protrusions 22, by electrostatic attraction. When the application of the DC voltage is stopped, the wafer W is released from the wafer mounting surface.

[0019] Instead of or in addition to the electrostatic attraction electrode, the electrode 26 may incorporate a heater electrode (resistance heating element) or an RF electrode for generating plasma. In this case, a heater power supply is connected to the heater electrode, and an RF power supply is connected to the RF electrode. The ceramic substrate 20 may incorporate one layer of the electrode 26, or two or more layers spaced apart. A ring heater may also be installed on the outer periphery 20b of the ceramic substrate 20 (i.e., below the focus ring 78).

[0020] The cooling plate 30 may be, for example, disk-shaped. The cooling plate 30 may have an annular flange portion on the lower surface 33 side, which is used to clamp the semiconductor manufacturing equipment member 10 to a jig inside the chamber. The thickness of the cooling plate 30 may be 5 to 50 mm. The cooling plate 30 may also be used as an RF electrode by connecting it to a radio frequency (RF) power source.

[0021] The cooling plate 30 can be a circular plate (having the same diameter as or larger than the ceramic substrate 20) with good electrical and thermal conductivity. A refrigerant channel 32 through which a refrigerant circulates can be formed inside the cooling plate 30. The refrigerant flowing through the refrigerant channel 32 is preferably a liquid, and more preferably an electrically insulating refrigerant. Examples of electrically insulating liquids include fluorine-based inert liquids. The refrigerant channel 32 can be formed, for example, in a single stroke across the entire cooling plate 30 in a plan view from one end (inlet) to the other end (outlet). To facilitate routing the refrigerant channel 32 across the entire cooling plate 30, the refrigerant channel 32 may be formed in a zigzag or spiral shape in a plan view. Other shapes are also possible. One end and the other end of the refrigerant channel 32 are connected to a supply port and a recovery port of an external refrigerant device (not shown) via refrigerant piping, respectively. The refrigerant supplied to one end of the refrigerant flow path 32 from the supply port of the external refrigerant device passes through the refrigerant flow path 32, returns from the other end of the refrigerant flow path 32 to the recovery port of the external refrigerant device, and after its temperature is adjusted, is supplied again from the supply port to one end of the refrigerant flow path 32.

[0022] The cooling plate 30 can be made of one or more materials selected from, for example, metals, ceramics, and metal-ceramic composites. Examples of metals include Al, Ti, Mo, and alloys thereof. Examples of metal-ceramic composites include metal matrix composites (MMCs) and ceramic matrix composites (CMCs). Specific examples of such composites include materials containing Si, SiC, and Ti (also referred to as SiSiCTi), materials in which porous SiC is impregnated with Al and / or Si, and composites of Al2O3 and TiC. A material in which porous SiC is impregnated with Al is called AlSiC, and a material in which porous SiC is impregnated with Si is called SiSiC.

[0023] It is preferable to select a material for the cooling plate 30 that has a linear expansion coefficient close to that of the material for the ceramic substrate 20. Having similar linear expansion coefficients for both materials reduces the stress applied to the bonding interface during heating, making it possible to suppress a decrease in bonding strength and the occurrence of cracks due to repeated heating and cooling. Specifically, if the linear expansion coefficient of the material constituting the ceramic substrate 20 measured in accordance with JIS Z2285:2003 during a temperature change from room temperature (e.g., 25°C) to 550°C is C1 ( / K), and the linear expansion coefficient of the material constituting the cooling plate 30 measured in accordance with JIS Z2285:2003 during a temperature change from room temperature (e.g., 25°C) to 550°C is C2 ( / K), then 0≦|C1−C2|≦5×10 -6 It is preferable that 0≦|C1-C2|≦3×10 -6 It is more preferable that 0≦|C1−C2|≦1×10 -6 For example, when the ceramic substrate 20 contains aluminum oxide and the cooling plate 30 contains one or more elements selected from Ti, Mo, and W, it is possible to keep |C1-C2| within the above range.

[0024] If it is not possible to obtain ceramic substrate and cooling plate samples of the shape and dimensions required for measurement from semiconductor manufacturing equipment components for measuring the linear expansion coefficient, measurements may be made using samples made of the same material.

[0025] 1, the lower surface 23 of the ceramic substrate 20 and the upper surface 31 of the cooling plate 30 are bonded via an amorphous layer 40. The amorphous layer 40 preferably contains at least one element constituting the ceramic substrate 20 and at least one element constituting the cooling plate 30.

[0026] When a longitudinal cross section of the semiconductor manufacturing equipment component 10 near the interface between the ceramic substrate 20 and the cooling plate 30 is observed with a transmission electron microscope (TEM) at 4,000,000 magnification, the amorphous layer 40 is observed as a thin band-like portion. The amorphous layer 40 may be a single layer or may be formed of multiple layers (e.g., three layers). The average thickness of the amorphous layer 40 is preferably 0.1 nm or more, more preferably 1 nm or more, to enhance the bonding strength between the ceramic substrate 20 and the cooling plate 30. Furthermore, the average thickness of the amorphous layer 40 is preferably 30 nm or less, more preferably 20 nm or less, to prevent the inclusion of different materials. Therefore, the average thickness of the amorphous layer 40 is preferably, for example, 0.1 nm or more to 30 nm or less, more preferably 1 nm or more to 20 nm or less. When the amorphous layer 40 is composed of multiple layers, the thickness of the amorphous layer 40 refers to the total thickness of the multiple layers.

[0027] The average thickness of the amorphous layer 40 is measured by TEM observation using the following procedure. On a TEM photograph (magnification: 4,000,000 times) of one field of view, the thickness of the amorphous layer 40 is measured at five locations at 10 nm intervals along the bonding interface, and the average thickness of the amorphous layer in one field of view is calculated. Similar thickness measurements by TEM observation are performed evenly on five fields of view, including near the center, near the outer periphery, and near the center of the radius when the semiconductor manufacturing equipment member 10 is viewed in plan. The average thickness of the amorphous layer 40 in the five fields of view is then taken as the measured value.

[0028] The fact that the thin band observed by TEM is an amorphous layer 40 can be confirmed by the fact that an unclear halo pattern of diffraction spots is observed inside the thin band when an electron diffraction pattern is obtained by TEM.

[0029] The fact that the amorphous layer 40 contains at least one element constituting the ceramic substrate 20 and at least one element constituting the cooling plate 30 can be confirmed by methods such as EDS (Energy Dispersive X-ray Spectroscopy) and EPMA (Electron Probe Micro Analyzer). In a preferred embodiment, the amorphous layer 40 contains at least one amorphous material constituting the ceramic substrate 20 (e.g., amorphous aluminum nitride, amorphous alumina, etc.) and at least one amorphous material constituting the cooling plate 30 (e.g., amorphous Ti, amorphous Mo, etc.).

[0030] In this way, the semiconductor manufacturing equipment member 10 according to one embodiment of the present invention can make the bonding layer between the ceramic substrate 20 and the cooling plate 30 extremely thin, thereby reducing the thermal resistance between the ceramic substrate 20 and the cooling plate 30. The thermal resistance between the ceramic substrate 20 and the cooling plate 30 can be, for example, 7000 m 2 ·K / W or less is preferable, 5000m 2 ·K / W or less is preferable, and 3000m 2 It is even more preferable that the thermal resistance between the ceramic substrate 20 and the cooling plate 30 is 1×10 K / W or less. -11 m 2 ·K / W or more.

[0031] The thermal resistance between the ceramic substrate 20 and the cooling plate 30 is R(m 2 When the thermal conductivity at room temperature is λ (W / (m K)), the thickness is t (m), and the thermal conductivity at room temperature is λ (W / (m K)), it can be calculated as R=t / λ. Thermal conductivity at room temperature is measured using the flash method specified in JIS R1611:2010.

[0032] The ceramic substrate 20 and the cooling plate 30 are bonded together via the amorphous layer 40 containing at least one element constituting the ceramic substrate 20 and at least one element constituting the cooling plate 30, thereby enabling a strong bond between the two. In one embodiment, the bond strength between the ceramic substrate 20 and the cooling plate 30 can be 50 MPa or more. The bond strength is more preferably 100 MPa or more, and even more preferably 200 MPa or more. There is no particular upper limit set for the bond strength between the ceramic substrate 20 and the cooling plate 30, but it may be 1000 MPa or less, or may be 800 MPa or less.

[0033] The bond strength between ceramic substrate 20 and cooling plate 30 is measured using the following procedure. A square plate 11, measuring 25 mm wide, 35 mm long, and 10 mm thick, made of the same material as ceramic substrate 20, and a square plate 12, made of the same material as cooling plate 30 and having the same dimensions as square plate 11, are vertically offset as shown in Figure 4 and bonded at room temperature under the same bonding conditions as those used in the manufacture of the semiconductor manufacturing equipment components to be measured. The bond area is 25 mm long and 25 mm wide. Using a shear peel tester such as the one shown in Figure 4, square plate 12 is fixed to support 13 with the bottom facing downward. A vertical downward load is applied to the upper square plate 11 to measure the shear peel strength of the bonded assembly at room temperature, which is then used as the bond strength. If a test piece of the same shape as the bonded assembly can be cut from the semiconductor manufacturing equipment component, it can also be used for measurement.

[0034] In a semiconductor manufacturing equipment component 10 according to one embodiment of the present invention, the ceramic substrate 20 and the cooling plate 30 are bonded together by an extremely thin amorphous layer 40. The amorphous layer 40 can be formed, for example, by room-temperature bonding the ceramic substrate 20 and the cooling plate 30. Room-temperature bonding is a method in which the bonding surfaces are activated by irradiating them with a fast atom beam (FAB) without heating, and the bonding is performed with the amorphous layer 40 formed on the surface. This makes it easier to process the bottom surface 23 of the ceramic substrate 20 and the top surface 31 of the cooling plate 30 than with a method in which the two are bonded together using a separate member such as a metal bonding material or a resin-based adhesive. For this reason, for example, the semiconductor manufacturing equipment member 10 according to one embodiment of the present invention may have one or more of the following: a flow path 521 defined by a recess 52a provided on the lower surface 23 of the ceramic substrate 20 and the upper surface 31 of the cooling plate 30; a flow path 522 defined by a recess 52b provided on the upper surface 31 of the cooling plate 30 and the lower surface 23 of the ceramic substrate 20; and a flow path 523 defined by a recess 52a provided on the lower surface 23 of the ceramic substrate 20 and the upper surface 31 of the cooling plate 30. The uses of the flow paths 521, 522, and 523 are not particularly limited, and they may be used, for example, as a flow path for a refrigerant or a gas flow path for a thermally conductive gas such as He. The flow paths 521, 522, and 523 may be formed in a single stroke from one end (inlet) to the other end (outlet). The flow channels 521, 522, and 523 may be formed in a zigzag or spiral shape in a plan view so as to be easily routed over the entire bonding interface between the ceramic substrate 20 and the cooling plate 30. They may also be formed in other shapes.

[0035] Because the amorphous layer 40 is extremely thin, it does not contribute to defining the flow paths 521, 522, and 523. For example, in the illustrated embodiment, regardless of whether the amorphous layer 40 is formed on the lower surface 23 of the ceramic substrate 20 that defines the flow path 522, the lower surface 23 defines the flow path.

[0036] The semiconductor manufacturing equipment member 10 according to the embodiment of FIG. 1 has a gas flow path for supplying a heat transfer gas, such as He gas, to a space on the backside of a wafer W placed on its upper surface 21. The gas flow path may include one or more types selected from a flow path 521 defined by a recess 52a provided on the lower surface 23 of the ceramic substrate 20 and the upper surface 31 of the cooling plate 30, a flow path 522 defined by a recess 52b provided on the upper surface 31 of the cooling plate 30 and the lower surface 23 of the ceramic substrate 20, and a flow path 523 defined by a recess 52a provided on the lower surface 23 of the ceramic substrate 20 and the upper surface 31 of the cooling plate 30. The semiconductor manufacturing equipment member 10 according to the embodiment of FIG. 1 has three types of flow paths, namely, flow path 521, flow path 522, and flow path 523, but may also include only one of these types. Of the three types of flow channels 521, 522, and 523, it is particularly preferable to have flow channel 521 or flow channel 522 for reasons of manufacturing costs.

[0037] The gas flow path may have a flow path 54 that communicates with the flow paths 521, 522, and 523, penetrates the cooling plate 30 from the upper surface 31 to the lower surface 33, and has an opening 53 on the lower surface 33. The gas flow path may also have a flow path 56 that communicates with the flow paths 521, 522, and 523, penetrates the ceramic substrate 20 from the upper surface 21 to the lower surface 23, and has an opening 51 on the upper surface 21. It is preferable that the opening 51 be provided on a portion of the upper surface 21 on which the seal band 25 and the plurality of protrusions 22 are provided, where the seal band 25 and the plurality of protrusions 22 are not provided (reference surface 21b).

[0038] When gas is supplied to the opening 53 of the cooling plate 30, the gas passes through the flow path 54, flow paths 521, 522, 523, and flow path 56, and then flows out of the opening 51 of the ceramic substrate 20, filling the space on the backside of the wafer W placed on the upper surface 21. The presence of this backside gas ensures efficient heat conduction between the wafer W and the ceramic substrate 20. Note that a plug (not shown) having a gas flow path may be embedded in the flow path 56 to suppress discharge, etc. In the illustrated embodiment, the cooling plate 30 has one opening 53. However, multiple openings 53 may be provided, with a gas flow system for each opening 53. Furthermore, the opening 53 may be provided on the side surface 34 of the cooling plate 30, rather than on the lower surface 33.

[0039] Additionally, the semiconductor manufacturing equipment member 10 may have a plurality of lift pin holes for inserting lift pins that move the wafer W up and down relative to the upper surface 21. A plurality of lift pin holes can be provided at equal intervals along concentric circles of the upper surface 21 when the upper surface 21 is viewed in plan view.

[0040] In one embodiment, the side surface 24 of the ceramic substrate 20 and the side surface 34 of the cooling plate 30 have portions that are covered with a continuous corrosion-resistant material 42, including the outer periphery 44 of the amorphous layer 40 that forms the boundary between them. Preferably, the entire side surface 24 (of the outer periphery 20b) of the ceramic substrate 20 and the side surface 34 of the cooling plate 30 are covered with the continuous corrosion-resistant material 42, including the outer periphery 44 of the amorphous layer 40 that forms the boundary between them. Examples of the corrosion-resistant material 42 include alumina and yttria. The corrosion-resistant material 42 is preferably in the form of a thermally sprayed film formed by thermal spraying.

[0041] When the ceramic substrate 20 and the cooling plate 30 are bonded with a resin-based bonding layer, it is difficult to form a thermal sprayed film that spans the cooling plate 30 and the ceramic substrate 20 with the resin-based bonding layer in between because the resin-based bonding layer would be damaged. However, because the amorphous layer 40 can be made of a material that can withstand thermal spraying, it is possible to form a thermal sprayed film that spans the cooling plate 30 and the ceramic substrate 20 with the amorphous layer 40 in between. Therefore, according to one embodiment of the present invention, a semiconductor manufacturing equipment component 10 with excellent corrosion resistance can be provided.

[0042] <2. How to use semiconductor manufacturing equipment parts> Next, an example of how to use the semiconductor manufacturing equipment member 10 will be described. First, the semiconductor manufacturing equipment member 10 is placed in a chamber (not shown). A focus ring 78 is placed on the upper surface 27 of the semiconductor manufacturing equipment member 10, and a disk-shaped wafer W is placed on the upper surface 21. The chamber is then depressurized using a vacuum pump to adjust the pressure to a predetermined vacuum level, and a voltage is applied to the electrodes 26 of the ceramic substrate 20 to generate an electrostatic adsorption force, thereby adsorbing and fixing the wafer W to the wafer mounting surface (specifically, the upper end surfaces 21c of the seal bands 25 and the upper end surfaces 21a of the protrusions 22).

[0043] Next, a process gas is supplied from a shower head (not shown) to create a reactive gas atmosphere at a predetermined pressure (several tens to several hundreds of Pa) inside the chamber. In this state, a high-frequency voltage such as an RF voltage is applied between an upper electrode (not shown) provided on the ceiling inside the chamber and the cooling plate 30 of the semiconductor manufacturing equipment member 10. This generates plasma between the wafer W and the shower head. The plasma is then used to process the wafer W (by performing CVD film formation or etching).

[0044] A refrigerant circulates through the refrigerant flow path 32 of the cooling plate 30. A supply port and a recovery port of an external refrigerant device (not shown) are connected to one end and the other end of the refrigerant flow path 32 via refrigerant piping, respectively. The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 passes through the refrigerant flow path 32, returns from the other end of the refrigerant flow path 32 to the recovery port of the external refrigerant device, has its temperature adjusted, and is then supplied again from the supply port to one end of the refrigerant flow path 32.

[0045] A backside gas can be introduced from a gas cylinder (not shown) through opening 53 of cooling plate 30. A thermally conductive gas (e.g., He gas) can be used as the backside gas. After passing through flow path 54, flow paths 521, 522, 523, and flow path 56, the backside gas flows out from opening 51 of ceramic substrate 20 and fills the space on the back side of wafer W placed on upper surface 21.

[0046] As wafers W are plasma-processed, focus ring 78 also wears out. However, since focus ring 78 is thicker than wafers W, focus ring 78 is replaced after processing multiple wafers W.

[0047] <3. Manufacturing examples of semiconductor manufacturing equipment components> Next, a method for manufacturing the semiconductor manufacturing equipment member 10 will be described with reference to Fig. 2. Fig. 2 is a manufacturing process diagram for the semiconductor manufacturing equipment member 10 according to one embodiment of the present invention. First, a ceramic substrate 20 and a cooling plate 30 are prepared (Fig. 2A).

[0048] The ceramic substrate 20 incorporates an electrode 26. The ceramic substrate 20 can be manufactured by hot-pressing and firing a ceramic molded body incorporating the electrode 26. The ceramic molded body may be manufactured by stacking a plurality of tape molded bodies, by a mold casting method, or by compressing ceramic powder.

[0049] Next, a plurality of protrusions 22 for mounting the wafer W are formed on the upper surface 21 of the ceramic substrate 20, and a seal band 25 is formed along the outer edge of the upper surface 21. A flow path 56 may be formed that penetrates the ceramic substrate 20 from the upper surface 21 to the lower surface 23 and has an opening 51 on the upper surface 21. The flow path 56 is formed to penetrate the ceramic substrate 20 in the vertical direction, avoiding the electrode 26. A recess 52a may be formed on the lower surface 23 of the ceramic substrate 20. Furthermore, the outer periphery may be machined to form an outer periphery 20b. The protrusions 22, seal band 25, flow path 56, recess 52a, and outer periphery 20b can be formed by machining. The ceramic substrate 20 may be machined after the cooling plate 30 is bonded.

[0050] The cooling plate 30 has a refrigerant flow path 32. The cooling plate 30 having the refrigerant flow path 32 can be manufactured, for example, by joining a plurality of MMC plate members, in which grooves and holes corresponding to the refrigerant flow paths 32 have been formed by machining, using a method such as TCB. Alternatively, a flow path 54 may be formed that penetrates the cooling plate 30 from the upper surface 31 to the lower surface 33 and has an opening 53 on the lower surface 33. The flow path 54 can be formed by machining the cooling plate 30 after the refrigerant flow paths 32 have been formed. Furthermore, a recess 52a may be formed on the upper surface 31 of the cooling plate 30.

[0051] Next, the ceramic substrate 20 is subjected to lapping using a polishing apparatus 60 shown in FIG. 3. The polishing apparatus 60 includes a large-diameter disc-shaped polishing platen 62 equipped with a polishing pad 64, a small-diameter disc-shaped carrier 66, and a pipe 68 for supplying a slurry containing abrasive grains to the polishing pad 64. The polishing platen 62 includes a shaft 67 at the center of its lower surface, which is rotated (spins) when driven by a drive motor (not shown). The carrier 66 includes a shaft 69 at the center of its upper surface, which is rotated (spins) when driven by a drive motor (not shown). The carrier 66 is positioned off-center of the polishing platen 62.

[0052] To polish the lower surface 23 of the ceramic substrate 20 using this polishing apparatus 60, the ceramic substrate 20 is mounted on the lower surface of the carrier 66 and sandwiched between the carrier 66 and the polishing pad 64 of the polishing table 62. A slurry containing abrasive grains is then supplied from a pipe 68 to the polishing pad 64. The slurry is then supplied between the ceramic substrate 20 and the polishing pad 64 of the polishing table 62. In this state, the carrier 66 presses the ceramic substrate 20 against the polishing pad 64, while the polishing table 62 and the carrier 66 rotate about their axes to perform polishing. The polishing conditions are set so that the surface roughness (arithmetic mean roughness) Ra of the lower surface 23 of the ceramic substrate 20 is 1 nm or less. The surface roughness (arithmetic mean roughness) Ra of the polished surface is measured using a non-contact surface roughness meter in accordance with ISO 25178.

[0053] The upper surface 31 of the cooling plate 30 is also subjected to lapping using the polishing device 60 in the same manner as the ceramic substrate 20. This makes it possible to make the surface roughness Ra of the upper surface 31 of the cooling plate 30 1 nm or less (for example, 0.2 nm to 1 nm).

[0054] Next, the lower surface 23 of the ceramic substrate 20 after lapping and the upper surface 31 of the cooling plate 30 after lapping are subjected to a surface activation treatment (fast atom beam (FAB) or plasma activation treatment) under high vacuum. The FAB conditions are set, for example, at a voltage of 0.5 to 2 kV, a current of 50 to 200 mA, and an irradiation time of 30 to 300 seconds. This removes oxides and adsorbed molecules from the lower surface 23 of the ceramic substrate 20 and the upper surface 31 of the cooling plate 30, and activates these surfaces by forming an amorphous layer 40 on them. Next, while maintaining the high vacuum condition, the lower surface 23 of the ceramic substrate 20 and the upper surface 31 of the cooling plate 30 are placed face to face and bonded under pressure ( FIG. 2B ). The load during pressing can be set, for example, to 0.1 to 50 kN.

[0055] Thereafter, if necessary, the semiconductor manufacturing equipment component 10 is completed by appropriately performing steps such as forming a sprayed film of corrosion-resistant material 42 that spans the cooling plate 30 and the ceramic substrate 20 with the amorphous layer 40 in between, and adjusting the overall shape. [Explanation of symbols]

[0056] 10: Semiconductor manufacturing equipment components 20: Ceramic substrate 20a: Central section 20b: Outer periphery 21:Top surface 21a: Upper end surface 21b: Reference plane 21c: Upper end surface 22: Protrusion 23: Bottom surface 24: Side 25: Seal band 26: Electrode 27:Top surface 30: Cooling plate 31:Top surface 32: Coolant flow path 33: Bottom surface 34: Side 40: Amorphous layer 42: Corrosion-resistant materials 44: Outer edge 51: Opening 52a: recess 52b: recess 53: Opening 54: Flow path 56: Flow path 60: Polishing equipment 62: Polishing plate 64: Polishing pad 66: Career 67: Shaft 68: Pipe 69: Shaft 78: Focus ring 521: Flow path 522: Flow path 523: Flow path W: Wafer

Claims

1. A semiconductor manufacturing equipment component comprising: a ceramic substrate having upper and lower surfaces on which a wafer can be placed and incorporating electrodes; and a cooling plate having upper and lower surfaces and incorporating a refrigerant flow path, the lower surface of the ceramic substrate and the upper surface of the cooling plate are joined via an amorphous layer; Components for semiconductor manufacturing equipment.

2. 2. The semiconductor manufacturing equipment member according to claim 1, wherein the amorphous layer contains at least one element constituting the ceramic substrate and at least one element constituting the cooling plate.

3. 3. The semiconductor manufacturing equipment member according to claim 1, wherein the side surfaces of the ceramic substrate and the cooling plate have portions covered with a continuous corrosion-resistant material, including the outer periphery of the amorphous layer that forms the boundary between the two.

4. 3. The semiconductor manufacturing equipment component according to claim 1, comprising one or more selected from the group consisting of a flow path defined by a recess provided on the lower surface of the ceramic substrate and the upper surface of the cooling plate, a flow path defined by a recess provided on the upper surface of the cooling plate and the lower surface of the ceramic substrate, and a flow path defined by a recess provided on the lower surface of the ceramic substrate and a recess provided on the upper surface of the cooling plate.

5. The thermal resistance between the ceramic substrate and the cooling plate is 7000m 2 3. The semiconductor manufacturing equipment member according to claim 1, wherein the hardness is 0.05 K / W or less.

6. The linear expansion coefficient of the material constituting the ceramic substrate measured in accordance with JIS Z2285:2003 in a temperature change from room temperature to 550°C is C 1 ( / K), and the linear expansion coefficient of the material constituting the cooling plate measured in accordance with JIS Z2285:2003 in a temperature change from room temperature to 550°C is C 2 ( / K), then 0≦|C 1 -C 2 |≦5×10 -6 3. The semiconductor manufacturing equipment member according to claim 1, wherein the following holds true:

7. 3. The semiconductor manufacturing equipment member according to claim 1, wherein the cooling plate is made of one or more materials selected from the group consisting of metals, ceramics, and metal-ceramic composites.

8. 3. The semiconductor manufacturing equipment member according to claim 1, wherein the ceramic substrate contains aluminum oxide, and the cooling plate contains one or more elements selected from the group consisting of Ti, Mo, and W.

9. 3. The semiconductor manufacturing equipment member according to claim 1, wherein the bonding strength between the ceramic substrate and the cooling plate is 50 MPa or more.

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