Weighting information generation device, and analog-digital conversion device

Abstract

To provide a weighting information generation device capable of generating weighting information to improve integral nonlinearity without using a highly accurate digital-analog converter.SOLUTION: A weighting information generation device 20 includes a voltage generation part 21, 22 for generating predetermined binary voltage, a voltage offset part 21, 23 for applying an offset voltage to a binary voltage generated by the voltage generation part 21, 22 to perform offset, and includes a voltage input part 21, 22, 23, 24 for sequentially inputting the binary voltage that gradually offset in each prescribed voltage to an analog-digital converter 10, and an information generation part 21 for acquiring an output value outputted from the analog-digital converter 10 and corresponding to the binary voltage, and generating weighting information on the basis of the acquired output value.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an analog-to-digital converter equipped with a weighting adjustment unit for correcting conversion accuracy, and in particular to a weighting information generation device that generates weighting information to be applied to the weighting adjustment unit, and an analog-to-digital conversion device equipped with this weighting information generation device and an analog-to-digital converter. [Background technology]

[0002] Traditionally, analog-to-digital converters (ADCs) have required linearity as a correlation between input and output values ​​to ensure conversion accuracy. Linearity is generally measured in terms of both differential nonlinearity (DNL) and integral nonlinearity (INL). Here, differential nonlinearity represents the deviation from the ideal value for each code, while integral nonlinearity represents the integrated value of differential nonlinearity. In particular, integral nonlinearity indicates overall linearity, and when an analog-to-digital converter has gain or offset errors, it often has a step-like inflection point.

[0003] Against this background, a measurement device for measuring integral nonlinearity has been proposed in the past to improve the accuracy of analog-digital converters (see Patent Document 1 below). This measurement device uses an analog-digital converter or a digital-analog converter (DAC) with higher accuracy than the target analog-digital converter, generates a known voltage, inputs that voltage to the target analog-digital converter to calculate differential nonlinearity (DNL), and further calculates integral nonlinearity by changing the voltage value of the digital-analog converter and repeating this multiple times.

[0004] The integral nonlinearity calculated in this way is stored as correction data for the analog-to-digital converter, and the obtained correction data is applied to the analog-to-digital converter during analog-to-digital conversion, thereby making it possible to obtain a corrected output with good linearity. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 11-74789 Summary of the Invention [Problem to be solved by the invention]

[0006] However, conventional measurement devices require a digital-to-analog converter with higher resolution and accuracy than the analog-to-digital converter being measured, which results in high manufacturing costs. Furthermore, the accuracy of the digital-to-analog converter must be maintained, which necessitates the establishment of a correction technique to guarantee the accuracy of the digital-to-analog converter.

[0007] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a weighting information generation device that can generate weighting information for improving the integral nonlinearity of an analog-to-digital converter without using a high-precision, expensive digital-to-analog converter, and an analog-to-digital conversion device that includes this weighting information generation device and an analog-to-digital converter. [Means for solving the problem]

[0008] To solve the above problems, the present invention provides: 1. An information generating device for generating weighting information to be applied to a weighting adjustment unit of an analog-to-digital converter including the weighting adjustment unit, a voltage input unit including a voltage generation unit that generates a predetermined two-value voltage (binary voltage) and a voltage offset unit that multiplies the binary voltage generated by the voltage generation unit by an offset voltage to offset the binary voltage, and that sequentially inputs the binary voltages that have been offset in stages by a predetermined voltage to the analog-to-digital converter; and an information generating unit that acquires an output value corresponding to the binary voltage output from the analog-to-digital converter and generates the weighting information based on the acquired output value.

[0009] According to this weighting information generating device, a voltage input unit generates binary voltages (offset binary voltages) that are offset in stages by a predetermined voltage, and the generated offset binary voltages are input sequentially to an analog-to-digital converter. Then, an information generating unit acquires output values ​​corresponding to the offset binary voltages output from the analog-to-digital converter, and generates weighting information based on the acquired output values.

[0010] According to the findings of the present inventors, in the case of a successive approximation type analog-to-digital converter, for example, the integral nonlinearity of the analog-to-digital converter often exhibits an inflection point near a voltage corresponding to the capacitance of the capacitor that constitutes it, because the integral nonlinearity is affected by the capacitance error of the capacitor that is formed.

[0011] Therefore, by inputting an offset binary voltage, including a voltage corresponding to the capacitance of the configured capacitor, into an analog-to-digital converter and verifying the output value, it is possible to determine whether or not an inflection point exists in the diagram representing the integral nonlinearity, in other words, whether or not the integral nonlinearity is sufficient.

[0012] If an inflection point appears in the integral nonlinearity, weighting information for adjusting the weighting adjustment unit to improve the integral nonlinearity is generated theoretically or empirically based on the relationship between the input value and the output value.

[0013] In this way, the weighting information generation device according to the present invention generates binary offset voltages that are offset in stages by a predetermined voltage and inputs these binary offset voltages to an analog-to-digital converter, thereby making it possible to verify the integral nonlinearity of the analog-to-digital converter and generate weighting information for improving the integral nonlinearity.

[0014] Therefore, compared to the conventional method in which a high-precision, expensive digital-to-analog converter is used, the integral nonlinearity of the analog-to-digital converter can be verified and improved with a cheaper configuration.

[0015] Furthermore, the information generation unit can be configured to generate weighting information such that each output value output from the analog-to-digital converter exhibits the same phase and is a value within a predetermined reference range.

[0016] Furthermore, the voltage input section may be configured such that at least one of the voltage input sections generates the binary voltage having voltages corresponding to 1 / 8, 1 / 4, 3 / 8, 1 / 2, 5 / 8, 3 / 4, and 7 / 8 of the full scale of the analog-to-digital converter as an offset voltage and inputs it to the analog-to-digital converter.

[0017] Furthermore, at least one of the voltage input sections is 2n-(1 / 2) of the full scale of the analog-to-digital conversion device. m The binary voltage having a voltage equivalent to the above may be generated as an offset voltage and input to the analog-to-digital converter. Here, m is the number of bits that is the resolution of the analog-to-digital converter. Furthermore, n is an integer that satisfies the following: n<2 m / 2

[0018] The voltage input unit is configured to sequentially input binary voltages offset by the same offset interval to the analog-to-digital converter, The information generating unit can be configured to acquire an output value corresponding to each binary voltage output from the analog-digital converter, compare one acquired output value with the other output values, and if the difference value exceeds a predetermined reference range or the sign of the difference value is reversed, store the input binary voltage, and then, when the stored input binary voltage is input from the voltage input unit to the analog-digital converter, adjust the weighting adjustment unit of the analog-digital converter so that the difference value between that output value and the other output value falls within the reference range and has the same sign, and generate the state of the weighting adjustment unit at that time as weighting information.

[0019] The present invention also relates to an analog-to-digital conversion device comprising any one of the weighting information generation devices described above and an analog-to-digital converter connected to the weighting information generation device. [Effects of the Invention]

[0020] According to the weighting information generating device of the present invention, by generating binary offset voltages that are offset in stages by a predetermined voltage and inputting these binary offset voltages to an analog-to-digital converter, it is possible to verify the integral nonlinearity of the analog-to-digital converter and generate weighting information for improving the integral nonlinearity. Therefore, compared to the conventional method that uses a high-precision, expensive digital-to-analog converter, it is possible to verify and improve the integral nonlinearity of the analog-to-digital converter with a less expensive configuration. [Brief explanation of the drawings]

[0021] [Figure 1] 1 is a circuit diagram showing a schematic configuration of an analog-to-digital conversion device according to an embodiment of the present invention. [Figure 2] 1 is a circuit diagram showing a schematic configuration of an analog-to-digital converter according to an embodiment of the present invention. [Figure 3] FIG. 2 is a circuit diagram showing a schematic configuration of a weighting adjustment unit according to the present embodiment. [Figure 4]FIG. 10 is an explanatory diagram for explaining a weighting information generation process. [Figure 5] FIG. 10 is an explanatory diagram for explaining a weighting information generation process. [Figure 6] FIG. 10 is an explanatory diagram for explaining a weighting information generation process. [Figure 7] FIG. 10 is an explanatory diagram for explaining a weighting information generation process. [Figure 8] FIG. 10 is an explanatory diagram for explaining a weighting information generation process. [Figure 9] FIG. 10 is a circuit diagram showing an analog-to-digital conversion device according to a modified example. [Figure 10] FIG. 10 is a circuit diagram showing an analog-to-digital conversion device according to a modified example. [Figure 11] FIG. 10 is a circuit diagram showing an analog-to-digital conversion device according to a modified example. [Figure 12] FIG. 10 is a circuit diagram showing an analog-to-digital conversion device according to a modified example. [Figure 13] 1 is an example of a waveform with actual integral nonlinearity. [Figure 14] FIG. 10 is a diagram for explaining the contents of another embodiment. [Figure 15] 10 is a flowchart of a correction process for integral nonlinearity in another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0022] Specific embodiments of the present invention will be described below with reference to the drawings. As shown in Fig. 1, an analog-to-digital conversion device 1 of this embodiment comprises an analog-to-digital converter 10 and a weighting information generation section 20.

[0023] <Analog-to-digital converter> FIG. 2 shows a schematic configuration of an analog-digital converter 10 of this example. This analog-digital converter 10 is a so-called successive approximation type analog-digital converter, and is configured using a weighted capacitor array. In this example, a converter with 12-bit resolution is shown. Reference numeral 11 denotes a comparator, 12 denotes a capacitor array unit, 13 denotes a switch control register, and 14 denotes a successive approximation logic circuit. The capacitor array unit 12 has an internal sample-and-hold function for holding an input voltage, and a circuit (capacitive digital-to-analog conversion circuit) with a digital-to-analog conversion function for generating a comparison voltage. This capacitor array unit 12 is based on the principle of charge redistribution to generate an analog voltage, and includes a plurality of capacitors (13 capacitors in this example) for binary weighting, and a capacitor for the least significant bit (2 0 ) (LSB (Least Significant Bit))) and a capacitor array including a dummy capacitor with the same capacitance as the capacitor corresponding to the LSB, and switches S1 to S 14 It consists of:

[0024] The least significant bit of the capacitor array (2 0 ) (LSB (Least Significant Bit)) is a capacitor with a standard capacitance C, then 2 bits (2 1 ) the capacitance of the capacitor corresponding to 2C (in other words, 2LSB), 3 bits (2 2 ) the capacitance of the capacitor corresponding to the most significant 12 bits (2 11 The capacitance of the capacitor corresponding to the MSB (Most Significant Bit) is set to 2048C (in other words, 2048LSB). However, the resolution is not limited to 12 bits, and any other suitable resolution can be used.

[0025] The switch control register 13 controls the switches S1 to S2 provided in the capacitance array unit 12. 14The control unit switches the connections of the switches S1 to S2 based on the processing result of the successive approximation logic circuit 14. 14 The successive approximation logic circuit 14 is a logic circuit that executes a search process in accordance with a binary search algorithm based on the output of the comparator 11.

[0026] In this analog-to-digital converter 10, first, the switches S1 to S2 of the capacitance array section 12 are 14 Connect S1 to the GRAND side to ground, and discharge the charge of each capacitor to 0. Next, with S1 still connected to the GRAND side, turn on switches S2 to S 14 V IN side, and apply the input voltage V IN After this, the switch S1 is disconnected from the GRAND side, and the switches S2 to S 14 is connected to the GRAND side. As a result, the potential of each capacitor connected to the negative side of the comparator 11 becomes -V IN Next, according to the search process of the successive approximation logic circuit 14 based on the output of the comparator 11, S corresponding to the most significant bit is 14 Then, the switches S corresponding to the lower bits are 13 ~S3 is the reference side V REF The capacitors corresponding to the higher bits are connected to the appropriate side, and a reference voltage V is applied to the capacitors according to the sequential binary search algorithm. REF is applied, and the input voltage V IN and the reference voltage V REF is compared by the comparator 11 to obtain the input voltage V IN and the reference voltage V REF When these become equal, the switch control register 13 outputs a digital signal of the input voltage.

[0027] Incidentally, in a position detection device (encoder) that uses two or more periodic signals with different phases, the ratio at which the two signals are added is changed to generate multiple phase signals, which are then binarized and added together to obtain a resolution several tens of times the period of the original periodic signals, thereby increasing the resolution of the encoder.

[0028] Recently, with the progress of increasing resolution, a method is becoming mainstream in which multiple periodic signals are converted into digital values ​​using an analog-to-digital converter, and then the phase angle is calculated using an arctangent function from the ratio of the amplitude values ​​of the periodic signals, and the difference in this phase angle for each sample is accumulated to obtain a resolution several hundred times greater than the original periodic signal period, thereby determining a highly accurate position.However, if the integral nonlinearity error (INL) of the analog-to-digital converter is large, distortion occurs in the periodic signal obtained from the analog-to-digital converter, which causes a problem of degraded division accuracy within one period of the periodic signal.

[0029] The causes of integral nonlinearity errors vary depending on the configuration of the analog-digital converter, but as mentioned above, the successive approximation type analog-digital converter of this example is configured so that the capacitance of the capacitors in capacitance array section 12 increases in powers of 2, from 1C, 2C, 4C, ... 1024C, 2048C, and so on. Therefore, when the capacitance of the capacitors formed as devices in the electronic circuit increases, the capacitance accuracy of the formed capacitors has a significantly larger error than the capacitance accuracy of the capacitor with the smallest capacitance. Therefore, in the case of high-resolution analog-digital converters, it is difficult to improve the accuracy of integral nonlinearity.

[0030] Therefore, in the past, as shown in FIG. 3, each capacitance section (capacitor) of the capacitance array section 12 was provided with a weighting adjustment section 15 for correcting the capacitance, and the integral nonlinearity of the analog-to-digital converter 10 was improved by appropriately setting the correction capacitance provided in the weighting adjustment section 15 based on the measurement results of the integral nonlinearity error (INL) of the analog-to-digital converter 10 so that the integral nonlinearity would have ideal linearity.

[0031] 3 has capacitors with capacitances of 0.5C, C, 2C, and 4C connected in parallel to a capacitor with a capacitance of 2044C, and by selectively enabling these capacitors, it is possible to correct (adjust) the capacitance of the capacitor array section 12 in the range of 2044.0C to 2051.5C. This weight adjustment section 15 is provided for capacitors with large capacitances that are prone to large errors, and in the capacitance array section 12 shown in FIG. 2, it is provided for capacitors corresponding to, for example, 1024C (=1024LSB), 2048C (=2048LSB), and 512C (=512LSB). However, the present invention is not limited to these.

[0032] However, as mentioned above, measuring integral nonlinearity requires a digital-to-analog converter (DAC), which is a highly accurate voltage generating means, and it is necessary to use this highly accurate digital-to-analog converter to finely set the voltage and repeatedly capture the output value from the digital-to-analog converter, making it difficult to achieve, including in terms of cost. Therefore, this embodiment provides a weighting information generating device 20 that generates weighting information for correcting integral nonlinearity using inexpensive means without using a highly accurate digital-to-analog converter, and under conditions where the number of measurement points is significantly reduced, as well as an analog-to-digital conversion device 1 that is composed of this weighting information generating unit 20 and an analog-to-digital converter 10.

[0033] <Considerations underlying the generation of weighting information> As described above, in the successive approximation type analog-to-digital converter 10 illustrated in this example, the capacitance of each capacitor in the capacitance array section 12 is set to 2 n times, and in the case of 12 bits in this example, there is a capacitance difference of 2048 times between the capacitance of the capacitor corresponding to the LSB and the capacitance of the capacitor corresponding to the MSB.

[0034] The capacitance setting error of each capacitor appears in integral nonlinearity, and when there is an error in the capacitance of the capacitor corresponding to the most significant bit, for example, an inflection point appears around 2048 LSB, which is full scale. When there is an error in the capacitance of the capacitor corresponding to the bit below that, an inflection point appears approximately every 1024 LSB. When there is an error in the capacitance of the capacitor corresponding to the bit below that, an inflection point appears approximately every 512 LSB. Here, LSB is the quantization unit and means the voltage corresponding to the least significant bit.

[0035] The capacitor with the smallest capacitance corresponding to the LSB has a smaller error rate than other capacitors, and the impact of this capacitance error on integral nonlinearity is small. On the other hand, in the case of a capacitor with a large capacitance, the impact of that capacitance error on integral nonlinearity is large. Therefore, for the part corresponding to a relatively large LSB, the integral nonlinearity can be improved by detecting the inflection point of the integral nonlinearity and correcting the capacitance according to the value of that inflection point.

[0036] Here, the relationship between the input voltage and the output voltage will be considered for several cases where the integral nonlinearity has no inflection point and where it has an inflection point.

[0037] First, as shown in FIG. 4(a), in the ideal case where the integral nonlinearity (INL) has no inflection point, i.e., when INL<1, the relationship between the input analog voltage and the output data is a straight line as shown in FIG. 4(b). Then, an arbitrary binary voltage, i.e., a pulsed voltage that forms a rectangular wave, is generated, and this reference binary voltage is multiplied by an offset voltage to generate binary voltages (offset binary voltages) that are offset in steps and at equal intervals by a predetermined voltage, and these are input to the analog-to-digital converter 10 having the characteristics described above. FIG. 4(C) shows the relationship between the input offset binary voltage and the output data from the analog-to-digital converter 10. That is, in FIG. 4(C), three magnitudes (three levels) of offset binary voltages V that are offset at equal intervals are generated. A , V B , V Care input to the analog-to-digital converter 10, and the differences A, B, and C of the corresponding three output data are the same value, that is, A=B=C.

[0038] Next, when the integral nonlinearity exhibits a "sawtooth" pattern that rises to the right, as shown in Figure 5(a), in other words, when the integral nonlinearity suddenly changes in the negative direction, the relationship between the input analog voltage and the output data will be as shown in Figure 5(b). Note that Figure 5(a) shows the integral nonlinearity when the capacitor corresponding to the full-scale of 2048 LSB has a capacitance error that is greater than the setting. As shown in Figure 5(a), the integral nonlinearity has an inflection point where the input voltage corresponds to 2048 LSB. Similarly, in the diagram showing the relationship between the input voltage and the output data, an inflection point appears where the input voltage corresponds to 2048 LSB (Figure 5(b)).

[0039] When several (for example, three) offset binary voltages are input to the analog-to-digital converter 10 having such characteristics, the relationship between the input analog voltage and the output data is as shown in FIG. 5(C). That is, in FIG. 5(C), three offset binary voltages V A , V B , V C is input to the analog-to-digital converter 10, but the intermediate voltage V B is the voltage corresponding to 2048LSB (the voltage corresponding to the inflection point), the voltage before and after this inflection point V A , V C The output data corresponding to these signals will have the same phase, and the differences A and C will be the same value. That is, A=C. On the other hand, the voltage V at the inflection point B The output data corresponding to this signal has an inverted phase with the output data before and after it, and the difference B is a different, smaller value than the differences A and C before and after it. That is, A=C>B.

[0040] Furthermore, when the integral nonlinearity exhibits a downward-sloping "sawtooth" curve as shown in Figure 6(a), in other words, when the integral nonlinearity suddenly changes in the positive direction, the relationship between the input analog voltage and the output data will be as shown in Figure 6(b). Note that Figure 6(a) shows the integral nonlinearity when the capacitor corresponding to the full-scale 2048 LSB has a capacitance error that is smaller than the setting. In this case, as shown in Figure 6(a), the integral nonlinearity has an inflection point where the input voltage corresponds to 2048 LSB. Similarly, in the diagram showing the relationship between the input voltage and the output data, an inflection point appears where the input voltage corresponds to 2048 LSB (Figure 6(b)).

[0041] When several (for example, three) offset binary voltages are input to the analog-to-digital converter 10 having such characteristics, as described above, the relationship between the input analog voltage and the output data is as shown in Fig. 6(C). That is, in Fig. 6(C), three offset binary voltages V A , V B , V C is input to the analog-to-digital converter 10, but the intermediate voltage V B is the voltage corresponding to 2048LSB (the voltage corresponding to the inflection point), the voltage before and after this inflection point V A , V C The output data corresponding to the voltage at the inflection point has the same phase as the output data before and after it, but the difference B is different from the differences A and C before and after it, and is a large value. That is, A=C <B。

[0042] Furthermore, when the relationship between the input analog voltage and the output data has an inflection point where the slope changes in the negative direction, as shown in the diagram of FIG. 7(a), for example, three offset binary voltages V A , V B , V C is input to the analog-to-digital converter 10, and the intermediate voltage V Bis set to a voltage corresponding to the inflection point, the output data differences A, B, and C gradually become smaller, that is, A>B>C, as shown in FIG.

[0043] On the other hand, if the relationship between the input analog voltage and the output data has an inflection point where the slope changes to a positive direction, as shown in the diagram of FIG. 7(b), for example, three offset binary voltages V A , V B , V C is input to the analog-to-digital converter 10, and the intermediate voltage V B When the voltage corresponding to the inflection point is set to a voltage, the output data differences A, B, and C gradually become larger values, as shown in FIG. 7(b). <B<C。

[0044] In this way, the difference value of the output data increases or decreases depending on the change in the slope at the inflection point, so in this case too, it is possible to determine the weighting direction.

[0045] In the examples shown in FIGS. 5 to 7, the capacitance of weighting adjustment unit 15 provided in the capacitor corresponding to 2048 LSB is adjusted so that the difference values ​​A, B, and C are positive and negative and have the same absolute value, that is, by selectively enabling each capacitor of weighting adjustment unit 15 and adjusting its capacitance, the integral nonlinearity of analog-to-digital converter 10 can be made closer to an ideal straight line, that is, the integral nonlinearity can be improved.

[0046] Furthermore, when the integral nonlinearity plots a rectangular waveform with multiple abrupt changes as shown in FIG. 8(a), the relationship between the input analog voltage and the output data plots as shown in FIG. 8(b). Note that FIG. 8(a) shows the integral nonlinearity when there is a capacitance error in the capacitor corresponding to the full scale of 2048 LSB and half of that, 1024 LSB. In this case, as shown in FIG. 8(a), the integral nonlinearity has inflection points at the input voltages of 1024 LSB and 2048 LSB. Similarly, in the plot showing the relationship between the input voltage and the output data, inflection points appear at the input voltages of 1024 LSB and 2048 LSB (FIG. 8(b)).

[0047] When several (for example, seven) offset binary voltages are input to the analog-digital converter 10 having such characteristics in the same manner as described above, the relationship between the input analog voltages and the output data is as shown in Fig. 8(C). That is, in Fig. 8(C), seven offset binary voltages offset at equal intervals are input to the analog-digital converter 10, and specifically, voltages corresponding to 1 / 8 (=512), 1 / 4 (=1024), 3 / 8 (=1536), 1 / 2 (=2048), 5 / 8 (=2560), 3 / 4 (=3072), and 7 / 8 (=3584) of the full scale (=4096), i.e., V A , V B , V C , V D , V E , V F , V G The voltages V corresponding to 1 / 4 (=1024), 1 / 2 (=2048), and 3 / 4 (=3072) of the full scale are input. B , V D , V F are voltages corresponding to 1024LSB and 2048LSB (=MSB), which indicate the inflection points, respectively. Regarding the specific input voltage, for example, in FIG. 8(c), if the full-scale input voltage is 8 [V] and the voltage width of the binary voltage is 0.1 [V], then the offset binary voltage V A , V B , V C , VD , V E , V F , V G becomes: V A =1±0.05[V], V B =2±0.05[V], V C =3±0.05[V], V D =4±0.05[V], V E =5±0.05[V], V F =6±0.05[V], V G =7±0.05[V] This becomes:

[0048] As shown in Figure 8(C), in this example, the input voltage V D The output data corresponding to the input voltage V is inverted in phase with the other output data. A , V B , V C , V D , V E , V F , V G If the differences of each output data are A, B, C, D, E, F, and G, respectively, they have the following relationship. A=C=E=G A E <F

[0049] In the example shown in FIG. 8, the capacitance of weighting adjustment unit 15 provided for the capacitors corresponding to 1024 LSB and 2048 LSB is adjusted so that the difference values ​​A, B, C, D, E, F, and G are positive and negative and have the same absolute value, thereby making it possible to bring the integral nonlinearity of analog-to-digital converter 10 closer to an ideal straight line, that is, to improve the integral nonlinearity.

[0050] ​As described above, integral nonlinearity can be verified by inputting offset voltages obtained by offsetting the binary voltage at predetermined intervals to the target analog-to-digital converter 10 and checking the output data. In particular, it is preferable that the input offset voltages include voltages corresponding to 1 / 8, 1 / 4, 3 / 8, 1 / 2, 5 / 8, 3 / 4, and 7 / 8 of the full scale of the analog-to-digital converter 10, and further, voltages corresponding to 2n-(1 / 2) of the full scale. m It is preferable to include a voltage corresponding to m, where m is the number of bits that is the resolution of the analog-to-digital converter 10. Furthermore, n is an integer that satisfies the following: n<2 m / 2

[0051] <Weighting Information Generation Unit> Based on the above considerations, the weighting information generation unit 20 in this example generates information for adjusting the weighting adjustment unit 15 provided for each capacitor in order to enhance the integral nonlinearity of the analog-to-digital converter 10, i.e., in this example, information regarding the capacitors to be enabled in each weighting adjustment unit 15.

[0052] Specifically, as shown in FIG. 1, the weighting information generating unit 20 of this example is made up of a control logic unit 21, an attenuator 22, a low-pass filter unit 23, an adder 24, a switch Sw, a memory 25, and the like.

[0053] The control logic unit 21 generates an arbitrary binary voltage, that is, a pulse voltage that forms a rectangular wave, and also generates an offset signal for multiplying this reference binary voltage by an offset voltage.

[0054] The accuracy of the generated binary voltage does not need to be highly precise, but only needs to be high enough to recognize the inflection point. This binary voltage is generated from a logic signal such as TTL (Transistor-Transistor Logic) or C-MOS (Complementary Metal Oxide Semiconductor) provided in the control logic unit 21, and the amplitude level of this voltage is controlled by the attenuator 22 before being input to the adder 24. The control of the amplitude level by the attenuator 22 is performed by the control logic unit 21.

[0055] The offset signal is generated by a PWM (Pulse Width Modulation) circuit provided in the control logic unit 21, and is passed through a low-pass filter unit 23 to be added as an offset voltage to the binary voltage output from the attenuator 22. The binary voltage thus offset (offset binary voltage) is then input to an adder 24. An offset power supply with the same voltage as the input offset voltage of the analog-to-digital converter 10 is connected to one input terminal of the adder 24, and when the offset binary voltage is input to the other terminal of the adder 24, the adder 24 outputs an analog voltage corresponding to the offset binary voltage to which the input offset voltage of the analog-to-digital converter 10 has been added.

[0056] As described above, the weighting information generation unit 20 generates binary voltages offset at predetermined intervals under the control of the control logic unit 21, and inputs the generated binary voltages to the target analog-to-digital converter 10. The input of the offset binary voltage to the analog-to-digital converter 10 can be executed by switching the switch Sw to the adder 24 side, and the switching of the switch Sw is controlled by the control logic unit 21. In this example, the control logic unit 21 and the attenuator 22 function as a voltage generation unit, the control logic unit 21 and the low-pass filter unit 23 function as a voltage offset unit, and the control logic unit 21, the attenuator 22, the low-pass filter unit 23, and the adder 24 function as a voltage input unit. The control logic unit 21 also functions as the information generation unit 21.

[0057] As described above, the binary voltages generated by the weighting information generating unit 20 preferably include voltages corresponding to 1 / 8, 1 / 4, 3 / 8, 1 / 2, 5 / 8, 3 / 4, and 7 / 8 of the full scale of the analog-to-digital converter 10, and further include voltages before and after these, or 2n-(1 / 2) of the full scale. m It is preferable to include a voltage equivalent to m, where m is the number of bits that is the resolution of the analog-to-digital conversion device.

[0058] In addition, the control logic unit 21 inputs the generated offset binary voltage to the analog-digital converter 10, acquires the output data output from the analog-digital converter 10, and stores the input value, that is, the offset binary voltage, and the corresponding output data in the memory 25 in association with each other.

[0059] Then, based on the acquired offset binary voltage and output data, the control logic unit 21 verifies (confirms) the fluctuation in values ​​between each output data, and executes a process to check whether or not an inflection point exists in the integral nonlinearity, i.e., to confirm the linearity of the integral nonlinearity.If an inflection point does not exist, the control logic unit 21 acquires the current effective state of the weighting adjustment unit of each adjustable capacitor as weighting information, and stores the information in memory 25.

[0060] On the other hand, if it is confirmed that an inflection point exists in the integral nonlinearity, the control logic unit 21 recognizes the offset binary voltage corresponding to the inflection point and the capacitor corresponding to the binary voltage, and then executes a process (adjustment process) for adjusting the effective state of the capacitor of the corresponding weight adjustment unit 15 in the analog-to-digital converter 10 according to the state of the inflection point. The adjustment process adjusts the weight adjustment unit 15 so that the phases of the output values ​​become the same and the difference values ​​become the same. The adjustment of the weight adjustment unit 15 can be performed based on theoretical or empirical judgment by considering the fluctuations between the output data.

[0061] After the adjustment process, the control logic unit 21 again generates an offset binary voltage and inputs it to the analog-digital converter 10, obtains the output data output from the analog-digital converter 10, correlates the input offset binary voltage with the output data, stores the correlated data in the memory 25, and then checks the linearity of the integral nonlinearity. If the linearity has been improved to fall within an allowable range, the effective state of the capacitors provided in each weighting adjustment unit 15 is stored in the memory 25 as weighting information.

[0062] On the other hand, if the linearity of the integral nonlinearity has not been improved, the above adjustment process is repeated to improve the linearity of the integral nonlinearity so that it falls within the allowable range, and the effective state of the capacitors of each weighting adjustment unit 15 after the improvement is stored in memory 25 as weighting information.

[0063] As described above, in the analog-to-digital conversion device 1 of this example, the weighting information generation unit 20 inputs a predetermined offset binary voltage to the analog-to-digital converter 10 under consideration, and the linearity of the integral nonlinearity of the analog-to-digital converter 10 is confirmed from the relationship between the output data output from the analog-to-digital converter 10 and the offset binary voltage, which is the input value. Furthermore, if the linearity is insufficient, the capacity of the weighting adjustment unit 15 of the analog-to-digital converter 10 is adjusted so that the linearity is within an acceptable range, and the adjusted weighting information is stored in the memory 25.

[0064] In this way, according to the analog-digital conversion device 1 of this example, the linearity of the integral nonlinearity of the target analog-digital converter 10 can be calibrated to fall within an allowable range by calibration using the weighting information generation unit 20. The analog-digital converter 10 after the calibration process can be separated from the analog-digital conversion device 1 and distributed. Alternatively, by reassembling the target analog-digital converter 10 into the analog-digital conversion device 1 of this example, the analog-digital converter 10 can be recalibrated based on the weighting information stored in the memory 25.

[0065] According to the analog-to-digital conversion device of this embodiment described above, it is possible to verify the integral nonlinearity of the analog-to-digital converter 10 and improve the integral nonlinearity of the analog-to-digital converter 10 using inexpensive devices such as the attenuator 22, the low-pass filter unit 23, and the adder 24. Therefore, compared to conventional embodiments that use high-precision, expensive digital-to-analog converters, it is possible to verify the integral nonlinearity of the analog-to-digital converter 10 at low cost.

[0066] In this example, the voltages in the vicinity of the capacitance of the capacitor of the analog-to-digital converter 10 are verified, and compared to the conventional method in which voltages are set precisely for verification, the number of measurement points can be significantly reduced for verification, making it possible to verify integral nonlinearity efficiently in a short time and also to improve it.

[0067] Although specific embodiments of the present invention have been described above, the specific aspects that the present invention can adopt are not limited to the above-mentioned examples.

[0068] For example, in the above example, a binary signal is generated by a PWM circuit provided in the control logic unit 21, and this signal is passed through the low-pass filter unit 23 to generate an offset voltage, but the configuration for generating an offset binary voltage is not limited to this. An example is shown in FIG. 9. An analog-to-digital conversion device 30 shown in FIG. 9 includes a weighting information generation unit 35 having an electronic volume 36 instead of the low-pass filter 23 of the above example, and in this respect, the weighting information generation unit 35 differs in configuration from the weighting information generation unit 20 of the above example. Note that in FIG. 9, the same components as those of the weighting information generation unit 20 are denoted by the same reference numerals.

[0069] In this weighting information generating unit 35, the amplitude level of the binary signal generated by the control logic unit 21 is controlled by the attenuator 22, and an offset binary voltage is generated by adding an offset voltage generated by the electronic volume 36 controlled by the control logic unit 21 to this. Even with this configuration, it is possible to generate an analog voltage for verification without using a conventional, highly accurate and expensive digital-to-analog converter.

[0070] 10 further includes a weighting information generating section 45 having a low-pass filter section 46 instead of the attenuator 22 of the above example, and in this respect the weighting information generating section 45 differs in configuration from the weighting information generating section 20 of the above example. Note that in FIG. 10, the same components as those of the weighting information generating section 20 are denoted by the same reference numerals.

[0071] In this weighting information generation unit 45, both a binary signal and an offset signal are generated by a PWM circuit provided in the control logic unit 21. The level of the binary signal is adjusted by passing through a low-pass filter unit 46 to become a binary voltage, and the offset signal is generated by passing through a low-pass filter unit 23 to become an offset voltage, and these are combined to form an offset binary voltage which is input to the adder 24. Even with this configuration, it is possible to generate an analog voltage for verification without using a conventional, highly accurate and expensive digital-to-analog converter.

[0072] 11 also includes a weighting information generation unit 55 that does not include the attenuator 22 of the above example. This weighting information generation unit 55 is configured to superimpose a binary signal and an offset signal generated by a PWM circuit in the control logic unit 21 and input the superimposed signal to the low-pass filter unit 23. Note that in FIG. 11, the same components as those in the weighting information generation unit 20 are denoted by the same reference numerals.

[0073] In this weighting information generating unit 55, the binary signal and the offset signal generated by the PWM circuit in the control logic unit 21 are superimposed and input to the low-pass filter unit 23, which then passes through the low-pass filter unit 23 to generate an offset binary voltage, which is then input to the adder 24. Even with this configuration, it is possible to generate an analog voltage for verification without using a conventional, highly accurate and expensive digital-to-analog converter.

[0074] An analog-to-digital conversion device 60 shown in Fig. 12 includes a weighting information generation unit 65 having an inexpensive digital-to-analog converter 66, instead of the attenuator 22, low-pass filter unit 23, and adder 24 of the above example. Note that in Fig. 12, the same components as those in the weighting information generation unit 20 are denoted by the same reference numerals.

[0075] In this weighting information generating unit 65, a digital signal for an offset binary voltage is input from the control logic unit 21 to a digital-to-analog converter 66, and an analog voltage corresponding to the offset binary voltage converted by the digital-to-analog converter 66 is input to the analog-to-digital converter 10. Even with this configuration, it is possible to generate an analog voltage for verification without using a conventional, highly accurate and expensive digital-to-analog converter.

[0076] In the above example, a successive approximation type analog-digital converter is used as the analog-digital converter 10, but this is not limiting and a parallel comparison type analog-digital converter may also be used. In the above example, a capacitive type analog-digital converter is used as the analog-digital converter 10, but this is not limiting and a resistive type analog-digital converter may also be used.

[0077] <Other embodiments> In the above-described embodiment, when integral nonlinearity determined from input / output data of the analog-digital converter 10 has an inflection point, the integral nonlinearity is corrected (the capacitor capacitance is corrected) based on two input voltages arranged on either side of the input voltage corresponding to the inflection point and the two output data corresponding to the input voltages. For example, in the example shown in FIGS. 5(A) to 5(C), the voltage VB corresponding to the inflection point of the integral nonlinearity is corrected based on the voltages VA and VC and the output data of the voltages VA and VC. This embodiment is based on the premise that the analog-digital converter 10 outputs ideal data (integral nonlinearity without inflection points) for the input voltages VA and VC. However, due to the structure of the analog-digital converter 10, the integral nonlinearity is actually output in a state where both small and large inflection points are mixed.

[0078] Figure 13 shows an example of an actual integral nonlinearity waveform. The vertical axis represents integral nonlinearity, and the horizontal axis represents digital code. Here, the integral nonlinearity of an 8-bit analog-to-digital converter is shown as an example. When analog-to-digital converter 10 ideally outputs a signal relative to its input, the integral nonlinearity waveform is a straight horizontal line (constant integral nonlinearity). However, in reality, due to various factors, the integral nonlinearity waveform has steps (inflection points). The waveform contains steps of various sizes. For example, small steps appear near digital code values ​​of 32, 96, 160, and 224, while large steps appear near digital code values ​​of 64, 128, and 192. Due to the structure of the analog-to-digital converter, these steps often appear mainly near powers of 2 and their multiples.

[0079] Let's say we want to reduce the magnitude of step A1 that appears at digital code value 128. For example, suppose we adjust the capacitor voltage appropriately to make step A1 zero. In this case, the magnitude of step A1 is reduced. However, reducing only the magnitude of step A1 affects the integral nonlinearity waveform in parts other than step A1. For example, step A2 at digital code value 64 will lower the waveform, while step A3 at digital code value 192 will raise the waveform. As a result, the range of integral nonlinearity values ​​will increase when viewed as the waveform as a whole.

[0080] Furthermore, when using the potential difference between two points to correct integral nonlinearity corresponding to a potential sandwiched between the two points, as in the above-described embodiment, the effectiveness of the correction depends on how the two points are selected. For example, when correcting the magnitude of a step A1 that appears at a digital code value of 128, suppose that digital code values ​​of 96 and 160 are selected as the two points used for correction. If the waveform of the integral nonlinearity at the two points is linear, the step A1 can be effectively corrected, as described in the above-described embodiment. However, there are steps at the digital code values ​​of 96 and 160. Therefore, the correction method of the above-described embodiment does not necessarily correct the magnitude of the step A1 appropriately. In such cases, processing such as reselecting the two points becomes necessary. The following processing method can be used to address this issue.

[0081] FIG. 14 is a diagram for explaining the contents of another embodiment. The vertical axis represents integral nonlinearity, and the horizontal axis represents digital code. In this embodiment, the process for obtaining the integral nonlinear waveform is the same as in the above-described embodiment. This embodiment differs from the above-described embodiment in that the step (integral nonlinearity error) is corrected using two regression lines instead of the potential difference between two points. The configuration of the weighting information generating device is also the same as in the above-described embodiment, and therefore will not be described here.

[0082] The weighting information generating unit 20 sets a correction region T for performing correction on the obtained integral nonlinear waveform, a first regression region R1 different from the correction region T, and a second regression region R2 different from the correction region T and the first regression region R1. The weighting information generating unit 20 sets each region so that the first regression region R1 and the second regression region R2 sandwich the correction region T.

[0083] The correction region T may be set after or before the integral nonlinearity waveform is obtained. For example, the correction region T may be set by locating steps in the obtained integral nonlinearity waveform. Steps often appear at positions where the digital code value is a power of 2 or a multiple thereof. The correction region T may be set in advance based on such prior information or empirical rules. The correction region T is set within a predetermined range of digital code values. In this example, the correction region T is set within a predetermined digital code value range centered around the position where the digital code value is 128. The predetermined digital code value range is set appropriately within a range in which the integral nonlinearity waveform is affected by steps.

[0084] The first regression region R1 is set to be a region different from the correction region T. The first regression region R1 is set to a range of digital code values ​​different from the correction region T. The first regression region R1 is set to a region where the digital code values ​​are smaller than the correction region T. In this example, the maximum value of the digital code values ​​in the first regression region R1 matches the minimum value of the digital code values ​​in the correction region T. The minimum value of the digital code values ​​in the first regression region R1 is set appropriately. The minimum value of the digital code values ​​in the first regression region R1 may be set so that the first regression region R1 covers the entire range where the digital code values ​​are smaller than the correction region T. The minimum value of the digital code values ​​in the first regression region R1 may be set so that the first regression region R1 covers a part of the range where the digital code values ​​are smaller than the correction region T.

[0085] The second regression region R2 is set to be a region different from the first regression region R1 and the correction region T. The second regression region R2 is set to a range of digital code values ​​different from the first regression region R1 and the correction region T. The second regression region R2 is set to a region where the digital code values ​​are larger than the correction region T. In this example, the minimum value of the digital code values ​​in the second regression region R2 coincides with the maximum value of the digital code values ​​in the correction region T. The maximum value of the digital code values ​​in the second regression region R2 is set appropriately. The maximum value of the digital code values ​​in the second regression region R2 may be set so that the second regression region R2 covers the entire range where the digital code values ​​are larger than the correction region T. The maximum value of the digital code values ​​in the second regression region R2 may be set so that the second regression region R2 covers a part of the range where the digital code values ​​are larger than the correction region T.

[0086] The weighting information generation unit 20 calculates a first regression line L1 in the first regression region R1. The weighting information generation unit 20 calculates the first regression line L1 based on the digital code value and the integral nonlinearity value in the first regression region R1. The calculation method is not particularly limited. The first regression line L1 is calculated, for example, by the least squares method. The first regression line L1 may also be calculated by the maximum likelihood estimation method, the least absolute deviation method, or the like. In short, the weighting information generation unit 20 performs regression analysis on the waveform of the obtained integral nonlinearity to calculate the first regression line L1. The first regression line L1 may be a straight line or a curve. The first regression line L1 may be calculated by simple regression analysis or multiple regression analysis.

[0087] The weighting information generating unit 20 calculates a second regression line L2 in the second regression region R2. The weighting information generating unit 20 calculates the second regression line L2 based on the digital code value and the integral nonlinearity value in the second regression region R2. The rest of the second regression line L2 is the same as the first regression line L1, so a description thereof will be omitted.

[0088] The weighting information generation unit 20 calculates the difference between the obtained first regression line L1 and second regression line L2. Specifically, the weighting information generation unit 20 virtually extends the first regression line L1 to the median value of the digital code values ​​in the correction region T. In this example, the median value is 128 in terms of digital code value. Similarly, the weighting information generation unit 20 virtually extends the second regression line L2 to the median value of the digital code values ​​in the correction region T. The weighting information generation unit 20 calculates the difference between the value of integral nonlinearity in the first regression line L1 and the value of integral nonlinearity in the second regression line L2 at the position of the median value of the digital code values ​​in the correction region T.

[0089] The weighting information generation unit 20 generates weighting information based on the calculated difference between the first regression line L1 and the second regression line L2. The weighting information generation unit 20 generates weighting information, for example, to reduce the calculated difference. Then, as in the above-described embodiment, the capacitance of the weighting adjustment unit 15 provided for each capacitor is adjusted based on the weighting information, thereby correcting the integral nonlinearity of the analog-to-digital converter 10. The method for reducing the difference is not particularly limited. For example, a bisection search method can be used to reduce the difference. The extent to which the difference is reduced depends on the accuracy of the capacitor capacitance correction. For example, when the bisection method is used, the processing ends when the difference diff no longer changes even when the correction value of the capacitor capacitance is changed.

[0090] 15 is a flowchart of integral nonlinearity correction processing in another embodiment. In the figure, the flow up to obtaining the integral nonlinearity waveform is omitted. First, the weighting information generation unit 20 sets a digital code value to be corrected in the obtained integral nonlinearity waveform (step S11). The weighting information generation unit 20 sets the above-mentioned correction region T with the set digital code value as the median value. In other words, this flowchart shows the case where the correction region T is set in advance.

[0091] Next, the weighting information generating unit 20 acquires output data necessary for determining the integral nonlinearity from the analog-to-digital converter 10. The weighting information generating unit 20 determines the waveform (data group) of the integral nonlinearity from the acquired output data (step S12).

[0092] Next, the weighting information generating section 20 sets a first regression region R1 and a second regression region R2 from the waveform of the integral nonlinearity thus obtained (step S13).

[0093] Next, the weighting information generating unit 20 calculates a first regression line L1 in the first regression region R1. The weighting information generating unit 20 calculates a second regression line L2 in the second regression region R2 (step S14). In this example, the first regression line L1 and the second regression line L2 are simple regression lines.

[0094] Next, the weighting information generation unit 20 expresses the first regression line L1 as a formula "y1 = ax1 + b", where y1 is the integral nonlinearity, x1 is the digital code value, a is a coefficient, and b is a constant. The weighting information generation unit 20 calculates the value of y1 when x1 = 2^n in the formula. Similarly, the weighting information generation unit 20 expresses the second regression line L2 as a formula "y2 = ax2 + b", where y2 is the integral nonlinearity, x2 is the digital code value, a is a coefficient, and b is a constant. The weighting information generation unit 20 calculates the value of y2 when x2 = 2^n in the formula (step S15).

[0095] Next, the weighting information generating unit 20 calculates the difference between the calculated values ​​of y1 and y2, ie, "diff=y2-y1" (step S16).

[0096] Next, the weighting information generating unit 20 adjusts the capacitor (weighting adjusting unit 15) of the analog-to-digital converter 10 corresponding to the median value (2̂n) of the digital code values ​​so as to reduce the calculated difference diff (step S17).

[0097] Next, the weighting information generation unit 20 checks the integral nonlinearity of the analog-digital converter 10 after the capacitance of the capacitors has been adjusted (step S18). Specifically, in step S18, the weighting information generation unit 20 executes steps S12 to S16 and checks whether the value of the difference diff is within a predetermined range (whether it has been reduced). If the weighting information generation unit 20 determines that the value of the difference diff is outside the predetermined range (NO in step S18), it returns to step S12. If the weighting information generation unit 20 determines that the value of the difference diff is within the predetermined range (YES in step S18), it checks whether the capacitances of all the capacitors in the analog-digital converter 10 have been adjusted (step S19).

[0098] If the capacitances of all the capacitors have not been adjusted (NO in step S19), the weighting information generation unit 20 returns to step S11. In this case, the weighting information generation unit 20 changes the median value (2^n) of the digital code values ​​in the correction region T and executes steps S12 to S18. If the capacitances of all the capacitors have been adjusted (YES in step S19), the weighting information generation unit 20 ends the correction process.

[0099] As described above, in the weighting information generating device according to the other embodiment, even if the step A1 (the integral nonlinearity value in the correction region T) to be corrected is corrected in the correction process, the effect of the correction is unlikely to affect the waveform in regions other than the correction region T. Furthermore, in the weighting information generating device according to the other embodiment, even if a step (integral nonlinearity error) exists in a region other than the correction region T, it is absorbed into the first and second regression lines. That is, the correction process can be performed while suppressing the effect of steps in regions other than the correction region T. Furthermore, in the weighting information generating device according to the other embodiment, the correction region T is set not only to the digital code value to be corrected, but also to a predetermined range including the digital code value. Therefore, even if the step does not strictly exist at a position that is a power of 2 in terms of the digital code value, it can be appropriately corrected as long as it is included in the correction region T. Therefore, the weighting information generating device according to the other embodiment can appropriately perform the correction process even if the integral nonlinearity waveform contains steps (errors) of various magnitudes. That is, the weighting information generating device according to the other embodiment improves the robustness of the correction process.

[0100] To reiterate, the above-described embodiments are illustrative in all respects and are not limiting. Variations and modifications are possible for those skilled in the art. The scope of the present invention is defined not by the above-described embodiments but by the claims. Furthermore, the scope of the present invention includes modifications from the embodiments within the scope of the claims and their equivalents. [Explanation of symbols]

[0101] 1 Analog-to-digital conversion device 10 Analog-to-Digital Converter 11 Comparator 12 Capacitive Array 13 Switch Control Register 14 Successive approximation logic circuit 15 Weighting adjustment section 20 Weighting information generation unit 21 Control Logic Section 22 Attenuator 23 Low-pass filter section 24 Adder 25 memory

Claims

1. 1. An information generating device for generating weighting information to be applied to a weighting adjustment unit of an analog-to-digital converter including the weighting adjustment unit, a voltage input unit including a voltage generation unit that generates a predetermined binary voltage, and a voltage offset unit that offsets the voltage generated by the voltage generation unit by multiplying the offset voltage by an offset voltage, and that sequentially inputs voltages that are offset in stages by a predetermined voltage to the analog-to-digital converter; and an information generating unit that acquires an output value corresponding to the voltage output from the analog-to-digital converter and generates the weighting information based on the acquired output value.

2. 2. The weighting information generating device according to claim 1, wherein the information generating unit is configured to generate weighting information such that each output value output from the analog-to-digital converter exhibits the same phase and is a value within a predetermined reference range.

3. 2. The weighting information generating device according to claim 1, wherein the voltage input unit is configured to generate the binary voltages, at least one of which has a voltage corresponding to 1 / 8, 1 / 4, 3 / 8, 1 / 2, 5 / 8, 3 / 4, and 7 / 8 of the full scale of the analog-to-digital converter, as offset voltages and input the offset voltages to the analog-to-digital converter.

4. At least one of the voltage input sections is further configured to have a voltage that is 2n-(1 / 2) of the full scale of the analog-to-digital converter. ｍ 4. The weighting information generating device according to claim 3, wherein the voltage having a voltage equivalent to the above is generated as an offset voltage and input to the analog-to-digital converter. Here, m is the number of bits that is the resolution of the analog-to-digital converter. Furthermore, n is an integer that satisfies the following. n<2 ｍ／２

5. the voltage input unit is configured to sequentially input voltages offset at the same offset intervals to the analog-to-digital converter; 2. The weighting information generating device according to claim 1, wherein the information generating unit is configured to acquire output values ​​corresponding to each voltage output from the analog-digital converter, compare one acquired output value with other output values, and if the difference value exceeds a predetermined reference range or the sign of the difference value is reversed, store the input voltage, and then, with the stored input voltage input from the voltage input unit to the analog-digital converter, adjust the weighting adjustment unit of the analog-digital converter so that the difference value between that output value and the other output value falls within the reference range and has the same sign, and generate the state of the weighting adjustment unit at that time as weighting information.

6. 2. The weighting information generation device according to claim 1, wherein the information generation unit is configured to acquire output values ​​corresponding to each voltage output from the analog-to-digital converter, set the output values ​​in a predetermined voltage range as output values ​​to be corrected, calculate a first regression line based on the output values ​​in a voltage range lower than the predetermined voltage range, calculate a second regression line based on the output values ​​in a voltage range higher than the predetermined voltage range, and generate the weighting information based on the first regression line and the second regression line.

7. An analog-to-digital converter having a weighting adjustment unit, The weight adjustment unit An analog-to-digital converter in which offset voltages are generated by multiplying a binary voltage by an offset voltage, and the offset voltages are offset in stages by a predetermined voltage and input into the analog-to-digital converter in sequence, and based on the output values ​​corresponding to the offset voltages output from the analog-to-digital converter, the output values ​​are adjusted so that they show the same phase and are values ​​within a predetermined reference range.

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