Nitride semiconductor device

Abstract

To provide a nitride semiconductor device in which self-turn-on is suppressed.SOLUTION: A nitride semiconductor device 10 includes a first transistor 10T1 and a second transistor 10T2. A first gate electrode 24G1 of the first transistor 10T1 is electrically connected to a second drain electrode 30D2 of the second transistor 10T2. A first source electrode 28S1 of the first transistor 10T1 is electrically connected to a second gate electrode 24G2 and a second source electrode 28S2 of the second transistor 10T2.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using group III nitride semiconductors (hereinafter sometimes simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMTs use a two-dimensional electron gas (2DEG) formed near the interface of a semiconductor heterojunction as a conductive path (channel) (see, for example, Patent Document 1). Power devices using HEMTs are recognized as devices that have lower on-resistance and are capable of high-speed, high-frequency operation compared to typical silicon (Si) power devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-165749

[0004] [overview] Since the gate threshold of a HEMT is relatively low (for example, about 1.5 V), self-turn-on can occur when the HEMT is used in a bridge circuit such as a DC / DC converter.

[0005] A nitride semiconductor device according to one embodiment of the present disclosure includes a first nitride semiconductor layer, a second nitride semiconductor layer located on the first nitride semiconductor layer and having a larger bandgap than the first nitride semiconductor layer, and a third nitride semiconductor layer located on the second nitride semiconductor layer and containing acceptor-type impurities. The third nitride semiconductor layer includes a first gate layer located in a first transistor region and a second gate layer located in a second transistor region. The nitride semiconductor device further includes a first source electrode and a first drain electrode located in contact with the second nitride semiconductor layer and in the first transistor region, a first gate electrode located on the first gate layer, a second source electrode and a second drain electrode located in contact with the second nitride semiconductor layer and in the second transistor region, and a second gate electrode located on the second gate layer. The first nitride semiconductor layer in the first transistor region, the second nitride semiconductor layer in the first transistor region, the first gate layer, the first source electrode, the first drain electrode, and the first gate electrode form a first transistor. The first nitride semiconductor layer in the second transistor region, the second nitride semiconductor layer in the second transistor region, the second gate layer, the second source electrode, the second drain electrode, and the second gate electrode constitute a second transistor, wherein the first gate electrode is electrically connected to the second drain electrode, and the first source electrode is electrically connected to the second gate electrode and the second source electrode. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view of a first transistor and a second transistor in an exemplary nitride semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a partially enlarged cross-sectional view of the first transistor shown in FIG. [Figure 3] FIG. 3 is a partially enlarged cross-sectional view of the second transistor shown in FIG. [Figure 4] FIG. 4 is a schematic plan view showing an exemplary planar layout of the nitride semiconductor device shown in FIG. [Figure 5] FIG. 5 is a partial enlarged plan view of the first transistor shown in FIG. [Figure 6] FIG. 6 is a partial enlarged plan view of the second transistor shown in FIG. [Figure 7] FIG. 7 is a schematic plan view showing a part of the electrode layer in addition to the wiring pattern of the wiring layer shown in FIG. [Figure 8] FIG. 8 is a schematic circuit diagram showing a circuit structure of a typical nitride semiconductor device including only a first transistor and not a second transistor, along with a charging current path. [Figure 9] FIG. 9 is a schematic circuit diagram showing the configuration of a typical bridge circuit used in a DC / DC converter, along with the current path. [Figure 10] FIG. 10 is a schematic circuit diagram showing the circuit structure of the nitride semiconductor device according to the first embodiment including both the first transistor and the second transistor, together with a charging current path. [Figure 11] FIG. 11 is a schematic cross-sectional view of a first transistor and a second transistor in an illustrative nitride semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is a partially enlarged cross-sectional view of the first transistor shown in FIG. [Figure 13] FIG. 13 is a partially enlarged cross-sectional view of the second transistor shown in FIG. [Figure 14] FIG. 14 is a schematic plan view showing a planar layout of a nitride semiconductor device according to a modification. [Figure 15] FIG. 15 is a partial enlarged plan view of the second transistor shown in FIG. [Figure 16] FIG. 16 is a schematic plan view showing the wiring pattern shown in FIG.

[0007] [Detailed explanation] Hereinafter, several embodiments of nitride semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0008] As used in this disclosure, terms such as "first," "second," "third," etc. are used merely to distinguish between objects and not to rank them. For example, in a structure in which a "first" element contains a "first" sub-element, and a "second" element contains a "second" sub-element, a particular claim may refer to the second sub-element of the second element without referring to the first sub-element of the first element.

[0009] Additionally, the phrase "at least one" used in this disclosure means one or more of a desired plurality of options. As an example, if the number of options is two, the phrase "at least one" means only one option or both of the two options. As another example, if the number of options is three or more, the phrase "at least one" means only one option or any combination of two or more options.

[0010] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0011] [First embodiment] A nitride semiconductor device 10 according to a first embodiment will be described with reference to FIGS. 1 to 10. In the present disclosure, components will be described based on mutually orthogonal X, Y, and Z axes shown in the figures. The term "plan view" used in the present disclosure refers to viewing the nitride semiconductor device 10 in the Z-axis direction, unless explicitly stated otherwise. In the following description, for convenience, the +Z direction may be referred to as up, the -Z direction as down, the +X direction as right, and the -X direction as left in the nitride semiconductor device 10 shown in FIG. 1. However, the up, down, left, and right directions of the nitride semiconductor device 10 are not limited to these directions.

[0012] [1-1. Schematic structure of nitride semiconductor device] FIG. 1 is a schematic cross-sectional view of a nitride semiconductor device 10 according to a first embodiment. The nitride semiconductor device 10 includes a first transistor 10T1 located in a first transistor region RT1 and a second transistor 10T2 located in a second transistor region RT2. The first and second transistors 10T1 and 10T2 are configured as HEMTs using nitride semiconductors. In one example, the first and second transistors 10T1 and 10T2 are GaN-HEMTs using GaN. The first and second transistors 10T1 and 10T2 are provided as power transistors used in power device applications, for example.

[0013] Fig. 2 is a partially enlarged cross-sectional view of the first transistor 10T1 shown on the left side of Fig. 1, and Fig. 3 is a partially enlarged cross-sectional view of the second transistor 10T2 shown on the right side of Fig. 1. For clarity, some of the components shown in Fig. 1 are omitted in Fig. 2 and Fig. 3. Below, the components of each of the first and second transistors 10T1 and 10T2 will be described with reference to Figs. 1 to 3.

[0014] 1, the nitride semiconductor device 10 includes a semiconductor substrate 12 and a buffer layer 14 located on the semiconductor substrate 12. The nitride semiconductor device 10 further includes an electron transit layer 16 and an electron supply layer 18 located on the electron transit layer 16. A back surface electrode 11 is provided on the lower surface (back surface) of the semiconductor substrate 12, and is electrically connected to a terminal electrode of a package (not shown).

[0015] The semiconductor substrate 12 may be formed of Si, silicon carbide (SiC), GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate 12 is a conductive Si substrate. The semiconductor substrate 12 may have a thickness of, for example, 100 μm or more and 1500 μm or less. In one example, the thickness of the semiconductor substrate 12 is 250 μm.

[0016] The buffer layer 14 includes one or more nitride semiconductor layers. The electron transport layer 16 is located on the buffer layer 14. The buffer layer 14 may be made of any material that can facilitate epitaxial growth of the electron transport layer 16.

[0017] For example, the buffer layer 14 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different Al compositions. For example, the buffer layer 14 may be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. To suppress leakage current in the buffer layer 14, impurities may be introduced into a portion of the buffer layer 14 to make the buffer layer 14 semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the impurity concentration may be, for example, 4×10 16 cm -3 It can be more than that.

[0018] The electron transport layer 16 may be, for example, a GaN layer. The electron transport layer 16 may have a thickness of, for example, 0.5 μm or more and 2 μm or less. In order to suppress the leakage current in the electron transport layer 16, the region other than the surface layer region of the electron transport layer 16 may be made semi-insulating by introducing impurities into a part of the electron transport layer 16. In this case, the impurity is, for example, C, and the concentration of the impurity in the electron transport layer 16 may be, for example, 4×10 16 cm -3 or more. The electron transport layer 16 corresponds to the first nitride semiconductor layer.

[0019] The electron supply layer 18 has a larger bandgap than the electron transport layer 16. The electron supply layer 18 may be, for example, an AlGaN layer. Since the larger the Al composition, the larger the bandgap, the electron supply layer 18 which is an AlGaN layer has a larger bandgap than the electron transport layer 16 which is a GaN layer. For example, the electron supply layer 18 is composed of Al X Ga (1-X) N with an Al composition ratio X. The Al composition ratio X may be 0.1 < X < 0.4, preferably 0.1 < X < 0.3. The electron supply layer 18 may have a thickness of, for example, 5 nm or more and 20 nm or less. In one example, the thickness of the electron supply layer 18 is 8 nm or more. The electron supply layer 18 corresponds to the second nitride semiconductor layer.

[0020] The electron transport layer 16 and the electron supply layer 18 are composed of nitride semiconductors having different lattice constants from each other. Therefore, the nitride semiconductor (for example, GaN) constituting the electron transport layer 16 and the nitride semiconductor (for example, AlGaN) constituting the electron supply layer 18 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 16 and the electron supply layer 18 and the piezo polarization caused by the crystal strain near the hetero-junction interface, the energy level of the conduction band of the electron transport layer 16 near the hetero-junction interface becomes lower than the Fermi level. As a result, the 2DEG 20 spreads in the electron transport layer 16 at a position close to the hetero-junction interface between the electron transport layer 16 and the electron supply layer 18 (for example, within a range of about several nm from the interface).

[0021] The nitride semiconductor device 10 further includes a first gate layer 22G1 located on the electron supply layer 18, and a first gate electrode 24G1 located on the first gate layer 22G1. The first gate layer 22G1 is partially provided on the electron supply layer 18. The first gate layer 22G1 is located in the first transistor region RT1.

[0022] The nitride semiconductor device 10 further includes a second gate layer 22G2 located on the electron supply layer 18, and a second gate electrode 24G2 located on the second gate layer 22G2. The second gate layer 22G2 is partially provided on the electron supply layer 18. The second gate layer 22G2 is located in the second transistor region RT2.

[0023] The first and second gate layers 22G1 and 22G2 are made of a nitride semiconductor containing acceptor-type impurities. For example, the first and second gate layers 22G1 and 22G2 may each be a gallium nitride layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities may include at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of the acceptor-type impurities in the first and second gate layers 22G1 and 22G2 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 In one example, the first and second gate layers 22G1 and 22G2 are each made of GaN containing at least one of Mg and Zn as an impurity. The first and second gate layers 22G1 and 22G2 each correspond to a third nitride semiconductor layer.

[0024] The first and second gate electrodes 24G1 and 24G2 each include one or more metal layers. In one example, the first and second gate electrodes 24G1 and 24G2 are each titanium nitride (TiN) layers. In another example, the first and second gate electrodes 24G1 and 24G2 each include a first metal layer made of Ti and a second metal layer formed of TiN and located on the first metal layer. The first gate electrode 24G1 forms a Schottky junction with the first gate layer 22G1. The first gate electrode 24G1 is partially disposed on the first gate layer 22G1. Similarly, the second gate electrode 24G2 forms a Schottky junction with the second gate layer 22G2. The second gate electrode 24G2 is partially disposed on the second gate layer 22G2. The first and second gate electrodes 24G1 and 24G2 may each have a thickness of, for example, 50 nm to 200 nm.

[0025] The nitride semiconductor device 10 further includes a passivation layer 26. The passivation layer 26 covers the electron supply layer 18, the first and second gate layers 22G1 and 22G2, and the first and second gate electrodes 24G1 and 24G2. The passivation layer 26 is formed of at least one of silicon nitride (SiN), silicon dioxide (SiO), silicon oxynitride (SiON), alumina (AlO), AlN, and aluminum oxynitride (AlON), for example. In one example, the passivation layer 26 is formed of a material containing SiN. The passivation layer 26 may have a thickness of, for example, 80 nm to 150 nm.

[0026] In the first transistor region RT1, the passivation layer 26 includes a first source opening 26S1 and a first drain opening 26D1 spaced apart from each other in a first direction (the X-axis direction in FIG. 1). The first gate layer 22G1 is located between the first source opening 26S1 and the first drain opening 26D1 in the first direction. The first gate layer 22G1 is located closer to the first source opening 26S1 than the first drain opening 26D1.

[0027] In the following, for convenience of explanation, the direction in which the first source opening 26S1, the first gate layer 22G1, and the first drain opening 26D1 are aligned in a planar view (the X-axis direction in FIG. 1) will be referred to as the first direction X, and the direction intersecting the first direction X in a planar view (the Y-axis direction perpendicular to the X-axis direction in FIG. 1) will be referred to as the second direction Y.

[0028] In the second transistor region RT2, the passivation layer 26 includes a second source opening 26S2 and a second drain opening 26D2 spaced apart from each other in the first direction X. The second gate layer 22G2 is located between the second source opening 26S2 and the second drain opening 26D2 in the first direction X. The second gate layer 22G2 is located closer to the second source opening 26S2 than the second drain opening 26D2.

[0029] The nitride semiconductor device 10 includes a first source electrode 28S1 in contact with the electron supply layer 18 through the first source opening 26S1 and a first drain electrode 30D1 in contact with the electron supply layer 18 through the first drain opening 26D1. The first source electrode 28S1 and the first drain electrode 30D1 may each include one or more metal layers. For example, the first source electrode 28S1 and the first drain electrode 30D1 may each be formed by combining two or more metal layers selected from a group including a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. In one example, the first source electrode 28S1 and the first drain electrode 30D1 each have a four-layer structure (Ti layer / AlCu layer / Ti layer / TiN layer) including, from the top surface side, a Ti layer, an AlCu layer, a Ti layer, and a TiN layer. The first source electrode 28S1 and the first drain electrode 30D1 are located in the first transistor region RT1.

[0030] Similarly, the nitride semiconductor device 10 includes a second source electrode 28S2 in contact with the electron supply layer 18 through the second source opening 26S2, and a second drain electrode 30D2 in contact with the electron supply layer 18 through the second drain opening 26D2. The second source electrode 28S2 and the second drain electrode 30D2 may be formed using a material similar to the material of the first source electrode 28S1 and the first drain electrode 30D1 described above. The second source electrode 28S2 and the second drain electrode 30D2 are located in the second transistor region RT2.

[0031] 2, the first source electrode 28S1 includes a first source contact portion 28SC1 that fills the first source opening 26S1 and is in contact with the electron supply layer 18, and a first source field plate portion 28SF1 that is formed integrally with the first source contact portion 28SC1 and is located on the passivation layer 26. The first source contact portion 28SC1 is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 through the first source opening 26S1.

[0032] The first source field plate portion 28SF1, for example, entirely covers the first gate electrode 24G1 and the first gate layer 22G1. The first source field plate portion 28SF1 includes a first field plate end portion 28E1 facing the first drain electrode 30D1. The first source field plate portion 28SF1 serves to alleviate electric field concentration near the end portion of the first gate layer 22G1 when a high voltage is applied between the source and drain of the first transistor 10T1 in an off state in which the 2DEG 20 in the region of the electron transit layer 16 directly below the first gate layer 22G1 has disappeared.

[0033] The first drain electrode 30D1 includes a first drain contact portion 30DC1 that fills the first drain opening 26D1 and is in contact with the electron supply layer 18. The first drain contact portion 30DC1 is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 through the first drain opening 26D1.

[0034] 3, the second source electrode 28S2 includes a second source contact portion 28SC2 that fills the second source opening 26S2 and is in contact with the electron supply layer 18, and a second source field plate portion 28SF2 that is formed integrally with the second source contact portion 28SC2 and is located on the passivation layer 26. The second source contact portion 28SC2 is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 via the second source opening 26S2.

[0035] The second source field plate portion 28SF2, for example, entirely covers the second gate electrode 24G2 and the second gate layer 22G2. The second source field plate portion 28SF2 includes a second field plate end portion 28E2 facing the second drain electrode 30D2. The second source field plate portion 28SF2 serves to alleviate electric field concentration near the end portion of the second gate layer 22G2 when a high voltage is applied between the source and drain of the second transistor 10T2 in an off state in which the 2DEG 20 in the region of the electron transit layer 16 directly below the second gate layer 22G2 has disappeared.

[0036] The second drain electrode 30D2 includes a second drain contact portion 30DC2 that fills the second drain opening 26D2 and is in contact with the electron supply layer 18. The second drain contact portion 30DC2 is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 through the first drain opening 26D1.

[0037] The first transistor 10T1 is composed of the electron transit layer 16 in the first transistor region RT1, the electron supply layer 18 in the first transistor region RT1, the first gate layer 22G1, the first gate electrode 24G1, the first source electrode 28S1, and the first drain electrode 30D1. The first transistor region RT1 can be referred to as the region in which these components of the first transistor 10T1 are arranged.

[0038] The second transistor 10T2 is composed of the electron transit layer 16 in the second transistor region RT2, the electron supply layer 18 in the second transistor region RT2, the second gate layer 22G2, the second gate electrode 24G2, the second source electrode 28S2, and the second drain electrode 30D2. The second transistor region RT2 can be referred to as the region in which these components of the second transistor 10T2 are arranged.

[0039] In the first transistor 10T1, the first gate layer 22G1 contains acceptor-type impurities, which raises the energy levels of the electron transit layer 16 and the electron supply layer 18. Therefore, in the region immediately below the first gate layer 22G1, the energy level of the conduction band of the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 is approximately the same as or higher than the Fermi level. As a result, when a gate control voltage that turns off the first transistor 10T1 is applied to the first gate electrode 24G1 (for example, when the gate-source voltage is 0 V or lower), a 2DEG 20 is not formed in the region of the electron transit layer 16 immediately below the first gate layer 22G1. On the other hand, a 2DEG 20 is formed in the region of the electron transit layer 16 other than the region immediately below the first gate layer 22G1.

[0040] In this way, the presence of the first gate layer 22G1 doped with acceptor-type impurities causes the 2DEG 20 to disappear in the region of the electron transit layer 16 immediately below the first gate layer 22G1, thereby achieving normally-off operation of the first transistor 10T1. When an appropriate gate control voltage (on voltage) is applied to the first gate electrode 24G1, a channel is formed by the 2DEG 20 in the region of the electron transit layer 16 immediately below the first gate layer 22G1, establishing conduction between the source and drain.

[0041] In the second transistor 10T2, the second gate layer 22G2 also contains acceptor-type impurities, and therefore, a normally-off operation is realized in the second transistor 10T2 based on the same principle as in the first transistor 10T1. In the second transistor 10T2, the second gate electrode 24G2 is electrically connected (shorted) to the second source electrode 28S2. The electrical connection structure of the first and second transistors 10T1 and 10T2 will be described later.

[0042] 1, the nitride semiconductor device 10 further includes a first insulating layer 32, a wiring layer 34 formed on the first insulating layer 32, a second insulating layer 36 formed on the first insulating layer 32 so as to cover the wiring layer 34, and an electrode layer 38 formed on the second insulating layer 36. The first insulating layer 32 is formed on the passivation layer 26 so as to cover the first and second source electrodes 28S1, 28S2 and the first and second drain electrodes 30D1, 30D2.

[0043] The first and second insulating layers 32, 36 are, for example, SiO2 layers, but may be formed of other insulating materials. The wiring layer 34 is formed of a conductive material such as gold (Au), Cu, or Al. The electrode layer 38 is formed of at least one conductive material selected from the group consisting of Ti, TiN, Al, Cu, an AlCu alloy, nickel (Ni), and Au. For example, the electrode layer 38 may have a layered structure including a metal layer and a plating layer covering the metal layer. In this case, the metal layer may have a four-layer structure including, from top to bottom, a Ti layer, a TiN layer, an AlCu layer, and a TiN layer. The plating layer may have a structure in which a Cu layer, a Ni layer, and an Au layer are stacked in this order on the metal layer. The configurations of the wiring layer 34 and the electrode layer 38 will be further described below.

[0044] [1-2. Planar Layout of Nitride Semiconductor Devices] Next, the planar layout of the nitride semiconductor device 10 of the first embodiment will be described with reference to FIGS. 4 to 7. FIG. 4 is a schematic plan view showing an exemplary planar layout of the nitride semiconductor device 10. FIG. 5 is a partial enlarged plan view of the first transistor 10T1, and is an enlarged view of a region F5 indicated by a dashed-dotted line in FIG. 4. FIG. 6 is a partial enlarged plan view of the second transistor 10T2, and is an enlarged view of a region F6 indicated by a dashed-dotted line in FIG. 4. FIG. 7 is a schematic plan view showing a part of the electrode layer 38 in addition to the wiring pattern of the wiring layer 34 shown in FIG. 4.

[0045] 7, the wiring layer 34 includes, for example, a first gate wiring 42, a first source wiring 44, a first drain wiring 46, a gate wiring pad 48, and a Kelvin source wiring pad 49, which are used as wiring paths to the first transistor 10T1. The wiring layer 34 also includes a second gate wiring 52, a second source wiring 54, and a second drain wiring 56, which are used as wiring paths to the second transistor 10T2. The gate wiring pad 48 and the Kelvin source wiring pad 49 are also used as wiring paths to the second transistor 10T2.

[0046] The first gate wiring 42 includes, for example, gate wiring portions 42A, 42B, 42C, 42D, and 42E as a plurality of first gate wiring portions. The gate wiring portions 42A, 42B, 42C, and 42D and the gate wiring pad 48 are located on the outer periphery of the wiring layer 34 in a plan view and are connected to each other in a ring shape, for example, along the outer periphery of a chip (not shown) of the nitride semiconductor device 10. The gate wiring portion 42E is located, for example, between the gate wiring portions 42B and 42D. The gate wiring portions 42A, 42B, 42C, 42D, and 42E and the gate wiring pad 48 are electrically connected to each other.

[0047] For example, the gate wiring portion 42A is connected to the gate wiring pad 48 (for example, the upper right corner of the gate wiring pad 48 in FIG. 7) and extends from the gate wiring pad 48 in the second direction Y. The gate wiring portion 42B extends in the first direction X from one end (the upper end in FIG. 7) of the gate wiring portion 42A. The gate wiring portion 42C extends in the second direction Y from one end (the left end in FIG. 7) of the gate wiring portion 42B.

[0048] The gate wiring portion 42D extends in the first direction X from one end (the lower end in FIG. 7) of the gate wiring portion 42C and is connected to the gate wiring pad 48 (for example, the lower left corner of the gate wiring pad 48 in FIG. 7). The gate wiring portion 42E extends in the first direction X from an intermediate portion of the gate wiring portion 42C in the second direction Y and is connected to the gate wiring pad 48 (for example, the upper left corner of the gate wiring pad 48 in FIG. 7).

[0049] The first source wiring 44 includes, for example, source wiring portions 44A, 44B, 44C, and 44D as a plurality of first source wiring portions. The first drain wiring 46 includes, for example, drain wiring portions 46A, 46B, 46C, and 46D as a plurality of first drain wiring portions. The source wiring portions 44A, 44B, 44C, and 44D and the drain wiring portions 46A, 46B, 46C, and 46D are arranged in the first transistor region RT1. For example, the source wiring portions 44A and 44B and the drain wiring portions 46A and 46B are arranged alternately one by one in the second direction Y. Similarly, the source wiring portions 44C and 44D and the drain wiring portions 46C and 46D are arranged alternately one by one in the second direction Y. The source wiring portions 44C and 44D are connected to the Kelvin source wiring pad 49 (for example, the left edge of the Kelvin source wiring pad 49 in FIG. 7).

[0050] The second gate wiring 52 includes, as a plurality of second gate wiring portions, for example, gate wiring portions 52A and 52B. The gate wiring portions 52A and 52B are connected to the Kelvin source wiring pad 49 (for example, the right edge of the Kelvin source wiring pad 49 in FIG. 7).

[0051] The second source wiring 54 includes, for example, source wiring portions 54A and 54B as the plurality of second source wiring portions. The source wiring portions 54A and 54B are connected to the Kelvin source wiring pad 49 (for example, the right edge of the Kelvin source wiring pad 49 in FIG. 7). The second drain wiring 56 includes, for example, drain wiring portions 56A and 56B as the plurality of second drain wiring portions. The drain wiring portions 56A and 56B are connected to the gate wiring pad 48 (for example, the left edge of the gate wiring pad 48 in FIG. 7). The gate wiring portions 52A and 52B, the source wiring portions 54A and 54B, and the drain wiring portions 56A and 56B are arranged in the second transistor region RT2.

[0052] 4, the second transistor region RT2 is disposed in a position close to the gate wiring pad 48. In the example of FIG. 4, the second transistor region RT2 is disposed in a position adjacent to the gate wiring pad 48, and in particular, in the first embodiment, the second drain wiring 56 (drain wiring portions 56A and 56B) is directly connected to the gate wiring pad 48. Therefore, no other wiring (e.g., the first gate wiring 42, etc.) is interposed between the gate wiring pad 48 and the second drain wiring 56. In this configuration, the amount of heat generated in the wiring layer 34 due to the provision of the second transistor region RT2 (i.e., the second transistor 10T2) can be minimized.

[0053] In the first embodiment, the wiring layer 34 includes the Kelvin source wiring pad 49. The Kelvin source wiring pad 49 is connected between the first source wiring 44 (source wiring portions 44C and 44D in the example of FIG. 4) of the first transistor 10T1 and the second gate wiring 52 (gate wiring portions 52A and 52B) of the second transistor 10T2. As described above, the Kelvin source wiring pad 49 connects (short-circuits) the second gate wiring 52 (gate wiring portions 52A and 52B) of the second transistor 10T2 and the second source wiring 54 (source wiring portions 54A and 54B). In this manner, the Kelvin source wiring pad 49 is used in part of the wiring path connecting the first transistor 10T1 and the second transistor 10T2. In this configuration, the Kelvin source wiring pad 49 can be used to control the gate-source voltage of the first transistor 10T1. This makes it possible to suppress the influence of electromotive noise caused by parasitic inductance coupled to the source (first source electrode 28S1) of the first transistor 10T1.

[0054] 5, in the first transistor region RT1, the first gate wiring 42 (in the example of FIG. 5, gate wiring portions 42B and 42E) is connected to the first gate electrode 24G1 by a gate through conductor 42V that penetrates the first insulating layer 32 (see FIG. 1). The first source wiring 44 (in the example of FIG. 5, source wiring portions 44A and 44B) is connected to the first source electrode 28S1 by a source through conductor 44V that penetrates the first insulating layer 32 (see FIG. 1). The first drain wiring 46 (in the example of FIG. 5, drain wiring portions 46A and 46B) is connected to the first drain electrode 30D1 by a drain through conductor 46V that penetrates the first insulating layer 32 (see FIG. 1). Note that the number of gate through conductors 42V, the number of source through conductors 44V, and the number of drain through conductors 46V are not limited to those shown in FIGS. 4 and 5.

[0055] 6, in the second transistor region RT2, the second gate wiring 52 (gate wiring portions 52A and 52B) is connected to the second gate electrode 24G2 by a gate through conductor 52V that penetrates the first insulating layer 32 (see FIG. 1). The second source wiring 54 (source wiring portions 54A and 54B) is connected to the second source electrode 28S2 by a source through conductor 54V that penetrates the first insulating layer 32 (see FIG. 1). The second drain wiring 56 (drain wiring portions 56A and 56B) is connected to the second drain electrode 30D2 by a drain through conductor 56V that penetrates the first insulating layer 32 (see FIG. 1). Note that the number of gate through conductors 52V, source through conductors 54V, and drain through conductors 56V is not limited to the numbers shown in FIGS. 4 and 6.

[0056] 4, the first transistor 10T1 includes a plurality of first transistor cells 10TC1 arranged along each of the first direction X and the second direction Y. The second transistor 10T2 includes a plurality of second transistor cells 10TC2 arranged along the first direction X. Note that the planar layout of the first and second transistors 10T1 and 10T2 shown in FIG. 4 is merely an example, and the number of first transistor cells 10TC1 arranged along the first direction X, the number of first transistor cells 10TC1 arranged along the second direction Y, and the number of second transistor cells 10TC2 arranged along the first direction X may be changed as appropriate depending on transistor design conditions such as the chip size of the nitride semiconductor device 10.

[0057] As shown in Fig. 7, the electrode layer 38 includes a plurality of source electrode pads 62 (two in the example of Fig. 7) and a plurality of drain electrode pads 64 (three in the example of Fig. 7). Although not shown, the electrode layer 38 also includes a gate electrode pad. The same potential (e.g., ground voltage) is applied to the plurality of source electrode pads 62. Similarly, the same potential (e.g., power supply voltage) is applied to the plurality of drain electrode pads 64.

[0058] Each source electrode pad 62 is connected to the first source wiring 44 by a source through conductor 62V that penetrates the second insulating layer 36 (see FIG. 1). Each drain electrode pad 64 is connected to the first drain wiring 46 by a drain through conductor 64V that penetrates the second insulating layer 36 (see FIG. 1). Although not shown here, the gate electrode pad is connected to, for example, the gate wiring pad 48 by a gate through conductor that penetrates the second insulating layer 36 (see FIG. 1). Note that the planar layout of the electrode layer 38 shown in FIG. 7 is merely an example, and the number of source electrode pads 62 and the number of drain electrode pads 64 may be changed as appropriate depending on the transistor design conditions.

[0059] [1-3. Electrical Connection Between the First Transistor and the Second Transistor] Next, the electrical connection between the first transistor 10T1 and the second transistor 10T2 will be described with reference to Fig. 10, as well as Figs. 4 to 7 described above. Fig. 10 is a schematic circuit diagram showing the circuit structure of the nitride semiconductor device 10 including both the first transistor 10T1 and the second transistor 10T2, along with a charging current path PC. The charging current path PC will be described later in the section on the operation of the nitride semiconductor device 10.

[0060] As shown in FIG. 10, the first gate electrode 24G1 of the first transistor 10T1 is electrically connected to the second drain electrode 30D2 of the second transistor 10T2 by the wiring structure (FIGS. 4 to 7) including the above-mentioned wiring layer 34 and the like.

[0061] In the first embodiment, the first gate electrode 24G1 is electrically connected to the second drain electrode 30D2 by a gate through conductor 42V (see Figures 4 and 5), a first gate wiring 42 (see Figures 4, 5, and 7), a gate wiring pad 48 (see Figures 4 and 7), a second drain wiring 56 (see Figures 4, 6, and 7), and a drain through conductor 56V (see Figures 4 and 6).

[0062] Also, as shown in FIG. 10, the first source electrode 28S1 of the first transistor 10T1 is electrically connected to the second gate electrode 24G2 and the second source electrode 28S2 of the second transistor 10T2 by a wiring structure (FIGS. 4 to 7) including the above-mentioned wiring layer 34, etc.

[0063] In the first embodiment, the first source electrode 28S1 is electrically connected to the second gate electrode 24G2 by a source through conductor 44V (see Figures 4 and 5), a first source wiring 44 (in the first embodiment, source wiring portions 44C, 44D: see Figures 4 and 7), a Kelvin source wiring pad 49 (see Figures 4, 6, and 7), a second gate wiring 52 (see Figures 4, 6, and 7), and a gate through conductor 52V (see Figures 4 and 6).

[0064] Furthermore, the first source electrode 28S1 is electrically connected to the second source electrode 28S2 by a source through conductor 44V (see Figures 4 and 5), a first source wiring 44 (source wiring portions 44C, 44D in the first embodiment: see Figures 4 and 7), a Kelvin source wiring pad 49 (see Figures 4, 6, and 7), a second source wiring 54 (see Figures 4, 6, and 7), and a source through conductor 54V (see Figures 4 and 6).

[0065] [1-4. Size of the first and second transistors] Next, the size of the first transistor 10T1 and the size of the second transistor 10T2 will be described with reference to the above-mentioned FIGS.

[0066] In the nitride semiconductor device 10, the size of the second transistor 10T2 is smaller than the size of the first transistor 10T1. As shown in Figures 4 to 6, the second transistor region RT2 in which the second transistor 10T2 is arranged has an area smaller than the first transistor region RT1 in which the first transistor 10T1 is arranged. In other words, the area of ​​the second transistor region RT2 in the chip size of the nitride semiconductor device 10 (or the size of the planar layout shown in Figure 4) is smaller than the area of ​​the first transistor region RT1 in the chip size (the size of the planar layout shown in Figure 4).

[0067] For example, the area of ​​the second transistor region RT2 relative to the chip size is determined taking into consideration the on-resistance of each of the first and second transistors 10T1 and 10T2. In one example, the area of ​​the second transistor region RT2 is determined so as to suppress the on-resistance of the second transistor 10T2 to 1 Ω or less. This minimizes the reduction in the area of ​​the first transistor region RT1 relative to the chip size and suppresses an increase in the on-resistance of the first transistor 10T1 while favorably obtaining the desired functionality of the second transistor 10T2.

[0068] In addition, in the first transistor 10T1 (see FIG. 2), the first drain contact portion 30DC1 is spaced a first distance D1 from the first gate electrode 24G1, while in the second transistor 10T2 (see FIG. 3), the second drain contact portion 30DC2 is spaced a second distance D2 from the second gate electrode 24G2 that is shorter than the first distance D1.

[0069] For example, the first distance D1 and the second distance D2 are determined taking into consideration the drain-source voltages of the first and second transistors 10T1 and 10T2. For example, the drain-source voltage of the second transistor 10T2, which is connected (short-circuited) between the gate and source of the first transistor 10T1, may be sufficient if it is equal to or greater than the gate-source breakdown voltage of the first transistor 10T1. In consideration of this, the second distance D2 is set to the minimum necessary distance, shorter than the first distance D1. This further reduces the area of ​​the second transistor region RT2 relative to the chip size, thereby minimizing the reduction in the area of ​​the first transistor region RT1.

[0070] [1-5. Function of nitride semiconductor device] Next, the operation of the nitride semiconductor device 10 will be described with reference to Figures 8 to 10. Figure 8 is a schematic circuit diagram of a nitride semiconductor device 10X that does not include a second transistor 10T2 and includes only a first transistor 10T1, as a comparative example of the nitride semiconductor device 10 of the first embodiment shown in Figure 10. Figure 9 is a schematic circuit diagram showing the configuration of a typical bridge circuit 70.

[0071] The bridge circuit 70 shown in Fig. 9 is used in, for example, a DC / DC converter. The bridge circuit 70 includes a high-side transistor 72 and a low-side transistor 74 connected in series and alternately turned on and off. The high-side transistor 72 and the low-side transistor 74 are each configured using, for example, a GaN-HEMT. An output inductor Lo is connected to the connection node between the high-side transistor 72 and the low-side transistor 74, and an output capacitance Co is connected to the output inductor Lo. The high-side transistor 72 and the low-side transistor 74 are controlled by a gate driver 76.

[0072] Here, assume that during operation of the bridge circuit 70, for example, the high-side transistor 72 and the low-side transistor 74 are both off and a reflux current I1 flows through the low-side transistor 74. In this state, a voltage E is applied to the high-side transistor 72, and the voltage applied to the low-side transistor 74 is substantially 0 V.

[0073] Next, when the high-side transistor 72 is turned on, a current I2 flows through the high-side transistor 72, causing the voltage applied to the high-side transistor 72 to begin to drop to 0 V. Meanwhile, a voltage E is applied to the low-side transistor 74, causing the drain voltage of the low-side transistor 74 to rise. At this time, immediately after the high-side transistor 72 is turned on, the drain voltage of the low-side transistor 74 rises sharply.

[0074] In this manner, during a transient period in which the drain voltage of the low-side transistor 74 rises suddenly, the parasitic capacitance present between the drain and source of the low-side transistor 74 is charged. For example, if the nitride semiconductor device 10X of FIG. 8 including only the first transistor 10T1 is applied to the low-side transistor 74, the parasitic capacitance (composite capacitance) of the first transistor 10T1 is charged by a current flowing along the charging current path PCX shown in FIG. 8. As shown in FIG. 8, the parasitic capacitance (composite capacitance) of the first transistor 10T1 includes a gate-source capacitance Cgs, a gate-drain capacitance Cgd, and a drain-source capacitance Cds.

[0075] When the first transistor 10T1 (the low-side transistor 74 in FIG. 9) is in an off state, the gate-source voltage of the first transistor 10T1 is, for example, 0 V, and therefore a short circuit SC is equivalently connected between the gate and source of the first transistor 10T1. However, because this short circuit SC includes a parasitic gate resistance Rg and a parasitic inductance Lg, the short circuit SC momentarily assumes a high impedance during the transition period in which the drain voltage of the first transistor 10T1 (the low-side transistor 74 in FIG. 9) begins to rise. The parasitic gate resistance Rg is generated due to, for example, the resistance of the first gate wiring 42, etc. The parasitic inductance Lg is generated due to, for example, the resistance of a gate wire, a lead frame, etc. (not shown).

[0076] Therefore, during the above-mentioned transition period, the charging current flowing to the gate-source capacitance Cgs of the first transistor 10T1 (low-side transistor 74 in FIG. 9) hardly flows into the short circuit SC (path indicated by the dotted arrow in FIG. 8), and instead flows directly into the gate-source capacitance Cgs. This causes the gate-source voltage of the first transistor 10T1 (low-side transistor 74 in FIG. 9) to unintentionally rise during the transition period, which can cause self-turn-on in the first transistor 10T1, which uses a HEMT with a relatively low gate threshold (in this example, a GaN-HEMT).

[0077] Here, the ratio of the gate-source voltage Vgs applied to the gate-source capacitance Cgs to the gate-drain voltage Vgd applied to the gate-drain capacitance Cgd is equal to the inverse ratio of the gate-source capacitance Cgs to the gate-drain capacitance Cgd, and is expressed as follows:

[0078] Vgs:Vgd=Cgd:Cgs Therefore, during the transition period, the change amount ΔVgs of the gate-source voltage Vgs is expressed as follows using the change amount ΔVgd of the gate-drain voltage Vgd:

[0079] ΔVgs=(Cgd / Cgs) ΔVgd This indicates that a large Cgd / Cgs ratio increases the change ΔVgs, which can cause the gate-source voltage Vgs to increase unintentionally, resulting in self-turn-on. This phenomenon is particularly likely to occur when the drain-source voltage Vds of the first transistor 10T1 starts to increase from 0 V.

[0080] In consideration of this point, the nitride semiconductor device 10 of the first embodiment is configured to connect the second transistor 10T2 between the gate and source of the first transistor 10T1 to reduce the value of Cgd / Cgs, thereby substantially increasing the gate-source capacitance Cgs of the first transistor 10T1. Thus, by applying the nitride semiconductor device 10 to the low-side transistor 74, it is possible to suppress the occurrence of self-turn-on of the first transistor 10T1 (the low-side transistor 74 in FIG. 9).

[0081] 10, when the nitride semiconductor device 10 is applied to the low-side transistor 74, part of the charging current flowing through the gate-source capacitance Cgs of the first transistor 10T1 (the low-side transistor 74 in FIG. 9) bypasses the second transistor 10T2. In the first embodiment, the value of the parasitic gate resistance Rg connected to the first gate electrode 24G1 of the first transistor 10T1 is set to 0.5 Ω or less. By setting the value of the parasitic gate resistance Rg to 0.5 Ω or less in this manner, part of the charging current is preferably maintained bypassing the second transistor 10T2, allowing the second transistor 10T2 to function effectively.

[0082] In particular, the second transistor 10T2 is provided for the purpose of applying the capacitance value of the output capacitance Coss of the second transistor 10T2 between the gate and source of the first transistor 10T1. The output capacitance Coss of the second transistor 10T2 varies depending on the drain-source voltage Vds applied to the second transistor 10T2 (i.e., the gate-source voltage Vgs of the first transistor 10T1). Therefore, the second transistor 10T2 functions as a variable capacitance.

[0083] Here, the output capacitance Coss of the second transistor 10T2 has a Vds dependency, being high when the drain-source voltage Vds of the second transistor 10T2 is low and being low when the drain-source voltage Vds of the second transistor 10T2 is high. Therefore, the output capacitance Coss of the second transistor 10T2 connected between the gate and source of the first transistor 10T1 is high when the gate-source voltage Vgs of the first transistor 10T1 is near 0 V and is low when the gate-source voltage Vgs of the first transistor 10T1 is near voltage E.

[0084] Therefore, during the transient period when the drain voltage of the low-side transistor 74 (see FIG. 9) begins to rise rapidly, the output capacitance Coss of the second transistor 10T2 has a high capacitance value. This effectively increases the gate-source capacitance Cgs of the first transistor 10T1 during the transient period (decreasing Cgd / Cgs), thereby contributing to reducing the change ΔVgs in the gate-source voltage Vgs. This makes it possible to suppress the occurrence of self-turn-on.

[0085] On the other hand, as described above, when the gate-source voltage Vgs of the first transistor 10T1 rises to near voltage E, the output capacitance Coss of the second transistor 10T2 decreases, preventing the gate-source capacitance Cgs of the first transistor 10T1 from remaining increased due to the output capacitance Coss of the second transistor 10T2. This prevents the output capacitance Coss of the second transistor 10T2 from increasing power loss in the first transistor 10T1 and limiting its high-speed switching characteristics.

[0086] [1-6. Advantages of nitride semiconductor devices] The nitride semiconductor device 10 of the first embodiment has the following advantages. (1-1) The nitride semiconductor device 10 includes a first transistor 10T1 located in a first transistor region RT1 and a second transistor 10T2 located in a second transistor region RT2. A first gate electrode 24G1 of the first transistor 10T1 is electrically connected to a second drain electrode 30D2 of the second transistor 10T2. A first source electrode 28S1 of the first transistor 10T1 is electrically connected to a second gate electrode 24G2 and a second source electrode 28S2 of the second transistor 10T2.

[0087] With this configuration, the output capacitance Coss of the second transistor 10T2 is added as a variable capacitance between the gate and source of the first transistor 10T1. This output capacitance Coss (variable capacitance) has a Vds dependency, being high when the drain-source voltage Vds of the second transistor 10T2 is low and being low when the drain-source voltage Vds of the second transistor 10T2 is high. This makes it possible to suppress the occurrence of self-turn-on while maintaining good high-speed switching characteristics of the first transistor 10T1.

[0088] (1-2) The second transistor region RT2 has a smaller area than the first transistor region RT1. With this configuration, the second transistor 10T2, which functions as a variable capacitor, can be formed with a relatively small area, minimizing the reduction in the area of ​​the first transistor region RT1 relative to the chip size. This makes it possible to obtain good functionality of the second transistor 10T2 while maintaining good high-speed switching characteristics of the first transistor 10T1.

[0089] (1-3) The second distance D2 from the second gate electrode 24G2 to the second drain contact portion 30DC2 in the second transistor 10T2 is shorter than the first distance D1 from the first gate electrode 24G1 to the first drain contact portion 30DC1 in the first transistor 10T1. This configuration reduces the area of ​​the second transistor region RT2 relative to the chip size, thereby minimizing the reduction in the area of ​​the first transistor region RT1.

[0090] (1-4) The first transistor 10T1 has a parasitic gate resistance Rg of 0.5 Ω or less, which allows a portion of the charging current flowing through the gate-source capacitance Cgs of the first transistor 10T1 to be diverted to the second transistor 10T2, thereby allowing the second transistor 10T2 to function effectively.

[0091] (1-5) The second transistor region RT2 is disposed in a position close to the gate wiring pad 48. In the example of FIG. 4, the second transistor region RT2 is disposed in a position adjacent to the gate wiring pad 48, and in particular, in the first embodiment, the second drain wiring 56 (drain wiring portions 56A and 56B) is directly connected to the gate wiring pad 48. Therefore, no other wiring (e.g., the first gate wiring 42, etc.) is interposed between the gate wiring pad 48 and the second drain wiring 56. In this configuration, the amount of heat generated in the wiring layer 34 due to the provision of the second transistor region RT2 can be minimized.

[0092] (1-6) The wiring layer 34 includes a Kelvin source wiring pad 49 connected between the first source wiring 44 of the first transistor 10T1 (source wiring portions 44C and 44D in the example of FIG. 4) and the second gate wiring 52 of the second transistor 10T2 (gate wiring portions 52A and 52B). In this configuration, the gate-source voltage of the first transistor 10T1 can be controlled using the Kelvin source wiring pad 49. This makes it possible to suppress the influence of electromotive noise caused by parasitic inductance coupled to the source (first source electrode 28S1) of the first transistor 10T1.

[0093] (1-7) The nitride semiconductor device 10 is configured as a HEMT using GaN. This allows the nitride semiconductor device having the advantages of (1-1) to (1-6) above to be provided for use as a power device using a GaN-HEMT.

[0094] [Second embodiment] Next, a nitride semiconductor device according to a second embodiment will be described with reference to Figures 11 to 13. The second embodiment differs from the first embodiment in that the configurations of the first gate layer 22G1 and the second gate layer 22G2 are changed. The other configurations are the same as those of the first embodiment. Below, a description of the components similar to those of the first embodiment will be omitted, and only components different from those of the first embodiment will be described.

[0095] Fig. 11 is a schematic cross-sectional view of a nitride semiconductor device 10A according to the second embodiment. Fig. 12 is a partially enlarged cross-sectional view of a first transistor 10T1 shown on the left side of Fig. 11, and Fig. 13 is a partially enlarged cross-sectional view of a second transistor 10T2 shown on the right side of Fig. 11.

[0096] 12 , in the second embodiment, the first gate layer 22G1 of the first transistor 10T1 includes a first body region 82B1, a first source side extension region 84S1, and a first drain side extension region 86D1. The first source side extension region 84S1 extends in the first direction X from the first body region 82B1 toward the first source contact portion 28SC1. The first drain side extension region 86D1 extends in the first direction X from the first body region 82B1 toward the first drain contact portion 30DC1.

[0097] The first body region 82B1 has a ridge or rectangular (or trapezoidal) cross-sectional shape. The first gate electrode 24G1 is located on the first body region 82B1. The first source side extension region 84S1 and the first drain side extension region 86D1 each have a thickness smaller than that of the first body region 82B1. For example, the thickness of each of the first source side extension region 84S1 and the first drain side extension region 86D1 is set to be smaller than half the thickness of the first body region 82B1.

[0098] For example, the thickness of the first body region 82B1 is set to be not less than 100 nm and not more than 200 nm. Here, the thickness of the first body region 82B1 refers to the distance from the upper surface of the first body region 82B1 to the lower surface (the lower surface of the first gate layer 22G1 in contact with the electron supply layer 18) of the first body region 82B1. The thickness of the first body region 82B1 can be determined in consideration of various parameters such as the gate breakdown voltage. In contrast, the thickness of each of the first source side extension region 84S1 and the first drain side extension region 86D1 is set to be not less than 10 nm and not more than 30 nm. The thickness of the first source side extension region 84S1 and the thickness of the first drain side extension region 86D1 may be the same or different. In the second embodiment, the thickness of the first source side extension region 84S1 and the thickness of the first drain side extension region 86D1 are the same.

[0099] In the first transistor 10T1, the first source-side extension region 84S1 and the first drain-side extension region 86D1 serve to alleviate electric field concentration near the end of the first gate layer 22G1 and near the end of the first gate electrode 24G1.

[0100] 13 , in the second embodiment, the second gate layer 22G2 of the second transistor 10T2 includes a second body region 82B2, a second source side extension region 84S2, and a second drain side extension region 86D2. The second source side extension region 84S2 extends in the first direction X from the second body region 82B2 toward the second source contact portion 28SC2. The second drain side extension region 86D2 extends in the first direction X from the second body region 82B2 toward the second drain contact portion 30DC2.

[0101] The second body region 82B2 has a ridge or rectangular (or trapezoidal) cross-sectional shape. The second gate electrode 24G2 is located on the second body region 82B2. The second source side extension region 84S2 and the second drain side extension region 86D2 each have a thickness smaller than that of the second body region 82B2. For example, the thickness of each of the second source side extension region 84S2 and the second drain side extension region 86D2 is set to be smaller than half the thickness of the second body region 82B2.

[0102] For example, the thickness of the second body region 82B2 is set to be not less than 200 nm and not more than 200 nm. Here, the thickness of the second body region 82B2 refers to the distance from the upper surface of the second body region 82B2 to the lower surface (the lower surface of the second gate layer 22G2 that contacts the electron supply layer 28) of the second body region 82B2. The thickness of the second body region 82B2 can be determined in consideration of various parameters such as the gate breakdown voltage. In contrast, the thickness of each of the second source side extension region 84S2 and the second drain side extension region 86D2 is set to be not less than 10 nm and not more than 30 nm, for example. The thickness of the second source side extension region 84S2 and the thickness of the second drain side extension region 86D2 may be the same or different. In the second embodiment, the thickness of the second source side extension region 84S2 and the thickness of the second drain side extension region 86D2 are the same, and further, the thickness of the first source side extension region 84S1, the thickness of the first drain side extension region 86D1, the thickness of the second source side extension region 84S2, and the thickness of the second drain side extension region 86D2 are the same.

[0103] In the first gate layer 22G1, the first drain side extension region 86D1 is formed longer in the first direction X than the first source side extension region 84S1. Similarly, in the second gate layer 22G2, the second drain side extension region 86D2 is formed longer in the first direction X than the second source side extension region 84S2. Furthermore, in the second embodiment, the length L2 (see FIG. 13) of the second drain side extension region 86D2 is set longer than the length L1 (see FIG. 12) of the first drain side extension region 86D1. Note that the length L1 corresponds to the first length, and the length L2 corresponds to the second length.

[0104] In the second transistor 10T2, the second source-side extension region 84S2 and the second drain-side extension region 86D2 serve to alleviate electric field concentration near the end of the second gate layer 22G2 and the end of the second gate electrode 24G2. Furthermore, the second drain-side extension region 86D2 of the second transistor 10T2 contributes to increasing the value of the output capacitance Coss of the second transistor 10T2 when the gate-source voltage Vgs of the first transistor 10T1 is near 0 V (i.e., the drain-source voltage Vds of the second transistor 10T2 is near 0 V), compared to when the second drain-side extension region 86D2 is not present. Additionally, the second drain-side extension region 86D2 also contributes to increasing the amount of change in the output capacitance Coss of the second transistor 10T2 when the gate-source voltage Vgs of the first transistor 10T1 increases from near 0 V. Therefore, by satisfying the above-mentioned relationship of L2>L1, it is possible to more effectively suppress the occurrence of self-turn-on and to maintain the high-speed switching characteristics of the first transistor 10T1 in a good condition.

[0105] The nitride semiconductor device 10A of the second embodiment as described above has the following advantages in addition to the advantages (1-1) to (1-7) described in the first embodiment. (2-1) The first transistor 10T1 has the first source side extension region 84S1 and the first drain side extension region 86D1, which can reduce electric field concentration near the end of the first gate layer 22G1 and near the end of the first gate electrode 24G1.

[0106] (2-2) The second transistor 10T2 has the second source side extension region 84S2 and the second drain side extension region 86D2, which can reduce electric field concentration near the end of the second gate layer 22G2 and near the end of the second gate electrode 24G2.

[0107] (2-3) The length L2 of the second drain side extension region 86D2 is set to be greater than the length L1 of the first drain side extension region 86D1. Such a relationship of L2>L1 makes it possible to more effectively suppress the occurrence of self-turn-on and maintain favorable high-speed switching characteristics of the first transistor 10T1.

[0108] [Example of change] The above-described embodiments can be modified, for example, as follows: The above-described embodiments and the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above-described embodiments will be assigned the same reference numerals as in the above-described embodiments, and their description will be omitted.

[0109] The planar layout of FIG. 4 described in the first embodiment may be modified as shown in FIGS. 14 to 16. FIG. 14 is a schematic plan view showing the planar layout of a nitride semiconductor device 10 according to a modification, and FIG. 15 is a partially enlarged plan view of the second transistor 10T2 (second transistor region RT2) shown in FIG. 14. FIG. 16 is a schematic plan view showing the wiring pattern shown in FIG. 14. In this modification, the second transistor 10T2 (second transistor region RT2) is disposed farther away from the gate wiring pad 48 than in the first embodiment. For example, as shown in FIGS. 14 and 16, the second transistor region RT2 is disposed at a position away from the gate wiring pad 48 via a part of the first gate wiring 42 (e.g., gate wiring portions 42A and 42B). In this modification, as shown in FIGS. 15 and 16, the second drain wiring 56 includes a drain wiring portion 56C in addition to drain wiring portions 56A and 56B. The drain wiring portion 56C connects the drain wiring portions 56A and 56B to the gate wiring portion 42B. The second source wiring 54 includes a source wiring portion 54C in addition to the source wiring portions 54A and 54B. The source wiring portion 54C connects the source wiring portions 54A and 54B to the first source wiring 44.

[0110] 14 to 16, the length of the first gate wiring 42 of the first transistor 10T1 can be made shorter than in the first embodiment by the amount that the second transistor region RT2 is arranged from the gate wiring pad 48 via a portion of the first gate wiring 42 (e.g., gate wiring portions 42A and 42B). This makes it possible to reduce the parasitic gate resistance Rg coupled to the first gate electrode 24G1 of the first transistor 10T1 compared to the first embodiment. This makes it easier for current to bypass and flow to the second transistor 10T2, allowing the second transistor 10T2 to effectively exhibit its function and suppress self-turn-on.

[0111] The first and second transistors 10T1 and 10T2 are not necessarily limited to being configured such that the second distance D2 is smaller than the first distance D1. For example, the first distance D1 and the second distance D2 may be the same.

[0112] The parasitic gate resistance Rg of the first transistor 10T1 is not limited to being set to 0.5 Ω or less. The value of the parasitic gate resistance Rg (0.5 Ω or less) is a more desirable value for making it easier for current to flow through the second transistor 10T2.

[0113] In the first embodiment, the wiring layer 34 may not include the Kelvin source wiring pad 49. That is, the Kelvin source wiring pad 49 is not an essential component of the technology of the present disclosure. However, as described above, by using the Kelvin source wiring pad 49, the high-speed switching characteristics of the first transistor 10T1 can be effectively utilized. Note that although the modification shown in FIG. 14 does not include the Kelvin source wiring pad 49, for example, the area of ​​the source wiring portion 54C shown in FIG. 16 may be enlarged and used as the Kelvin source wiring pad 49.

[0114] In the second embodiment, only one of the first transistor 10T1 and the second transistor 10T2 may have a gate layer structure including the source-side extension region and the drain-side extension region as described above.

[0115] In the second embodiment, the first and second transistors 10T1 and 10T2 are not necessarily limited to being configured so that the second length L2 is greater than the first length L1. The number of source electrode pads 62 and the number of drain electrode pads 64 are not limited to those in the above embodiment.

[0116] The first and second transistors 10T1 and 10T2 are not limited to HEMTs using GaN, but may be other nitride semiconductor transistors. The term "on" as used in this disclosure includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0117] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described herein being "up" and "down" of the vertical direction. For example, the X axis direction may be the vertical direction, or the Y axis direction may be the vertical direction.

[0118] [Note] The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0119] [Appendix 1] a first nitride semiconductor layer (16); a second nitride semiconductor layer (18) located on the first nitride semiconductor layer (16) and having a band gap larger than that of the first nitride semiconductor layer (16); a third nitride semiconductor layer (22G1, 22G2) located on the second nitride semiconductor layer (18) and containing an acceptor-type impurity, a first gate layer (22G1) located in a first transistor region (RT1); a second gate layer (22G2) located in the second transistor region (RT2); the third nitride semiconductor layer (22G1, 22G2) including a first source electrode (28S1) and a first drain electrode (30D1) in contact with the second nitride semiconductor layer (18) and located in the first transistor region (RT1); a first gate electrode (24G1) located on the first gate layer (22G1); a second source electrode (28S2) and a second drain electrode (30D2) in contact with the second nitride semiconductor layer (18) and located in the second transistor region (RT2); a second gate electrode (24G2) located on the second gate layer (22G2); Equipped with the first nitride semiconductor layer (16) in the first transistor region (RT1), the second nitride semiconductor layer (18) in the first transistor region (RT1), the first gate layer (22G1), the first source electrode (28S1), the first drain electrode (30D1), and the first gate electrode (24G1) constitute a first transistor (10T1); the first nitride semiconductor layer (16) in the second transistor region (RT2), the second nitride semiconductor layer (18) in the second transistor region (RT2), the second gate layer (22G2), the second source electrode (28S2), the second drain electrode (30D2), and the second gate electrode (24G2) constitute a second transistor (10T2); the first gate electrode (24G1) is electrically connected to the second drain electrode (30D2); The nitride semiconductor device (10; 10A), wherein the first source electrode (28S1) is electrically connected to the second gate electrode (24G2) and the second source electrode (28S2).

[0120] [Appendix 2] The nitride semiconductor device (10; 10A) according to Supplementary Note 1, wherein the second transistor region (RT2) has an area smaller than that of the first transistor region (RT1).

[0121] [Appendix 3] the first source electrode (28S1) includes a first source contact portion (28SC1) in contact with the second nitride semiconductor layer (18), and the first drain electrode (30D1) includes a first drain contact portion (30DC1) in contact with the second nitride semiconductor layer (18); the second source electrode (28S2) includes a second source contact portion (28SC2) in contact with the second nitride semiconductor layer (18), and the second drain electrode (30D2) includes a second drain contact portion (30DC2) in contact with the second nitride semiconductor layer (18); the first gate electrode (24G1) is located between the first source contact portion (28SC1) and the first drain contact portion (30DC1), and the first drain contact portion (30DC1) is spaced apart from the first gate electrode (24G1) by a first distance (D1); the second gate electrode (24G2) is located between the second source contact portion (28SC2) and the second drain contact portion (30DC2), and the second drain contact portion (30DC2) is spaced apart from the second gate electrode (24G2) by a second distance (D2); The nitride semiconductor device (10; 10A) according to appendix 1 or 2, wherein the second distance (D2) is shorter than the first distance (D1).

[0122] [Appendix 4] The nitride semiconductor device (10; 10A) according to Appendix 1 or 2, wherein the first transistor (10T1) has a parasitic gate resistance (Rg) of 0.5Ω or less.

[0123] [Appendix 5] the first source electrode (28S1) includes a first source contact portion (28SC1) in contact with the second nitride semiconductor layer (18), and the first drain electrode (30D1) includes a first drain contact portion (30DC1) in contact with the second nitride semiconductor layer (18); The first gate layer (22G1) is a first body region (82B1); a first source side extension region (84S1) extending from the first body region (82B1) toward the first source contact portion (28SC1); a first drain side extension region (86D1) extending from the first body region (82B1) toward the first drain contact portion (30DC1), The nitride semiconductor device (10A) according to any one of claims 1 to 4, wherein the thickness of each of the first source side extension region (84S1) and the first drain side extension region (86D1) is smaller than the thickness of the first body region (82B1).

[0124] [Appendix 6] The first gate layer (22G1) is a first body region (82B1); a first source side extension region (84S1) extending from the first body region (82B1) toward the first source contact portion (28SC1); a first drain side extension region (86D1) extending from the first body region (82B1) toward the first drain contact portion (30DC1), The nitride semiconductor device (10A) according to Appendix 3, wherein the thickness of each of the first source side extension region (84S1) and the first drain side extension region (86D1) is smaller than the thickness of the first body region (82B1).

[0125] [Appendix 7] the second source electrode (28S2) includes a second source contact portion (28SC2) in contact with the second nitride semiconductor layer (18), and the second drain electrode (30D2) includes a second drain contact portion (30DC2) in contact with the second nitride semiconductor layer (18); The second gate layer (22G2) is a second body region (82B2); a second source side extension region (84S2) extending from the second body region (82B2) toward the second source contact portion (28SC2); a second drain side extension region (86D2) extending from the second body region (82B2) toward the second drain contact portion (30DC2), The nitride semiconductor device (10A) according to any one of claims 1, 2, 4, and 5, wherein the thickness of each of the second source side extension region (84S2) and the second drain side extension region (86D2) is smaller than the thickness of the second body region (82B2).

[0126] [Appendix 8] The second gate layer (22G2) is a second body region (82B2); a second source side extension region (84S2) extending from the second body region (82B2) toward the second source contact portion (28SC2); a second drain side extension region (86D2) extending from the second body region (82B2) toward the second drain contact portion (30DC2), The nitride semiconductor device (10A) according to Supplementary Note 3, wherein the thickness of each of the second source side extension region (84S2) and the second drain side extension region (86D2) is smaller than the thickness of the second body region (82B2).

[0127] [Appendix 9] the first source electrode (28S1) includes a first source contact portion (28SC1) in contact with the second nitride semiconductor layer (18), and the first drain electrode (30D1) includes a first drain contact portion (30DC1) in contact with the second nitride semiconductor layer (18); the second source electrode (28S2) includes a second source contact portion (28SC2) in contact with the second nitride semiconductor layer (18), and the second drain electrode (30D2) includes a second drain contact portion (30DC2) in contact with the second nitride semiconductor layer (18); The first gate layer (22G1) is a first body region (82B1); a first source side extension region (84S1) extending from the first body region (82B1) toward the first source contact portion (28SC1); a first drain side extension region (86D1) extending from the first body region (82B1) toward the first drain contact portion (30DC1), a thickness of each of the first source side extension region (84S1) and the first drain side extension region (86D1) is smaller than a thickness of the first body region (82B1); The second gate layer (22G2) is a second body region (82B2); a second source side extension region (84S2) extending from the second body region (82B2) toward the second source contact portion (28SC2); a second drain side extension region (86D2) extending from the second body region (82B2) toward the second drain contact portion (30DC2), a thickness of each of the second source side extension region (84S2) and the second drain side extension region (86D2) is smaller than a thickness of the second body region (82B2); the first drain-side extension region (86D1) extends a first length (L1) from the first body region (82B1); the second drain-side extension region (86D2) extends a second length (L2) from the second body region (82B2); The nitride semiconductor device (10A) according to any one of claims 1 to 4, wherein the second length (L2) is greater than the first length (L1).

[0128] [Appendix 10] The first gate layer (22G1) is a first body region (82B1); a first source side extension region (84S1) extending from the first body region (82B1) toward the first source contact portion (28SC1); a first drain side extension region (86D1) extending from the first body region (82B1) toward the first drain contact portion (30DC1), a thickness of each of the first source side extension region (84S1) and the first drain side extension region (86D1) is smaller than a thickness of the first body region (82B1); The second gate layer (22G2) is a second body region (82B2); a second source side extension region (84S2) extending from the second body region (82B2) toward the second source contact portion (28SC2); a second drain side extension region (86D2) extending from the second body region (82B2) toward the second drain contact portion (30DC2), a thickness of each of the second source side extension region (84S2) and the second drain side extension region (86D2) is smaller than a thickness of the second body region (82B2); the first drain-side extension region (86D1) extends a first length (L1) from the first body region (82B1); the second drain-side extension region (86D2) extends a second length (L2) from the second body region (82B2); The nitride semiconductor device (10A) according to Appendix 3, wherein the second length (L2) is greater than the first length (L1).

[0129] [Appendix 11] a first gate wiring (42) electrically connected to the first gate electrode (24G1); a first source wiring (44) electrically connected to the first source electrode (28S1); a first drain wiring (46) electrically connected to the first drain electrode (30D1); a gate wiring pad (48) connected to the first gate wiring (46); Furthermore, The nitride semiconductor device (10) according to any one of appendices 1 to 10, wherein the second transistor region (RT2) is disposed at a position adjacent to the gate wiring pad (48).

[0130] [Appendix 12] a second gate wiring (52) electrically connected to the second gate electrode (24G2); a second source wiring (54) electrically connected to the second source electrode (28S2); a second drain wiring (56) electrically connected to the second drain electrode (30D2); a Kelvin source wiring pad (49) connected between the first source wiring (44) and the second gate wiring (52); 12. The nitride semiconductor device (10) according to claim 11, further comprising:

[0131] [Appendix 13] a first gate wiring (42) electrically connected to the first gate electrode (24G1); a first source wiring (44) electrically connected to the first source electrode (28S1); a first drain wiring (46) electrically connected to the first drain electrode (30D1); a gate wiring pad (48) connected to the first gate wiring (46); Furthermore, The nitride semiconductor device (10) according to any one of appendices 1 to 10, wherein the second transistor region (RT2) is arranged at a position via a part of the first gate wiring (42). [Explanation of symbols]

[0132] 10, 10A...Nitride semiconductor device 10T1...first transistor 10TC1...first transistor cell 10T2...Second transistor 10TC2...Second transistor cell 11...Back electrode 12...Semiconductor substrate 14...Buffer layer 16...Electron transit layer (first nitride semiconductor layer) 18...Electron supply layer (second nitride semiconductor layer) 20...2DEG 22G1...first gate layer (third nitride semiconductor layer) 22G2: Second gate layer (third nitride semiconductor layer) 24G1...First gate electrode 24G2...Second gate electrode 26...passivation layer 26S1...First source opening 26D1...First drain opening 26S2...Second source opening 26D2...Second drain opening 28S1...First source electrode 28SC1...First source contact 28SF1: First source field plate 28E1...First field plate edge 30D1...first drain electrode 30DC1...First drain contact part 28S2...Second source electrode 28SC2...Second source contact part 28SF2: Second source field plate 28E2...Second field plate edge 30D2...second drain electrode 30DC2...Second drain contact part 32...First insulating layer 34...Wiring layer 36...Second insulating layer 38...electrode layer 42...First gate wiring 42A, 42B, 42C, 42D, 42E...Gate wiring section 42V...Gate through conductor 44...First source wiring 44A, 44B, 44C, 44D...Source wiring section 44V...Source through conductor 46...First drain wiring 46A, 46B, 46C, 46D...Drain wiring section 46V...Drain through conductor 48...Gate wiring pad 49...Kelvin source wiring pad 52...Second gate wiring 52A, 52B...Gate wiring section 52V...Gate through conductor 54...Second source wiring 54A, 54B...Source wiring section 54V...Source through conductor 56...Second drain wiring 56A, 56B...Drain wiring section 56V...Drain through conductor 62...Source electrode pad 62V...Source through conductor 64...Drain electrode pad 64V...Drain through conductor 70...Bridge circuit 72...High-side transistor 74...Low-side transistor 76...Gate driver 82B1…1st body area 84S1...First source side extension area 86D1...1st drain side extension area 82B2…Second body area 84S2…Second source side extension area 86D2…Second drain side extension area RT1: First transistor region RT2: Second transistor region D1: First distance D2…Second distance L1...First length L2: Second length X…first direction Y...Second direction

Claims

1. a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a third nitride semiconductor layer located on the second nitride semiconductor layer and containing an acceptor-type impurity, a first gate layer located in the first transistor region; a second gate layer located in the second transistor region; the third nitride semiconductor layer comprising: a first source electrode and a first drain electrode in contact with the second nitride semiconductor layer and located in the first transistor region; a first gate electrode located on the first gate layer; a second source electrode and a second drain electrode in contact with the second nitride semiconductor layer and located in the second transistor region; a second gate electrode located on the second gate layer; Equipped with the first nitride semiconductor layer in the first transistor region, the second nitride semiconductor layer in the first transistor region, the first gate layer, the first source electrode, the first drain electrode, and the first gate electrode constitute a first transistor; the first nitride semiconductor layer in the second transistor region, the second nitride semiconductor layer in the second transistor region, the second gate layer, the second source electrode, the second drain electrode, and the second gate electrode constitute a second transistor; the first gate electrode is electrically connected to the second drain electrode; the first source electrode is electrically connected to the second gate electrode and the second source electrode.

2. The nitride semiconductor device according to claim 1 , wherein said second transistor region has an area smaller than that of said first transistor region.

3. the first source electrode includes a first source contact portion in contact with the second nitride semiconductor layer, and the first drain electrode includes a first drain contact portion in contact with the second nitride semiconductor layer; the second source electrode includes a second source contact portion in contact with the second nitride semiconductor layer, and the second drain electrode includes a second drain contact portion in contact with the second nitride semiconductor layer; the first gate electrode is located between the first source contact portion and the first drain contact portion, and the first drain contact portion is spaced a first distance from the first gate electrode; the second gate electrode is located between the second source contact portion and the second drain contact portion, and the second drain contact portion is spaced a second distance from the second gate electrode; The nitride semiconductor device according to claim 1 , wherein said second distance is shorter than said first distance.

4. The nitride semiconductor device according to claim 1 , wherein said first transistor has a parasitic gate resistance of 0.5Ω or less.

5. the first source electrode includes a first source contact portion in contact with the second nitride semiconductor layer, and the first drain electrode includes a first drain contact portion in contact with the second nitride semiconductor layer; The first gate layer is a first body region; a first source side extension region extending from the first body region toward the first source contact portion; a first drain side extension region extending from the first body region toward the first drain contact portion, a thickness of each of the first source side extension region and the first drain side extension region is smaller than a thickness of the first body region; The nitride semiconductor device according to claim 1 .

6. the second source electrode includes a second source contact portion in contact with the second nitride semiconductor layer, and the second drain electrode includes a second drain contact portion in contact with the second nitride semiconductor layer; The second gate layer is a second body region; a second source side extension region extending from the second body region toward the second source contact portion; a second drain side extension region extending from the second body region toward the second drain contact portion, The nitride semiconductor device according to claim 1 , wherein the second source side extension region and the second drain side extension region each have a thickness smaller than a thickness of the second body region.

7. the first source electrode includes a first source contact portion in contact with the second nitride semiconductor layer, and the first drain electrode includes a first drain contact portion in contact with the second nitride semiconductor layer; the second source electrode includes a second source contact portion in contact with the second nitride semiconductor layer, and the second drain electrode includes a second drain contact portion in contact with the second nitride semiconductor layer; The first gate layer is a first body region; a first source side extension region extending from the first body region toward the first source contact portion; a first drain side extension region extending from the first body region toward the first drain contact portion, a thickness of each of the first source side extension region and the first drain side extension region is smaller than a thickness of the first body region; The second gate layer is a second body region; a second source side extension region extending from the second body region toward the second source contact portion; a second drain side extension region extending from the second body region toward the second drain contact portion, a thickness of each of the second source side extension region and the second drain side extension region is smaller than a thickness of the second body region; the first drain-side extension region extends a first length from the first body region; the second drain-side extension region extends a second length from the second body region; The nitride semiconductor device according to claim 1 , wherein said second length is greater than said first length.

8. a first gate wiring electrically connected to the first gate electrode; a first source wiring electrically connected to the first source electrode; a first drain wiring electrically connected to the first drain electrode; a gate wiring pad connected to the first gate wiring; Furthermore, The nitride semiconductor device according to claim 1 , wherein said second transistor region is disposed at a position adjacent to said gate wiring pad.

9. a second gate wiring electrically connected to the second gate electrode; a second source wiring electrically connected to the second source electrode; a second drain wiring electrically connected to the second drain electrode; a Kelvin source wiring pad connected between the first source wiring and the second gate wiring; The nitride semiconductor device according to claim 8 , further comprising:

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