Factor analysis support device and factor analysis support method

Abstract

To automate a statistical processing in an analysis of a factor of them, make efficient of an analysis of a factor, and reduce a labor of an analyzer when an electrical characteristic defect or an abnormality occurs in a pre-process of a manufacturing process of a power semiconductor.SOLUTION: A factor analysis support device includes one or more processors, and one or more memory resources. The factor analysis support device supports a factor analysis of an electrical characteristic defect occurring in a product chip of a power semiconductor in a manufacturing process of the power semiconductor chip. A wafer in which the product chips are formed at a plurality of positions includes TEGs formed at a plurality of positions different from the product chips, and a memory resource (14) has inspection data which is a result of performing an electrical characteristic inspection on the product chips, and a WAT data which is a result of performing a plurality of tests on the TEGs. A processor (13) analyzes a correlation between the WAT data and the inspection data for each TEG, and outputs an evaluation index indicating a priority order as a candidate of a factor causing a defect in the inspection data and a test item corresponding to the WAT data corresponding to an evaluation index.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a factorial analysis support device and a factorial analysis support method. [Background technology]

[0002] The manufacturing process for power semiconductors is divided into a front-end process in which circuits consisting of minute chips (dies) are formed using silicon or silicon carbide as a base material, and a back-end process in which these chips are cut out and assembled into modules. In the front-end process, several hundred processes are carried out in succession, including film deposition, etching, and ion implantation. Once the front-end manufacturing process is complete, electrical characteristics tests are conducted on each individual chip. This electrical characteristics test evaluates whether each chip on the wafer complies with the product specifications. Chips that are determined to be non-conforming do not proceed to the back-end process and are treated as defective products, so improving the quality of electrical characteristics in the front-end process is an important factor that directly contributes to improving the overall yield.

[0003] However, due to the complexity and continuity of the pre-processing, it is difficult to identify the causes of electrical property defects and implement countermeasures. Furthermore, investigating the causes of these defects requires the deep knowledge and know-how of experienced analysts. For this reason, manufacturing sites need a system that can efficiently analyze electrical property test data and help identify the causes, without relying on the analytical skills of analysts.

[0004] For example, Patent Document 1 discloses a TEG test that measures device characteristics of a TEG (Test Element Group), which is a circuit dedicated to measuring various characteristics formed in the gap between chips, rather than the chip itself; an inspection data analysis program that aims to provide a technology for automatically narrowing down inspection items with significant variations in inspection data, a process for reading inspection data comprising multiple measurement items measured at multiple locations on multiple inspection objects, a process for testing the significant differences in the inspection data for each measurement location for each measurement item, and a process for displaying the inspection data for each measurement item selected based on the significant differences on a display device. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-142384 Summary of the Invention [Problem to be solved by the invention]

[0006] The program described in Patent Document 1 uses a display format that allows visual identification of significant differences at each measurement point, such as changes in brightness and saturation (shading and color coding) and box-and-whisker plots, to clearly communicate to the operator (analyst) which measurement points have significant variations. However, the technology in Patent Document 1 evaluates in-plane variations using inspection data from a TEG formed nearby, rather than from the thin-film device to be shipped as a product, making it difficult to determine whether the TEG measurement values ​​and their variations are related to defective electrical characteristics of the actual product device.

[0007] In the manufacturing of semiconductor devices, including power semiconductors, TEG chip inspections are conducted to perform intermediate evaluations of wafer quality at each stage of the manufacturing process. Measurement values ​​from these inspections include, for example, film thickness after etching. There are dozens of TEG inspection items, and these types vary from product to product. Furthermore, multiple pieces of equipment may be used for a single manufacturing process. Therefore, matching the TEG inspection measurement items with the manufacturing process and the equipment used requires advanced know-how regarding product design and manufacturing processes.

[0008] In the case of the technology described in Patent Document 1, the user (analyst) performs an in-depth analysis to determine which manufacturing process and which equipment the root cause is in, relying on TEG test items with significant within-wafer variations in characteristic values. Therefore, in order for the analyst to perform an in-depth analysis, he or she needs to investigate which manufacturing process and equipment are related based on the extracted TEG test items. Therefore, it is difficult and time-consuming for the user to determine which manufacturing process or equipment is responsible for the cause of the characteristic defects in the product device.

[0009] The present disclosure has been made in consideration of the above-mentioned problems, and aims to automate statistical processing in analyzing the causes of electrical characteristic defects or abnormalities that occur in the upstream steps of the power semiconductor manufacturing process, thereby making the analysis of the causes more efficient and reducing the labor required by analysts. [Means for solving the problem]

[0010] In order to solve the above problems, the factor analysis support device of the present disclosure has one or more processors and one or more memory resources, and is a device that supports the analysis of the causes of electrical characteristic defects that occur in product chips of power semiconductors during the manufacturing process of power semiconductor chips, wherein a wafer on which the product chips are formed at multiple positions includes TEGs formed at multiple positions different from the product chips, and the memory resource has test data that is the result of conducting an electrical characteristic test on the product chips and WAT data that is the result of conducting multiple tests on the TEGs, and the processor analyzes the correlation between the WAT data and the test data for each TEG, and outputs an evaluation index that represents the priority of candidate factors that cause the test data to be defective, and test items that correspond to the WAT data that corresponds to the evaluation index. [Effects of the Invention]

[0011] According to the present disclosure, when electrical characteristic defects or abnormalities occur in the upstream process of the power semiconductor manufacturing process, statistical processing in the analysis of the causes can be automated, the analysis of the causes can be made more efficient, and the labor of the analyst can be reduced, thereby improving the quality and yield of power semiconductor modules.

[0012] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is an overall configuration diagram showing a system including a factorial analysis support device according to an embodiment; [Figure 2] 1 is a diagram showing the layout of product chips in a wafer that is a target in the factor analysis support device according to the embodiment; [Figure 3] FIG. 10 shows two types of wafers with different chip positions and different numbers and positions of TEGs. [Figure 4] 10 is a table showing the test results for each chip. [Figure 5] 1 is a table showing the results of various WAT tests on wafers. [Figure 6] 13 is a flowchart showing the processing in the data extraction unit 1302, the data combination unit 1303, and the factor analysis execution unit 1304 in FIG. [Figure 7] FIG. 10 is a diagram showing an example of a correspondence relationship between a TEG ID and a product chip ID. [Figure 8] FIG. 7 is a diagram showing an example of a data table that combines WAT data of a TEG and characteristic value inspection data of a product chip linked to the TEG, which is processed in step S605 of FIG. 6. [Figure 9] FIG. 10 is a diagram showing another example of the correspondence between the TEG ID and the product chip ID. [Figure 10] 10 is a flowchart showing the processing in a factor analysis execution unit 1304 of FIG. [Figure 11] FIG. 10 is a diagram showing a summary of simple correlation plots obtained as a result of simple correlation analysis between WAT test items and user-specified characteristic test items. [Figure 12] FIG. 7 is a diagram showing an example of a data table stored in the WAT-manufacturing process DB 1410 in step S607 of FIG. [Figure 13]FIG. 2 is a diagram showing an example of a data table stored in a manufacturing process-equipment DB 1409 of FIG. [Figure 14] 10 is a flowchart showing the processing in the machine difference analysis execution unit 1305 of FIG. [Figure 15] 1. FIG. 4 is a diagram showing an example of a screen displayed to a user on the display unit 17 of FIG. [Figure 16] 16 is a diagram showing an example of a screen displayed on the display unit 17 of FIG. 1 as a result of transition from the screen shown in FIG. 15. FIG. [Figure 17] 17 is a diagram showing an example of a screen displayed on the display unit 17 of FIG. 1 as a result of transition from the screen shown in FIG. 16. FIG. [Figure 18] 18 is a diagram showing an example of a screen displayed on the display unit 17 of FIG. 1 as a result of transition from the screen shown in FIG. 17. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present disclosure relates to a technology for improving the quality and yield of electrical characteristic inspections of power semiconductor devices, in which inspection data is analyzed by an information processing device to narrow down causes of defects and present the results to an operator.

[0015] Examples of the present disclosure will be described below with reference to the drawings. The examples are merely illustrative of the present disclosure, and appropriate omissions and simplifications have been made for clarity. The present disclosure can be implemented in various other forms. Unless otherwise specified, each component may be singular or plural. The position, size, shape, and range of each component shown in the drawings may not represent the actual position, size, shape, and range in order to facilitate understanding of the invention. Therefore, the present disclosure is not necessarily limited to the position, size, shape, and range disclosed in the drawings. While various types of information may be described using terms such as "table," "list," and "queue," these types of information may also be expressed using other data structures. For example, various types of information such as "XX table," "XX list," and "XX queue" may also be referred to as "XX information." When describing identification information, terms such as "identification information," "identifier," "name," "ID," and "number" are used, but these terms are interchangeable. In all drawings illustrating the embodiments, identical components are generally designated by the same reference numerals, and repeated description thereof will be omitted. Furthermore, in the following examples, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Furthermore, when it is stated that "comprises A," "consists of A," "is made of A," "has A," or "includes A," other elements are not excluded unless otherwise specified to refer to only that element. Similarly, in the following examples, when referring to the shape, positional relationship, etc. of components, etc., it includes those that are substantially similar or similar to that shape, etc., unless otherwise specified or considered to be clearly not essential in principle. In each drawing, the same components are denoted by the same reference numerals, and detailed descriptions of overlapping parts are omitted. [Example]

[0016] 1 to 18, an apparatus and a method for supporting a user in performing factor analysis on a manufacturing process of a power semiconductor will be described. In the following description, the apparatus will be referred to as a "factor analysis support apparatus" and the method will be referred to as a "factor analysis support method."

[0017] FIG. 1 is a diagram showing the overall configuration of a system including a factorial analysis support device according to this embodiment.

[0018] As shown in Fig. 1, the system of this embodiment mainly comprises a manufacturing facility 10 and a computer server 12. The computer server 12 is a factor analysis support device. The manufacturing facility 10 and the computer server 12 are connected via a communication network 11, enabling data communication between them. The communication network 11 is, for example, the Internet, a LAN (Local Area Network), or a WAN (Wide Area Network).

[0019] The manufacturing facility 10 includes a manufacturing device 1001 , a characteristic inspection device 1002 , and a WAT ​​device 1003 .

[0020] The manufacturing equipment 1001 is manufacturing equipment related to the front-end process of power semiconductors, and includes, for example, an etcher that etches wafers, a cleaning device that cleans foreign matter from the wafer surface, and an ion implanter that injects impurities into the wafer to change its electrical characteristics. A wafer is a thin, disk-shaped piece of silicon from which semiconductor devices are manufactured. Multiple semiconductor devices formed on a wafer are sometimes called "chips" or "product chips."

[0021] The characteristic inspection equipment 1002 is a semiconductor parametric analyzer or an LCR meter that measures static characteristics such as on-resistance and threshold voltage, and dynamic characteristics such as switching time and capacitance characteristics, of devices on a completed wafer after all processing has been completed in the manufacturing equipment 1001. The measured values ​​measured by the characteristic inspection equipment 1002 are judged as pass or fail based on the standards established for each product type, and are sent to and stored in a specific database (described later) in the computer server 12 together with the measured values ​​and pass / fail information. In the description of this embodiment, data related to the measured values ​​measured by the characteristic inspection equipment may be referred to as "characteristic value inspection data." The characteristic value inspection data may also be simply referred to as "inspection data."

[0022] The WAT device 1003 will now be described. The WAT (Wafer Acceptance Test) is a test that performs intermediate evaluation of the quality of semiconductor devices formed on a wafer during the manufacturing process, unlike a characteristic inspection of product chips on a completed wafer.

[0023] In this embodiment, characteristic testing is performed on product chips on a finished wafer, but the WAT is not performed on the product chips but on a TEG (Test Elements Group) formed on the wafer at a location that does not overlap the product chips. The TEG has test structures designed on the wafer and has circuits that are different from those of the product chips. This allows it to obtain information about the manufacturing process that cannot be obtained by characteristic testing of the product chips, and is used for process monitoring and evaluation.

[0024] WAT items include physical property tests such as wafer flatness and film thickness, as well as electrical property tests of the circuits formed on the wafer. Measurement values ​​obtained by WAT are used for early detection of defective products and process improvement. A WAT device is a device that performs WAT and includes a probing machine, inspection microscope, optical inspection system, Ellipson meter, etc. Data related to measurements obtained by a WAT ​​device is sometimes called "WAT data."

[0025] The components of the computer server 12 will now be described.

[0026] The computer server 12 comprises a calculation unit 13 (processor), a storage unit 14 (memory resource), a communication unit 15, an input unit 16, and a display unit 17. Although Fig. 1 shows an example in which the calculation unit 13, storage unit 14, input unit 16, and display unit 17 are installed within the computer server 12, they may be installed in separate locations and interconnected via a network or the like.

[0027] The calculation unit 13 includes a data storage execution unit 1301 , a data extraction unit 1302 , a data combination unit 1303 , a factor analysis execution unit 1304 , an instrument difference analysis execution unit 1305 , and a result display execution unit 1306 .

[0028] The storage unit 14 has a data saving program 1400, a data extraction program 1401, a data linking program 1402, a factor analysis program 1403, an machine difference analysis program 1404, a display program 1405, an in-wafer chip position DB 1406, a WAT ​​measurement value DB 1407, a characteristic value inspection DB 1408, a manufacturing process-equipment DB 1409, and a WAT-manufacturing process DB 1410. Here, "DB" is an abbreviation for database.

[0029] The communication unit 15 communicates data between the manufacturing equipment 10 and the computer server 12 via the communication network 11. The input unit 16 and the display unit 17 may be a personal computer (PC), a mobile terminal such as a smartphone, or the like. The user inputs data using a mouse, keyboard, or the like in the case of a PC, or a touch panel, or the like in the case of a mobile terminal such as a smartphone. A touch panel, or the like, may also be used in the case of a PC. The display unit 17 has a monitor. The display unit 17 may also be configured to project an image onto a screen, a wall surface, or the like.

[0030] Below, an overview of the processing of the computer server 12 will be explained using each component of the calculation unit 13 and the storage unit 14. Details of each process will be described later using other figures.

[0031] The data storage execution unit 1301 stores various measurement values ​​and pass / fail judgment results output from the characteristic inspection device 1002 and the WAT device 1003 in a characteristic value inspection DB 1408 and a WAT ​​measurement value DB 1407 via the communication network 11 and the communication unit 15. The programs corresponding to the execution contents of the data storage execution unit 1301 are stored in a data storage program 1400.

[0032] The data extraction unit 1302 extracts data corresponding to the information input by the user from various data stored in a WAT ​​measurement value DB 1407, a characteristic value inspection DB 1408, a manufacturing process-equipment DB 1409, a WAT-manufacturing process DB 1410, and an in-wafer chip position DB 1406, in accordance with the information input by the user through the input unit 16. A program corresponding to the execution contents of the data extraction unit 1302 is stored in a data extraction program 1401.

[0033] The data combining unit 1303 combines WAT data extracted from a WAT ​​measurement value DB 1407 and characteristic value inspection data extracted from a characteristic value inspection DB 1408 based on chip coordinate position information within a wafer stored in an intra-wafer chip position DB 1406 and information input by a user through the input unit 16. A program corresponding to the execution contents of data combining is stored in a data combining program 1402.

[0034] The factor analysis execution unit 1304 executes a factor analysis program 1403, which is a program corresponding to the execution content of the factor analysis, and performs the factor analysis described later with reference to FIG. 6 based on information input by the user via the input unit 16.

[0035] The machine difference analysis execution unit 1305 executes a machine difference analysis program 1404, which is a program corresponding to the execution contents of the machine difference analysis, and performs a factor analysis, which will be described later with reference to FIG. 14, based on information input by the user via the input unit 16.

[0036] The result display execution unit 1306 visually outputs the information output by the factor analysis execution unit 1304, the information output by the machine difference analysis execution unit 1305, and information related to the GUI included in the display program 1405 to the display unit 17. A program corresponding to the execution content of the result display is saved in the display program 1405.

[0037] FIG. 2 is a diagram showing the layout of product chips in a wafer that is the subject of the factor analysis support device according to this embodiment.

[0038] In this diagram, wafers identified by wafer numbers (W01, W02, ..., W25) are manufactured for each manufacturing lot (LOT) of power semiconductors. The manufacturing lots are identified by lot numbers (01 to 04). Of the manufacturing lot with lot number 01, wafer 203 with wafer number W01 is selected.

[0039] Product chips 204 (semiconductor devices) identified by chip numbers (1 to 81) are formed on the wafer 203. TEGs 205 are also formed at positions on the wafer 203 different from the product chips 204. The TEGs 205 are identified by symbols A to E. The chip numbers and the symbols of the TEGs 205 correspond to two-dimensional coordinates (X axis, Y axis). A diagram showing the product chips 204 and TEGs 205 on the wafer 203 in this way is also referred to as a "wafer map" in this specification. The above two-dimensional coordinates are also referred to as "coordinate data."

[0040] The chip number may be written as "chip ID" or "CHIPID", and the wafer number as "wafer ID". The position and number of chips within a wafer, and the number and position of TEGs, vary depending on the product type.

[0041] FIG. 3 shows two types of wafers that differ in the position of the chips and the number and position of the TEGs.

[0042] This figure shows a wafer map 301 for product type B001 and a wafer map 302 for product type C001. In wafer map 301 for product type B001, product chips with chip numbers 1 to 81 are formed within the wafer, and TEGs are arranged at positions marked with symbols A to E. On the other hand, in wafer map 302 for product type C001, product chips with chip numbers 1 to 83 are formed, and TEGs are arranged at positions marked with symbols A to C. In this way, the positions and number of TEGs differ for each manufactured product type.

[0043] FIG. 4 is a table showing the test results for each chip.

[0044] This figure shows the results of inspections performed by a characteristic inspection device for each chip corresponding to the wafer ID and chip ID of production lot 01 of product type A001. The inspection items are dynamic characteristic inspection A, dynamic characteristic inspection B, and static characteristic inspection A.

[0045] The table shown in this figure is also called a "characteristic value inspection data table." The characteristic value inspection data included in this table, which corresponds to the product chip type, manufacturing lot, wafer number, and chip number, is created by the data saving execution unit 1301 in Figure 1 and is sequentially saved in the characteristic value inspection DB 1408. Note that while Figure 4 shows the case of product type A001 and manufacturing lot 01, other product type names and manufacturing lots may also be stored.

[0046] FIG. 5 is a table showing the results of various WAT tests on wafers.

[0047] This figure shows a data table in which various WAT inspection items are linked to each wafer ID included in production LOT 01 of product type A001. This data table may be called a "WAT data table."

[0048] As shown in wafer 203 (FIG. 2), a total of five TEGs are arranged within the wafer for product type A001. Then, for each TEG, ten types of WAT corresponding to the manufacturing process are performed by WAT device 1003 (FIG. 1). Therefore, the WAT data table in FIG. 5 also shows the measurement values ​​of ten types of WAT test items for the five TEGs within the wafer. The WAT data table is sequentially stored in WAT measurement value DB 1407 by data storage execution unit 1301 in FIG. 1.

[0049] 5 shows the case of product type A001 and production lot 01, but the WAT data table may store other product types and production lots. There is also no limit to the number of WAT test items or TEGs.

[0050] Fig. 6 is a flowchart showing the processing in the data extraction unit 1302, data combination unit 1303, and factor analysis execution unit 1304 in Fig. 1. In the following description, the reference numerals shown in Fig. 1 will be used as appropriate.

[0051] 6, when the program of the factor analysis execution unit 1304 is executed, user-specified information regarding the type, manufacturing lot, and electrical characteristic inspection items is input through the input unit 16 (step S601). Next, characteristic value inspection data corresponding to the user-specified type, manufacturing lot, and characteristic inspection items are extracted from the characteristic value inspection DB 1408, and WAT data is extracted from the WAT measurement value DB 1407 (step S602). Next, chip position information within the wafer for the user-specified type is extracted from the chip position within the wafer DB 1406 (step S603). Next, while checking the information displayed on the display unit 17, the user associates the TEG with the associated product chip ID for each TEG ID, and inputs the associated information to the data combining unit 1303 through the input unit 16 (step S604).

[0052] The TEG ID is an identification code for the TEG. The linking of the TEG with the associated product chip ID will be described later with reference to FIGS. 7 and 9.

[0053] Next, the data combining unit 1303 combines the WAT data with the characteristic value inspection data of the product chips associated with the TEG for each TEG ID based on the information linking the TEG with the associated product chip ID (step S605). The data table obtained by this combination will be described later with reference to FIG.

[0054] Next, a factor analysis is performed on the characteristic test items specified by the user using the combined data table obtained in step S605, and an evaluation index indicating the priority order for in-depth analysis for each WAT test item (sometimes referred to as "factor priority order" in this embodiment) is calculated (step S606). Here, the evaluation index is, for example, a correlation coefficient between WAT test data and characteristic value test data. An example of the calculation will be described later with reference to FIG. 10.

[0055] Next, to link the WAT test item with the manufacturing process in which the WAT test item was performed and the name of the equipment used in the manufacturing process, the target product type and manufacturing process data related to the target WAT test item are extracted from the WAT-manufacturing process DB 1410. Furthermore, the target product type and the name of the equipment that performed the target manufacturing process are extracted from the manufacturing process-equipment DB 1409 (step S607). The data tables stored in the WAT-manufacturing process DB 1410 and the manufacturing process-equipment DB 1409 will be described later with reference to FIGS. 12 and 13.

[0056] Next, display information including evaluation indexes representing the priority of factors, a simple correlation plot between WAT test items and characteristic test items, and manufacturing process information and equipment information related to the WAT test items is sent to the display unit 17 (step S608).

[0057] FIG. 7 is a diagram showing an example of the correspondence between the TEG ID and the product chip ID.

[0058] This figure shows an example of the results of the user associating the TEG with the related product chip ID for each TEG ID in step S604 (FIG. 6) processed by the factor analysis support device.

[0059] 7 shows an example in which a user has associated product chips in a wafer of type A001, as explained with reference to FIG. 2, based on the TEG information. The lower part of the figure shows a wafer map 702 of type A001, which is shown to the user via the display unit 17. The user specifies the product chips associated with the TEG while checking this wafer map 702 on the display unit 17.

[0060] Furthermore, the TEGs identified by symbols A to E (TEG IDs) are linked to adjacent product chips. Linking table 701 shows the linking results. For example, TEG ID: A is linked to adjacent product chip IDs 2, 3, 4, 7, 8, 14, 15, and 16. Based on this linking table 701 for product type A001, the WAT data of the TEG and the characteristic value inspection data of the product chips linked to the TEG are linked. An example of the linked data table will be described with reference to FIG. 8.

[0061] Fig. 8 is a diagram showing an example of a data table that combines the WAT data of the TEG and the characteristic value inspection data of the product chips linked to the TEG, which is processed in step S605 of Fig. 6. This data table may be referred to as a "combined data table."

[0062] The combined data table shown in Fig. 8 is a data table in which characteristic value test data of characteristic test items corresponding to each CHIP ID, TEG ID, and WAT data of WAT test items for each TEG ID correspond to each other. Note that CHIP ID is an identification code of a chip (CHIP).

[0063] This diagram only shows the case where the product type is A001, the manufacturing lot is LOT01, and the wafer ID is 1, but in reality, data for multiple product types, multiple manufacturing lots, and multiple wafer IDs can be saved. Using this combined data table makes it possible to perform factor analysis between the characteristic data of the product chip and the WAT data corresponding to each step in the manufacturing process.

[0064] FIG. 9 is a diagram showing another example of the correspondence relationship between the TEG ID and the product chip ID.

[0065] 7, this figure shows an example of the results of the user associating the TEG with the related product chip ID for each TEG ID in step S604 (FIG. 6) processed by the factor analysis support device.

[0066] 7 shows a wafer map of product type A001, while Fig. 9 shows a wafer map 902 of product type B001. Table 901 is a data table linking TEGIDs specified by the user with product chip IDs based on the wafer map 902.

[0067] In power semiconductors, the number and location of TEGs within a wafer differs for each product type. For this reason, for example, when performing correlation analysis between WAT data and characteristic value inspection data, it may be desirable to make the number of product chips linked to TEGIDs the same across TEGIDs. Table 901 for product type B001 is the result of a user selection so that the number of product chips linked to TEGs across TEGIDs is the same. However, it is not necessary to make the numbers the same, and users can flexibly change the association between TEGIDs and product chip IDs in accordance with their product type, design know-how, and the purpose of data analysis.

[0068] 9, not only the product chips adjacent to one TEG, but also the product chips adjacent to the adjacent product chips are linked to that TEG. For example, TEGID:A is linked to product chip IDs of adjacent product chips 2, 3, 4, 7, and 8, and is also linked to product chip IDs of product chips adjacent to the adjacent product chips 14, 15, and 16. Furthermore, TEGID:C is linked to product chip IDs of adjacent product chips 36, 37, 38, 53, and 54, and is also linked to product chip IDs of product chips adjacent to the adjacent product chips 19, 39, and 55.

[0069] FIG. 10 is a flowchart showing the processing in the factor analysis execution unit 1304 of FIG.

[0070] The process shown in Fig. 10 performs factor analysis on the combined data table. Specifically, factors are prioritized by correlation analysis, but a regression model that predicts the objective variable from the characteristic test items and the explanatory variables from all WAT data can be created by machine learning regression analysis (e.g., multiple regression analysis, ridge regression analysis, random forest regression, gradient boosting regression, deep neural network regression), and the importance of the regression model in influencing the objective variable can be used as an evaluation index.

[0071] In FIG. 10, first, based on the combined data table shown in FIG. 8, the correlation coefficient between the characteristic test item selected by the user and all WAT test items is calculated for each TEGID (step S101).

[0072] Here, a case where the characteristic inspection item selected by the user is dynamic characteristic inspection A will be described using the combined data table of FIG. 8 as an example.

[0073] First, since there are five types of TEGID, A to E, a total of five correlation coefficients are calculated between WAT test item 1 and dynamic characteristics test item A. Since there are 10 WAT test items in the combined data table, a total of 50 correlation coefficients are calculated.

[0074] Next, for all the calculated correlation coefficients, the absolute values ​​of the correlation coefficients are calculated to compare their magnitudes, and the correlation coefficients are sorted in descending order by their absolute values ​​(step S102). Next, a simple correlation plot is created with the WAT test items on the horizontal axis and the characteristic test items on the vertical axis (step S103). The absolute values ​​of the correlation coefficients and the simple correlation plot are sent to the display unit 17 (FIG. 1) together with information about the manufacturing process and manufacturing equipment extracted in step S607 shown in FIG. 6.

[0075] FIG. 11 is a diagram showing a collection of simple correlation plots obtained as a result of simple correlation analysis between WAT test items and user-specified characteristic test items.

[0076] The simple correlation plot shown in this figure is the result of analysis performed using the combined data table for product type A001 in step S607 of FIG. 6 and step S103 of FIG.

[0077] Since product type A001 has five TEGs, A to E, FIG. 11 displays a total of five single correlation plots 11A, 11B, 11C, 11D, and 11E together with a legend 110 for each production lot in each single correlation plot. Graphs and the like may be displayed together in this manner for the user on the screen of a display device. In all single correlation plots, the vertical axis represents dynamic characteristic test A, and the horizontal axis represents WAT test item 3 corresponding to TEGID. Single correlation plot 11A represents the case of TEGID:A, single correlation plot 11B represents the case of TEGID:B, single correlation plot 11C represents the case of TEGID:C, single correlation plot 11D represents the case of TEGID:D, and single correlation plot 11E represents the case of TEGID:E.

[0078] In FIG. 11, only TEGID:B shown in simple correlation plot 11B has a correlation between WAT test item 3 and dynamic characteristic test A. When wafer map 702 for product type A001 shown in FIG. 7 is checked, TEGID:B is formed at the center of the wafer. Therefore, since only WAT test item 3 at the wafer center has a correlation, the user can determine that the cause of the defect that occurred this time is a cause that is likely to occur at the wafer center in the manufacturing process related to WAT test item 3.

[0079] In this way, by linking TEGIDs with their surrounding product chips, then separating them by TEGID, and checking the correlation between characteristic items and WAT data, users can confirm the position dependency of factors.

[0080] FIG. 12 is a diagram showing an example of a data table stored in the WAT-manufacturing process DB 1410 in step S607 of FIG.

[0081] As shown in Figure 12, a data table linking the manufacturing process steps and the WAT inspection items related to each step for each product type is sometimes called a "WAT-manufacturing process data table." Because the manufacturing process and WAT inspection items differ for each power semiconductor product type, a WAT-manufacturing process data table is created for each power semiconductor product type. As in the WAT-manufacturing process data table, multiple WAT inspection items may correspond to one manufacturing process, or conversely, multiple manufacturing processes may correspond to one WAT inspection item. By using this WAT-manufacturing process data table, users can add WAT inspection items that are potential defect factors for characteristic inspection items and also understand the manufacturing processes related to those potential factors.

[0082] FIG. 13 is a diagram showing an example of a data table stored in the manufacturing process-equipment DB 1409 of FIG.

[0083] As shown in Figure 13, a data table linking the manufacturing process and equipment used for each product type is sometimes called a "manufacturing process-equipment data table." Because the manufacturing process and equipment used vary for each power semiconductor product type, a separate manufacturing process-equipment data table is created for each power semiconductor product type. Also, as in the manufacturing process-equipment data table, multiple pieces of equipment may correspond to a single manufacturing process, or conversely, one piece of equipment may correspond to multiple manufacturing processes. By using this manufacturing process-equipment data table, users can add WAT inspection items that are potential defect factors for characteristic inspection items and also understand the manufacturing equipment related to those potential factors. In particular, in power semiconductor processes, production volume can be improved by using multiple pieces of equipment in parallel in the same manufacturing process. In such cases, so-called equipment differences can become a defect factor.

[0084] Therefore, as will be described later using Figure 14, after extracting multiple devices corresponding to the WAT test items, it is useful for the user to proceed with factor analysis if they can check whether there are any statistically significant differences in the WAT test data between those devices.

[0085] FIG. 14 is a flowchart showing the processing in the machine difference analysis execution unit 1305 in FIG.

[0086] The process in the machine difference analysis execution unit 1305 is executed in response to a user instruction when there are multiple manufacturing devices extracted as candidate factors for the target product type and target characteristic item output by the factor analysis execution unit 1304.

[0087] When the machine difference analysis execution unit 1305 executes processing in response to a user instruction, a histogram of the WAT test data extracted by the factor analysis execution unit 1304 and selected by the user is first created for each machine (step S121). Next, a known statistical testing method is used to determine whether the histograms for each machine have a statistically significant difference (step S122). Known statistical testing methods, such as t-tests and Mann-Whitney U tests, are used to determine whether there is a significant difference between multiple distributions. Next, the histogram data created in step S121 and data including the results of the statistical testing output in step S122 are sent to the display unit 17 (step S123).

[0088] Fig. 15 is a diagram showing an example of a screen displayed to the user on the display unit 17 in Fig. 1. The screen shown in this figure is configured as a GUI (Graphical User Interface) to allow operations such as moving a pointer with a mouse, touchpad, etc., and selecting by clicking, etc. Note that a GUI in which the screen is a touch panel is also applicable.

[0089] As shown in Fig. 15, the screen displays a mode display section 1501, a WAT ​​analysis display section 1502, and an instrument difference analysis display section 1503, and the display varies depending on the analysis mode currently being performed. In Fig. 15, the WAT analysis display section 1502 is lit because this is the screen for performing WAT analysis.

[0090] Also displayed on the screen are a product type selection section 1506, a characteristic inspection item selection section 1507, a manufacturing lot selection section 1508, and a selection information save button 1509. The user can input data to the factor analysis support device by performing operations such as moving a pointer with a mouse or the like, or selecting by clicking, etc. The user selects the product type of the power semiconductor to be analyzed in the product type selection section 1506, selects the characteristic inspection items to be analyzed in the characteristic inspection item selection section 1507, and selects the manufacturing lot to be analyzed in the manufacturing lot selection section 1508, and then clicks the selection information save button 1509. This operation displays a correspondence area 1510 between the TEG and the product chip.

[0091] 7 and 9 by clicking on TEG and product chip association area 1510. TEG and product chip association area 1510 displays a wafer map display area 1511, an association result registration button 1512, and a TEG and product chip registration area 1513. Wafer map display area 1511 displays a wafer map of the product type selected by the user in product type selection area 1506. In wafer map display area 1511, product chips are identified by numbers (1 to 81 in the case of FIG. 15), and TEGs are identified by letters (A to E in the case of FIG. 15). After selecting a TEG ID in TEG and product chip registration area 1513, the user uses selection pointer 1514 to specify the product chip associated with the TEG ID while viewing wafer map display area 1511.

[0092] In FIG. 15, for TEGID:A, CHIPID:2, 3, 4, 7, 8, 14, 15, and 16 are selected. For TEGID:B, CHIPID:32 is selected by a selection pointer 1514. After the user completes the linking in the TEG and product chip registration area 1513, he or she clicks the linking result registration button 1512. This operation makes it possible to click the analysis execution button 1504. When the analysis execution button 1504 is clicked, operations are performed by the data extraction unit 1302, data combination unit 1303, and factor analysis execution unit 1304, and the screen transitions to the screen shown in FIG. 16.

[0093] FIG. 16 is a diagram showing an example of a screen displayed on the display unit 17 of FIG. 1 as a result of transition from the screen shown in FIG.

[0094] When the analysis execution button 1504 is clicked on the display shown in FIG. 15, the WAT analysis result 161 shown in FIG. 16 is displayed.

[0095] The screen first displays a factor priority graph 162 obtained as a result of factor analysis performed on the characteristic test item specified by the user. The factor priority graph 162 displays the WAT test items sorted in order of priority and their priorities. The user can select a WAT ​​test item using a selection pointer 167. When a WAT ​​test item is selected, a simple correlation plot 163 (including a legend) is displayed, with the selected WAT test item on the horizontal axis and the user-specified characteristic test on the vertical axis. A display other TEG results button 168, a manufacturing process name 164 associated with the WAT test item, a device name 165 associated with the WAT test item, and an execute machine difference analysis button 166 are also displayed. When the user selects the manufacturing process name 164 associated with the WAT test item using the selection pointer 167 and clicks the execute machine difference analysis button 166, the machine difference analysis execution unit 1305 is executed for the device associated with the selected manufacturing process, and the screen transitions to the screen shown in FIG. 17. Furthermore, clicking the display other TEG results button 168 transitions to the screen shown in FIG. 18.

[0096] FIG. 17 is a diagram showing an example of a screen displayed on the display unit 17 in FIG. 1 as a result of transition from the screen shown in FIG.

[0097] 16, clicking the machine difference analysis execution button 166 displays the selected manufacturing process name 171, the associated equipment name 172, and, as the machine difference analysis results, a histogram 173 of characteristic inspection items sorted by equipment, a histogram legend 174, and machine difference analysis results 175, as shown in Fig. 17. Based on the displayed histogram 173 and machine difference analysis results 175, the user can consider whether the equipment corresponding to the WAT inspection item selected as a candidate factor has a machine difference that may affect the WAT inspection item.

[0098] FIG. 18 is a diagram showing an example of a screen displayed on display unit 17 in FIG. 1 as a result of transition from the screen shown in FIG.

[0099] When the display other TEG results button 168 is clicked on the screen shown in Fig. 16, a single correlation plot 181 is displayed, which is the same as the single correlation plot 163 in Fig. 16, with the selected WAT test item on the horizontal axis and the user-specified characteristic test item on the vertical axis, as shown in Fig. 18. In addition, a single correlation plot 182 is displayed for each TEGID different from that of the single correlation plot 181, with the same WAT test item on the vertical axis and the user-specified characteristic test item on the horizontal axis.

[0100] 18 displays simple correlation plots 182 for all TEGIDs. The user can use the scroll bar to check the simple correlation plots for all TEGIDs. In this way, by comparing the simple correlation plots 182 between TEGIDs for inspection items that are candidate factors for characteristic inspection items, the user can isolate the position dependency of the factor (whether it appears in a specific area within the wafer or appears over the entire wafer), thereby making the user's factor analysis more efficient.

[0101] The present disclosure is not limited to the above-described examples and includes various modifications. The above-described examples have been described in detail to clearly explain the present disclosure and are not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of an example with the configuration of another example, or to add the configuration of another example to the configuration of an example. It is also possible to add or replace part of the configuration of an example with configurations of well-known technology, commonly used technology, etc. For example, with regard to the GUI configuration, while operations such as pointer movement and selection by clicking are performed in the above-described examples, this is not limited to this and may also include a configuration using a touch panel integrated with the screen. Furthermore, configurations that do not use non-essential components are also considered to be included in embodiments of the present disclosure.

[0102] In the above embodiment, a power semiconductor chip manufacturing process is described, but the present disclosure is not limited to this and can also be applied to chip manufacturing processes for semiconductors other than power semiconductors.

[0103] 2 to 5, 7 to 9, and 11 to 13 may be displayed on the screen of the display unit as they are, thereby assisting the user in understanding and making decisions.

[0104] Preferred embodiments of the present disclosure will be summarized below.

[0105] The multiple tests performed on the TEG to obtain WAT data are intended to evaluate the quality of wafers at each step of the manufacturing process. The memory resource further stores data corresponding to the test items corresponding to the WAT data, the names of the manufacturing process steps in which the test items were performed, and the names of the equipment used in the steps. The processor outputs the names of the steps in which the test items were performed and the names of the equipment used in the steps in association with each other. This configuration allows analysts to confirm the manufacturing process and the names of the equipment in which the primary cause exists, thereby improving the efficiency of in-depth analysis and countermeasure selection.

[0106] When there are multiple WAT devices that performed test items corresponding to the WAT data corresponding to the evaluation index, the processor determines whether or not there is a statistically significant difference in the WAT data values ​​between the multiple WAT devices, thereby determining whether or not the test items corresponding to the WAT data corresponding to the evaluation index in the test data are caused by the WAT device, and outputs the resulting machine difference analysis result. This configuration allows the analyst to understand whether there is a difference between the WAT devices, and can efficiently identify the WAT device where the cause is present.

[0107] The display unit displays the evaluation index output from the processor and the test item corresponding to the WAT data corresponding to the evaluation index.

[0108] The display unit displays the name of the step in which the test item was performed and the name of the device used in the step in association with each other.

[0109] The display unit displays the results of the machine difference analysis.

[0110] The memory resource further includes coordinate data of the product chips and the TEG. The processor calculates the distance between the TEG and the product chips based on the coordinate data, and sets the product chips whose distance is equal to or less than a predetermined value as targets for analyzing the correlation between the WAT data and the test data.

[0111] The display unit displays, in descending order of evaluation index, the test items corresponding to the WAT data corresponding to the evaluation index, the correlation between the WAT data and the test data, the name of the step in which the test item was performed, and the name of the equipment used in the step.

[0112] The processor compares the measured values ​​of the test items corresponding to the WAT data with high evaluation indices between the multiple TEGs to determine whether the test items corresponding to the WAT data with high evaluation indices are tests with position dependency. The display unit displays the determination result.

[0113] The causal analysis support method uses one or more processors and one or more memory resources to support the causal analysis of electrical characteristic defects that occur in product chips of power semiconductors during a manufacturing process of the power semiconductor chips. A wafer on which product chips are formed at multiple locations includes TEGs formed at multiple locations different from the product chips. The memory resource has test data resulting from an electrical characteristic test performed on the product chips and WAT data resulting from multiple tests performed on the TEGs. The processor analyzes the correlation between the WAT data and the test data for each TEG, and outputs an evaluation index indicating the priority order of candidate causes of the test data to be defective, and test items corresponding to the WAT data corresponding to the evaluation index.

[0114] According to the present disclosure, when electrical characteristic defects or abnormalities occur in the upstream process of the power semiconductor manufacturing process, the statistical processing in the analysis of the causes is automated and non-personalized, making the analysis of the causes more efficient, reducing the analyst's workload, and enabling rapid in-depth analysis.

[0115] According to the present disclosure, it is possible to detect factors that cannot be extracted by analysis using the average value of all product chips. [Explanation of symbols]

[0116] 10: Manufacturing equipment, 11: Communication network, 11A, 11B, 11C, 11D, 11E: Simple correlation plot, 12: Computer server, 13: Calculation unit, 14: Memory unit, 15: Communication unit, 16: Input unit, 17: Display unit, 110: Legend for each manufacturing lot, 161: WAT analysis result, 162: Factor priority graph, 163: Simple correlation plot, 164: Manufacturing process name related to WAT inspection item, 165: Equipment name related to WAT inspection item, 166: Machine difference analysis execution button, 167: Selection pointer, 1 68: Other TEG result display button, 171: Manufacturing process name, 172: Equipment name, 173: Histogram, 174: Histogram legend, 175: Machine difference analysis result, 181, 182: Simple correlation plot, 203: Wafer, 204: Product chip, 205: TEG, 301, 302: Wafer map, 701: Linking table, 702: Wafer map, 901: Table, 902: Wafer map, 1001: Manufacturing equipment, 1002: Characteristic inspection equipment, 1003: WAT equipment, 1301: Data storage execution Row section, 1302: data extraction section, 1303: data combination section, 1304: factor analysis execution section, 1305: machine difference analysis execution section, 1306: result display execution section, 1400: data saving program, 1401: data extraction program, 1402: data combination program, 1403: factor analysis program, 1404: machine difference analysis program, 1405: display program, 1406: wafer chip position DB, 1407: WAT measurement value DB, 1408: characteristic value inspection DB, 1409: manufacturing process-equipment DB, 1410: WAT-manufacturing process DB, 1501: mode display section, 1502: WAT analysis display section, 1503: machine difference analysis display section, 1504: analysis execution button, 1506: product type selection section, 1507: characteristic inspection item selection section, 1508: manufacturing lot selection section, 1509: selection information save button, 1510: TEG and product chip association area, 1511: wafer map display section, 1512: association result registration button, 1513: TEG and product chip registration area, 1514: selection pointer.

Claims

1. one or more processors and one or more memory resources; An apparatus for supporting analysis of causes of electrical characteristic defects occurring in power semiconductor product chips during a manufacturing process of power semiconductor chips, the wafer on which the product chips are formed at a plurality of positions includes TEGs formed at a plurality of positions different from the product chips; The memory resource is Inspection data obtained by performing an electrical characteristic test on the product chip; WAT data resulting from multiple tests performed on the TEG; The processor: Analyzing the correlation between the WAT data and the test data for each TEG; A factor analysis support device that outputs an evaluation index indicating a priority order of candidate factors that cause the inspection data to be defective, and a test item corresponding to the WAT data that corresponds to the evaluation index.

2. the plurality of tests are for evaluating the quality of the wafer at each step of the manufacturing process; The memory resource further includes data corresponding to the test item corresponding to the WAT data, the name of the step in the manufacturing process in which the test item was performed, and the name of the device used in the step; 2. The factor analysis support device according to claim 1, wherein the processor outputs the name of the step in which the test item was performed and the name of the device used in the step in association with each other.

3. 2. The factor analysis support device of claim 1, wherein, when there are multiple WAT devices that have performed the test items corresponding to the WAT data corresponding to the evaluation index, the processor determines whether the test items corresponding to the WAT data corresponding to the evaluation index in the test data are caused by the WAT device by testing whether there is a statistically significant difference in the values ​​of the WAT data between the multiple WAT devices, and outputs the resulting machine difference analysis result.

4. Further comprising a display unit, 2. The factor analysis support device according to claim 1, wherein the display unit displays the evaluation index output from the processor and the test item corresponding to the WAT data corresponding to the evaluation index.

5. Further comprising a display unit, 3. The factor analysis support device according to claim 2, wherein the display unit displays the name of the step in which the test item was performed and the name of the device used in the step in association with each other.

6. Further comprising a display unit, The factor analysis support device according to claim 3 , wherein the display unit displays the machine difference analysis results.

7. the memory resource further includes coordinate data of the product chip and the TEG; The factor analysis support device of claim 1, wherein the processor calculates the distance between the TEG and the product chip based on the coordinate data, and sets the product chips whose distance is less than a predetermined value as targets for analyzing the correlation between the WAT data and the test data.

8. Further comprising a display unit, 3. The factor analysis support device according to claim 2, wherein the display unit displays, in descending order of the evaluation index, the test items corresponding to the WAT data corresponding to the evaluation index, the correlation between the WAT data and the test data, the names of the steps in which the test items were performed, and the names of the devices used in the steps.

9. Further comprising a display unit, The processor compares the measurement values ​​of the test item corresponding to the WAT data having a high evaluation index between the plurality of TEGs, thereby determining whether the test item corresponding to the WAT data having a high evaluation index is a test having position dependency; 2. The factorial analysis support device according to claim 1, wherein said display unit displays the determination result.

10. using one or more processors and one or more memory resources, A method for supporting analysis of causes of electrical characteristic defects occurring in a power semiconductor product chip during a manufacturing process of the power semiconductor chip, comprising: the wafer on which the product chips are formed at a plurality of positions includes TEGs formed at a plurality of positions different from the product chips; The memory resource is Inspection data obtained by performing an electrical characteristic test on the product chip; WAT data resulting from multiple tests performed on the TEG; the processor: Analyzing the correlation between the WAT data and the test data for each TEG; A factor analysis support method that outputs an evaluation index that indicates a priority order as a candidate factor for the test data being defective, and a test item corresponding to the WAT data that corresponds to the evaluation index.

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