High aspect ratio vias with low stress in integrated circuit packages

Abstract

To provide an integrated circuit package substrate having high aspect ratio vias with low stress.SOLUTION: In an integrated circuit package, a package substrate 110 includes: a core 130 having a via 202 extending through the substrate; a first conductive material 236 in the via 202; a dielectric liner 234 at least partially between a wall 211 of the via 202 and the first conductive material; and a second conductive material 238 in the via 202. The second conductive material is closer to a central region of the via 202 than the first conductive material is to the central region of the via 202. The first conductive material is different from the second conductive material. The first conductive material is at least partially between the dielectric material and the second conductive material.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates generally to integrated circuit packages, and more particularly to high aspect ratio vias with low stress in integrated circuit packages. [Background technology]

[0002] In many integrated circuit packages, one or more semiconductor dies are mechanically and electrically coupled to an underlying package substrate. Often, such package substrates include a package core that provides structural integrity for the package substrate. In recent years, package substrates have been developed using glass cores. Using laser-assisted etching, crack-free, high-density vias (e.g., openings or holes) are formed within the glass core and subsequently plated with metal to serve as electrical pathways or interconnects to carry power and / or signals to and / or from the semiconductor dies and / or other electrical components on the package substrate. [Brief explanation of the drawings]

[0003] [Figure 1] 1 illustrates an exemplary integrated circuit (IC) package constructed in accordance with the teachings disclosed herein.

[0004] [Figure 2] 2 is a cross-sectional view of an example implementation of the package substrate of FIG. 1 at a point in the fabrication process in which the build-up region of FIG. 1 is partially formed.

[0005] [Figure 3] 2 is a cross-sectional view of another exemplary implementation of the package substrate of FIG. 1.

[0006] [Figure 4] 4 illustrates different stages in an exemplary fabrication process for producing the exemplary through glass via (TGV) shown in FIG. 2 and / or FIG. 3. [Figure 5]4 illustrates different stages in an exemplary fabrication process for producing the exemplary through glass via (TGV) shown in FIG. 2 and / or FIG. 3. [Figure 6] 4 illustrates different stages in an exemplary fabrication process for producing the exemplary through glass via (TGV) shown in FIG. 2 and / or FIG. 3. [Figure 7] 4 illustrates different stages in an exemplary fabrication process for producing the exemplary through glass via (TGV) shown in FIG. 2 and / or FIG. 3. [Figure 8] 4 illustrates different stages in an exemplary fabrication process for producing the exemplary through glass via (TGV) shown in FIG. 2 and / or FIG. 3. [Figure 9] 4 illustrates different stages in an exemplary fabrication process for producing the exemplary through glass via (TGV) shown in FIG. 2 and / or FIG. 3.

[0007] [Figure 10] 10 is a flowchart illustrating an exemplary method for manufacturing any one of the exemplary TGVs of FIGS. 2-9.

[0008] [Figure 11] FIG. 1 is a top view of a wafer including dies that may be included in an IC package constructed in accordance with the teachings disclosed herein.

[0009] [Figure 12] 1 is a cross-sectional side view of an IC device that may be included in an IC package constructed in accordance with the teachings disclosed herein.

[0010] [Figure 13] 1 is a cross-sectional side view of an IC device assembly that may include an IC package constructed in accordance with the teachings disclosed herein.

[0011] [Figure 14]FIG. 1 is a block diagram of an example electrical device that may include an IC package constructed in accordance with the teachings disclosed herein.

[0012] Generally, the same reference numbers are used throughout the drawings and accompanying written description to refer to the same or similar parts. The figures are not necessarily to scale. Instead, thicknesses of layers or regions may be exaggerated in the drawings. While layers and regions having clear lines and boundaries are shown in the figures, some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may be observable, blended, and / or irregular. DETAILED DESCRIPTION OF THE INVENTION

[0013] Glass cores for package substrates offer mechanical and electrical advantages over organic cores (e.g., epoxy-based prepreg layers with glass cloth). Specifically, glass cores offer greater structural rigidity than similarly sized organic cores. Furthermore, glass cores may allow smaller vias to be distributed at a smaller pitch than is possible using organic cores, thereby enabling higher interconnect densities. However, a challenge with using glass cores is the large difference in the coefficient of thermal expansion (CTE) of the glass relative to the CTE of the conductive material (e.g., plated copper) used for the interconnects extending through the glass core. As a result, there is a risk of introducing stresses, and potentially damage, to the glass core from plastic deformation (e.g., expansion and contraction) of the copper relative to the glass core during different temperature cycles (e.g., high temperatures during reflow operations) experienced during the fabrication of the associated integrated circuit package.

[0014] Examples disclosed herein mitigate CTE mismatch concerns by utilizing a seed layer stack of multiple different materials between the glass core and the copper to be subsequently plated thereon. More specifically, in some examples, the different materials in the seed layer stack include at least one of a stress-reducing liner, a metal seed layer, and an interposer (any of which may itself include one or more material layers). In some examples, the stress-reducing liner is a low-modulus material that absorbs some of the stress created by the CTE mismatch between the glass and the plated copper. The metal seed layer provides electrical conductivity to enable electroplating of the copper. In some such examples, the interposer acts as a transition between the metal seed layer and the plated copper, facilitating the electroplating process and promoting adhesion of the copper to the underlying metal seed layer.

[0015] Reducing stress between the glass core and the plated via extending through it becomes particularly challenging as the via width or diameter decreases due to the resulting increase in the via's height-to-width aspect ratio. In particular, standard techniques for depositing seed layers inside vias (e.g., using physical vapor deposition (PVD)) are limited to aspect ratios no greater than 5 (e.g., vias that are five times longer (taller) than their width). Examples disclosed herein rely on different techniques, such as atomic layer deposition (ALD), to deposit material into the seed layer stack in vias having aspect ratios much greater than 5 (e.g., at least 6, at least 7, at least 9, at least 10, at least 12, at least 15, at least 20, etc.). ALD can be used to line the interior surfaces of vias with high aspect ratios because it enables conformal coating regardless of the position and / or orientation of the surface being coated and allows for high coverage over uneven surfaces. Furthermore, the thickness of films or coatings deposited using ALD can be precisely controlled (e.g., in the sub-nanometer range). While ALD can be used to deposit materials inside high-aspect-ratio vias, not all materials are suitable for deposition using ALD techniques. Accordingly, the examples disclosed herein identify suitable materials that serve the intended functions of different layers in a seed layer stack while also being suitable for deposition via ALD. This may significantly reduce stress in glass cores with high-aspect-ratio vias (e.g., through-glass vias, TGVs) to improve the mechanical reliability of the cores and increase yield. In particular, simulated experiments show that the examples disclosed herein achieve a reduction in stress in glass cores to less than half (e.g., one-third) of the stress experienced in glass cores fabricated using known techniques.

[0016] 1 illustrates an exemplary integrated circuit (IC) package 100 constructed in accordance with the teachings disclosed herein. In the illustrated example, the IC package 100 is electrically coupled to a circuit board 102 via an array of contact pads or lands 104 on a mounting surface 105 (e.g., a bottom surface) of the package 100. In some examples, the IC package 100 may include balls, pins, and / or pads in addition to or in place of the contact pads 104 to enable electrical coupling of the package 100 to the circuit board 102. In this example, the package 100 includes two semiconductor (e.g., silicon) dies 106, 108 (sometimes referred to as chips or chiplets) attached to a package substrate 110 and encapsulated by a package lid or mold compound 112. The package substrate 110 is therefore an exemplary means for supporting the semiconductor dies. 1 includes two dies 106, 108, in other examples, package 100 may have only one die or more than two dies. In some examples, one of dies 106, 108 (or a separate die) is embedded in package substrate 110. Dies 106, 108 may provide any suitable type of functionality (e.g., data processing, memory storage, etc.).

[0017] As shown in the illustrated example, each of the dies 106, 108 is electrically and mechanically coupled to the substrate 110 via a corresponding array of interconnects 114. In FIG. 1 , the interconnects are shown as bumps. However, the interconnects 114 may be any other type of electrical connection in addition to or instead of the depicted bumps (e.g., balls, pins, pads, wire bonds, etc.). The electrical connection (e.g., interconnects 114) between the dies 106, 108 and the substrate 110 is sometimes referred to as a first-level interconnect. In contrast, the electrical connection (e.g., pads 104) between the IC package 100 and the circuit board 102 is sometimes referred to as a second-level interconnect. In some examples, the second-level interconnect is used to electrically couple the IC package 100 to some component other than the circuit board (e.g., an interposer, another IC package, etc.). In some examples, one or both of the dies 106, 108 may be stacked on top of one or more other dies and / or interposers. In such an example, the die 106, 108 may be coupled to the underlying die and / or interposer via a first set of first-level interconnects, and the underlying die and / or interposer may be connected to the package substrate 110 via a separate set of first-level interconnects associated with the underlying die and / or interposer. Accordingly, as used herein, first-level interconnects refers to interconnects (e.g., balls, bumps, pins, pads, wire bonds, etc.) between the die and the package substrate or between the die and the underlying die and / or interposer.

[0018] 1 , the interconnects 114 of the first level interconnect include two different types of bumps corresponding to core bumps 116 and bridge bumps 118. As used herein, core bumps 116 are bumps on the dies 106, 108 through which electrical signals pass between the dies 106, 108 and components external to the IC package 100. More specifically, as shown in the illustrated example, when the dies 106, 108 are attached to the package substrate 110, the core bumps 116 are physically connected and electrically coupled to contact pads 120 on the inner surface 122 of the substrate 110. The contact pads 120 on the inner surface 122 of the package substrate 110 are electrically coupled to pads 104 on the bottom (external) surface 105 of the substrate 110 (e.g., the surface opposite the inner surface 122) via internal interconnects 124 within the substrate 110. As a result, there is a continuous electrical signal path (e.g., a continuous electrical signal path) between the interconnects 114 of the dies 106, 108 and the pads 104 attached to the circuit board 102, passing through the contact pads 120 and interconnects 124 provided therebetween.

[0019] As used herein, bridge bumps 118 are bumps on the dies 106, 108 through which electrical signals pass between different ones of the dies 106, 108 within the package 100. Thus, as shown in the illustrated example, the bridge bumps 118 of the first die 106 are electrically coupled to the bridge bumps 118 of the second die 108 via interconnect bridges 126 embedded in the package substrate 110. As depicted in FIG. 1 , the core bumps 116 are typically larger than the bridge bumps 118. In some examples, the interconnect bridges 126 and associated bridge bumps 118 are omitted.

[0020] In some examples, underfill material 119 is disposed between the dies 106, 108 and the package substrate 110, around and / or between the first level interconnects 114 (e.g., around and / or between the core bumps 116 and / or bridge bumps 118). In the example shown, only the first die 106 is associated with the underfill material 119. However, in other examples, both dies 106, 108 are associated with the underfill material 119. In other examples, the underfill material 119 is omitted. In some examples, mold compound 112 is used as the underfill material surrounding the first level interconnects 114.

[0021] In some examples, the IC package 100 includes additional passive components, such as surface-mount resistors, capacitors, and / or inductors, located on the bottom (external) surface 105 of the package substrate 110 and / or the top (internal) surface 122 of the package substrate 110.

[0022] For illustrative purposes, the internal interconnects 124 are shown as straight lines extending directly between the pads 104 on the bottom surface 105 and the contact pads on the inner surface 122. However, in some examples, the internal interconnects 124 are defined by traces or routing in separate conductive (e.g., metal) layers within a build-up region 128 on one or both sides of a substrate core 130 (e.g., a base substrate) in the package substrate 110. In such examples, the build-up region 128 includes a dielectric layer to separate the different conductive layers. In such examples, the traces or routing in the different conductive layers are electrically coupled (to define the complete electrical path of the internal interconnects 124) by conductive (e.g., metal) vias extending between the different conductive layers. Furthermore, in some examples, the internal interconnects 124 include vias extending through the substrate core 130.

[0023] In some examples, the substrate core 130 is a glass substrate or glass core. In some examples, the glass substrate (e.g., the glass core 130) includes quartz, fused silica, and / or borosilicate glass. In some examples, the glass substrate (e.g., the glass core 130) includes at least 20% (by weight) of each of silicon (Si) and oxygen (O). In other examples, the glass substrate (e.g., the glass core 130) includes a greater amount of at least one of silicon or oxygen (e.g., at least 25% by weight, at least 30% by weight, at least 35% by weight, at least 40% by weight, etc.). In some examples, the glass substrate (e.g., the glass core 130) includes at least 5% by weight of aluminum (Al). In some examples, the glass substrate (e.g., the glass core 130) includes at least one glass layer, but does not include epoxy or glass fiber (e.g., does not include an epoxy-based prepreg layer with glass cloth). In some examples, the glass substrate (e.g., the glass core 130) corresponds to a single piece of glass extending the full height / thickness of the core. In some examples, the glass core 130 has a substantially coextensive rectangular shape in plan view, with layers above and below the core (e.g., substantially coextensive with the build-up region 128). The glass core 130 provides rigidity and mechanical support or strength to the package substrate 110 and the rest of the package 100. Thus, the glass core 130 is an exemplary means for strengthening the package substrate 110. In some examples, the thickness of the glass core 130 is driven by the size (e.g., footprint) of the package 100. For example, in some cases, a larger package 100 includes a substrate 110 with a larger (e.g., thicker) core 130 compared to a smaller package 100, where a thicker core is not required.

[0024] 2 is a cross-sectional view of an example implementation 200 of the package substrate 110 of FIG. 1 at a point in the fabrication process where the build-up region 128 of FIG. 1 is partially formed. Specifically, the package substrate 110 shown in FIG. 2 includes a plurality of through-glass vias (TGVs) 202 (e.g., openings, through-holes, etc.) that extend across the core 130 from a first (external) surface 204 of the core 130 to a second (external) surface 206 of the core. The TGVs 202 include a conductive fill material 208 (e.g., plated copper) that has been electroplated onto a seed layer stack 210 that lines walls 211 (sidewalls, interior surfaces) of the TGVs 202. In some examples, electroplating of the conductive fill material 208 is implemented to fill the TGVs 202. That is, the conductive fill material 208 fills a central region of the TGVs 202.

[0025] As shown in the illustrated example, the TGVs 202 are coupled to respective first via pads 212 extending along the first surface 204 of the core 130 in the first metal layer 214 of the build-up region 128 on the first surface 204. Similarly, the TGVs 202 are coupled to respective second via pads 216 extending along the second surface 206 of the core 130 in the first metal layer 218 of the build-up region 128 on the second surface 206. In some examples, the via pads 212, 216 comprise portions of the seed layer stack 210 extending along the outer surfaces 204, 206 of the core 130. In this example, a first dielectric layer 220 is deposited over the first via pad 212 and the first surface 204 of the core 130, and a second dielectric layer 222 is deposited over the second via pad 216 and the second surface 206 of the core 130. Additionally, as shown in the illustrated example, an additional metal via 224 extends through each of the dielectric layers 220, 222 to electrically couple the via pad in the first metal layer 214, 218 adjacent the core 130 to the second metal layer 226, 228 on the opposite side of the dielectric layers 220, 222. In this example, the TGV 202 and the associated additional via 224 define at least a portion of the internal interconnect 124 shown in FIG.

[0026] As depicted in the illustrated example, the TGV 202 has a height 230 (e.g., length, depth) that is significantly greater than the width 232 (e.g., diameter) of the TGV 202. Thus, the TGV 202 has a relatively high height-to-width aspect ratio. In this example, the height 230 of the TGV corresponds to the thickness of the core 130. As package sizes continue to increase, the thickness of the core 130, and thus the height 230 of the TGV 202, also increases. In some examples, the thickness of the core 130 (and the height 230 of the TGV 202) can be at least 800 micrometers (um) or more (e.g., at least 900 um, at least 1000 um (1 millimeter (mm)), at least 1.2 mm, at least 1.4 mm, etc.). While the core thickness (and thus the height 230 of the TGV) increases with technological advances, the width 232 of the TGV 202 remains constant or even becomes smaller with technological advances, thereby resulting in an ever-increasing aspect ratio. For example, the width 232 of the TGV 202 may be significantly less than or equal to approximately 100 μm (e.g., less than or equal to approximately 75 μm, less than or equal to approximately 55 μm, less than or equal to approximately 45 μm, less than or equal to approximately 30 μm, etc.). Based on these dimensions, the aspect ratio of the TGV 202 may therefore be much greater than 5 (e.g., at least 6, at least 7, at least 9, at least 10, at least 12, at least 15, at least 20, etc.). Such a large aspect ratio makes it difficult, if not impossible, to line the wall 211 with the material of the seed layer stack 210 using standard deposition techniques. More specifically, standard PVD processes for depositing metal seed layers are typically limited to aspect ratios not exceeding 5.

[0027] One limitation of the PVD process is that PVD is a directional deposition process that deposits material non-uniformly depending on the orientation of the surface onto which the material is deposited and the position and / or distance of the surface relative to other surfaces onto which the material is deposited. That is, PVD results in a non-conformal coating or film on the underlying substrate, with the thickness varying depending on the location of the coating or film at which the thickness is measured. For example, when depositing material on a substrate containing through-holes (such as TGV 202 in FIG. 2 ), much more material accumulates on the surface of the substrate surrounding the through-hole opening, with less material deposited on the through-hole walls the farther into the through-hole. For at least these reasons, attempts to deposit a metal seed layer on the walls 211 of TGV 202 (which has a high aspect ratio) are prone to gaps or voids in the coverage of the walls 211, which can result in gaps or voids in the conductive fill material 208 electroplated on such seed layer.

[0028] The directional nature of PVD also means that depositing material onto an underlying surface requires direct line-of-sight. However, many TGVs 202 do not have perfectly straight walls 211. Rather, as shown in the exemplary TGV 300 shown schematically in FIG. 3 , the TGV 300 often includes tapered (e.g., sloping, angled) walls that define overhanging features that prevent direct line-of-sight deposition. Therefore, the use of PVD is not a viable option for depositing a seed layer within a TGV that can then be used to fill the TGV with electroplated copper. Any one of the TGVs 202 of FIG. 2 could alternatively have a profile similar to the exemplary TGV 300 of FIG. 3 . Furthermore, in other examples, the TGV could have any other suitable profile.

[0029] The examples disclosed herein overcome the above-mentioned limitations of PVD through the use of atomic layer deposition (ALD) techniques. Unlike PVD, ALD is not a directional deposition process. ALD provides a conformal coating on all exterior surfaces of a substrate, regardless of whether a direct line of sight exists. That is, unlike PVD, the thickness of a layer of material deposited using ALD can be substantially consistent across all surfaces on which the material is deposited, regardless of the position and / or orientation of the surfaces or their spatial relationship to one another. In other words, as shown in FIG. 3 , the seed layer 302 has a substantially uniform thickness, with a first thickness 304 at the first end of the TGV 300 approximately equal to the second thickness of the seed layer 302 at the second end of the TGV 300. Furthermore, as shown in the illustrated example, the seed layer 302 has a third thickness 306 at the midpoint of the TGV 300 approximately equal to the first thickness 304 and approximately equal to the second thickness 306. Furthermore, each of the first, second, and third thicknesses 304, 306, 308 is approximately equal to the fourth thickness 310 of the seed layer 302 on the outer surfaces 204, 206 of the core 130. More generally, in some instances, due to the use of ALD, the seed layer 302 has a thickness that varies by less than 5% between any two points on the seed layer 302. As used herein, different thicknesses are "approximately equal," meaning that there is less than a 5% difference between the thicknesses. Similarly, as used herein, a "substantially consistent thickness" and a "substantially uniform thickness" of a material layer refer to a layer having a thickness that varies by less than 5% over the entire area covered by the material layer.

[0030] In some examples, as shown in the inset of FIG. 2 , the seed layer stack 210 includes a stack of multiple different material layers. In some examples, one or more of the different material layers in the seed layer stack 210 are deposited using an ALD process. In this example, the seed layer stack 210 includes a dielectric liner 234 (e.g., a stress-reducing liner, a stress buffer layer), a metal seed layer 236 (e.g., a first conductive material, a conductive liner), and an interposer 238 (e.g., a second conductive material, a transition layer). More specifically, in this example, the metal seed layer 236 is between the dielectric liner 234 and the interposer 238. Furthermore, in this example, the dielectric liner 234 is closer to the core 130 than either the metal seed layer 236 or the interposer 238. Specifically, in this example, the dielectric liner 234 is in contact with the core 130 (e.g., in contact with the sidewall 211 of the TGV 202). In some examples, the dielectric liner 234 is omitted such that the metallic seed layer 236 is in direct contact with the core 130. As shown in the illustrated example, the insert 238 is closer to the conductive fill material 208 than either the dielectric liner 234 or the metallic seed layer 236. Specifically, in this example, the insert 238 is in contact with the conductive fill material 208. In some examples, the insert 238 is omitted such that the metallic seed layer 236 is in direct contact with the conductive fill material 208.

[0031] In some examples, the dielectric liner 234 is a relatively low modulus material (e.g., a material having a Young's modulus less than 2 gigapascals (GPa)) that reduces stress resulting from a CTE mismatch between the glass core 130 and the metal used for the conductive fill material 208. In some examples, the conductive fill material 208 includes copper. In other examples, different metals may be used for the conductive fill material 208. In some examples, the dielectric liner 234 is a polymer (e.g., parylene, polyimide, epoxy), Si x O y C z H w , SiN x C y Hz and / or SiO x In some examples, the dielectric liner 234 includes an organic material with inorganic fillers. In some examples, the dielectric liner 234 includes a fiber-reinforced polymer. In some examples, the dielectric liner 234 includes multiple layers of different materials.

[0032] In some examples, the metal seed layer 236 includes a conductive material for carrying a current applied to the substrate (e.g., the core 130) to facilitate electroplating of the conductive fill material 208. Furthermore, in this example, the metal seed layer 236 includes a material that can be deposited using ALD. More specifically, in some examples, the metal seed layer 236 includes at least one of ruthenium or copper and / or oxides of such metals. However, other materials may also be utilized for the metal seed layer 236 (e.g., molybdenum, titanium, vanadium, chromium, iron, cobalt, nickel, zinc, zirconium, rhodium, palladium, silver, cadmium, tantalum, tungsten, iridium, platinum, gold, etc. and / or oxides of such metals). In some examples, the metal seed layer 236 includes any suitable electrically conductive metal oxide layer (e.g., zinc oxide). In some examples, the metal seed layer 236 is free of titanium or contains only at least trace amounts of titanium (e.g., less than 1 wt%, less than 0.5 wt%, less than 0.1 wt%, etc.). In some examples, the metal seed layer 236 includes multiple layers of different materials. In some examples, the metal seed layer 236 includes a different material than the conductive fill material 208. That is, in some examples, the metal seed layer 236 includes a different composition than the conductive fill material 208.

[0033] In this example, the insert 238 functions as a transition layer between the metal seed layer 236 and the conductive fill material 208 to improve adhesion between the metal seed layer 236 and the conductive fill material 208. In some examples, the insert 238 includes a conductive material that can be deposited using ALD. In some examples, the insert 238 includes at least one of titanium or copper. In some examples, the insert 238 includes at least one of TiN, SiN, TaN, or SiOx. In some examples, the insert 238 includes multiple layers of different materials.

[0034] In some examples, each of the material layers in the seed layer stack 210 has a different thickness. More specifically, in some examples, the dielectric liner 234 has a first thickness 240 that is significantly greater than the second thickness 242 of the metal seed layer 236 and significantly greater than the third thickness 244 of the interposer 238. The greater thickness of the dielectric liner 234 provides stress relief, as described above. In some examples, the first thickness 240 of the dielectric liner is at least 300 nanometers (nm) (0.3 um), and may be significantly greater (e.g., at least 0.5 um, at least 0.75 um, at least 1 um, at least 2 um, at least 5 um, at least 7.5 um, at least 9 um, etc.). In contrast, in some examples, the second thickness 242 of the metal seed layer 236 is less than or equal to approximately 100 nm (e.g., less than or equal to approximately 75 nm, less than or equal to approximately 50 nm, less than or equal to approximately 25 nm, less than or equal to approximately 10 nm, less than or equal to approximately 5 nm, less than or equal to approximately 3 nm, etc.), and may be approximately 1 nm or less. In some examples, the second thickness 242 is greater than 100 nm. In some examples, the third thickness 244 of the insert 238 is also less than or equal to approximately 100 nm (e.g., less than or equal to approximately 75 nm, less than or equal to approximately 50 nm, less than or equal to approximately 25 nm, less than or equal to approximately 10 nm, less than or equal to approximately 5 nm, less than or equal to approximately 3 nm, etc.), and may be approximately 1 nm or less. In some examples, the third thickness 244 is greater than 100 nm. In some examples, the third thickness 244 of the insert 238 is less than or equal to the second thickness 242 of the metal seed layer 236. In other examples, the third thickness 244 of the insert 238 is greater than the second thickness 242 of the metal seed layer 236.

[0035] 4 through 9 illustrate different stages in an exemplary fabrication process for producing plated-through holes or TGVs, such as TGVs 202, 300 shown in FIGS. 2 and / or 3. More specifically, FIG. 4 depicts stages of fabrication following the creation of a via 402 (e.g., TGV, through-hole, opening) extending through the glass core 130. In this example, the TGV 402 is defined by an interior sidewall 404 that extends in a straight line from the first and second (exterior) surfaces 204, 206 of the core 130. More specifically, in this example, the sidewall 404 extends in a direction that is substantially perpendicular (e.g., within 5 degrees of perpendicular) to the exterior surfaces 204, 206. However, in other examples, the sidewall 404 may extend at a non-perpendicular angle to the exterior surfaces 204, 206. Furthermore, in some examples, the sidewall 404 may not be a continuous straight line. Rather, in some examples, the sidewall 404 may define an hourglass shape, such as that shown in the illustrated example of Figure 3. In other examples, the sidewall 404 may have any other suitable shape or profile.

[0036] 5 depicts a stage of fabrication following deposition of a dielectric liner 234 on the exposed surfaces of the core 130. In this example, the exposed surfaces include the outer surfaces 204, 206 of the core 130 as well as the sidewalls 404 of the TGVs 402 in the core 130. In some examples, the dielectric liner 234 is deposited via spin coating, slit coating, chemical vapor deposition (CVD), or vacuum lamination. In some examples, these deposition processes result in the TGVs 402 being substantially or completely filled with the dielectric liner 234. In such examples, a subsequent laser drilling process through the filled TGVs 402 is performed to remove the dielectric liner 234 from a central region of the TGVs 402, such that the dielectric liner 234 is limited to the sidewalls 404 of the TGVs 402 (e.g., lines).

[0037] 6 depicts a subsequent stage of fabrication after deposition of a metal seed layer 236 on the dielectric liner 234. In this example, the TGVs 402 have a relatively high aspect ratio (e.g., greater than 5), so standard PVD processes are not feasible. Accordingly, in some examples, the metal seed layer 236 is deposited via an ALD process. More specifically, in some examples, the metal seed layer 236 is deposited using thermal ALD or plasma enhanced.

[0038] 7 depicts a subsequent stage of fabrication after deposition of the insert 238 onto the metal seed layer 236. In some examples, the deposition process utilized to deposit the insert 238 may depend on the material used for the insert 238. For example, if the insert 238 includes a titanium / copper layer, the insert may be deposited via sputtering. In other examples, if the insert 238 is to be a dry-deposited seed metal (e.g., copper or other suitable metal), an ALD process may be used. As noted above, the dielectric liner 234, metal seed layer 236, and insert 238 collectively correspond to the seed layer stack 210 described above in connection with FIGS. 2 and 3. In some examples, the insert 238 is omitted.

[0039] 8 depicts a subsequent stage of fabrication after deposition of conductive fill material 208 onto metal seed layer 236 (and insert 238). In some examples, conductive fill material 208 is deposited via electroplating using metal seed layer 236 (and insert 238) as a conductive underlying surface. As shown in the illustrated example, conductive fill material 208 is electroplated to fill a central region of TGV 402 (e.g., remaining open space within TGV 402). Additionally, as shown in FIG. 8, conductive fill material 208 also extends across outer surfaces 204, 260 of core 130.

[0040] 9 depicts a subsequent stage of fabrication after removing excess portions of the conductive fill material 208, the insert 238, and / or the metal seed layer 236 on the outer surfaces 204, 206 of the core 130. In some examples, the excess portions of material are removed via an etching process (e.g., wet etching, dry etching, etc.). As shown in the example illustrated in FIG. 9, the remaining portions of material on the outer surfaces 204, 206 define first and second via pads 902, 904 at either end of the TGV 402.

[0041] FIG. 10 is a flowchart illustrating an example method 1000 for manufacturing any one of the example TGVs 202, 300, 402 of FIGS. 2-9. In some examples, some or all of the operations outlined in the example method of FIG. 10 are performed automatically by fabrication equipment programmed to perform such operations. Although the example fabrication method is described with reference to the flowchart illustrated in FIG. 10, many other methods may alternatively be used. For example, the order of execution of the blocks may be changed, and / or some of the described blocks may be combined, divided, rearranged, omitted, removed, and / or implemented in any other manner. Furthermore, in some examples, additional processing operations may be performed before, during, and / or after any of the blocks depicted in the illustrated examples.

[0042] Referring specifically to FIG. 10 , an exemplary process begins at block 1002 by providing high aspect ratio vias (e.g., vias 202, 300, 402) in a glass core (e.g., core 130). The operations associated with block 1002 are represented by FIG. 4 , as discussed above. At block 1004, the exemplary process includes depositing a dielectric liner (e.g., dielectric liner 234) across the outer surfaces (e.g., surfaces 204, 206) of the glass core 130 and along the sidewalls (e.g., sidewalls 211, 404) of the vias 202, 300, 402. The dielectric liner 234 functions as a stress buffer between the glass core 130 and any subsequently added metal layers. The operations associated with block 1004 are represented by FIG. 5 , as discussed above.

[0043] In block 1006, the exemplary process includes depositing a metal seed layer (e.g., metal seed layer 236) on dielectric liner 234 using atomic layer deposition (ALD). In this example, ALD is utilized because of the high aspect ratio of vias 202, 300, 402. The operations associated with block 1006 are represented by FIG. 6 , as described above. In block 1008, the exemplary process includes depositing an insert (e.g., insert 238) on metal seed layer 236. In some examples, block 1008 is omitted. The operations associated with block 1008 are represented by FIG. 7 , as described above. In block 1010, the exemplary process includes electroplating a conductive fill material (e.g., conductive fill material 208) on insert 238 (and / or metal seed layer 236) to fill vias 202, 300, 402. The operations associated with block 1010 are represented by FIG. 8 , as described above. At block 1012, the exemplary process includes removing excess material. Specifically, portions of the conductive fill material 208, the interposer 238, and / or the metal seed layer 236 are removed (e.g., via etching) to define a first metal layer (e.g., first metal layers 214, 218) on the outer surfaces 204, 206 of the glass core 130. The operations associated with block 1012 are represented by FIG. 9 , as described above. The exemplary process then ends, and the resulting device may proceed to a subsequent fabrication process, for example, to add a build-up region 128 on the glass core 130.

[0044] The example TGVs 202, 300, 402 disclosed herein may be included in any suitable electronic component. Figures 11-14 illustrate various examples of devices that may include and / or are included in the example IC package 100 of Figure 1 that includes the example TGVs 202, 300, 402 disclosed herein.

[0045] FIG. 11 is a top view of a wafer 1100 and dies 1102 that may be included in the IC package 100 of FIG. 1 (e.g., any suitable number of dies 106, 108) having a substrate including one or more of the example TGVs 202, 300, 402 disclosed herein. The wafer 1100 includes one or more dies 1102 having semiconductor material and circuitry. Each of the dies 1102 may be a repeating unit of a semiconductor product. After fabrication of the semiconductor product is complete, the wafer 1100 may undergo a singulation process in which the dies 1102 are separated from one another to provide discrete “chips.” The dies 1102 include one or more transistors (e.g., some of the transistors 1240 of FIG. 12 , described below), support circuitry for routing electrical signals to the transistors, passive components (e.g., traces, resistors, capacitors, inductors, and / or other circuitry), and / or any other components. In some examples, the die 1102 may include and / or implement memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM®) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuitry or electronics. A plurality of these devices may be combined on a single die 1102. For example, a memory array of multiple memory circuits may be formed on the same die 1102 as programmable circuits (e.g., processor circuit 1402 of FIG. 14 ) and / or other logic circuits. Such memory may store information for use by the programmable circuits. The exemplary IC package 100 disclosed herein may be manufactured using die-to-wafer assembly techniques in which several dies are attached to a wafer 1100 containing other dies, and the wafer 1100 is subsequently singulated.

[0046] FIG. 12 is a cross-sectional side view of an IC device 1200 that may be included in the exemplary IC package 100 (e.g., any one of the dies 106, 108) having a substrate including one or more of the exemplary TGVs 202, 300, 402 disclosed herein. One or more of the IC devices 1200 may be included in one or more dies 1102 ( FIG. 11 ). The IC device 1200 may be formed in a die substrate 1202 (e.g., wafer 1100 of FIG. 11 ) and included in a die (e.g., die 1102 of FIG. 11 ). The die substrate 1202 may be a semiconductor substrate including, for example, a semiconductor material including an n-type or p-type material system (or a combination of both). The die substrate 1202 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some examples, the die substrate 1202 may be formed using alternative materials. Such materials may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Additional materials classified as II-VI, III-V, or IV may also be used to form the die substrate 1202. A few examples of materials from which the die substrate 1202 may be formed are described here, but any material that can serve as the foundation for the IC device 1200 may be used. The die substrate 1202 may be part of a singulated die (e.g., die 1102 of FIG. 11 ) or a wafer (e.g., wafer 1100 of FIG. 11 ).

[0047] The IC device 1200 may include one or more device layers 1204 disposed on and / or above a die substrate 1202. The device layer 1204 may include features of one or more transistors 1240 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1202. The device layer 1204 may include, for example, one or more source and / or drain (S / D) regions 1220, a gate 1222 for controlling the flow of current between the S / D regions 1220, and one or more S / D contacts 1224 for routing electrical signals to and from the S / D regions 1220. The transistor 1240 may include additional features, such as device isolation regions, gate contacts, and the like, not shown for clarity. The transistor 1240 is not limited to the type and configuration shown in FIG. 12 and may include a variety of other types and / or configurations, such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors can include FinFET transistors such as double-gate or tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

[0048] Each transistor 1240 may include a gate 1222 including a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric materials. The high-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and / or zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate. In some instances, an annealing process may be performed on the gate dielectric to improve the quality of the gate dielectric when high-k materials are used.

[0049] A gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether transistor 1240 is to be a p-type metal oxide semiconductor (PMOS) or n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers, such as barrier layers, may be included. For PMOS transistors, metals that may be used in the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and / or any of the metals described below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that may be used in the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and / or aluminum carbide), and / or any of the metals mentioned above with reference to PMOS transistors (e.g., for work function tuning).

[0050] In some examples, when viewed as a cross-section of transistor 1240 along the source-channel-drain direction, the gate electrode may include a U-shaped structure including a bottom portion substantially parallel to the surface of die substrate 1202 and two sidewall portions substantially perpendicular to the top surface of die substrate 1202. In other examples, at least one of the metal layers forming the gate electrode may be a flat layer that is substantially parallel to the top surface of die substrate 1202 and does not include sidewall portions substantially perpendicular to the top surface of die substrate 1202. In other examples, the gate electrode may include a combination of U-shaped and / or flat non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed on one or more flat non-U-shaped layers.

[0051] In some examples, a pair of sidewall spacers may be formed on opposing sides of the gate stack to surround the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and / or silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some examples, multiple spacer pairs may be used, for example, two, three, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0052] The S / D regions 1220 may be formed in the die substrate 1202 adjacent to the gate 1222 of the corresponding transistor 1240. The S / D regions 1220 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 1202 to form the S / D regions 1220. An annealing process to activate the dopants and diffuse them further into the die substrate 1202 may follow the ion-implantation process. In the latter process, the die substrate 1202 may first be etched to form recesses at the locations of the S / D regions 1220. An epitaxial deposition process may then be performed to fill the recesses with the material used to fabricate the S / D regions 1220. In some implementations, the S / D regions 1220 may be fabricated using silicon alloys such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be doped in situ with a dopant such as boron, arsenic, or phosphorus. In some examples, the S / D regions 1220 may be formed using one or more alternative semiconductor materials, such as germanium or a III-V material or alloy. In further examples, one or more layers of metal and / or metal alloy may be used to form the S / D regions 1220.

[0053] Electrical signals, such as power and / or input / output (I / O) signals, may be routed to and / or from devices (e.g., transistor 1240) in device layer 1204 through one or more interconnect layers (shown in FIG. 12 as interconnect layers 1206-1210) disposed on device layer 1204. For example, electrically conductive features (e.g., gate 1222 and S / D contacts 1224) in device layer 1204 may be electrically coupled to interconnect structures 1228 in interconnect layers 1206-1210. One or more interconnect layers 1206-1210 may form a metallization stack (also referred to as an “ILD” stack) 1219 of IC device 1200.

[0054] Interconnect structures 1228 may be arranged within interconnect layers 1206-1210 to route electrical signals according to a variety of designs (notably, such arrangements are not limited to the particular configuration of interconnect structures 1228 shown in Figure 12). Although a particular number of interconnect layers 1206-1210 are shown in Figure 12, examples of the present disclosure include IC devices having more or fewer interconnect layers than those shown.

[0055] In some examples, the interconnect structures 1228 may include lines 1228a and / or vias 1228b filled with a conductive material, such as metal. The lines 1228a may be arranged to route electrical signals in a plane that is substantially parallel to the surface of the die substrate 1202 on which the device layer 1204 is formed. For example, the lines 1228a may route electrical signals in a direction into and / or out of the page from the perspective of FIG. 12. The vias 1228b may be arranged to route electrical signals in a plane that is substantially perpendicular to the surface of the die substrate 1202 on which the device layer 1204 is formed. In some examples, the vias 1228b may electrically couple together the lines 1228a of different interconnect layers 1206-1210.

[0056] 12, the interconnect layers 1206-1210 can include a dielectric material 1226 disposed between interconnect structures 1228. In some examples, the dielectric material 1226 disposed between the interconnect structures 1228 in different ones of the interconnect layers 1206-1210 can have different compositions. In other examples, the composition of the dielectric material 1226 between different interconnect layers 1206-1210 can be the same.

[0057] A first interconnect layer 1206 (referred to as metal 1 or "M1") may be formed directly on the device layer 1204. In some examples, as shown, the first interconnect layer 1206 may include lines 1228a and / or vias 1228b. The lines 1228a of the first interconnect layer 1206 may be coupled to contacts (e.g., S / D contacts 1224) of the device layer 1204.

[0058] A second interconnect layer 1208 (referred to as metal 2 or "M2") may be formed directly over the first interconnect layer 1206. In some examples, the second interconnect layer 1208 may include vias 1228b for coupling lines 1228a of the second interconnect layer 1208 with lines 1228a of the first interconnect layer 1206. Although the lines 1228a and vias 1228b are structurally depicted as lines within each interconnect layer (e.g., within the second interconnect layer 1208) for clarity, in some examples the lines 1228a and vias 1228b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0059] The third interconnect layer 1210 (referred to as metal 3 or "M3") (and additional interconnect layers, if desired) may be formed successively on the second interconnect layer 1208 according to techniques and / or configurations similar to those described in connection with the second interconnect layer 1208 or the first interconnect layer 1206. In some examples, interconnect layers "higher" in the metallization stack 1219 within the IC device 1200 (i.e., farther away from the device layer 1204) may be thicker.

[0060] The IC device 1200 may include a solder resist material 1234 (e.g., polyimide or a similar material) and one or more conductive contacts 1236 formed on the interconnect layers 1206-1210. In FIG. 12 , the conductive contacts 1236 are illustrated as taking the form of bond pads. The conductive contacts 1236 may be electrically coupled to the interconnect structure 1228 and may be configured to route electrical signals from the transistor 1240 to other external devices. For example, solder bonds may be formed on the one or more conductive contacts 1236 to mechanically and / or electrically couple a chip including the IC device 1200 to another component (e.g., a circuit board). The IC device 1200 may include additional or alternative structures for routing electrical signals from the interconnect layers 1206-1210. For example, the conductive contacts 1236 may include other similar features (e.g., posts) that route electrical signals to external components.

[0061] 13 is a cross-sectional side view of an IC device assembly 1300 that may include the example IC package 100 of FIG. 1 having a substrate that includes one or more of the example TGVs 202, 300, 402 disclosed herein. In some examples, the IC device assembly corresponds to the example IC package 100 of FIG. 1. The IC device assembly 1300 includes multiple components disposed on a circuit board 1302 (which may be, for example, a motherboard). The IC device assembly 1300 includes multiple components disposed on a first side 1340 of the circuit board 1302 and on an opposing second side 1342 of the circuit board 1302; typically, components may be disposed on one or both of the sides 1340 and 1342. Any of the IC packages described below with reference to the IC device assembly 2200 may take the form of the example IC package 100 of FIG. 1.

[0062] In some examples, the circuit board 1302 may be a printed circuit board (PCB) that includes multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed (optionally in conjunction with other metal layers) to route electrical signals between components coupled to the circuit board 1302 in a desired circuit pattern. In other examples, the circuit board 1302 may be a non-PCB substrate.

[0063] 13 includes a package-on-interposer structure 1336 coupled to a first surface 1340 of a circuit board 1302 by a coupling component 1316. The coupling component 1316 may electrically and mechanically couple the package-on-interposer structure 1336 to the circuit board 1302 and may include solder balls (as shown in FIG. 13), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0064] The package-on-interposer structure 1336 may include an IC package 1320 coupled to the interposer 1304 by a coupling component 1318. The coupling component 1318 may take any suitable form for the application, such as those described above with reference to the coupling component 1316. While a single IC package 1320 is shown in FIG. 13, multiple IC packages may be coupled to the interposer 1304, and indeed additional interposers may be coupled to the interposer 1304. The interposer 1304 may provide an intervening substrate used to bridge the circuit board 1302 and the IC package 1320. The IC package 1320 may be or include, for example, a die (such as the die 1102 in FIG. 11), an IC device (such as the IC device 1200 in FIG. 12), or any other suitable component. In general, the interposer 1304 may spread connections to a wider pitch or reroute connections to different connections. For example, interposer 1304 may include an IC package 1320 (e.g., a die) coupled to a set of BGA conductive contacts of coupling component 1316 for coupling to circuit board 1302. In the example illustrated in FIG. 13, IC package 1320 and circuit board 1302 are attached to opposite sides of interposer 1304; in other examples, IC package 1320 and circuit board 1302 may be attached to the same side of interposer 1304. In some examples, three or more components may be interconnected by interposer 1304.

[0065] In some examples, the interposer 1304 may be formed as a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some examples, the interposer 1304 may be formed of a polymeric material such as epoxy, fiberglass-reinforced epoxy, epoxy with inorganic fillers, ceramic material, or polyimide. In some examples, the interposer 1304 may be formed of alternative rigid or flexible materials. Such materials may include the same materials mentioned above for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 1304 may include metal interconnects 1308 and vias 1310, including, but not limited to, through-silicon vias (TSVs) 1306. The interposer 1304 may further include embedded devices 1314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the package interposer 1304. The package-on-interposer structure 1336 may take the form of any of the package-on-interposer structures known in the art.

[0066] IC device assembly 1300 may include an IC package 1324 coupled to a first surface 1340 of circuit board 1302 by a coupling component 1322. Coupling component 1322 may take the form of any of the examples described above with reference to coupling component 1316, and IC package 1324 may take the form of any of the examples described above with reference to IC package 1320.

[0067] 13 includes a package-on-package structure 1334 coupled to a second surface 1342 of a circuit board 1302 by a coupling component 1328. The package-on-package structure 1334 may include a first IC package 1326 and a second IC package 1332 coupled together by a coupling component 1330 such that the first IC package 1326 is disposed between the circuit board 1302 and the second IC package 1332. The coupling components 1328, 1330 may take the form of any of the examples of coupling component 1316 described above, and the IC packages 1326, 1332 may take the form of any of the examples of IC package 1320 described above. The package-on-package structure 1334 may be configured according to any of the package-on-package structures known in the art.

[0068] FIG. 14 is a block diagram of an example electrical device 1400 that may include one or more of the example IC packages 100 of FIG. 1 having a substrate that includes one or more of the example TGVs 202, 300, 402 disclosed herein. For example, any suitable components of the electrical device 1400 may include one or more of the device assemblies 1300, IC devices 1200, or die 1102 disclosed herein and may be disposed in the example IC package 100. While multiple components are shown in FIG. 14 as being included in the electrical device 1400, any one or more of these components may be omitted or duplicated if appropriate for the application. In some examples, some or all of the components included in the electrical device 1400 may be mounted on one or more motherboards. In some examples, some or all of these components are fabricated on a single system-on-chip (SoC) die.

[0069] 14 , but electrical device 1400 may include interface circuitry for coupling one or more components. For example, electrical device 1400 may not include display 1406, but may include display interface circuitry (e.g., connectors and driver circuitry) to which display 1406 may be coupled. In another set of examples, electrical device 1400 may not include audio input device 1418 (e.g., a microphone) or audio output device 1408 (e.g., a speaker, headset, earbuds, etc.), but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which audio input device 1418 or audio output device 1408 may be coupled.

[0070] The electrical device 1400 may include a programmable circuit 1402 (e.g., one or more processing devices). The programmable circuit 1402 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The electrical device 1400 may include a memory 1404. The memory 1404 may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some examples, the memory 1404 may include memory that shares a die with the programmable circuit 1402. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0071] In some examples, electrical device 1400 may include a communications chip 1412 (e.g., one or more communications chips). For example, communications chip 1412 may be configured to manage wireless communications for the transfer of data to and from electrical device 1400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data through the use of modulated electromagnetic radiation over a non-solid medium. Although associated devices may not include wiring in some examples, the term does not imply that associated devices do not include any wiring.

[0072] The communications chip 1412 may implement any of a number of wireless standards or protocols, including, but not limited to, Institute of Electrical and Electronics Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), the IEEE 802.16 standard (e.g., the IEEE 802.16-1205 amendment), and the Long Term Evolution (LTE) project with any amendments, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks. The acronym stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed IEEE 802.16 standard compliance and interoperability testing. The communications chip 1412 may operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communications chip 1412 may operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communications chip 1412 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and their derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond. The communications chip 1412 may operate according to other wireless protocols in other examples. Electrical device 1400 may include an antenna 1422 for facilitating wireless communication and / or for receiving other wireless communications (such as AM or FM radio transmissions).

[0073] In some examples, the communications chip 1412 may manage wired communications, such as electrical, optical, or any other suitable communications protocol (e.g., Ethernet). As noted above, the communications chip 1412 may include multiple communications chips. For example, a first communications chip 1412 may be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communications chip 1412 may be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, the first communications chip 1412 may be dedicated to wireless communications, and the second communications chip 1412 may be dedicated to wired communications.

[0074] Electrical device 1400 may include battery / power circuitry 1414. Battery / power circuitry 1414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of electrical device 1400 to an energy source (e.g., AC line power) separate from electrical device 1400.

[0075] The electrical device 1400 may include a display 1406 (or corresponding interface circuitry, as described above). The display device 1406 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0076] The electrical device 1400 may include an audio output device 1408 (or corresponding interface circuitry, as described above), which may include any device that generates an audible indicator, such as a speaker, a headset, or earbuds.

[0077] The electrical device 1400 may include an audio input device 1418 (or corresponding interface circuitry, as described above), which may include any device that generates signals representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a Musical Instrument Digital Interface (MIDI) output).

[0078] The electrical device 1400 may include a GPS circuit 1416. The GPS circuit 1416 may communicate with a satellite-based system to receive the location of the electrical device 1400 as is known in the art.

[0079] Electrical device 1400 may include any other output device(s) 1410 (or corresponding interface circuitry, as described above). Examples of other output device(s) 1410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0080] The electrical device 1400 may include any other input device(s) 1420 (or corresponding interface circuitry, as described above). Examples of the other input device(s) 1420 may include an accelerometer, a gyroscope, a compass, an imaging device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0081] Electrical device 1400 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electrical device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some examples, electrical device 1400 may be any other electronic device that processes data.

[0082] The terms "including" and "comprising" (and all their forms and tenses) are used herein as open-ended terms. Thus, whenever a claim uses any form of "include" or "comprise" (e.g., "comprises," "includes," "comprising," "including," "having," etc.) as a preamble or within any type of claim recitation, it is to be understood that additional elements, terms, etc. may be present without departing from the scope of the corresponding claim or recitation. As used herein, the phrase "at least" is open-ended in the same way that the terms "including" and "comprising" are open-ended when used, for example, as a transitional phrase in a claim preamble. The term "and / or," when used in the form of, for example, A, B, and / or C, refers to any combination or subset of A, B, and C, such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. When used herein in the context of describing a structure, component, item, object, and / or thing, the phrase "at least one of A and B" is intended to refer to an implementation that includes either (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, when used herein in the context of describing a structure, component, item, object, and / or thing, the phrase "at least one of A or B" is intended to refer to an implementation that includes either (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.When used herein in the context of describing the performance or execution of a process, instruction, operation, act, or the like, the phrase "at least one of A and B" is intended to refer to an implementation that includes either (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, when used herein in the context of describing the performance or execution of a process, instruction, operation, act, or the like, the phrase "at least one of A or B" is intended to refer to an implementation that includes either (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0083] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude a plurality. As used herein, the term "a" or "an" object refers to one or more of that object. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably herein. Furthermore, although individually listed, multiple means, elements, or actions may be implemented, for example, by the same entity or object. Additionally, although individual features may be included in different examples or claims, they may in some cases be combined, and their inclusion in different examples or claims does not imply that a combination of features is not feasible and / or advantageous.

[0084] As used herein, unless otherwise stated, the term "above" describes the relationship of two portions to the Earth. A first portion is above a second portion if the second portion has at least one portion between the Earth and the first portion. Similarly, as used herein, a first portion is "below" a second portion if the first portion is closer to the Earth than the second portion. As noted above, a first portion can be above or below a second portion, with or without other portions therebetween, with or without the first and second portions touching, or without the first and second portions directly contacting each other.

[0085] Notwithstanding the above, when referring to a semiconductor device (e.g., a transistor), a semiconductor die including a semiconductor device, and / or an integrated circuit (IC) package including a semiconductor die during fabrication or manufacturing, “above” does not refer to the earth, but instead to the underlying substrate upon which the associated components are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein, unless otherwise stated or implied by context, a first component (e.g., a transistor or other semiconductor device) within a semiconductor die is “above” a second component within the semiconductor die if, during fabrication / manufacturing, the first component is farther away from the substrate (e.g., a semiconductor wafer) upon which the two components are fabricated or otherwise provided than the second component. Similarly, unless otherwise stated or implied by context, a first component (e.g., a semiconductor die) within an IC package is “above” a second component within the IC package if, during fabrication, the first component is farther away from the printed circuit board (PCB) upon which the IC package will be mounted or attached. It is understood that a semiconductor device is often used in an orientation different from its orientation during fabrication. Thus, when referring to a semiconductor device (e.g., a transistor), a semiconductor die that includes the semiconductor device, and / or an integrated circuit (IC) package that includes the semiconductor die during use, the definition of "above" in the previous paragraph (i.e., the term "above" describes the relationship of two parts relative to the Earth) may be determined based on the context of use.

[0086] As used in this patent, a description of any part (e.g., a layer, film, area, region, or plate) being on (e.g., positioned on, located on, disposed on, or formed on) another part in any manner indicates that the referenced part is either in contact with the other part, or that the referenced part is on top of the other part with one or more intermediate parts located therebetween.

[0087] As used herein, unless otherwise indicated, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between, and / or relative movement between, the elements referenced by the connection reference. As such, a connection reference does not necessarily infer that two elements are directly connected and / or in a fixed relationship to one another. As used herein, a statement that a part is "in contact with" another part is defined to mean that there are no intermediate parts between the two parts.

[0088] Unless otherwise specifically stated, descriptors such as "first," "second," "third," etc. are used herein without any negation or otherwise implying any sense of priority, physical order, placement within a list, and / or ordering in any way, but are merely used as labels and / or arbitrary names to distinguish elements to facilitate understanding of the disclosed examples. In some instances, the descriptor "first" may be used to refer to an element in the detailed description, while the same element may be referred to in the claims using a different descriptor such as "second" or "third." In such instances, it should be understood that such descriptors are merely used to separately identify those elements within the context of the description (e.g., in the claims) (although the elements may otherwise share the same name, for example).

[0089] As used herein, "approximately" and "about" modify their objects / values ​​to recognize the existence of potential variations that occur in real-world applications. For example, "approximately" and "about" may modify dimensions that may not be exact due to manufacturing tolerances and / or other real-world imperfections, as understood by those skilled in the art. For example, "approximately" and "about" may indicate that such dimensions may be within a tolerance range of + / - 10%, unless otherwise specified herein.

[0090] As used herein, "substantially real-time" refers to occurring nearly instantaneously, although it is recognized that there may be real-world delays due to computing time, transmission, etc. Thus, unless otherwise specified, "substantially real-time" refers to real-time plus one second.

[0091] As used herein, the phrase "communicate" (including variations thereof) encompasses direct communication and / or indirect communication through one or more intermediary components and does not require direct physical (e.g., wired) communication and / or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and / or one-time events.

[0092] As used herein, "programmable circuitry" is defined to include (i) one or more special-purpose electrical circuits (e.g., application-specific circuits (ASICs)) that have a structure to perform a particular operation and that include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based electrical circuits that are programmable with instructions to perform a particular function and / or operation and that include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors such as a central processor unit (CPU) that can execute first instructions to perform one or more operations and / or functions; a field programmable gate array (FPGA) that can be programmed with second instructions to cause the configuration and / or structure of the FPGA to instantiate one or more operations and / or functions corresponding to the first instructions; a graphics processor unit (GPU) that can execute first instructions to perform one or more operations and / or functions; a digital signal processor (DSP), XPU, network processing unit (NPU) that can execute first instructions to perform one or more operations and / or functions; one or more microcontrollers that can execute first instructions to perform one or more operations and / or functions; and / or an integrated circuit such as an application specific integrated circuit (ASIC). For example, an XPU may be implemented by a heterogeneous computing system that includes multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof) and orchestration technology (e.g., an application programming interface (API)) that can assign a computing task to any one of the multiple types of programmable circuitry that is suitable and available to perform the computing task.

[0093] As used herein, an integrated circuit / circuitry is defined as one or more semiconductor packages that include one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuitry, a semiconductor substrate combining multiple circuit elements, a system on a chip (SoC), etc.

[0094] From the foregoing, it will be appreciated that exemplary systems, apparatus, products, and methods have been disclosed that enable the fabrication of high aspect ratio plated vias in a glass core. Plating metal (e.g., copper) within through-glass vias creates a risk of failure due to high stresses imposed on the glass core as a result of the CTE mismatch between the glass and the plated metal. However, the examples disclosed herein alleviate this concern through the use of a dielectric liner between the glass core and the plated metal, which acts as a stress buffer.

[0095] A further challenge with electroplating high aspect ratio vias is the inability to obtain complete coverage of the interior sidewalls of the vias using standard deposition techniques. The examples disclosed herein overcome these challenges by utilizing atomic layer deposition (ALD) to deposit a metal seed layer within the via. Not all conductive materials suitable for metal seed layers are compatible with ALD, and at least some compatible conductive materials do not provide strong adhesion with the metal that will be subsequently electroplated thereon. Accordingly, in some examples, an intercalator or transition layer is deposited on the metal seed layer deposited using ALD to promote greater adhesion for reliable production of high aspect ratio vias.

[0096] Further examples and combinations thereof include:

[0097] Example 1 includes a package substrate comprising a core having a via extending therethrough, a first conductive material in the via, a dielectric material at least partially between a wall of the via and the first conductive material, and a second conductive material in the via, wherein the second conductive material is closer to a central region of the via than the first conductive material is to the central region of the via, the first conductive material is different from the second conductive material, and the first conductive material is at least partially between the dielectric material and the second conductive material.

[0098] Example 2 includes the package substrate of Example 1, wherein the core is a glass core.

[0099] Example 3 includes the package substrate of any one of Examples 1 or 2, wherein the first conductive material comprises ruthenium and the second conductive material comprises copper.

[0100] Example 4 includes the package substrate of Example 3, wherein the first conductive material comprises both ruthenium and copper.

[0101] Example 5 includes the package substrate of any one of Examples 1 to 4, wherein the via has an aspect ratio of at least 6.

[0102] Example 6 includes the package substrate of Example 5, wherein the first conductive material has a first thickness at a first end of the via, a second thickness at a second end of the via, and a third thickness at a midpoint of the via, the first thickness being approximately equal to the second thickness and approximately equal to the third thickness.

[0103] Example 7 includes the package substrate of any one of Examples 1 to 6, wherein the dielectric material has a thickness between approximately 0.5 micrometers and 9 micrometers.

[0104] Example 8 includes the package substrate of any one of Examples 1 to 7, wherein the first conductive material has a thickness of less than 70 nanometers.

[0105] Example 9 includes the package substrate of any one of Examples 1 to 8, further comprising a third conductive material at least partially between the first conductive material and the second conductive material, the third conductive material being different from the first conductive material and different from the second conductive material.

[0106] Example 10 includes the package substrate of example 9, wherein the third conductive material has a thickness between approximately 5 nanometers and 100 nanometers.

[0107] Example 11 includes the package substrate of any one of Examples 9 or 10, wherein the third conductive material includes at least one of titanium or copper.

[0108] Example 12 includes a package substrate comprising: a glass core having a through hole extending from a first surface of the glass core to a second surface of the glass core; a dielectric liner covering an inner surface of the through hole; a conductive liner covering the dielectric liner; and a conductive fill material within the through hole, the conductive liner having a different composition than the conductive fill material, and the conductive liner separating the dielectric liner from the conductive fill material.

[0109] Example 13 includes the package substrate of Example 12, wherein the conductive liner includes ruthenium.

[0110] Example 14 includes the package substrate of any one of Examples 12 or 13, wherein the length of the through hole is at least 10 times the width of the through hole, and the conductive liner conformally coats the dielectric liner with a substantially consistent thickness along the length of the through hole.

[0111] Example 15 includes the package substrate of any one of Examples 12 to 14, wherein the conductive liner includes less than 0.1 wt % titanium.

[0112] Example 16 includes the package substrate of any one of Examples 12 to 15, wherein the dielectric liner includes an inorganic filler.

[0113] Example 17 includes the package substrate of any one of Examples 12 to 16, wherein the dielectric liner includes at least one of an epoxy, a polyimide, or a parylene.

[0114] Example 18 includes the package substrate of any one of Examples 12 to 17, wherein the dielectric liner includes silicon and at least one of oxygen, nitrogen, hydrogen, or carbon.

[0115] Example 19 includes a system comprising a semiconductor die, a package substrate including a glass core, the glass core having an opening with a height-to-width aspect ratio of at least 9, a first conductive material in the opening, and a second conductive material between the first conductive material and a sidewall of the opening, the second conductive material having a thickness that differs by less than 5% between any two points on the sidewall of the opening, and the second conductive material including ruthenium.

[0116] Example 20 includes the system of example 19, further including at least one of a keyboard or a display.

[0117] The following claims are hereby incorporated by reference into this detailed description. Although certain exemplary systems, apparatus, products, and methods are disclosed herein, the scope of coverage of this patent is not limited thereto. To the contrary, this patent covers all systems, apparatus, products, and methods that fall even slightly within the scope of the claims of this patent.

Claims

1. a core having a via extending therethrough; a first conductive material in the via; a dielectric material at least partially between the wall of the via and the first conductive material; and a second conductive material in the via; Equipped with The second conductive material is closer to the central region of the via than the first conductive material is to the central region of the via, the first conductive material is different from the second conductive material, and the first conductive material is at least partially between the dielectric material and the second conductive material. Package substrate.

2. The package substrate of claim 1 , wherein the core is a glass core.

3. The package substrate of claim 1 , wherein the first conductive material comprises ruthenium and the second conductive material comprises copper.

4. The package substrate of claim 3 , wherein the first conductive material comprises both ruthenium and copper.

5. The package substrate of claim 1 , wherein the via has an aspect ratio of at least 6.

6. 6. The package substrate of claim 5, wherein the first conductive material has a first thickness at a first end of the via, a second thickness at a second end of the via, and a third thickness at a midpoint of the via, the first thickness being approximately equal to the second thickness and approximately equal to the third thickness.

7. The package substrate of claim 1 , wherein the dielectric material has a thickness between approximately 0.5 micrometers and 9 micrometers.

8. The package substrate of claim 1 , wherein the first conductive material has a thickness of less than 70 nanometers.

9. 9. The package substrate of claim 1, further comprising a third conductive material at least partially between the first conductive material and the second conductive material, the third conductive material being different from the first conductive material and different from the second conductive material.

10. The package substrate of claim 9 , wherein the third conductive material has a thickness between approximately 5 nanometers and 100 nanometers.

11. The package substrate of claim 9 , wherein the third conductive material comprises at least one of titanium or copper.

12. a glass core having a through hole extending from a first surface of the glass core to a second surface of the glass core; a dielectric liner covering the inner surface of the through hole; a conductive liner covering the dielectric liner; and the conductive filler material in the through-hole Equipped with The conductive liner comprises a different composition than the conductive fill material, and the conductive liner separates the dielectric liner from the conductive fill material. Package substrate.

13. The package substrate of claim 12 , wherein the conductive liner comprises ruthenium.

14. 13. The package substrate of claim 12, wherein the length of the through hole is at least 10 times the width of the through hole, and the conductive liner conformally coats the dielectric liner with a substantially consistent thickness along the length of the through hole.

15. The package substrate of claim 12 , wherein the conductive liner comprises less than 0.1 wt % titanium.

16. The package substrate of claim 12 , wherein the dielectric liner comprises an inorganic filler.

17. The package substrate of claim 12 , wherein the dielectric liner comprises at least one of an epoxy, a polyimide, or a parylene.

18. 18. The package substrate of claim 12, wherein the dielectric liner comprises silicon and at least one of oxygen, nitrogen, hydrogen, or carbon.

19. semiconductor die; a package substrate including a glass core, said glass core having an opening with a height-to-width aspect ratio of at least 9; a first conductive material in the opening; and a second conductive material between the first conductive material and the sidewall of the opening; Equipped with The second conductive material has a thickness that varies by less than 5% between any two points on the sidewall of the opening, and the second conductive material comprises ruthenium. system.

20. 20. The system of claim 19, further comprising at least one of a keyboard or a display.

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