Manufacturing method for semiconductor device

Abstract

To provide a manufacturing method for a semiconductor device with high yield.SOLUTION: In a semiconductor device including an oxide semiconductor on a substrate, when an insulator is formed in contact with a gate insulator or an oxide semiconductor such as an interlayer film, the constant derived from film formation conditions is set in a certain range; thus, the insulator can be formed without hydrogen diffusing to the oxide semiconductor. Specifically, the set values of the film formation power, the execution electrode area, the film formation pressure, and the flow rate of film formation gas including hydrogen in the film formation conditions can be selected as appropriate.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] TECHNICAL FIELD One embodiment of the present invention relates to a semiconductor device and a manufacturing method of the semiconductor device.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] Technology that constructs transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

[0005] In oxide semiconductors, c-axis aligned crystalline (CAAC) structures and nanocrystalline (nc) structures, which are neither single crystal nor amorphous, have been found (see Non-Patent Documents 1 and 2).

[0006] Non-Patent Documents 1 and 2 disclose techniques for manufacturing a transistor using an oxide semiconductor having a CAAC structure. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a method for manufacturing a semiconductor device, in which an oxide semiconductor is formed over a substrate and an insulator is formed over the oxide semiconductor by chemical vapor deposition so as to satisfy the following relationship (1): where PW [W] is deposition power, S [cm 2 ] represents the effective electrode area, P [Pa] represents the deposition pressure, and f [sccm] represents the flow rate of the silane (SiH4)-based deposition gas.

[0011]

number

[0012] One embodiment of the present invention is a method for manufacturing a semiconductor device, in which an oxide semiconductor is formed over a substrate and an insulator is formed over the oxide semiconductor by chemical vapor deposition so as to satisfy the following relationship (2): where PW [W] is deposition power, S [cm 2 ] represents the effective electrode area, P [Pa] represents the deposition pressure, and f [sccm] represents the flow rate of the silane (SiH4)-based deposition gas.

[0013]

number

[0014] In the above method for manufacturing a semiconductor device, an oxide semiconductor is formed, a conductor is formed in contact with the oxide semiconductor, and part of the conductor is removed to expose the oxide semiconductor. Then, an insulator is formed in the exposed region of the oxide semiconductor.

[0015] In the above method for manufacturing a semiconductor device, a metal oxide film is formed in contact with a conductor.

[0016] In the above, the metal oxide film is a method for manufacturing a semiconductor device that suppresses diffusion of hydrogen and impurities.

[0017] In the above method for manufacturing a semiconductor device, the oxide semiconductor is an In—Ga—Zn oxide. [Effects of the Invention]

[0018] According to one embodiment of the present invention, a semiconductor device can be manufactured with high yield and low cost.

[0019] According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to another embodiment of the present invention, a semiconductor device with excellent electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0020] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0021] [Figure 1] 1A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 1B to 1D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 2] 2A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 2B to 2D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 3] 3A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 3B to 3D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 4] 4A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 4B to 4D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 5]5A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 5B to 5D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 6] 6A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 6B to 6D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 7] 7A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 7B to 7D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 8] 8A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 8B to 8D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 9] 9A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 9B to 9D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 10] 10A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 10B and 10C are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 11] 11A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 11B to 11D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 12] FIG. 12 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 13] FIG. 13 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 14] FIG. 14 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 15] FIG. 15A is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention, and FIG. 15B is a perspective view. [Figure 16] 16A to 16H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 17] FIG. 17A is a block diagram of a semiconductor device according to one embodiment of the present invention, and FIG. 17B is a schematic diagram. [Figure 18]18A to 18E are schematic diagrams of a memory device according to one embodiment of the present invention. [Figure 19] 19A to 19H are diagrams illustrating an electronic device according to one embodiment of the present invention. [Figure 20] FIG. 20A is a schematic diagram of a sample according to this example, and FIG. 20B is a diagram illustrating the concentration of added deuterium. [Figure 21] FIG. 21A is a schematic diagram of a sample according to this example, and FIG. 21B is a diagram illustrating the state of the top surface. [Figure 22] 22A and 22B are diagrams illustrating the state of the upper surface of the sample according to this example. [Figure 23] FIG. 23 is a diagram illustrating the rate of film floating in the sample according to this example. [Figure 24] 24A and 24B are diagrams illustrating a cross section of a sample according to this example. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0023] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers, resist masks, etc. may be unintentionally thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same symbols are used for identical parts or parts having similar functions across different drawings, and repeated explanations may be omitted. When referring to similar functions, the same hatch pattern may be used and no particular symbols may be assigned.

[0024] In order to make the invention easier to understand, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0025] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc. in the description. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification.

[0026] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0027] For example, if it is explicitly stated in this specification that X and Y are connected, it is assumed that the specification also discloses cases in which X and Y are electrically connected, cases in which X and Y are functionally connected, and cases in which X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is assumed that connections other than those shown in a figure or text are also disclosed in a figure or text. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0028] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. In this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0029] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0030] Note that the channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0031] The channel width refers to, for example, the length of a channel formation region in a region where a semiconductor (or a portion of the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or the length of the channel formation region in a direction perpendicular to the channel length direction in the channel formation region. Note that the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a single transistor may not be determined to a single value. Therefore, in this specification, the channel width refers to any one value, maximum value, minimum value, or average value in the channel formation region.

[0032] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In such a case, the effective channel width is larger than the apparent channel width.

[0033] In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0034] In this specification, when simply referred to as a channel width, it may refer to an apparent channel width. Alternatively, when simply referred to as a channel width, it may refer to an effective channel width. Note that values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0035] Note that impurities in a semiconductor refer to, for example, substances other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the density of defect states in the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen vacancies in the oxide semiconductor.

[0036] In this specification and the like, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0037] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0038] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0039] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0040] Furthermore, in this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1 x 10 at 85°C -18 A or less, or 1 x 10 at 125°C -16 This means that it is A or below.

[0041] (Embodiment 1) In this embodiment, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention will be described. The transistor 200 according to one embodiment of the present invention is a transistor including an oxide semiconductor in a channel formation region.

[0042] Here, an example of a semiconductor device including a transistor according to one embodiment of the present invention will be described in detail with reference to drawings.

[0043] <Configuration example of semiconductor device> FIG. 1 shows a top view and a cross-sectional view of a semiconductor device including a transistor 200 according to one embodiment of the present invention. FIG. 1A is a top view of the semiconductor device. FIGS. 1B and 1C are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A. FIG. 1C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 1A. FIG. 1D is a cross-sectional view of a portion indicated by a dashed line A5-A6 in FIG. 1A. Note that some elements are omitted from the top view of FIG. 1A for clarity.

[0044] A semiconductor device of one embodiment of the present invention includes a transistor 200 and an insulator 214, an insulator 216, an insulator 280, an insulator 282, and an insulator 284, which function as interlayer films. Note that the insulator 280 is provided in contact with at least the oxide 230.

[0045] [Transistor 200] 1 , the transistor 200 is disposed on a substrate (not shown) and includes a conductor 205 disposed so as to be embedded in an insulator 216, an insulator 222 disposed on the insulator 216 and on the conductor 205, an insulator 224 disposed on the insulator 222, an oxide 230 (oxide 230a and oxide 230b) disposed on the insulator 224, an insulator 250 disposed on the oxide 230, a conductor 260 (conductor 260a and conductor 260b) disposed on the insulator 250, a conductor 240a and a conductor 240b in contact with a portion of the top surface of the oxide 230b, an insulator 245a on the conductor 240a, and an insulator 245b on the conductor 240b. Note that the conductors 240a and 240b may be collectively referred to as the conductor 240. The insulator 245a and the insulator 245b may be collectively referred to as the insulator 245.

[0046] Furthermore, in the transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as an oxide semiconductor for the oxide 230 (oxide 230a and oxide 230b) including a region where a channel is formed (hereinafter also referred to as a channel formation region).

[0047] As the oxide semiconductor, for example, a metal oxide such as In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used. Alternatively, as the oxide semiconductor, In-Ga-Zn oxide, In-Ga oxide, or In-Zn oxide may be used.

[0048] Note that the oxide semiconductor functioning as a channel formation region preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. By using an oxide semiconductor with such a wide band gap, the off-state current of the transistor can be reduced.

[0049] The transistor 200 using an oxide semiconductor for a channel formation region has an extremely small leakage current in an off-state; therefore, a semiconductor device with low power consumption can be provided.

[0050] Furthermore, by using an oxide semiconductor, various elements can be stacked and integrated three-dimensionally. That is, since an oxide semiconductor can be deposited by a method such as sputtering, circuits can be laid out not only on the plane of a substrate but also in the vertical direction to form a three-dimensional integrated circuit (3D integrated circuit).

[0051] On the other hand, the electrical characteristics of a transistor using an oxide semiconductor tend to change due to impurities and oxygen vacancies in the oxide semiconductor, and the transistor tends to have normally-on characteristics (characteristics in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Examples of impurities in an oxide semiconductor that affect the electrical characteristics of a transistor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0052] Here, the influence of each impurity in an oxide semiconductor will be described.

[0053] When impurities are mixed into an oxide semiconductor, defect states or oxygen vacancies may be formed. When impurities are mixed into a channel formation region of an oxide semiconductor, the electrical characteristics of a transistor using the oxide semiconductor are likely to fluctuate, and the reliability may be reduced. Furthermore, when oxygen vacancies are present in the channel formation region, the transistor is likely to have normally-on characteristics.

[0054] The defect levels may include trap levels. Charges trapped in the trap levels of metal oxides take a long time to disappear and may behave like fixed charges. Therefore, a transistor having a channel formation region made of a metal oxide with a high density of trap levels may have unstable electrical characteristics.

[0055] Furthermore, the presence of impurities in the channel formation region of the oxide semiconductor may reduce the crystallinity of the channel formation region or the crystallinity of an oxide provided in contact with the channel formation region. The low crystallinity of the channel formation region tends to reduce the stability or reliability of the transistor. Furthermore, the low crystallinity of the oxide provided in contact with the channel formation region may form an interface state, which may reduce the stability or reliability of the transistor.

[0056] Therefore, in order to improve the stability or reliability of a transistor, it is effective to reduce the impurity concentration in the channel formation region of the oxide semiconductor and in its vicinity.

[0057] Specifically, the concentration of impurities such as hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, and silicon in and around the channel formation region of the oxide semiconductor, which is obtained by secondary ion mass spectrometry (SIMS), is set to 1×10 20 atoms / cm 3 Less than or equal to 2 x 10 19 atoms / cm 3 Do the following:

[0058] Alternatively, the impurity concentration in the channel formation region of the oxide semiconductor and its vicinity, as determined by elemental analysis using EDX, is set to 1.0 atomic % or less. When an oxide containing element M is used as the oxide semiconductor, the concentration ratio of the impurity to element M in the channel formation region of the oxide semiconductor and its vicinity is set to less than 0.10, preferably less than 0.05. Here, the concentration of element M used in calculating the concentration ratio may be the concentration in the same region as the region where the impurity concentration is calculated, or may be the concentration in the oxide semiconductor.

[0059] Furthermore, metal oxides with reduced impurity concentrations have a low defect state density, and therefore may also have a low trap state density.

[0060] Therefore, it is preferable to use a high-purity intrinsic oxide semiconductor in which impurities and oxygen vacancies are reduced as the oxide semiconductor used for the channel formation region of a transistor. Note that in this specification and the like, a high-purity intrinsic oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic oxide semiconductor or a substantially high-purity intrinsic oxide semiconductor.

[0061] Even when a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor is formed, impurities may diffuse into the oxide semiconductor from a structure in contact with the oxide semiconductor or from the outside of the structure.

[0062] In particular, hydrogen may be added when an insulator that functions as a gate insulator and is formed in contact with an oxide semiconductor or an insulator that functions as an interlayer film is formed.

[0063] Specifically, the gate insulator or the interlayer film can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, etc. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0064] On the other hand, when silicon oxide and silicon oxynitride are formed by chemical vapor deposition (CVD), silane (SiH4)-based deposition gases containing hydrogen, such as monosilane (SiH4), tetraethoxysilane ([Si(OC2H5)4]; TEOS), and trimethoxysilane ([Si(OCH3)3H]; TMS), may be used.

[0065] Organosilane gas may also be used. For example, in addition to the aforementioned tetraethoxysilane (TEOS: chemical formula Si(OC2H5)4), silicon-containing compounds such as tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), and trisdimethylaminosilane (SiH(N(CH3)2)3) may also be used.

[0066] When an insulator is formed using a deposition gas containing hydrogen, hydrogen contained in the deposition gas is likely to diffuse into an oxide semiconductor exposed at a surface where the insulator is to be deposited.

[0067] Furthermore, among impurities, hydrogen has a small atomic radius and therefore tends to move easily (or to diffuse easily) in an insulating layer or a conductive layer.

[0068] Also, when a conductor is provided in contact with a metal oxide, when hydrogen reaches such a structure (a laminated structure of a metal oxide and a conductor), there is a high probability that film lifting and film peeling (also referred to as peeling) will occur between the metal oxide and the conductor.

[0069] That is, when provided in contact with a conductor between an oxide semiconductor, which is a metal oxide, and a conductor, or when an insulating metal oxide is provided in contact with a conductor as part of a transistor structure, hydrogen diffused in the oxide semiconductor may reach the interface between the metal oxide and the conductor, and film lifting and film peeling may occur.

[0070] Specifically, in a semiconductor device having the transistor 200 shown in FIG. 1, film lifting or film peeling tends to occur at the surface where the oxide 230b and the conductor 240 are in contact, or at the surface where the conductor 240 and the insulator 245 are in contact.

[0071] Therefore, in the present embodiment, when a film-forming gas containing hydrogen is used in chemical vapor deposition for forming a structure constituting a semiconductor, a film-forming condition is used in which a constant Y satisfying the following formula is 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0. The constant Y can be expressed using the film-forming power PW [W], the execution electrode area S [cm 2 , the film-forming pressure P [Pa], and the flow rate f [sccm] of the film-forming gas containing hydrogen.

[0072]

Equation

[0073] By performing film formation using the film-forming condition in which the above constant Y is 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0, it is possible to suppress hydrogen in the film-forming atmosphere from diffusing from the film-forming surface exposed to the film-forming gas into the interior of the film-forming object. That is, by setting the film-forming power PW, the pressure P, and the flow rate f to optimal conditions, it is possible to form an insulator without hydrogen contained in the film-forming gas diffusing into the interior of the film-forming object.

[0074] Further, by disposing an insulator formed under a film formation condition where the above constant Y satisfies 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0, in proximity to the metal oxide, it is possible to suppress film floating and film peeling (also referred to as peeling) that occur between the metal oxide and the conductor. Specifically, in the semiconductor device having the transistor 200 shown in FIG. 1, it is possible to prevent film floating or film peeling that may occur on the surface where the oxide 230b and the conductor 240 are in contact, or on the surface where the conductor 240 and the insulator 245 are in contact.

[0075] Hereinafter, the detailed structure of the transistor will be described.

[0076] The oxide 230 preferably has a laminated structure of a plurality of oxide layers having different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b.

[0077] In the transistor 200 shown in FIG. 1, the oxide 230 is shown having a structure in which two layers, the oxide 230a and the oxide 230b, are laminated. However, the present invention is not limited to this. For example, a single layer of the oxide 230b or a structure provided with a laminated structure of three or more layers may be used. Further, the oxide 230a and the oxide 230b may each have a laminated structure.

[0078] Also, as shown in FIG. 1D, at least the side surfaces of the oxide 230b and the conductor 240 are preferably substantially perpendicular to the surface where the insulator 224 and the oxide 230a are in contact. Specifically, in FIG. 1D, the side surfaces of the oxide 230b and the conductor 240 are preferably set to 60 degrees or more and 95 degrees or less, preferably 88 degrees or more and 92 degrees or less, with respect to the surface where the insulator 224 and the oxide 230a are in contact.

[0079] 1C, the upper end of the oxide 230 in the channel formation region preferably has a curved shape. That is, in the channel formation region, the upper surface and side surface of the oxide 230 should be smoothly connected by a curved surface without forming corners. Because the channel formation region does not have corners, electric field concentration due to the electric field of either or both of the conductor 260 functioning as the first gate electrode and the conductor 205 functioning as the second gate electrode does not occur, and deterioration of the oxide 230 can be suppressed.

[0080] 1D, the upper end of the oxide 230 in the region overlapping with the conductor 240 preferably has a shape with a smaller curvature than the upper end of the oxide 230 in the channel formation region. The above structure can be formed by processing the oxide 230b and the conductor 240 using the same mask. Therefore, since the conductor 240 overlaps within the projected area of ​​the oxide 230b, a miniaturized transistor can be fabricated.

[0081] The conductor 260 functions as a first gate electrode (also called a top gate).

[0082] Here, the ends of the conductors 240a and 240b are preferably flush with the side surfaces of the openings. Also, as shown in Figure 1B or 1C, the top surface of the conductor 260 is substantially flush with the top surfaces of the insulator 250 and the oxide 230c.

[0083] 1C , in the region where the conductor 260 and the oxide 230 do not overlap, the shortest distance from the surface where the conductor 260 and the insulator 250 contact each other to the top surface of the insulator 222 is preferably shorter than the shortest distance from the surface where the oxide 230b and the oxide 230a contact each other to the top surface of the insulator 222. In other words, in the channel width direction of the transistor 200, the side surface of the oxide 230b is covered with the conductor 260 at least via the insulator 250.

[0084] The conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, so that the electric field of the conductor 260 acts on the entire channel formation region of the oxide 230b. Therefore, the on-state current of the transistor 200 can be increased, and the frequency characteristics can be improved.

[0085] It is preferable that the conductor 260 has a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260a is preferably arranged so as to surround the bottom and side surfaces of the conductor 260b.

[0086] The conductor 260a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0087] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0088] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0089] In FIG. 1, the conductor 260 is shown as having a two-layer structure of the conductor 260a and the conductor 260b, but it may have a single-layer structure or a laminated structure of three or more layers.

[0090] The conductor 205 functions as a second gate (also called a bottom gate) electrode.

[0091] Furthermore, when the conductor 205 functions as a gate electrode, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.

[0092] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulator 216 or the insulator 214.

[0093] In addition, in the channel width direction, the conductor 205 is preferably provided to be larger than the channel formation region in the oxide 230. In particular, as shown in FIG. 1C, it is preferable that the conductor 205 extends so as to intersect with the channel width direction of the oxide 230.

[0094] Here, it is preferable that the conductor 205 and the conductor 260 overlap with each other through an insulator on the outside of the side surface in the channel width direction of the oxide 230. With this structure, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 functioning as a first gate electrode and the electric field of the conductor 205 functioning as a second gate electrode.

[0095] 1 shows the conductor 205 as a laminate of a first conductor and a second conductor, but the present invention is not limited to this. For example, the conductor 205 may be configured as a single layer or a laminate structure of three or more layers. When the structure has a laminate structure, ordinal numbers may be assigned to indicate the order of formation to distinguish them.

[0096] Here, the first conductor of the conductor 205 is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0097] By using a conductive material that has the function of suppressing oxygen diffusion as the first conductor of the conductor 205, it is possible to suppress the second conductor of the conductor 205 from being oxidized and its conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the first conductor of the conductor 205 may be a single layer or a multilayer of the above conductive materials. For example, the first conductor of the conductor 205 may be a multilayer of tantalum, tantalum nitride, ruthenium, or ruthenium oxide with titanium or titanium nitride.

[0098] Furthermore, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component for the second conductor of the conductor 205. Note that although the second conductor of the conductor 205 is illustrated as a single layer, it may have a laminated structure, for example, a laminate of titanium or titanium nitride and the conductive material.

[0099] 1C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Furthermore, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0100] The conductor 240 (conductor 240a and conductor 240b) functions as a source electrode or a drain electrode.

[0101] Specifically, it is preferable to use TaNxOy as the conductor 240. Note that TaNxOy may contain aluminum. In addition, for example, titanium nitride, nitride containing titanium and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. may also be used. These materials are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when they absorb oxygen.

[0102] It is also preferable to provide an insulator 245 over the conductor 240 to function as a barrier layer.

[0103] 1B, the insulator 245 is preferably in contact with the top surface of the conductor 240. This structure can prevent the conductor 240 from absorbing excess oxygen contained in the insulator 280. Furthermore, by preventing oxidation of the conductor 240, an increase in contact resistance between the transistor 200 and wiring can be prevented. This allows the transistor 200 to have good electrical characteristics and reliability.

[0104] Therefore, it is preferable that the insulator 245 has a function of suppressing oxygen diffusion. For example, it is preferable that the insulator 245 has a function of suppressing oxygen diffusion more than the insulator 280.

[0105] For example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed as the insulator 245. Alternatively, for example, an insulator containing aluminum nitride may be used as the insulator 245.

[0106] Insulator 250 serves as the first gate insulator.

[0107] The insulator 250 is disposed in contact with at least the oxide 230. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, etc. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0108] Furthermore, it is preferable that the insulator 250 be made of an oxide material from which some oxygen is released by heating. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0 × 10 19 molecules / cm 3 More preferably, 2.0 × 10 19 molecules / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0109] By providing an insulator 250 that releases oxygen upon heating in contact with the oxide 230, oxygen can be effectively supplied to the channel formation region of the oxide 230b, thereby reducing oxygen vacancies in the channel formation region of the oxide 230b. Therefore, a transistor with reduced fluctuations in electrical characteristics, stable electrical characteristics, and improved reliability can be provided. Furthermore, it is preferable that the concentrations of impurities such as water and hydrogen in the insulator 250 be reduced.

[0110] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0111] The metal oxide may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a high-k metal oxide with a high dielectric constant. By forming the gate insulator into a laminated structure of the insulator 250 and the metal oxide, a thermally stable laminated structure with a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, it also allows the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator to be reduced.

[0112] Specifically, it is possible to use a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.

[0113] The metal oxide may also function as a part of the first gate electrode. For example, an oxide semiconductor that can be used as the oxide 230 can be used as the metal oxide. In this case, by forming the conductor 260 by a sputtering method, the electrical resistance of the metal oxide can be reduced to make it a conductor.

[0114] The inclusion of the metal oxide can improve the on-state current of the transistor 200 without weakening the influence of the electric field from the conductor 260. Furthermore, the physical thickness of the insulator 250 and the metal oxide can maintain a distance between the conductor 260 and the oxide 230, thereby suppressing leakage current between the conductor 260 and the oxide 230. Furthermore, the provision of a stacked structure of the insulator 250 and the metal oxide can easily and appropriately adjust the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230.

[0115] Insulator 222 and insulator 224 function as a second gate insulator.

[0116] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0117] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 can be prevented from reacting with the insulator 224 or the oxygen contained in the oxide 230.

[0118] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0119] The insulator 222 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0120] The insulator 224 in contact with the oxide 230 preferably releases oxygen by heating, similar to the insulator 250. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

[0121] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structures are not limited to those made of the same material, and may be those made of different materials.

[0122] The insulators 214, 216, 280, 282, and 284 function as interlayer films.

[0123] The insulator 214 preferably functions as an insulating barrier film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200. Therefore, the insulator 214 is preferably made of an insulating material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms. Alternatively, the insulator 214 is preferably made of an insulating material that suppresses the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0124] For example, it is preferable to use aluminum oxide, silicon nitride, or the like as the insulator 214. This can prevent impurities such as water and hydrogen from diffusing from the substrate side of the insulator 214 toward the transistor 200. Alternatively, it can prevent oxygen contained in the insulator 224 or the like from diffusing toward the substrate side of the insulator 214. Note that the insulator 214 may have a stacked structure of two or more layers. In this case, the insulator 214 is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials. For example, a stacked structure of aluminum oxide and silicon nitride may be used.

[0125] For example, it is preferable to use a silicon nitride film formed by sputtering as the insulator 214. This can reduce the hydrogen concentration in the insulator 214 and further suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side relative to the insulator 214.

[0126] The insulator 216, which functions as an interlayer film, preferably has a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. For example, the insulator 216 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with vacancies, or the like, as appropriate.

[0127] The insulator 216 preferably has a region where the hydrogen concentration is low and oxygen is present in excess of the stoichiometric composition (hereinafter also referred to as an excess oxygen region) or oxygen that is released by heating (hereinafter also referred to as excess oxygen). For example, the insulator 216 is preferably made of silicon oxide formed by sputtering. This can suppress hydrogen from entering the oxide 230, or can supply oxygen to the oxide 230 and reduce oxygen vacancies in the oxide 230. Therefore, a transistor with suppressed fluctuations in electrical characteristics, stable electrical characteristics, and improved reliability can be provided.

[0128] The insulator 216 may have a layered structure. For example, the insulator 216 may have a configuration in which an insulator similar to the insulator 214 is provided at least in the portion that contacts the side surface of the conductor 205. With such a configuration, it is possible to prevent the conductor 205 from being oxidized by the oxygen contained in the insulator 216. Alternatively, it is possible to prevent the amount of oxygen contained in the insulator 216 from decreasing due to the conductor 205.

[0129] The insulator 280 is provided on the insulator 224, the oxide 230, and the conductor 240. The top surface of the insulator 280 may also be planarized.

[0130] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce the parasitic capacitance that occurs between wirings. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is released by heating.

[0131] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. The insulator 280 also preferably has a low hydrogen concentration and an excess oxygen region or excess oxygen, and may be formed using, for example, the same material as the insulator 216. The insulator 280 may have a stacked structure of two or more layers.

[0132] Like the insulator 214, the insulator 282 preferably functions as an insulating barrier film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280. Also, like the insulator 214, the insulator 282 preferably has a low hydrogen concentration and a function of suppressing the diffusion of hydrogen.

[0133] 1B, the insulator 282 preferably contacts the top surfaces of the conductor 260 and the insulator 250. This can prevent impurities such as hydrogen contained in the insulator 284 from entering the insulator 250. This can prevent adverse effects on the electrical characteristics and reliability of the transistor.

[0134] An insulator 284 that functions as an interlayer film is preferably provided on the insulator 282. The insulator 284 preferably has a low dielectric constant, similar to the insulator 216. Furthermore, the insulator 284 preferably has a reduced concentration of impurities such as water and hydrogen, similar to the insulator 224.

[0135] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0136] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride and a metal oxide. Examples of other substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, or the like.

[0137] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0138] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0139] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0140] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0141] Furthermore, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding it with an insulator (such as the insulator 214, the insulator 222, the insulator 245, or the insulator 282) that has a function of suppressing the permeation of oxygen and impurities such as hydrogen. Examples of insulators that have a function of suppressing the permeation of oxygen and impurities such as hydrogen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum, and these insulators may be used in a single layer or a stack. Specifically, examples of insulators that have a function of suppressing the permeation of oxygen and impurities such as hydrogen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0142] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0143] <<Conductors>> The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0144] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0145] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0146] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0147] <<Metal oxides>> It is preferable to use a metal oxide that functions as an oxide semiconductor as the oxide 230. Metal oxides that can be used as the oxide 230 according to the present invention will be described below.

[0148] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0149] Here, we consider a case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, there are cases where a combination of the aforementioned elements can be used as element M.

[0150] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0151] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors, such as CAAC-OS, polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0152] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distorted crystal structure refers to the change in the lattice orientation between regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement in the regions where multiple nanocrystals are connected.

[0153] Nanocrystals are basically hexagonal, but not necessarily regular hexagons; they can also have non-regular hexagonal shapes. Furthermore, the lattice arrangement of CAAC-OS can be pentagonal, heptagonal, or other shapes due to distortion. It is difficult to identify clear grain boundaries in CAAC-OS, even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the ab-plane direction and the change in interatomic bond distance caused by substitution of metal elements.

[0154] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as an (M,Zn) layer) are stacked. Note that indium and the element M are mutually substituted, and when the element M in an (M,Zn) layer is substituted with indium, it can also be expressed as an (In,M,Zn) layer. When the indium in an In layer is substituted with the element M, it can also be expressed as an (In,M) layer.

[0155] CAAC-OS is a metal oxide with high crystallinity. Because it is difficult to identify clear grain boundaries in CAAC-OS, it is unlikely that the electron mobility will decrease due to grain boundaries. Furthermore, because the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects, CAAC-OS can be considered a metal oxide with few impurities or defects (such as oxygen vacancies). Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0156] The nc-OS has periodic atomic arrangement in a small region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0157] In-Ga-Zn oxide (hereinafter referred to as IGZO), a type of metal oxide containing indium, gallium, and zinc, can sometimes have a stable structure when made into the above-mentioned nanocrystals. In particular, since IGZO tends to have difficulty growing crystals in the atmosphere, it may be structurally more stable to make it into smaller crystals (for example, the above-mentioned nanocrystals) than larger crystals (here, crystals of a few millimeters or a few centimeters).

[0158] The a-like OS is a metal oxide having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0159] Oxide semiconductors (metal oxides) have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0160] <Method for manufacturing semiconductor device> Next, a method for manufacturing a semiconductor device including the transistor 200 according to one embodiment of the present invention, which is illustrated in FIG. 1, will be described with reference to FIGS.

[0161] 2 to 8, A in each figure represents a top view. B in each figure represents a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in A, and is also a cross-sectional view of the transistor 200 in the channel length direction. C in each figure represents a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in A, and is also a cross-sectional view of the transistor 200 in the channel width direction. D in each figure represents a cross-sectional view corresponding to the portion indicated by the dashed dotted line A5-A6 in A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted from the top view in A in each figure for clarity.

[0162] First, a substrate (not shown) is prepared, and then a film of the insulator 214 is formed on the substrate. The insulator 214 can be formed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), or the like.

[0163] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0164] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0165] Furthermore, ALD utilizes the self-regulating properties of atoms to deposit atoms layer by layer, enabling the formation of ultrathin films, films with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films formed at low temperatures. ALD also includes plasma-enhanced ALD (PEALD), which utilizes plasma. Using plasma can sometimes be preferable because it enables film formation at lower temperatures. Note that some precursors used in ALD contain impurities such as carbon. Therefore, films formed by ALD may contain higher amounts of impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0166] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0167] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0168] In this embodiment, an aluminum oxide film is formed by sputtering as the insulator 214. Alternatively, the insulator 214 may have a multilayer structure.

[0169] Next, the insulator 216 is deposited on the insulator 214. The insulator 216 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxynitride film is deposited by a CVD method as an insulating film to be the insulator 216.

[0170] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The region where the opening is formed may also be referred to as an opening. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form the groove. For example, if silicon oxynitride is used for the insulator 216 that forms the groove, the insulator 214 may be silicon nitride, aluminum oxide, or hafnium oxide.

[0171] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source may be used. For example, an inductively coupled plasma (ICP) etching apparatus may be used as the dry etching apparatus having a high-density plasma source.

[0172] After the opening is formed, a conductive film that will become the first conductor of the conductor 205 is formed. The conductive film preferably contains a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film can be a stacked film of a conductor that has a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0173] In this embodiment, a tantalum nitride film or a film in which titanium nitride is laminated on tantalum nitride is formed by sputtering as a conductive film to be the first conductor of conductor 205. By using such a metal nitride as the first conductor of conductor 205, even if a metal that easily diffuses, such as copper, is used as the second conductor of conductor 205 (described later), the metal can be prevented from diffusing out of the first conductor of conductor 205.

[0174] Next, a conductive film that will be the second conductor of the conductor 205 is formed on the conductive film that will be the first conductor of the conductor 205. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as the conductive film.

[0175] Next, a chemical mechanical polishing (CMP) process is performed to remove a portion of the conductive film that will become the first conductor of the conductor 205 and a portion of the conductive film that will become the second conductor of the conductor 205, thereby exposing the insulator 216. As a result, the conductive film that will become the first conductor of the conductor 205 and the conductive film that will become the second conductor of the conductor 205 remain only in the opening. This makes it possible to form the conductor 205 that has a flat upper surface and includes the first conductor of the conductor 205 and the second conductor of the conductor 205 (see FIG. 2).

[0176] After forming the conductor 205, a process may be performed in which a portion of the second conductor of the conductor 205 is removed to form a groove in the second conductor of the conductor 205, a conductive film is formed on the conductor 205 and the insulator 216 so as to fill the groove, and a CMP process is performed. The CMP process removes a portion of the conductive film to expose the insulator 216. The portion of the second conductor of the conductor 205 may be removed by dry etching or the like.

[0177] Through the above process, the conductor 205 including the conductive film can be formed with a flat top surface. By improving the flatness of the top surfaces of the insulator 216 and the conductor 205, the crystallinity of the oxide 230 can be improved. Note that the conductive film may be made of a material similar to that of the first conductor of the conductor 205 or the second conductor of the conductor 205.

[0178] Hereinafter, a method for forming the conductor 205 that differs from the above will be described.

[0179] A conductive film that will become the conductor 205 is deposited on the insulator 214. The conductive film that will become the conductor 205 can be deposited using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductive film that will become the conductor 205 can also be a multilayer film. For example, a tungsten film is deposited as the conductive film that will become the conductor 205.

[0180] Next, the conductive film that will become the conductor 205 is processed using lithography to form the conductor 205 .

[0181] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. Then, etching is performed through the resist mask to process conductors, semiconductors, insulators, and the like into desired shapes. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or an ion beam may also be used instead of the light described above. When an electron beam or an ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0182] Alternatively, a hard mask made of an insulator or a conductor may be used instead of a resist mask. When using a hard mask, an insulating film or a conductive film that will serve as a hard mask material is formed on the conductive film that will become the conductor 205, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. Etching of the conductive film that will become the conductor 205 may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching of the conductive film that will become the conductor 205. On the other hand, if the material of the hard mask does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0183] Next, an insulating film that will become the insulator 216 is formed on the insulator 214 and the conductor 205. The insulating film is formed so as to be in contact with the top surface and side surfaces of the conductor 205. The insulating film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0184] Here, it is preferable that the thickness of the insulating film that becomes the insulator 216 is equal to or greater than the thickness of the conductor 205. For example, if the thickness of the conductor 205 is 1, the thickness of the insulating film that becomes the insulator 216 is 1 or greater and 3 or less.

[0185] Next, a CMP process is performed on the insulating film that will become the insulator 216, thereby removing a portion of the insulating film that will become the insulator 216 and exposing the surface of the conductor 205. This makes it possible to form the conductor 205 and the insulator 216 with flat upper surfaces. These are the different methods for forming the conductor 205.

[0186] Next, the insulator 222 is deposited over the insulator 216 and the conductor 205. The insulator 222 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, hafnium oxide or aluminum oxide is deposited as the insulator 222 by an ALD method.

[0187] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment may be performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by another heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0188] In this embodiment, heat treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour after the formation of the insulator 222, followed by heat treatment in an oxygen atmosphere at 400° C. for 1 hour. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. The heat treatment can also be performed at the timing after the formation of the insulator 224.

[0189] Next, the insulator 224 is deposited over the insulator 222. The insulator 224 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxynitride film is deposited as the insulator 224 by a CVD method.

[0190] Here, when forming the insulator 224, a film-forming condition is used in which the constant Y satisfying the above-mentioned Equation 1 is 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0. By forming a film using a film-forming condition where the constant Y is 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0, a high-quality film with a reduced hydrogen concentration can be formed. Also, by setting the film-forming power PW, pressure P, and flow rate f to optimal conditions, an insulator can be formed without hydrogen contained in the film-forming gas being driven into the object to be film-formed.

[0191] Further, in order to form an excess oxygen region in the insulator 224, plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use, for example, a device having a power source for generating high-density plasma using microwaves. Alternatively, it may have a power source for applying RF (Radio Frequency) to the substrate side. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the insulator 224. Alternatively, after performing plasma treatment containing an inert gas using this device, plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. Note that by appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In that case, heat treatment may not be performed.

[0192] Specifically, as an example of the plasma treatment, there is microwave-excited plasma treatment. By performing microwave-excited plasma treatment, hydrogen, water, or impurities, which are impurities in the insulator as the object to be treated, can be removed. Further, by performing microwave-excited plasma treatment, the film quality of the insulator can be modified to suppress the diffusion of hydrogen, water, or impurities. Therefore, in a subsequent process such as forming a conductive film to be the conductor 260 or a post-treatment such as heat treatment, it is possible to suppress the diffusion of hydrogen, water, or impurities to the oxide 230 through the insulator 250 and the insulator 224.

[0193] For example, in solid silicon oxide, the bond energy between a hydrogen atom and a silicon atom is 3.3 eV, the bond energy between a carbon atom and a silicon atom is 3.4 eV, and the bond energy between a nitrogen atom and a silicon atom is 3.5 eV. Therefore, to remove a hydrogen atom bonded to a silicon atom, the bond between the hydrogen atom and the silicon atom can be broken by colliding a radical or ion with an energy of at least 3.3 eV with the bond between the hydrogen atom and the silicon atom.

[0194] Similarly, for other impurities such as nitrogen and carbon, the bond between the impurity atom and the silicon atom can be broken by colliding a radical or ion having energy at least equal to the bond energy with the bond between the impurity atom and the silicon atom.

[0195] Here, the radicals and ions generated by microwave-excited plasma are the ground state O( 3 P), the first excited state of the oxygen atom radical O( 1 D), and the monovalent cation of the oxygen molecule, O2+. O( 3 P) energy is 2.42 eV, O( 1 D) The energy is 4.6 eV. 2 Since + has a charge, it is accelerated by the potential distribution in the plasma and the bias, so the energy is not uniquely determined, but at least, even with only the internal energy, O( 1 D) have higher energy.

[0196] That is, O( 1 Radicals and ions such as O2+ and O2+ can break bonds between hydrogen, nitrogen, and carbon atoms and silicon atoms in the insulator 250, thereby removing the hydrogen, nitrogen, and carbon atoms bonded to the silicon atoms. Furthermore, impurities such as hydrogen, nitrogen, and carbon can be reduced by thermal energy applied to the substrate during microwave-excited plasma processing.

[0197] On the other hand, O(3 Since O(P) has low reactivity, it does not react with the insulator 250 and diffuses deep into the film. 3 P) reaches the oxide 230 through the insulator 250 and diffuses into the oxide 230. 3 When P) approaches an oxygen vacancy with hydrogen, the hydrogen in the oxygen vacancy is released from the oxygen vacancy and replaced by O( 3 The oxygen vacancies are compensated for by the inclusion of P. Therefore, the generation of electrons, which are carriers, in the oxide 230 can be suppressed.

[0198] In addition, the O( 3 The proportion of O(P) increases when the microwave-excited plasma treatment is performed under high pressure conditions. 3 It is preferable that the proportion of O2 / O2+Ar is high. Therefore, the microwave-excited plasma treatment should be performed at a pressure of 133 Pa or higher, preferably 200 Pa, and more preferably 400 Pa or higher. The oxygen flow rate ratio (O2 / O2+Ar) should be 50% or lower, preferably 10% to 30%.

[0199] Alternatively, an aluminum oxide film may be formed on the insulator 224 by, for example, a sputtering method, and then CMP processing may be performed until the aluminum oxide reaches the insulator 224. This CMP processing can planarize and smooth the surface of the insulator 224. Placing the aluminum oxide on the insulator 224 and performing CMP processing facilitates detection of the end point of the CMP processing. Furthermore, the CMP processing may polish a portion of the insulator 224, resulting in a thinner film of the insulator 224. However, the film thickness can be adjusted during the formation of the insulator 224. Planarizing and smoothing the surface of the insulator 224 may prevent a deterioration in the coverage of the oxide film to be formed later and may prevent a decrease in the yield of the semiconductor device. Furthermore, forming an aluminum oxide film on the insulator 224 by a sputtering method is preferable because it allows oxygen to be added to the insulator 224.

[0200] Next, oxide films 230A and 230B are sequentially formed on insulator 224 (see FIG. 2). Preferably, oxide films 230A and 230B are formed consecutively without being exposed to the atmosphere. By forming the films without being exposed to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to oxide films 230A and 230B, and to keep the vicinity of the interface between oxide films 230A and 230B clean.

[0201] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0202] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0203] In particular, during the deposition of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0204] When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by forming the oxide film while heating the substrate.

[0205] In this embodiment, oxide film 230A is formed by sputtering using an In-Ga-Zn oxide target with an atomic ratio of 1:3:4. Oxide film 230B is formed by sputtering using an In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. Each oxide film can be formed to suit the desired characteristics of oxide 230 by appropriately selecting the film formation conditions and atomic ratio.

[0206] It is preferable to form the insulator 222, the insulator 224, the oxide film 230A, and the oxide film 230B without exposing them to the atmosphere, for example, by using a multi-chamber film forming apparatus.

[0207] Next, a heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. The heat treatment can remove impurities such as water and hydrogen from the oxide film 230A and the oxide film 230B. In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 400°C for one hour, followed by another heat treatment in an oxygen atmosphere at 400°C for one hour.

[0208] Next, a conductive film 240A is formed on the oxide film 230B. The conductive film 240A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like (see FIG. 2). Note that a heat treatment may be performed before the formation of the conductive film 240A. The heat treatment may be performed under reduced pressure, and the conductive film 240A may be formed immediately after the formation of the oxide film 230A without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230B can be removed, and the moisture and hydrogen concentrations in the oxide films 230A and 230B can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is set to 200° C.

[0209] Subsequently, an insulating film 245A that functions as a barrier layer is formed.

[0210] For example, aluminum oxide may be formed by an ALD method as the insulating film 245A. By forming the insulating film using the ALD method, a dense film with reduced defects such as cracks and pinholes and a uniform thickness can be formed.

[0211] Next, a film 290A serving as a hard mask is formed over the insulating film 245A (see FIG. 2). For example, the film 290A serving as a hard mask may be formed by sputtering using tungsten or tantalum nitride.

[0212] Next, a resist mask 292 is formed on the film 290A to be the hard mask by photolithography. The resist mask 292 is used to selectively remove parts of the film 290A to be the hard mask and the insulating film 245A, thereby forming a hard mask 290B and an insulating layer 245B (FIG. 3).

[0213] Next, using the hard mask 290B and the insulating layer 245B, a portion of the conductive film 240A is selectively removed to form an island-shaped conductive layer 240B (FIG. 4). At this time, a portion or all of the hard mask 290B may be removed.

[0214] Next, the oxide film 230A and a portion of the oxide film 230B are selectively removed using the island-shaped conductive layer 240B, the insulating layer 245B, and the hard mask 290B as a mask. Note that in this process, a portion of the insulator 224 may also be removed at the same time. Thereafter, the hard mask 290B is removed, thereby forming a stacked structure of the island-shaped oxide 230a, the island-shaped oxide 230b, the island-shaped conductive layer 240B, and the island-shaped insulating layer 245B.

[0215] In addition, in this step, by processing the conductive film 240A using the hard mask 290B, the occurrence of unnecessary etching (also called CD loss) in the shape of the conductor 240 can be suppressed.

[0216] For example, when a resist mask is used, the mask may be side-etched during etching, exposing the edge surface of the workpiece and rounding the corners. If the defect is large in the conductor 240, the volume of the conductor 240 may be reduced below the design value, resulting in a smaller on-current.

[0217] Therefore, by using a hard mask, the shape of the hard mask can be maintained during etching by using a material with a large etch rate selectivity relative to the hard mask as the workpiece, and the workpiece can be prevented from becoming deformed. Specifically, if the etch rate of the material used for the hard mask is 1, the etch rate of the workpiece should be 5 or more, preferably 10 or more, as the mask.

[0218] Next, an insulating film 280A is formed on the stacked structure of the island-shaped oxide 230a, the island-shaped oxide 230b, the island-shaped conductive layer 240B, and the island-shaped insulating layer 245B. The insulating film 280A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0219] In this embodiment, a silicon oxide film is formed as the insulating film 280A by CVD method or sputtering method. Note that, before forming the insulating film 280A, heat treatment may be performed. The heat treatment is performed under reduced pressure, and the insulating film may be continuously formed without being exposed to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 224 etc. can be removed, and further the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the insulator 224 can be reduced. The above-described heat treatment conditions can be used.

[0220] Here, when forming the insulator 280, a film formation condition is used in which a constant Y satisfying the above-mentioned formula (1) is 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0. By forming a film using the film formation condition in which the constant Y is 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0, a high-quality film with a reduced hydrogen concentration can be formed. Further, by setting the film formation power PW, the pressure P, and the flow rate f to optimal conditions, the insulator can be formed without hydrogen contained in the film formation gas being driven into the objects to be film-formed (specifically, the insulator 224, the oxide 230, the conductive layer 240B, and the insulating layer 245B).

[0221] Also, the insulating film 280A may have a multilayer structure. For example, a structure in which a silicon oxide film is formed by sputtering method and a silicon oxide film is formed on the silicon oxide film by CVD method may be used.

[0222] Next, CMP treatment is performed on the insulating film 280A to form an insulator 280 with a flat upper surface (see FIG. 5). Subsequently, a part of the insulator 280 and a part of the conductive layer 240B are processed to form an opening reaching the oxide 230b (see FIG. 6).

[0223] 1, the conductor 260 is provided by filling an opening formed in the insulator 280 or the like. In other words, by filling the conductor 260 in an opening formed in the insulator 280 with the insulator 250 or the like interposed therebetween, the conductor 260 can be disposed in a self-aligned manner in the region between the conductor 240a and the conductor 240b without alignment.

[0224] The opening is preferably formed to overlap the conductor 205. By forming the opening, the conductor 240a, the conductive layer 240B, the insulator 245a, and the insulating layer 245B are formed. At this time, the thickness of the oxide 230b in the region overlapping the opening may be thin (see FIG. 6).

[0225] Furthermore, a portion of insulator 280, a portion of insulating layer 245B, and a portion of conductive layer 240B may be processed under different conditions. For example, a portion of insulator 280 may be processed by dry etching, a portion of insulating layer 245B may be processed by wet etching, and a portion of conductive layer 240B may be processed by dry etching.

[0226] Here, it is preferable to remove impurities attached to the surface of or diffused into the oxide 230a, the oxide 230b, etc. Examples of such impurities include those originating from components contained in the insulator 280, the insulating layer 245B, and the conductive layer 240B, components contained in the materials used in the device used to form the openings, and components contained in the gas or liquid used in etching. Examples of such impurities include aluminum, silicon, tantalum, fluorine, and chlorine.

[0227] A cleaning treatment may be carried out to remove the above-mentioned impurities, etc. Cleaning methods include wet cleaning using a cleaning solution, plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate.

[0228] As wet cleaning, an aqueous solution obtained by diluting ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, etc. with carbonated water or pure water, pure water, carbonated water, etc. may be used for the cleaning treatment. Further, ultrasonic cleaning using these aqueous solutions, pure water, or carbonated water may be performed. Further, these cleanings may be appropriately combined and performed.

[0229] Next, heat treatment may be performed. The heat treatment is preferably performed in an atmosphere containing oxygen. Further, the heat treatment may be performed under reduced pressure, and the oxide film 230C may be continuously formed without being exposed to the atmosphere (see FIG. 7). By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b, etc. can be removed, and further, the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In the present embodiment, the temperature of the heat treatment is 200°C.

[0230] The insulating film 250A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. (see FIG. 7). In the present embodiment, as the insulating film 250A, silicon oxynitride is formed by the CVD method. Note that the film formation temperature when forming the insulating film 250A is preferably 350°C or higher and lower than 450°C, particularly around 400°C. By forming the insulating film 250A at 400°C, an insulating film with few impurities can be formed.

[0231] Here, when forming the insulating film 250A, a film formation condition in which a constant Y satisfying the above-mentioned number 1 is 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0 is used. By forming the film using a film formation condition in which the constant Y is 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0, a high-quality film with a reduced hydrogen concentration can be formed. Further, by setting the film formation power PW, the pressure P, and the flow rate f to optimal conditions, hydrogen contained in the film formation gas can be prevented from being driven into the objects to be film-formed (specifically, the insulator 224, the oxide 230, the conductor 240, the insulator 245, and the insulator 280), and an insulator can be formed.

[0232] Next, the conductive film 260A and the conductive film 260B are formed in this order. The conductive film 260A and the conductive film 260B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film 260A is formed using an ALD method, and the conductive film 260B is formed using a CVD method (see FIG. 7).

[0233] Next, the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed, thereby forming the insulator 250 and the conductor 260 (the conductor 260a and the conductor 260b) (see FIG. 8). The insulator 250 is disposed so as to cover the inner wall of the opening. The conductor 260 is disposed so as to fill the opening with the insulator 250 interposed therebetween.

[0234] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280.

[0235] Next, the insulator 282 is formed over the insulator 250, the conductor 260, and the insulator 280. The insulator 282 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulator 282 is preferably formed, for example, as an aluminum oxide film or a silicon nitride film by sputtering. Forming an aluminum oxide film or a silicon nitride film by sputtering can prevent hydrogen from diffusing into the oxide 230. Furthermore, forming the insulator 282 in contact with the conductor 260 is preferable because it can prevent oxidation of the conductor 260.

[0236] Furthermore, oxygen can be supplied to the insulator 280 by forming an aluminum oxide film as the insulator 282 by a sputtering method. The oxygen supplied to the insulator 280 may be supplied to the channel formation region of the oxide 230b through the insulator 250. Furthermore, when oxygen is supplied to the insulator 280, the oxygen contained in the insulator 280 before the formation of the insulator 282 may be supplied to the channel formation region of the oxide 230b through the insulator 250.

[0237] The insulator 282 may have a multilayer structure. For example, an aluminum oxide film may be formed by sputtering, and a silicon nitride film may be formed over the aluminum oxide film by sputtering.

[0238] Next, heat treatment may be performed. The heat treatment can be performed under the above-described heat treatment conditions. The heat treatment can reduce the moisture and hydrogen concentrations in the insulator 280. Furthermore, oxygen contained in the insulator 282 can be introduced into the insulator 280.

[0239] Before forming the insulator 282, an aluminum oxide film may be first formed on the insulator 280 or the like by sputtering, followed by heat treatment under the above-described heat treatment conditions, and then a step of removing the aluminum oxide film by CMP may be performed. This step allows more excess oxygen regions to be formed in the insulator 280. In this step, part of the insulator 280, part of the conductor 260, and part of the insulator 250 may be removed.

[0240] Alternatively, an insulator may be provided between the insulator 280 and the insulator 282. For example, a silicon oxide film formed by a sputtering method may be used as the insulator. By providing the insulator, an excess oxygen region can be formed in the insulator 280.

[0241] Next, an insulator 284 may be formed on the insulator 282. The insulator 284 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 1).

[0242] Through the above steps, a semiconductor device including the transistor 200 illustrated in FIG. 1 can be manufactured.

[0243] Alternatively, after the transistor 200 is formed, an opening may be formed to surround the transistor 200, and an insulator with a high barrier property against hydrogen or water may be formed to cover the opening.

[0244] Note that, as an insulator having a barrier property, specifically, a metal oxide such as aluminum oxide or a nitride such as silicon nitride may have a function of suppressing the diffusion of hydrogen (hereinafter also referred to as a barrier property against hydrogen). In particular, compared to silicon oxide, aluminum oxide and silicon nitride have a function of suppressing the diffusion of impurities such as oxygen, water, and hydrogen.

[0245] By enclosing the transistor 200 in the insulator with high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 200 may be collectively enclosed in an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 200, for example, it is preferable to form an opening that reaches the insulator 214 or the insulator 222 and form the insulator with high barrier properties in contact with the insulator 214 or the insulator 222, because this can serve as part of the manufacturing process of the transistor 200. Note that the insulator with high barrier properties against hydrogen or water may be made of a material similar to that of the insulator 222, for example.

[0246] According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to another embodiment of the present invention, a semiconductor device with excellent electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0247] <Semiconductor Device Modification 1> An example of a semiconductor device including a transistor 200 according to one embodiment of the present invention will be described below with reference to FIG.

[0248] Here, Fig. 9A shows a top view. Fig. 9B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 9A. Fig. 9C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 9A. Fig. 9D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in Fig. 9A. In the top view of Fig. 9A, some elements are omitted for clarity.

[0249] 9 differs from the semiconductor device shown in FIG. 1 in that it includes oxide 230c. By providing oxide 230c, defects that occur on the surface of oxide 230b or oxide 230a when openings are formed can be filled by processing insulator 280, insulator 245, and conductor 240. Note that oxide 230a, oxide 230b, and oxide 230c may be collectively referred to as oxide 230.

[0250] The oxide 230c can be made of the same metal oxide as can be made of the oxide 230a or the oxide 230b.

[0251] For example, when the oxide 230b is an In-Ga-Zn oxide, the oxide 230a and the oxide 230c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, or gallium oxide.

[0252] Furthermore, the oxide 230b and the oxide 230c preferably have crystallinity. For example, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) described later. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), a highly crystalline, and a dense structure. This can prevent the source electrode or drain electrode from extracting oxygen from the oxide 230b. Furthermore, even when heat treatment is performed, because the extraction of oxygen from the oxide 230b can be reduced, the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0253] 9, the oxide 230c is shown as a single layer, but the present invention is not limited to this. For example, the oxide 230c may have a stacked structure of two or more layers.

[0254] The film that becomes the oxide 230c can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The film that becomes the oxide 230c can be formed using a film formation method similar to that used for the oxide film 230A or the oxide film 230B, depending on the desired characteristics of the oxide film 230C. In this embodiment, the film that becomes the oxide 230c is formed by sputtering using an In-Ga-Zn oxide target with an In:Ga:Zn=1:3:4 atomic ratio or 4:2:4.1 atomic ratio. Alternatively, the film that becomes the oxide 230c is formed by sputtering using an In-Ga-Zn oxide target with an In:Ga:Zn=4:2:4.1 atomic ratio, and then a film is formed thereon using an In-Ga-Zn oxide target with an In:Ga:Zn=1:3:4 atomic ratio.

[0255] In particular, during the deposition of the film that becomes the oxide 230c, some of the oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Therefore, the proportion of oxygen contained in the sputtering gas for the film that becomes the oxide 230c should be 70% or more, preferably 80% or more, and more preferably 100%.

[0256] Next, a heat treatment may be performed. The heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed continuously without exposure to the atmosphere. By performing such a treatment, the moisture and hydrogen adsorbed on the surface of the film that becomes the oxide 230c can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, and the oxide film 230C can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0257] <Modification 2 of Semiconductor Device> An example of a semiconductor device including a transistor 200 according to one embodiment of the present invention will be described below with reference to FIGS.

[0258] Here, Fig. 10A shows a top view. Fig. 10B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 10A. Fig. 10C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 10A. In the top view of Fig. 10A, some elements are omitted for clarity.

[0259] 10 differs from the semiconductor device shown in FIG. 9 in that the oxide 230b has a layered structure, the oxide 230c has a layered structure, and the insulators 273 and 274 are included.

[0260] The oxide 230c may have a stacked structure of two or more layers. For example, in FIG. 10, the oxide 230c has a first oxide and a second oxide disposed on the first oxide of the oxide 230c.

[0261] Specifically, the first oxide of oxide 230c preferably contains at least one of the metal elements constituting the metal oxide used in oxide 230b, and more preferably contains all of the metal elements. For example, the first oxide of oxide 230c may be an In-Ga-Zn oxide, and the second oxide of oxide 230c may be an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide. This structure can reduce the defect state density at the interface between oxide 230b and the first oxide of oxide 230c.

[0262] Furthermore, the second oxide of the oxide 230c is preferably a metal oxide that suppresses oxygen diffusion or permeation more than the first oxide of the oxide 230c. By providing the second oxide of the oxide 230c between the insulator 250 and the first oxide of the oxide 230c, it is possible to suppress the diffusion of oxygen contained in the insulator 280 into the insulator 250. Therefore, the oxygen is more likely to be supplied to the oxide 230b via the first oxide of the oxide 230c.

[0263] Furthermore, by making the atomic ratio of In to the main component metal element in the metal oxide used for the second oxide of the oxide 230c smaller than the atomic ratio of In to the main component metal element in the metal oxide used for the first oxide of the oxide 230c, it is possible to suppress diffusion of In toward the insulator 250. Because the insulator 250 functions as a gate insulator, if In gets mixed into the insulator 250 or the like, it will cause poor transistor characteristics. Therefore, by forming the oxide 230c into a stacked structure, it is possible to provide a highly reliable semiconductor device.

[0264] The oxide 230b may have a stacked structure of two or more layers. For example, in FIG. 10, the oxide 230b has a first oxide layer and a second oxide layer disposed on the first oxide layer.

[0265] Specifically, the second oxide of the oxide 230b is preferably provided between the first oxide of the oxide 230b and the conductor 240 (conductor 240a and conductor 240b) that functions as a source electrode or a drain electrode. In this structure, the second oxide of the oxide 230b preferably has a function of suppressing oxygen permeation.

[0266] Therefore, it is preferable to place the second oxide of the oxide 230b, which has the function of suppressing oxygen permeation, between the conductor 240, which functions as a source electrode or a drain electrode, and the first oxide of the oxide 230b, because this reduces the electrical resistance between the conductor 240 and the first oxide of the oxide 230b. This structure can improve the electrical characteristics and reliability of the transistor 200.

[0267] That is, since the conductor 240 and the first oxide of the oxide 230b are not in contact with each other, it is possible to prevent the conductor 240 from absorbing oxygen from the first oxide of the oxide 230b. By preventing oxidation of the conductor 240, it is possible to prevent a decrease in the conductivity of the conductor 240.

[0268] The second oxide of the oxide 230b may be a metal oxide containing the element M. In particular, the element M may be aluminum, gallium, yttrium, or tin. The second oxide of the oxide 230b preferably has a higher concentration of the element M than the first oxide of the oxide 230b. Gallium oxide may also be used as the second oxide of the oxide 230b. A metal oxide such as an In-M-Zn oxide may also be used as the second oxide of the oxide 230b.

[0269] Specifically, the atomic ratio of the element M to In in the metal oxide used for the second oxide 230b is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the first oxide 230b. The thickness of the second oxide 230b is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm. The second oxide 230b is preferably crystalline. Crystalline second oxide 230b can reduce oxygen release from the first oxide 230b. For example, if the second oxide 230b has a crystalline structure such as a hexagonal crystal, oxygen release from the first oxide 230b can be suppressed.

[0270] Furthermore, when the conductor 240 (conductor 240a and conductor 240b) comes into contact with the oxide 230, oxygen in the oxide 230 may diffuse into the conductor 240, causing the conductor 240 to oxidize. When the conductor 240 is oxidized, there is a high probability that the conductivity of the conductor 240 will decrease. The diffusion of oxygen in the oxide 230 into the conductor 240 can be rephrased as the conductor 240 absorbing the oxygen in the oxide 230.

[0271] Furthermore, oxygen in the oxide 230 (typically, the oxide 230b) may diffuse into the conductor 240, forming a heterogeneous layer between the conductor 240 and the oxide 230. Since the heterogeneous layer contains more oxygen than the conductor 240, it is presumed that the heterogeneous layer has insulating properties. In this case, the three-layer structure of the conductor 240, the heterogeneous layer, and the oxide 230 can be regarded as a three-layer structure consisting of a metal, an insulator, and a semiconductor, and may be called a MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure mainly based on the MIS structure.

[0272] Furthermore, an insulator 273 having barrier properties may be provided to cover the top surface of the conductor 240, the oxide 230a, the oxide 230b, and the side surfaces of the conductor 240. When the insulator 273 is provided, the insulator 245 is not necessarily provided.

[0273] For example, in the region of the oxide 230 overlapping with the conductor 240, a metal element of the conductor 240 is added, or oxygen is absorbed by the conductor 240, causing oxygen deficiency. In other words, the resistance may be locally reduced near the surface of the oxide 230 in contact with the conductor 240. The reduction in resistance in the region where the oxide 230 and the conductor 240 overlap can improve the on-current of the transistor 200.

[0274] On the other hand, excess oxygen in insulator 280 diffuses into oxide 230 from the side surfaces of oxide 230 in the region overlapping with conductor 240, which may reduce the localized low-resistance region that occurs in oxide 230 in the region overlapping with conductor 240, resulting in a decrease in the on-state current of transistor 200.

[0275] Therefore, by providing the insulator 273, it is possible to prevent excess oxygen contained in the insulator 280 from being supplied from the side surface of the oxide 230 in the region overlapping with the conductor 240. On the other hand, the excess oxygen contained in the insulator 280 can be supplied to the channel formation region of the oxide 230b via the oxide 230c. Therefore, the oxygen vacancies occurring in the channel formation region of the oxide 230 can be efficiently compensated for without reducing the resistive region occurring near the surface of the oxide 230 in contact with the conductor 240.

[0276] Furthermore, if the insulator 224 has an excess oxygen region, the excess oxygen in the insulator 224 diffuses to the oxide 230b via the oxide 230a in the oxide 230. In other words, the excess oxygen can be supplied from the oxide 230a side. Therefore, the oxygen vacancies occurring in the channel formation region of the oxide 230 can be compensated for while suppressing the reduction of the resistive region occurring near the surface of the oxide 230 that contacts the conductor 240.

[0277] Note that an aluminum oxide film formed using a sputtering apparatus is preferably used as the insulator 273. By forming an aluminum oxide film as the insulator 273 in an oxygen gas atmosphere, excess oxygen can be introduced into the insulator 224 while the insulator 273 is being formed.

[0278] Further, an insulator 274 may be provided over the insulator 273. Note that, like the insulator 273, the insulator 274 preferably has a function of suppressing oxygen diffusion.

[0279] Specifically, the insulator 273 formed by sputtering has poor film coverage. Therefore, it is preferable to form the insulator 274 by the ALD method. The ALD method can form a film with excellent step coverage and thickness uniformity, so it is less affected by the shape of the workpiece and has good step coverage.

[0280] <Application examples of semiconductor devices> An example in which the stacked structure of interlayer films and plugs of one embodiment of the present invention are applied to a semiconductor device including a transistor 200 of this embodiment will be described below with reference to FIGS.

[0281] Here, Fig. 11A shows a top view. Fig. 11B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 11A. Fig. 11C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 11A. Fig. 11D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in Fig. 11A. In the top view of Fig. 11A, some elements are omitted for clarity.

[0282] 11, the insulator 280, the insulator 282, the insulator 283, and the insulator 284 have openings that expose the transistor 200. The openings also include conductors 246 (conductors 246a and 246b) that function as plugs connected to the transistor 200. The openings also include insulators 247 on the side surfaces of the openings.

[0283] Note that the conductor 246 functions as a plug or wiring that is electrically connected to the transistor 200 .

[0284] 11 includes an insulator 212 and an insulator 283 that function as barrier layers above and below the transistor 200. The insulator 212 and the insulator 283 are in contact with each other in a region that is the side surface of the transistor 200 or the edge of the substrate. In other words, the semiconductor device shown in FIG. 11 has a structure in which the transistor 200 and the insulator 280 having an excess oxygen region are sealed by a barrier layer.

[0285] The region where the insulator 212 and the insulator 283 contact each other may be provided along a scribe line. For example, when a plurality of transistors 200 are arranged in a matrix, the region where the insulator 212 and the insulator 283 contact each other may be provided along the matrix in which the plurality of transistors are arranged.

[0286] Note that when the region where the insulator 212 and the insulator 283 are in contact with each other is provided at the edge of the substrate, the region may overlap with the scribe line.

[0287] The insulator 283 is provided on the insulator 282. The insulator 284 is made of a material that has a high etching rate selectivity with respect to the conductor 248 when processing the conductor 248. Therefore, the insulator 284 may be provided on the insulator 283 as needed.

[0288] The insulator 247 is preferably in contact with the insulator 283. When the insulator 247 and the insulator 283 are in contact with each other, the transistor 200 and the insulator 280 including the excess oxygen region are sealed by a barrier layer.

[0289] Specifically, insulator 247 is provided in contact with the sidewalls of the openings of insulators 283, 282, and 280, and conductor 246 is formed in contact with the side surface of insulator 247. Transistor 200 is located at least partially at the bottom of the opening, and conductor 246 is in contact with transistor 200.

[0290] In the <Modifications of the semiconductor device> and <Application examples of the semiconductor device>, structures having the same functions as those constituting the semiconductor device shown in <Configuration examples of the semiconductor device> are denoted by the same reference numerals. In these items, the materials described in detail in <Configuration examples of the semiconductor device> can also be used as the constituent materials of the semiconductor device.

[0291] As described above, a semiconductor device with high reliability can be provided. It is also possible to provide a semiconductor device with good electrical characteristics. It is also possible to provide a semiconductor device that can be miniaturized or highly integrated. It is also possible to provide a semiconductor device with low power consumption.

[0292] The structures, methods, and the like described in this embodiment can be used in appropriate combination with structures, methods, and the like described in other embodiment modes and examples.

[0293] (Embodiment 2) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0294] [Storage device 1] 12 illustrates an example of a semiconductor device (memory device) using a capacitor according to one embodiment of the present invention. In the semiconductor device according to one embodiment of the present invention, a transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistor 200. Preferably, the capacitor 100 or the transistor 300 at least partially overlaps with the transistor 200. This reduces the area occupied by the capacitor 100, the transistor 200, and the transistor 300 in a top view, thereby enabling miniaturization or high integration of the semiconductor device according to this embodiment. Note that the semiconductor device according to this embodiment can be applied to, for example, a logic circuit typified by a central processing unit (CPU) or a graphics processing unit (GPU), or a memory circuit typified by a dynamic random access memory (DRAM) or a non-volatile memory (NVM).

[0295] Note that the transistor 200 described in the above embodiment can be used as the transistor 200. Therefore, the description in the above embodiment can be referred to for the transistor 200 and the layers including the transistor 200.

[0296] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. The transistor 200 has a low off-state current, and therefore, when used in a memory device, stored data can be retained for a long time. That is, refresh operations are not required or the frequency of refresh operations is extremely low, thereby enabling the memory device to sufficiently reduce its power consumption. Furthermore, compared to transistors using silicon for their semiconductor layers, the transistor 200 has favorable electrical characteristics at high temperatures. For example, the transistor 200 exhibits favorable electrical characteristics even in a temperature range of 125° C. to 150° C. Furthermore, in a temperature range of 125° C. to 150° C., the transistor 200 has an on / off ratio of 10 or more orders of magnitude higher. In other words, compared to transistors using silicon for their semiconductor layers, the transistor 200 exhibits excellent transistor characteristics, such as on-state current and frequency characteristics, as the temperature increases.

[0297] 12 , a wiring 1001 is electrically connected to the source of a transistor 300, a wiring 1002 is electrically connected to the drain of the transistor 300, and a wiring 1007 is electrically connected to the gate of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of a transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. The other of the source and drain of the transistor 200 is electrically connected to one electrode of a capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0298] The semiconductor device shown in FIG. 12 has a characteristic that electric charge stored in one electrode of the capacitor element 100 can be retained by switching the transistor 200, thereby enabling writing, retention, and reading of information. The transistor 200 is an element provided with a back gate in addition to a source, a gate (top gate), and a drain. That is, because it is a four-terminal element, it has the characteristic that independent control of input and output can be easily performed compared to two-terminal elements such as magnetoresistive random access memory (MRAM), resistive random access memory (ReRAM), and phase-change memory (PCM) that utilize magnetic tunnel junction (MTJ) characteristics. Furthermore, MRAM, ReRAM, and PCM may undergo structural changes at the atomic level when rewriting information. On the other hand, the semiconductor device shown in FIG. 12 operates by charging or discharging electrons using a transistor and a capacitor element when rewriting information, and therefore has the characteristics of excellent durability against repeated rewriting and minimal structural changes.

[0299] 12 can be arranged in a matrix to form a memory cell array. In this case, the transistor 300 can be used as a read circuit or a driver circuit connected to the memory cell array. The semiconductor device shown in FIG. 12 also forms a memory cell array as described above. When the semiconductor device shown in FIG. 12 is used as a memory element, an operating frequency of 200 MHz or higher can be achieved, for example, at a drive voltage of 2.5 V and an evaluation environment temperature range of −40° C. to 85° C.

[0300] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 316 that functions as a gate electrode, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as source and drain regions.

[0301] Here, an insulator 315 is disposed over the semiconductor region 313, and a conductor 316 is disposed over the insulator 315. The transistors 300 formed in the same layer are electrically isolated by an insulator 312 that functions as an element isolation insulating layer. The insulator 312 can be an insulator similar to the insulator 326 described later. The transistor 300 may be either a p-channel type or an n-channel type.

[0302] The substrate 311 preferably includes a semiconductor such as a silicon-based semiconductor, and preferably includes single-crystal silicon, in the region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or drain region, and the low-resistance region 314b. Alternatively, the substrate 311 may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a high electron mobility transistor (HEMT) by using GaAs and GaAlAs, or the like.

[0303] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0304] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0305] Since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use metal materials such as tungsten and aluminum as a laminate for the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0306] Here, the transistor 300 shown in FIG. 12 has a semiconductor region 313 (a part of the substrate 311) where a channel is formed, which has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Such a transistor 300 is also called a FIN transistor because it utilizes the convex portion of the semiconductor substrate. An insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. While the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0307] Note that the transistor 300 shown in FIG. 12 is just an example, and the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration and driving method.

[0308] 12, the semiconductor device has a transistor 300 and a transistor 200 stacked one on top of the other. For example, the transistor 300 can be formed of a silicon-based semiconductor material, and the transistor 200 can be formed of an oxide semiconductor. In this way, the semiconductor device shown in FIG. 12 can be formed by mixing a silicon-based semiconductor material and an oxide semiconductor in different layers. The semiconductor device shown in FIG. 12 can be fabricated using the same process as a manufacturing device used for silicon-based semiconductor materials, and can also be highly integrated.

[0309] <Capacitor element> The capacitive element 100 has an insulator 114 on an insulator 160, an insulator 140 on the insulator 114, a conductor 110 disposed in an opening formed in the insulator 114 and the insulator 140, an insulator 130 on the conductor 110 and the insulator 140, a conductor 120 on the insulator 130, and an insulator 150 on the conductor 120 and the insulator 130. Here, at least a portion of the conductor 110, the insulator 130, and the conductor 120 are disposed in the openings formed in the insulator 114 and the insulator 140.

[0310] The conductor 110 functions as the lower electrode of the capacitor 100, the conductor 120 functions as the upper electrode of the capacitor 100, and the insulator 130 functions as the dielectric of the capacitor 100. The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surfaces of the openings in the insulators 114 and 140, allowing for a larger capacitance per unit area. Therefore, the deeper the openings, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0311] The insulators 114 and 150 may be made of an insulator that can be used for the insulator 280. The insulator 140 preferably functions as an etching stopper when forming an opening in the insulator 114, and may be made of an insulator that can be used for the insulator 214.

[0312] The shape of the openings formed in the insulator 114 and the insulator 140 when viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. Here, it is preferable that the area over which the openings and the transistor 200 overlap in the top view is large. With such a structure, the area occupied by a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0313] The conductor 110 is arranged in contact with the insulator 140 and an opening formed in the insulator 114. The top surface of the conductor 110 preferably substantially coincides with the top surface of the insulator 140. The bottom surface of the conductor 110 is in contact with the conductor 152 provided on the insulator 160. The conductor 110 is preferably formed by an ALD method, a CVD method, or the like, and may be formed from a conductor that can be used for the conductor 205, for example.

[0314] The insulator 130 is disposed to cover the conductor 110 and the insulator 140. For example, the insulator 130 is preferably formed by an ALD method, a CVD method, or the like. The insulator 130 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and may be formed as a stacked layer or a single layer. For example, the insulator 130 may be an insulating film stacked in this order of zirconium oxide, aluminum oxide, and zirconium oxide.

[0315] Furthermore, it is preferable to use a material with high dielectric strength, such as silicon oxynitride, or a high dielectric constant (high-k) material for the insulator 130. Alternatively, a stacked structure of a material with high dielectric strength and a material with high dielectric constant (high-k) may be used.

[0316] Examples of high-dielectric-constant (high-k) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. By using such high-k materials, the capacitance of the capacitor 100 can be sufficiently ensured even if the insulator 130 is made thick. By making the insulator 130 thicker, the leakage current between the conductor 110 and the conductor 120 can be suppressed.

[0317] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with vacancies, and resin. For example, silicon nitride (SiN) formed using the ALD method is x ), silicon oxide (SiO x ), silicon nitride (SiN x ) can be used. By using such an insulator with high dielectric strength, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0318] The conductor 120 is arranged to fill the openings formed in the insulator 140 and the insulator 114. The conductor 120 is electrically connected to the wiring 1005 via the conductors 112 and 153. The conductor 120 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using, for example, a conductor that can be used for the conductor 205.

[0319] Furthermore, the transistor 200 includes an oxide semiconductor and is therefore compatible with the capacitor 100. Specifically, the transistor 200 including an oxide semiconductor has a small off-state current; therefore, when used in combination with the capacitor 100, stored data can be retained for a long time.

[0320] <Wiring layer> Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductor functioning as a plug or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0321] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328 and 330, which are electrically connected to the conductor 153 functioning as a terminal, are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings.

[0322] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0323] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Fig. 12, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0324] An insulator 210, an insulator 212, an insulator 214, and an insulator 216 are stacked in this order over the insulator 354 and the conductor 356. A conductor 218 and a conductor (conductor 205) that constitutes the transistor 200 are embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. The conductor 218 functions as a plug or wiring that is electrically connected to the transistor 300.

[0325] The conductor 112 and conductors (the conductors 120 and 110) that constitute the capacitor 100 are embedded in the insulators 114, 140, 130, 150, and 154. The conductor 112 functions as a plug or wiring that electrically connects the capacitor 100, the transistor 200, or the transistor 300 to the conductor 153 that functions as a terminal.

[0326] In addition, a conductor 153 is provided over the insulator 154 and is covered with an insulator 156. Here, the conductor 153 is in contact with the top surface of the conductor 112 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[0327] Insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides. For example, by using a material with a low dielectric constant as the insulator that functions as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0328] For example, insulators 320, 322, 326, 352, 354, 212, 114, 150, and 156 preferably have a low dielectric constant. For example, the insulators preferably include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, pore-containing silicon oxide, and resin. Alternatively, the insulators preferably have a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or pore-containing silicon oxide, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with resin to form a thermally stable layered structure with a low dielectric constant. Examples of suitable resins include polyester, polyolefin, polyamide (e.g., nylon, aramid), polyimide, polycarbonate, and acrylic.

[0329] Furthermore, the resistivity of the insulator provided above or below the conductor 152 or the conductor 153 is 1.0×10 12 Ωcm or more 1.0×10 15 Ωcm or less, preferably 5.0×10 12 Ωcm or more 1.0×10 14 Ωcm or less, more preferably 1.0×10 13 Ωcm or more 5.0×10 13 It is preferable that the resistivity of the insulator provided above or below the conductor 152 or 153 be in the above-mentioned range. By setting the resistivity of the insulator in this range, the insulator can maintain its insulating properties while dispersing charge accumulated between wirings of the transistor 200, the transistor 300, the capacitor 100, the conductor 152, etc., and can suppress poor characteristics and electrostatic breakdown of the transistor and a semiconductor device including the transistor due to the charge, which is preferable. Silicon nitride or silicon nitride oxide can be used as such an insulator. For example, the resistivity of the insulator 160 or the insulator 154 may be set in the above-mentioned range.

[0330] Furthermore, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, the insulators 324, 350, 210, and the like can be insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0331] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0332] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0333] For example, the conductors 328, 330, 356, 218, conductor 112, conductor 152, conductor 153, etc. can be formed using a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. High-melting-point materials such as tungsten and molybdenum that have both heat resistance and conductivity are preferably used, and tungsten is preferred. Alternatively, they are preferably formed using low-resistance conductive materials such as aluminum and copper. The use of low-resistance conductive materials can reduce wiring resistance.

[0334] <Wiring or plug in layer provided with oxide semiconductor> When an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0335] 12, for example, an insulator 247 may be provided between the insulator 280 having excess oxygen and the conductor 248. When the insulator 247 and the insulator 282 are provided in contact with each other, the conductor 248 and the transistor 200 can be sealed with the insulator having barrier properties.

[0336] That is, the insulator 247 can prevent excess oxygen in the insulator 280 from being absorbed by the conductor 248. Furthermore, the insulator 247 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 248.

[0337] Here, the conductor 248 functions as a plug or wiring that electrically connects to the transistor 200 or the transistor 300 .

[0338] Specifically, insulator 247 is provided in contact with the side walls of the openings of insulators 284, 282, and 280, and conductor 248 is formed in contact with the side surface of insulator 247. Conductor 240 is located on at least a part of the bottom of the opening, and conductor 248 is in contact with conductor 240.

[0339] The conductor 248 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 248 may have a layered structure. Note that although the transistor 200 illustrates a structure in which the conductor 248 has a two-layer structure, the present invention is not limited to this. For example, the conductor 248 may have a single layer structure or a layered structure of three or more layers.

[0340] Furthermore, when the conductor 248 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the conductor that contacts the conductor 240 and also contacts the insulators 280, 282, and 284 via the insulator 247. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Using such a conductive material can prevent oxygen added to the insulator 280 from being absorbed by the conductor 248. Furthermore, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in layers above the insulator 284 into the oxide 230 through the conductor 248.

[0341] The insulator 247 may be, for example, an insulator that can be used for the insulator 214. The insulator 247 can prevent impurities such as water and hydrogen contained in the insulator 280 from diffusing into the oxide 230 through the conductor 248. The insulator 247 can also prevent oxygen contained in the insulator 280 from being absorbed by the conductor 248.

[0342] Although not shown, a conductor 152 functioning as wiring may be disposed in contact with the upper surface of the upper surface of the conductor 248. The conductor functioning as wiring is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may also be formed so as to be embedded in an opening provided in an insulator.

[0343] The above is a description of the configuration example. By using this configuration, a semiconductor device using a transistor including an oxide semiconductor can be miniaturized or highly integrated. Furthermore, in a semiconductor device using a transistor including an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Furthermore, a transistor including an oxide semiconductor with high on-state current can be provided. Furthermore, a transistor including an oxide semiconductor with low off-state current can be provided. Furthermore, a semiconductor device with reduced power consumption can be provided.

[0344] [Storage device 2] An example of a semiconductor device (memory device) using the semiconductor device of one embodiment of the present invention is shown in Fig. 13. The semiconductor device shown in Fig. 13 includes a transistor 200, a transistor 300, and a capacitor 100, similar to the semiconductor device shown in Fig. 12. However, the semiconductor device shown in Fig. 13 differs from the semiconductor device shown in Fig. 12 in that the capacitor 100 is a planar type and the transistor 200 and the transistor 300 are electrically connected to each other.

[0345] In the semiconductor device of one embodiment of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200. Preferably, the capacitor 100 or the transistor 300 at least partially overlaps with the transistor 200. This can reduce the area occupied by the capacitor 100, the transistor 200, and the transistor 300 in a top view, thereby enabling miniaturization or high integration of the semiconductor device according to this embodiment.

[0346] Note that the above-described transistors 200 and 300 can be used as the transistors 200 and 300. Therefore, the above description can be referred to for the transistors 200 and 300 and the layers including these.

[0347] 13, a wiring 2001 is electrically connected to the source of the transistor 300, and a wiring 2002 is electrically connected to the drain of the transistor 300. A wiring 2003 is electrically connected to one of the source and drain of the transistor 200, a wiring 2004 is electrically connected to the first gate of the transistor 200, and a wiring 2006 is electrically connected to the second gate of the transistor 200. A gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and a wiring 2005 is electrically connected to the other electrode of the capacitor 100. Note that hereinafter, a node where the gate of the transistor 300, the other of the source and drain of the transistor 200, and one electrode of the capacitor 100 are connected to each other may be referred to as a node FG.

[0348] The semiconductor device in FIG. 13 has a characteristic that the potential of the gate (node ​​FG) of the transistor 300 can be held by switching the transistor 200, thereby enabling writing, holding, and reading of data.

[0349] Moreover, the semiconductor device shown in FIG. 13 can be arranged in a matrix to form a memory cell array.

[0350] Since the layer including the transistor 300 has a structure similar to that of the semiconductor device shown in FIG. 12, the above description can be referred to for the structure below the insulator 354.

[0351] Insulator 210, insulator 212, insulator 214, and insulator 216 are arranged on insulator 354. Here, like insulator 350, insulator 210 may be an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0352] A conductor 218 is embedded in the insulators 210, 212, 214, and 216. The conductor 218 functions as a plug or wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. For example, the conductor 218 is electrically connected to a conductor 316 that functions as the gate electrode of the transistor 300.

[0353] The conductor 248 also functions as a plug or a wiring electrically connected to the transistor 200 or the transistor 300. For example, the conductor 248 electrically connects the conductor 240b functioning as the other of the source and drain of the transistor 200 to the conductor 110 functioning as one of the electrodes of the capacitor 100.

[0354] The planar capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Note that the conductor 110, the conductor 120, and the insulator 130 can be the same as those described in the memory device 1.

[0355] The conductor 153 and the conductor 110 are provided in contact with the top surface of the conductor 248. The conductor 153 is in contact with the top surface of the conductor 248 and functions as a terminal of the transistor 200 or the transistor 300.

[0356] The conductor 153 and the conductor 110 are covered with an insulator 130, and the conductor 120 is arranged so as to overlap the conductor 110 with the insulator 130 interposed therebetween. Furthermore, an insulator 114 is arranged on the conductor 120 and the insulator 130.

[0357] 13 shows an example in which a planar capacitor is used as the capacitor 100, but the semiconductor device described in this embodiment is not limited to this. For example, a cylindrical capacitor 100 as shown in FIG. 12 may be used as the capacitor 100.

[0358] [Storage device 3] An example of a memory device using a semiconductor device according to one embodiment of the present invention is illustrated in Fig. 14. The memory device illustrated in Fig. 14 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 shown in Fig. 13.

[0359] The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 is connected to the second gate of the transistor 200. In this configuration, when the second gate of the transistor 200 is held at a negative potential, the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source of the transistor 400 are 0 V. Because the drain current of the transistor 400 is very small when the second gate voltage and the first gate voltage are 0 V, the negative potential of the second gate of the transistor 200 can be maintained for a long time without supplying power to the transistors 200 and 400. This allows a memory device including the transistor 200 and 400 to retain stored content for a long time.

[0360] 14 , the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the backgate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and the wiring 1005 is electrically connected to the other electrode of the capacitor 100. The wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, the wiring 1009 is electrically connected to the backgate of the transistor 400, and the wiring 1010 is electrically connected to the drain of the transistor 400. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.

[0361] 14 can be arranged in a matrix to form a memory cell array, similar to the memory devices shown in FIGS. 12 and 13. Note that one transistor 400 can control the second gate voltages of the plurality of transistors 200. Therefore, it is preferable to provide fewer transistors 400 than transistors 200.

[0362] <Transistor 400> The transistor 400 is formed in the same layer as the transistor 200 and can be fabricated in parallel. The transistor 400 includes a conductor 460 (conductor 460a and conductor 460b) functioning as a first gate electrode, a conductor 405 functioning as a second gate electrode, insulators 222, 224, and 450 functioning as gate insulating layers, an oxide 430c having a region where a channel is to be formed, a conductor 440a, an oxide 431a, and an oxide 431b functioning as one of a source and a drain, a conductor 440b, an oxide 432a, and an oxide 432b functioning as the other of the source and the drain, and insulators 445a and 445b functioning as a barrier layer.

[0363] In the transistor 400, the conductor 405 is in the same layer as the conductor 205. The oxide 431a and the oxide 432a are in the same layer as the oxide 230a, and the oxide 431b and the oxide 432b are in the same layer as the oxide 230b. The conductor 440 (the conductor 440a and the conductor 440b) is in the same layer as the conductor 240. The insulator 445 (the insulator 445a and the insulator 445b) is in the same layer as the insulator 245. The oxide 430c is in the same layer as the oxide 230c. The insulator 450 is in the same layer as the insulator 250. The conductor 460 is in the same layer as the conductor 260.

[0364] Note that structures formed in the same layer can be formed simultaneously. For example, oxide 430c can be formed by processing the oxide film that will become oxide 230c.

[0365] The oxide 430c functioning as an active layer of the transistor 400 has reduced oxygen vacancies and reduced impurities such as hydrogen and water, similar to the oxide 230. As a result, the threshold voltage of the transistor 400 can be made higher than 0 V, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be made very small.

[0366] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0367] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes and examples.

[0368] (Embodiment 3) In this embodiment, a transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a memory device including a capacitor (hereinafter also referred to as an OS memory device) according to one embodiment of the present invention will be described with reference to FIGS. 15 and 16 . The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. The off-state current of the OS transistor is extremely small, so the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

[0369] <Storage device configuration example> 15A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0370] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is connected to a memory cell in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 also includes, for example, a row decoder, a word line driver circuit, etc., and can select a row to access.

[0371] The memory device 1400 is supplied with a low power supply voltage (VSS) from the outside as power supply voltages, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470. Control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are also input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and WDATA is input to a write circuit.

[0372] The control logic circuit 1460 processes external input signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0373] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0374] 15A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited to this. For example, as shown in FIG. 15B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0375] FIG. 16 illustrates an example of the configuration of a memory cell that can be applied to the above-described memory cell MC.

[0376] [DOSRAM] 16A to 16C show circuit configuration examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 16A includes a transistor M1 and a capacitor CA. The transistor M1 includes a gate (sometimes referred to as a top gate) and a back gate.

[0377] The first terminal of the transistor M1 is connected to the first terminal of the capacitance element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, the back gate of the transistor M1 is connected to the wiring BGL, and the second terminal of the capacitance element CA is connected to the wiring CAL.

[0378] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0379] 16A corresponds to the memory device shown in FIG. 12. That is, the transistor M1 corresponds to the transistor 200, the capacitor CA corresponds to the capacitor 100, the wiring BIL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, and the wiring CAL corresponds to the wiring 1005. Note that the transistor 300 shown in FIG. 12 corresponds to a transistor provided in the peripheral circuit 1411 of the memory device 1400 shown in FIG. 15B.

[0380] The memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may have a configuration in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 16B. Furthermore, for example, the memory cell MC may be a memory cell configured with a single-gate transistor, that is, a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 16C.

[0381] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Furthermore, the refresh operation of the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0382] Furthermore, in the DOSRAM, if the sense amplifier is configured to overlap under the memory cell array 1470 as described above, the bit line can be shortened, which reduces the bit line capacitance and the storage capacitance of the memory cell.

[0383] [NOSRAM] 16D to 16G show circuit configuration examples of a gain cell type memory cell having two transistors and one capacitor. The memory cell 1474 shown in FIG. 16D includes a transistor M2, a transistor M3, and a capacitor CB. The transistor M2 has a top gate (sometimes simply referred to as a gate) and a back gate. In this specification and the like, a memory device having a gain cell type memory cell using an OS transistor as the transistor M2 may be referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0384] The first terminal of transistor M2 is connected to the first terminal of capacitor CB, the second terminal of transistor M2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitor CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitor CB.

[0385] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0386] 16D corresponds to the memory device shown in Fig. 13. That is, the transistor M2 corresponds to the transistor 200, the capacitor CB corresponds to the capacitor 100, the transistor M3 corresponds to the transistor 300, the wiring WBL corresponds to the wiring 2003, the wiring WOL corresponds to the wiring 2004, the wiring BGL corresponds to the wiring 2006, the wiring CAL corresponds to the wiring 2005, the wiring RBL corresponds to the wiring 2002, and the wiring SL corresponds to the wiring 2001.

[0387] Furthermore, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 16E. Furthermore, for example, the memory cell MC may be configured as a memory cell including a single-gate transistor, i.e., a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 16F. Furthermore, for example, the memory cell MC may be configured such that the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 16G.

[0388] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor CB can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be significantly reduced. This allows written data to be held by the transistor M2 for a long time, thereby reducing the frequency of refreshing the memory cell. Furthermore, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0389] Note that the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, may be referred to as a Si transistor). The conductivity type of the Si transistor may be either an n-channel type or a p-channel type. The Si transistor may have higher field-effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read transistor. Furthermore, by using a Si transistor as the transistor M3, the transistor M2 can be stacked on top of the transistor M3, thereby reducing the area occupied by the memory cell and achieving higher integration of the memory device.

[0390] Furthermore, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured as a circuit using only n-type transistors.

[0391] 16H shows an example of a gain cell type memory cell having three transistors and one capacitor. The memory cell 1478 shown in FIG. 16H includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL. The GNDL wiring is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to wirings RBL and WBL instead of wiring BIL.

[0392] The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not necessarily have a back gate.

[0393] Note that the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, or the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured as a circuit using only n-channel transistors.

[0394] When the semiconductor device described in the above embodiment is used in the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistors M5 and M6 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be significantly reduced.

[0395] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.

[0396] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes, examples, and the like.

[0397] (Fourth embodiment) In this embodiment, an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown with reference to Fig. 17. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0398] As shown in FIG. 17A, a chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0399] 17B, ​​the chip 1200 is provided with bumps (not shown), which are connected to a first surface of a printed circuit board (PCB) 1201. In addition, a plurality of bumps 1202 are provided on the backside of the first surface of the PCB 1201, which is connected to a motherboard 1203.

[0400] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM described in the previous embodiment may be used as the DRAM 1221. Also, for example, the NOSRAM described in the previous embodiment may be used as the flash memory 1222.

[0401] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the NOSRAM or DOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing and multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-and-accumulate operations with low power consumption.

[0402] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of the calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212.

[0403] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0404] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0405] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0406] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0407] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0408] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204.

[0409] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a small size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0410] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes, examples, and the like.

[0411] (Embodiment 5) In this embodiment, an application example of a storage device using the semiconductor device described in the previous embodiment will be described. The semiconductor device described in the previous embodiment can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), recording / playback devices, navigation systems, etc.). Note that the term "computer" as used herein includes tablet computers, notebook computers, desktop computers, and large-scale computers such as server systems. Alternatively, the semiconductor device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). FIG. 18 schematically shows several configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment can be processed into packaged memory chips and used in various storage devices and removable memories.

[0412] 18A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1105 on the board 1104.

[0413] FIG. 18B is a schematic diagram of the appearance of an SD card, and FIG. 18C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113. A wireless chip with a wireless communication function may also be provided on the substrate 1113. This enables reading and writing of data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1114 of the substrate 1113, etc.

[0414] FIG. 18D is a schematic diagram of the appearance of an SSD, and FIG. 18E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chip 1154, memory chip 1155, and controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be, for example, a DOSRAM chip. By providing memory chip 1154 on the back side of board 1153, the capacity of SSD 1150 can be increased. The semiconductor device described in the previous embodiment can be incorporated into memory chip 1154 of board 1153, etc.

[0415] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes, examples, and the like.

[0416] (Embodiment 6) A semiconductor device according to one embodiment of the present invention can be used in a processor such as a CPU or a GPU, or a chip. Figure 19 illustrates a specific example of an electronic device including a processor such as a CPU or a GPU, or a chip according to one embodiment of the present invention.

[0417] <Electronic devices and systems> A GPU or chip according to one embodiment of the present invention can be mounted in various electronic devices. Examples of such electronic devices include electronic devices with relatively large screens, such as televisions, monitors for desktop or notebook information terminals, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game machines, personal digital assistants, and audio playback devices. Furthermore, by providing an electronic device with a GPU or chip according to one embodiment of the present invention, it is possible to equip the electronic device with artificial intelligence.

[0418] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0419] An electronic device according to one embodiment of the present invention may have a sensor (including a function for measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0420] An electronic device according to one embodiment of the present invention can have various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, etc. Figure 19 shows an example of an electronic device.

[0421] [Information terminal] 19A shows a mobile phone (smartphone), which is one type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. As input interfaces, a touch panel is provided on the display unit 5102 and buttons are provided on the housing 5101.

[0422] By applying the chip of one embodiment of the present invention, the information terminal 5100 can execute applications using artificial intelligence. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display portion 5102, an application that recognizes characters, figures, and the like input by a user to a touch panel provided in the display portion 5102 and displays them on the display portion 5102, and an application that performs biometric authentication such as fingerprint or voiceprint authentication.

[0423] 19B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0424] The notebook information terminal 5200 can execute applications using artificial intelligence by applying a chip of one embodiment of the present invention, similar to the information terminal 5100 described above. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Furthermore, new artificial intelligence can be developed by using the notebook information terminal 5200.

[0425] 19A and 19B, the electronic devices are illustrated as examples of a smartphone and a notebook information terminal, respectively, but information terminals other than smartphones and notebook information terminals can also be applied. Examples of information terminals other than smartphones and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0426] [Game consoles] FIG. 19C illustrates a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, and the like. The housing 5302 and the housing 5303 can be detached from the housing 5301. By attaching the connection unit 5305 of the housing 5301 to another housing (not shown), the video displayed on the display unit 5304 can be output to another video device (not shown). In this case, the housing 5302 and the housing 5303 can each function as an operation unit. This allows multiple players to play a game simultaneously. The chips described in the above embodiments can be incorporated into the substrates of the housings 5301, 5302, and 5303.

[0427] 19D shows an example of a game machine, a stationary game machine 5400. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wire.

[0428] A game machine with low power consumption can be realized by applying a GPU or a chip of one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0429] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5300, the portable game console 5300 can have artificial intelligence.

[0430] Originally, the expression of the progress of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game console 5300, it becomes possible to express things that are not limited to the game program. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of people appearing in the game.

[0431] Furthermore, when playing a game requiring multiple players on the portable game console 5300, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent an artificial intelligence game player.

[0432] 19C and 19D illustrate a portable game machine and a stationary game machine as examples of game machines, but game machines to which the GPU or chip of one embodiment of the present invention is applied are not limited to these. Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0433] [Mainframe Computer] The GPU or chip according to one embodiment of the present invention can be applied to a mainframe computer.

[0434] 19E is a diagram showing a supercomputer 5500, which is an example of a mainframe computer. FIG. 19F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0435] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and the GPU or chip described in the above embodiment can be mounted on the boards.

[0436] The supercomputer 5500 is a large-scale computer primarily used for scientific and technological calculations. Scientific and technological calculations require high-speed processing of enormous amounts of calculations, resulting in high power consumption and large amounts of heat generated by the chip. By applying a GPU or chip according to one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. Furthermore, low power consumption can reduce heat generation from circuits, thereby reducing the impact of heat generation on the circuits themselves, peripheral circuits, and modules.

[0437] 19E and 19F illustrate a supercomputer as an example of a mainframe computer, but the mainframe computer to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. Examples of the mainframe computer to which the GPU or chip of one embodiment of the present invention is applied include a computer (server) that provides services, a large general-purpose computer (mainframe), etc.

[0438] [Moving object] The GPU or chip according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the area around the driver's seat of an automobile.

[0439] Fig. 19G is a diagram showing the area around the windshield inside the interior of an automobile, which is an example of a moving body, showing display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0440] The display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, air conditioning settings, etc. The display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, allowing for improved design. The display panels 5701 to 5703 can also be used as lighting devices.

[0441] The display panel 5704 can complement the view (blind spot) blocked by the pillar by displaying an image from an imaging device (not shown) installed in the vehicle. That is, by displaying an image from an imaging device installed outside the vehicle, blind spots can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0442] Since the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system for automobiles. The chip can also be used in a system that provides road guidance, hazard prediction, etc. The display panels 5701 to 5704 may be configured to display information such as road guidance and hazard prediction.

[0443] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies can include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets), and the chip of one embodiment of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

[0444] [electric appliances] 19H shows an example of an electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0445] The electric refrigerator-freezer 5800 having artificial intelligence can be realized by applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800. By using artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800 and their expiration dates, a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5800, and the like.

[0446] Although electric refrigerator-freezers have been described as an example of electrical appliances, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0447] The electronic devices, functions of the electronic devices, application examples of artificial intelligence, and effects thereof described in this embodiment can be appropriately combined with descriptions of other electronic devices.

[0448] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes, examples, and the like. [Example]

[0449] In this example, a stacked layer structure including an insulator according to one embodiment of the present invention was fabricated and analyzed by SIMS. In this example, Samples 1A to 1H were fabricated.

[0450] <1. Sample composition and preparation method> Sample 1A, Sample 1B, Sample 1C, Sample 1D, Sample 1E, Sample 1F, Sample 1G, and Sample 1H according to one embodiment of the present invention will be described below. The structures of Samples 1A to 1H are shown in FIG. 20A . Samples 1A to 1H each include a substrate 900, an insulator 914 over the substrate 900, an insulator 916 over the insulator 914, an insulator 922 over the insulator 916, an oxide semiconductor 930 (oxide semiconductor 930a, oxide semiconductor 930b, oxide semiconductor 930c, and oxide semiconductor 903d) over the insulator 922, and an insulator 950 over the oxide semiconductor 930.

[0451] Next, the method for preparing each sample will be described.

[0452] First, a silicon substrate was prepared as the substrate 900. Subsequently, a thermal oxide film was formed on the substrate 900 as the insulator 914 to a thickness of 100 nm.

[0453] Next, a 20-nm-thick hafnium oxide film was formed as an insulator 916 over the insulator 914. Subsequently, a 30-nm-thick silicon oxynitride film was formed as an insulator 922 over the insulator 916.

[0454] Next, a 5-nm-thick oxide semiconductor 930a containing In, Ga, and Zn was deposited on the insulator 922 by sputtering. The oxide semiconductor 930a was deposited using an oxide target containing In, Ga, and Zn (atomic ratio In:Ga:Zn=1:3:4), oxygen (O) at a flow rate of 45 sccm as a deposition gas, under conditions of a deposition pressure of 0.7 Pa, a deposition power of 500 W, a substrate temperature of 130°C, and a target-to-substrate distance of 60 mm. Subsequently, a 15-nm-thick oxide semiconductor 930b containing In, Ga, and Zn was deposited on the oxide semiconductor 930a by sputtering. The oxide semiconductor 930b was formed using an oxide target containing In, Ga, and Zn (atomic ratio In:Ga:Zn=4:2:4.1), oxygen (O) at a flow rate of 45 sccm as the film formation gas, a film formation pressure of 0.7 Pa, a film formation power of 500 W, a substrate temperature of 130°C, and a target-substrate distance of 60 mm.

[0455] Next, a heat treatment was carried out at 200° C. for 5 minutes in a reduced pressure atmosphere.

[0456] Next, an oxide semiconductor 930c containing In, Ga, and Zn was formed on the oxide semiconductor 930b by sputtering to a thickness of 8 nm. The oxide semiconductor 930c was formed using an oxide target containing In, Ga, and Zn (atomic ratio In:Ga:Zn=4:2:4.1), oxygen (O2) at a flow rate of 45 sccm as the film formation gas, under conditions of a film formation pressure of 0.7 Pa, a film formation power of 500 W, a substrate temperature of 130°C, and a target-to-substrate distance of 60 mm. Next, an oxide semiconductor 930b containing In, Ga, and Zn was formed on the oxide semiconductor 930a by sputtering to a thickness of 8 nm. The oxide semiconductor 930d was formed using an oxide target containing In, Ga, and Zn (atomic ratio In:Ga:Zn=1:3:4), oxygen (O) at a flow rate of 45 sccm as the film formation gas, a film formation pressure of 0.7 Pa, a film formation power of 500 W, a substrate temperature of 130°C, and a target-substrate distance of 60 mm.

[0457] Next, a silicon oxide film with a thickness of 10.8 nm was formed by a CVD method over the oxide semiconductor 930d as the insulator 950. Table 1 shows the film formation conditions for Samples 1A to 1H.

[0458] In addition, deuterium (D2) was added at a flow rate of 200 sccm during the formation of the insulator 950, and the amount of hydrogen diffusing into the film-forming object during the film formation was examined.

[0459] [Table 1]

[0460] Samples 1A to 1H of this example were fabricated through the above steps. Measurements of each sample were performed on Samples 1A to 1H before and after heat treatment, which simulated the thermal history of subsequent steps.

[0461] The heat treatment was carried out in a nitrogen atmosphere at 400° C. for 1 hour.

[0462] <2. Measurement of the amount of deuterium (D2) in the oxide semiconductor 930 of each sample> Next, SIMS analysis was performed from the substrate side using the oxide semiconductors 930 of Samples 1A to 1H as quantification layers to detect the deuterium (D2) concentrations and measure the amounts of deuterium in the oxide semiconductors 930. The hydrogen concentrations were evaluated by secondary ion mass spectrometry (SIMS), and a dynamic SIMS instrument IMS-7f manufactured by CAMECA Corporation was used as the analyzer.

[0463] FIG. 20B shows the concentration of deuterium (D2) [atoms / cm 3 ] calculated by integrating the profile of the deuterium (D2) concentration in the oxide semiconductor 930, which is the quantification layer, for each sample. 2 ] is shown.

[0464] From FIG. 20B, by setting the value of the constant Y to 0 < Y < 18, preferably 0 < Y ≤ 7.0, in the film formation conditions of the insulator 950, it was possible to reduce the amount of hydrogen diffusing into the film formation target (in this example, the oxide semiconductor 930) in the step of forming the insulator 950.

[0465] That is, in the film formation power PW [W], the execution electrode area S [cm 2 , the film formation pressure P [Pa], and the flow rate f [sccm] of the film formation gas containing hydrogen, which are variables for determining the value of the constant Y, the following was found.

[0466] It was confirmed that when the flow rate f [sccm] of the film formation gas increases, the amount of hydrogen diffusing into the film formation target is reduced. On the other hand, it was confirmed that the amount of hydrogen diffusing into the film formation target increases as the film formation power per unit area calculated by dividing the film formation power PW [W] by the execution electrode area S [cm 2 and the film formation pressure P [Pa] increase.

[0467] In particular, it was found that the increase amount of the hydrogen amount diffusing into the film formation target when the film formation power is increased is relatively small. On the other hand, when the film formation pressure P [Pa] was increased, the amount of hydrogen diffusing into the film formation target increased gently. Also, it was found that the increase in the amount of diffusing hydrogen accompanying the increase in the flow rate f [sccm] of the film formation gas has a large slope and a greater influence than the film formation power and the film formation pressure P [Pa].

[0468] From the above, in the film formation conditions of the insulator, by setting the value of the constant Y to 0 < Y < 17, preferably 0 < Y ≤ 7.0, it was possible to provide an insulator that can be formed without diffusing hydrogen to the film formation target.

[0469] As described above, the configuration shown in this embodiment can be used in appropriate combination with other embodiments or other implementation forms.

Example

[0470] In this example, a stacked layer structure including an insulator according to one embodiment of the present invention was fabricated and observed using an optical microscope. In this example, Samples 2A to 2I were fabricated.

[0471] <1. Sample composition and preparation method> Sample 2A, Sample 2B, Sample 2C, Sample 2D, Sample 2E, Sample 2F, Sample 2G, Sample 2H, and Sample 2I according to one embodiment of the present invention will be described below. The structures of Samples 2A to 2I are shown in FIG. Each of Samples 2A to 2I includes a substrate 800, an insulator 814 over the substrate 800, an insulator 816 over the insulator 814, an insulator 820 over the insulator 816, an insulator 822 over the insulator 820, an insulator 824 over the insulator 822, an oxide semiconductor 830 (oxide semiconductor 830a and oxide semiconductor 830b) over the insulator 824, a conductor 840 over the oxide semiconductor 830, an insulator 845 (insulator 845a and insulator 845b) over the conductor 840, and an insulator 880 over the insulator 845.

[0472] Next, the method for preparing each sample will be described.

[0473] First, a silicon substrate was prepared as the substrate 800. Subsequently, a thermal oxide film was formed on the substrate 800 as the insulator 814 to a thickness of 400 nm.

[0474] Next, a 40-nm-thick aluminum oxide film was deposited over the insulator 814 as the insulator 816. Subsequently, a 200-nm-thick silicon oxynitride film was deposited over the insulator 816 as the insulator 820.

[0475] Next, a 20-nm-thick hafnium oxide film was formed as an insulator 822 over the insulator 820. Subsequently, a 30-nm-thick silicon oxynitride film was formed as an insulator 824 over the insulator 822.

[0476] Next, a 5-nm-thick oxide semiconductor 830a containing In, Ga, and Zn was formed on the insulator 824 by sputtering. The oxide semiconductor 830a was formed using an oxide target containing In, Ga, and Zn (atomic ratio In:Ga:Zn=1:3:4), oxygen (O2) at a flow rate of 45 sccm as a deposition gas, under conditions of a deposition pressure of 0.7 Pa, a deposition power of 500 W, a substrate temperature of 130°C, and a target-to-substrate distance of 60 mm. Subsequently, a 15-nm-thick oxide semiconductor 830b containing In, Ga, and Zn was formed on the oxide semiconductor 830a by sputtering. The oxide semiconductor 830b was formed using an oxide target containing In, Ga, and Zn (atomic ratio In:Ga:Zn=4:2:4.1), oxygen (O) at a flow rate of 45 sccm as the film formation gas, a film formation pressure of 0.7 Pa, a film formation power of 500 W, a substrate temperature of 130°C, and a target-substrate distance of 60 mm.

[0477] Next, a 25-nm-thick tungsten nitride film was formed as the conductor 840 over the oxide semiconductor 830b by a sputtering method.

[0478] Next, a 5-nm-thick aluminum oxide film was formed by sputtering as the insulator 845a on the conductor 840. Subsequently, a 3-nm-thick aluminum oxide film was formed by ALD as the insulator 845b on the insulator 845a.

[0479] Next, a silicon oxide film with a thickness of 170 nm was formed over the insulator 845b by a CVD method as the insulator 880. Table 2 shows the film formation conditions for Samples 2A to 2I.

[0480] [Table 2]

[0481] By the above steps, Samples 2A to 2I of this example were fabricated.

[0482] <2. Observation of Each Sample by Optical Microscopy Image> Next, the results of observing Samples 2A to 2I with an optical microscope (bright field, magnification 1000 times) are shown in FIGS. 21B and FIG. 22.

[0483] FIG. 21B shows optical micrographs of Samples 2A, 2B, 2C, and 2D under the condition that the film formation pressure during film formation is 200 [Pa]. Further, FIG. 22A shows optical micrographs of Sample 2B and Sample 2E under the condition that the film formation power during film formation is 120 [W]. Further, FIG. 22B shows optical micrographs of Sample 2C, Sample 2F, and Sample 2G under the condition that the film formation power during film formation is 85 [W].

[0484] From FIG. 21B, it was found that the smaller the film formation power during film formation, the less film lifting. Also, from FIG. 22, it was found that the smaller the film formation pressure during film formation, the less film lifting.

[0485] Here, FIG. 23 shows the ratio (%) of film lifting with respect to the value of constant Y in Samples 2A to 2I. The ratio of film lifting was calculated by image analysis of the optical microscope image. From FIG. 23, it was confirmed that there is a correlation between the value of constant Y and the ratio at which film lifting occurs.

[0486] That is, by setting the value of constant Y to 0 < Y < 10, the occurrence of film lifting and peeling could be reduced. In particular, by setting the value of constant Y to 0 < Y ≤ 8.0, the occurrence of film lifting and peeling could be prevented.

[0487] Therefore, under the film formation conditions of the insulator 880, by setting the value of constant Y to 0 < Y ≤ 8.0, the occurrence of film lifting and peeling between the insulator adjacent to the insulator 880 and the conductor could be prevented.

[0488] As described above, the configuration shown in this embodiment can be used in appropriate combination with other embodiments or other implementation forms.

Example

[0489] 9 which is one embodiment of the present invention, were fabricated as Sample 3A and Sample 3B, and a reliability test was performed on the transistor 200. Note that the transistor 200 was designed to have a channel length of 60 nm and a channel width of 60 nm.

[0490] <Sample preparation method> The methods for fabricating Samples 3A and 3B will be described below.

[0491] The oxides 230a, 230b, and 230c were formed by sputtering In-Ga-Zn oxide. The oxide 230a was formed by depositing a 5-nm-thick In-Ga-Zn oxide film using a target with an atomic ratio of In:Ga:Zn=1:3:4. The oxide 230b was formed by depositing a 15-nm-thick In-Ga-Zn oxide film using a target with an atomic ratio of In:Ga:Zn=4:2:4.1.

[0492] Furthermore, an In-Ga-Zn oxide was formed as oxide 230c by a sputtering method. First, an In-Ga-Zn oxide film with a thickness of 8 nm was formed using a target with an atomic ratio of In:Ga:Zn=4:2:4.1, and then an In-Ga-Zn oxide film with a thickness of 8 nm was formed using a target with an atomic ratio of In:Ga:Zn=1:3:4.

[0493] Furthermore, titanium nitride was formed by sputtering to a film thickness of 25 nm as the conductor 240. Subsequently, aluminum oxide was formed as the insulator 245. To form the film that would become the insulator 245, first, a 5 nm thick aluminum oxide film was formed by sputtering, and then a 3 nm thick aluminum oxide film was formed by ALD.

[0494] Furthermore, as the insulator 280 that functions as an interlayer film in contact with the transistor 200, a silicon oxynitride (SiON) film having a thickness of 110 nm was formed by a CVD method.

[0495] The film formation conditions for the insulator 280 in each sample are shown below.

[0496] [Table 3]

[0497] As a result, Samples 3A and 3B were prepared.

[0498] <2. Cross-sectional observation of each sample> Cross-sectional observation was performed on Sample 3A and Sample 3B. The cross-sectional observation was performed using a scanning transmission electron microscope (STEM). The observation device used was an HD-2700 manufactured by Hitachi High-Technologies Corporation. The cross-sectional STEM observation results are shown in Figure 24.

[0499] FIG. 24A shows a STEM photograph of the cross section of Sample 3A, in which the constant Y is 32.5, and FIG. 24B shows a STEM photograph of the cross section of Sample 3B, in which the constant Y is 1.9.

[0500] 24, it was confirmed that the transistor 200 of the present invention can be provided by using an insulator with a constant Y of 1.9 as the insulator 280 in contact with the transistor 200. On the other hand, it was confirmed that film floating occurs between the oxide 230 and the conductor 240 when an insulator with a constant Y of 32.5 is used as the insulator 280 in contact with the transistor 200.

[0501] As described above, the configuration shown in this embodiment can be used in appropriate combination with other embodiments or other mode of embodiment. [Explanation of symbols]

[0502] 200: transistor, 205: conductor, 210: insulator, 212: insulator, 214: insulator, 216: insulator, 218: conductor, 222: insulator, 224: insulator, 230: oxide, 230a: oxide, 230A: oxide film, 230b: oxide, 230B: oxide film, 230c: oxide, 230C: oxide film, 240: conductor, 240a: conductor, 240A: conductive film, 240b: conductor, 240B: conductive layer, 245: insulator, 245a: insulator, 245A: insulating film, 245b: insulator, 245B: insulating layer, 246: conductor, 247: insulator, 248: conductor 250: insulator, 250A: insulating film, 260: conductor, 260a: conductor, 260A: conductive film, 260b: conductor, 260B: conductive film, 273: insulator, 274: insulator, 280: insulator, 280A: insulating film, 282: insulator, 283: insulator, 284: insulator, 290: hard mask, 290A: film, 290B: hard mask, 292: resist mask, 295: opening, 300: transistor, 311: substrate, 312: insulator, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320 : insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 400: transistor, 405: conductor, 405a: conductor, 405b: conductor, 430c: oxide, 431a: oxide, 431b: oxide, 432a: oxide, 432b: oxide, 440: conductor, 440a: conductor, 440b: conductor, 445: insulator, 445a: insulator, 445b: insulator, 450: insulator, 460: conductor, 460a: conductor, 460b: conductor, 80 0: substrate, 814: insulator, 816: insulator, 820: insulator, 822: insulator, 824: insulator, 830: oxide semiconductor, 830a: oxide semiconductor, 830b: oxide semiconductor, 840: conductor, 845: insulator, 845a: insulator, 845b: insulator, 880: insulator, 900: substrate, 903d: oxide semiconductor, 914: insulator, 916: insulator, 922: insulator, 924: insulator, 930: oxide semiconductor, 930a: oxide semiconductor, 930b: oxide semiconductor, 930c: oxide semiconductor, 930d: oxide semiconductor, 950: insulator, 980: insulator

Claims

[Claim 1] an oxide semiconductor serving as a channel formation region is formed over a substrate; forming a conductor that functions as a source electrode or a drain electrode in contact with the oxide semiconductor; removing a portion of the conductor to expose the oxide semiconductor; The method for manufacturing a semiconductor device further comprises forming an insulator in the exposed region of the oxide semiconductor by chemical vapor deposition under a condition that satisfies the following relationship (1): [Equation 1] (Where, PW [W] is the film formation power, S [cm ２ ] is the effective electrode area, P [Pa] is the deposition pressure, and f [sccm] is the flow rate of silane (SiH ４ ) represents the flow rate of the deposition gas in the system.

Images