MOS transistor and manufacturing method thereof

Abstract

To manufacture a MOS transistor with low on-resistance.SOLUTION: A manufacturing method for a MOS transistor includes the steps of etching a surface of a SiC substrate with hydrogen gas while the SiC substrate is heated to a temperature of 1200°C or higher, forming an amorphous silicon layer on the surface of the SiC substrate after the etching with hydrogen gas, forming a gate insulating film made of silicon oxide on the surface of the amorphous silicon layer by chemical vapor deposition, and performing a nitrogen termination treatment on the SiC substrate after the gate insulating film is formed.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a MOS transistor and a manufacturing method thereof.

[0002] In the method for manufacturing a MOS transistor disclosed in Patent Document 1, a substrate made of SiC (i.e., silicon carbide) is etched with hydrogen gas (i.e., H2) in a silicon-rich atmosphere. This cleans the surface of the SiC substrate and forms a thin film of silicon crystal (i.e., Si) on the surface of the SiC substrate. Next, a silicon oxide film (i.e., SiO2) is formed as a gate insulating film on the surface of the silicon thin film formed on the surface of the SiC substrate. At this time, the silicon thin film is oxidized, thereby suppressing oxidation of the surface of the SiC substrate. By suppressing oxidation of the surface of the SiC substrate in this way, the interface state density at the interface between the silicon oxide film and the SiC substrate can be reduced. By reducing the interface state density at the interface between the silicon oxide film and the SiC substrate, channel mobility is improved and channel resistance is reduced. Therefore, the on-resistance of the MOS transistor can be reduced. After the silicon oxide film is formed, a nitrogen termination treatment is performed. The nitrogen termination treatment can further reduce the interface state density at the interface between the silicon oxide film and the SiC substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-192397 Summary of the Invention [Problem to be solved by the invention]

[0004] This specification proposes a technique for manufacturing a MOS transistor with low on-resistance by a method different from that of Patent Document 1. [Means for solving the problem]

[0005] The method for manufacturing a MOS transistor disclosed in this specification includes the steps of: etching a surface of a SiC substrate with hydrogen gas while the SiC substrate is heated to a temperature of 1200°C or higher; forming an amorphous silicon layer on the surface of the SiC substrate after the etching with hydrogen gas; forming a gate insulating film made of silicon oxide on the surface of the amorphous silicon layer by chemical vapor deposition; and performing a nitrogen termination treatment on the SiC substrate after the gate insulating film is formed.

[0006] In this manufacturing method, the surface of the SiC substrate is cleaned by etching with hydrogen gas. Then, an amorphous silicon layer is formed on the surface of the SiC substrate. Next, a gate insulating film made of silicon oxide is formed on the surface of the amorphous silicon layer by chemical vapor deposition (hereinafter sometimes referred to as CVD). When the gate insulating film is formed, the amorphous silicon layer is oxidized to form silicon oxide. This suppresses oxidation of the surface of the SiC substrate. Then, nitrogen termination is performed to terminate the SiC crystals with nitrogen at the interface between the gate insulating film and the SiC substrate. This manufacturing method can suppress oxidation of the SiC substrate during the formation of the gate insulating film, thereby reducing the interface state density at the interface between the gate insulating film and the SiC substrate. Therefore, this manufacturing method can reduce channel resistance, enabling the manufacture of MOS transistors with low on-resistance. [Brief explanation of the drawings]

[0007] [Figure 1] Cross-sectional view of a MOS transistor. [Figure 2] FIG. [Figure 3] FIG. [Figure 4] Electron diffraction image of the amorphous layer. [Figure 5] 10 is a photograph of the shoulder of a gate structure formed by the manufacturing method of the embodiment (high-temperature hydrogen etching for 15 minutes). [Figure 6]10 is a photograph of the shoulder of a gate structure formed by the manufacturing method of the embodiment (high-temperature hydrogen etching for 30 minutes). [Figure 7] 10 is a photograph of a shoulder portion of a gate structure formed by a manufacturing method of a comparative example. [Figure 8] Evaluation results of the breakdown voltage of the gate insulating film in Figs. DETAILED DESCRIPTION OF THE INVENTION

[0008] In one example manufacturing method disclosed in this specification (hereinafter referred to as a specific example manufacturing method), a trench may be provided in a main surface of the SiC substrate. In the step of etching the surface of the SiC substrate, the side surface of the trench may be etched with hydrogen gas. In the step of forming the amorphous silicon layer, the amorphous silicon layer may be formed on the side surface of the trench. In the step of forming the gate insulating film, the gate insulating film may be formed on the surface of the amorphous silicon layer covering the side surface of the trench.

[0009] According to the manufacturing method of the specific example, a trench-gate MOS transistor with low on-resistance can be suitably manufactured, as described below. The hydrogen etching process of Patent Document 1 (i.e., a process of hydrogen-etching a SiC substrate in a silicon-rich atmosphere) does not allow for the formation of a thin silicon film on the sidewall of the trench. Therefore, in a trench-gate MOS transistor, it is not possible to reduce the interface state density at the interface between the gate insulating film and the SiC substrate (i.e., the sidewall of the trench). That is, the technique of Patent Document 1 makes it difficult to reduce the channel resistance of a trench-gate MOS transistor, making it difficult to manufacture a trench-gate MOS transistor with low on-resistance. In contrast, the manufacturing method of the specific example cleans the sidewall of the trench by etching with hydrogen gas. Then, an amorphous silicon layer is formed on the sidewall of the trench. The amorphous silicon layer can be suitably formed on the sidewall of the trench. Next, a gate insulating film made of silicon oxide is formed on the surface of the amorphous silicon layer by chemical vapor deposition (hereinafter sometimes referred to as CVD). When the gate insulating film is formed, the amorphous silicon layer is oxidized to form silicon oxide. This suppresses oxidation of the sidewalls of the trench. Then, nitrogen termination is performed to terminate the SiC crystal with nitrogen at the interface between the gate insulating film and the SiC substrate. Thus, according to the specific example manufacturing method, oxidation of the sidewalls of the trench can be suppressed during the formation of the gate insulating film, thereby reducing the interface state density at the interface between the gate insulating film and the SiC substrate. Therefore, according to this manufacturing method, it is possible to reduce the channel resistance, and a trench-gate MOS transistor with low on-resistance can be manufactured.

[0010] In one example manufacturing method disclosed herein, the etching with hydrogen gas may etch the side surface of the trench and the main surface of the SiC substrate. The amorphous silicon layer forming step may form the amorphous silicon layer on the side surface of the trench and the main surface of the SiC substrate. The gate insulating film forming step may form the gate insulating film on the surface of the amorphous silicon layer in an area covering the side surface of the trench and the main surface of the SiC substrate.

[0011] In one example manufacturing method disclosed herein, the amorphous silicon layer may be formed by chemical vapor deposition.

[0012] This configuration allows the amorphous silicon layer to be formed favorably.

[0013] In one example of a manufacturing method disclosed in the present specification, the amorphous silicon layer may be formed in a nitrogen atmosphere by chemical vapor deposition while the SiC substrate is heated to a temperature of 400°C or higher and 550°C or lower.

[0014] This configuration allows the amorphous silicon layer to be formed favorably.

[0015] In one example of the manufacturing method disclosed in the present specification, the amorphous silicon layer may be formed by chemical vapor deposition in a state where the SiC substrate is placed under a pressure of 0.3 Torr or more and 1.0 Torr or less.

[0016] This configuration allows the amorphous silicon layer to be formed favorably.

[0017] In one example of the manufacturing method disclosed in the present specification, the amorphous silicon layer on the side surface of the trench may have a thickness of 6 nm or less.

[0018] If the amorphous silicon layer is too thick, a portion of the amorphous silicon layer may remain unoxidized. In contrast, if the thickness of the amorphous silicon layer is 6 nm or less, the amorphous silicon layer can be prevented from remaining unoxidized.

[0019] In the exemplary manufacturing method disclosed in the present specification, the main surface of the SiC substrate may be a surface of an epitaxial layer.

[0020] In one example of the manufacturing method disclosed in the present specification, the nitrogen termination treatment may involve heating the SiC substrate to a temperature of 1200° C. or higher in nitrogen gas or nitrogen oxide gas.

[0021] In one example manufacturing method disclosed in the present specification, after the gate insulating film is formed, in a cross section of the main surface of the SiC substrate along a direction perpendicular to the trench and a thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the trench may be connected by an arc with a minimum radius of curvature of 53 nm or more.

[0022] This configuration can suppress current leakage at the boundary between the main surface of the SiC substrate and the side surface of the trench.

[0023] In one example manufacturing method disclosed in the present specification, after the gate insulating film is formed, in a cross section of the main surface of the SiC substrate along a direction perpendicular to the trench and a thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the trench may be connected by an elliptical arc or a circular arc with an oblateness of 0.29 or less.

[0024] This configuration can suppress current leakage at the boundary between the main surface of the SiC substrate and the side surface of the trench.

[0025] A MOS transistor according to an example disclosed herein may include a SiC substrate having a trench formed in a main surface thereof, a gate insulating film covering a side surface of the trench, and a gate electrode formed in the trench. In a cross section of the main surface taken along a direction perpendicular to the trench and a thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the trench may be connected by an arc having a minimum radius of curvature of 53 nm or more.

[0026] This configuration can suppress current leakage at the boundary between the main surface of the SiC substrate and the side surface of the trench.

[0027] An example MOS transistor disclosed in this specification may include a SiC substrate having a trench formed in a main surface thereof, a gate insulating film covering a side surface of the trench, and a gate electrode formed in the trench. In a cross section of the main surface taken along a direction perpendicular to the trench and a thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the trench may be connected by an elliptical arc or a circular arc having an oblateness of 0.29 or less.

[0028] This configuration can suppress current leakage at the boundary between the main surface of the SiC substrate and the side surface of the trench.

[0029] FIG. 1 shows a MOS transistor 10 manufactured by a manufacturing method according to the embodiment. The MOS transistor 10 includes a SiC substrate 12, a gate insulating film 14, a gate electrode 16, an interlayer insulating film 18, a source electrode 20, and a drain electrode 22. The SiC substrate 12 has an upper surface 12a and a lower surface 12b as major surfaces. A plurality of trenches 24 are provided in the upper surface 12a of the SiC substrate 12. The trenches 24 extend linearly and parallel to each other on the upper surface 12a. The gate insulating film 14 covers the inner surfaces of each trench 24 (i.e., the side surfaces 24a and bottom surfaces 24b of the trenches 24). A gate electrode 16 is disposed in each trench 24. The gate electrode 16 is insulated from the SiC substrate 12 by the gate insulating film 14. The interlayer insulating film 18 covers the upper surface of the gate electrode 16. The source electrode 20 covers the upper surface 12a of the SiC substrate 12 and the upper surface of the interlayer insulating film 18. The source electrode 20 is insulated from the gate electrode 16 by an interlayer insulating film 18. The drain electrode 22 covers the lower surface 12b of the SiC substrate 12.

[0030] The SiC substrate 12 has a source region 30, a contact region 32, a body region 34, a drift region 36, and a drain region 38. The source region 30 is an n-type region having a high n-type impurity concentration. The source region 30 is in contact with a source electrode 20 and a gate insulating film 14. The contact region 32 is a p-type region having a high p-type impurity concentration. The contact region 32 is in contact with the source electrode 20. The body region 34 is a p-type region having a lower p-type impurity concentration than the contact region 32. The body region 34 is in contact with the source region 30 and the contact region 32 from below. The body region 34 is in contact with the gate insulating film 14 below the source region 30. The drift region 36 is an n-type region having a lower n-type impurity concentration than the source region 30. The drift region 36 is in contact with the body region 34 from below. The drift region 36 is in contact with the body region 34 from below. The drift region 36 is in contact with the gate insulating film 14 below the body region 34. The drain region 38 is an n-type region having a higher n-type impurity concentration than the drift region 36. The drain region 38 contacts the drift region 36 from below. The drain region 38 contacts the drain electrode 22.

[0031] When a potential equal to or greater than the threshold is applied to the gate electrode 16, a channel is formed in the body region 34 along the gate insulating film 14 (i.e., the side surface 24a of the trench 24). The channel connects the source region 30 and the drift region 36. When a potential higher than that of the source electrode 20 is applied to the drain electrode 22 with the channel formed, electrons flow from the source region 30 to the drain region 38 via the channel and the drift region 36.

[0032] Next, a manufacturing method of the MOS transistor 10 will be described as an example. The manufacturing method of the example allows manufacturing a MOS transistor 10 with low on-resistance. The manufacturing method of the example is characterized by the method of forming the trench gate structure. Therefore, in each figure explaining the manufacturing method, illustration of the p-type region and n-type region in the SiC substrate 12 is omitted.

[0033] As shown in FIG. 2(a), a SiC substrate 12 is prepared before trench formation. The SiC layer exposed on the upper surface 12a is an epitaxial layer (i.e., a SiC layer formed by epitaxial growth). Although not shown in FIG. 2, a source region 30, a contact region 32, a body region 34, a drift region 36, and a drain region 38 are provided within the SiC substrate 12.

[0034] First, as shown in FIG. 2(b), the upper surface 12a of the SiC substrate 12 is selectively etched to form trenches 24 in the upper surface 12a.

[0035] Carbon defects having C-C bonds exist at a high density on the surface of the SiC substrate 12. The carbon defects form interface states and capture electrons. When carbon defects exist at a high density at the interface between the side surface 24a of the trench 24 and the gate insulating film 14, Coulomb scattering occurs due to electrons captured in the interface states. In this case, the channel mobility decreases and the channel resistance increases. In contrast, as described below, in the manufacturing method of the embodiment, a gate structure can be formed with a low interface state density on the side surface 24a of the trench 24.

[0036] After forming the trench 24 as shown in FIG. 2(b), high-temperature hydrogen etching is performed as shown in FIG. 3(a). In high-temperature hydrogen etching, the SiC substrate 12 is heated to a temperature of 1200°C or higher (e.g., 1300°C) in hydrogen (H2) gas. The hydrogen gas then etches the surface of the SiC substrate 12 (i.e., the upper surface 12a and the inner surface of the trench 24). Here, a very thin layer near the surface of the SiC substrate 12 is etched. As a result, carbon defects can be removed from the surface of the SiC substrate 12. In other words, high-temperature hydrogen etching can reduce the carbon defect density on the surface of the SiC substrate 12.

[0037] Next, the amorphous silicon layer formation process shown in FIG. 3(b) is performed. Here, a low-pressure CVD apparatus is used to form a silicon layer on the surface of the SiC substrate 12 in a nitrogen atmosphere. SiH4 gas and N2 gas are used. The deposition temperature is controlled to 400°C or higher and 550°C or lower, and the deposition pressure is controlled to 0.3 Torr or higher and 1.0 Torr or lower. Performing CVD under these low-temperature and low-pressure conditions results in slow growth of the silicon layer. As a result, an amorphous silicon layer 42 with a relatively uniform thickness is formed on the upper surface 12a of the SiC substrate 12 and the inner surface of the trench 24. FIG. 4 shows an electron diffraction image of the amorphous silicon layer 42 formed on the side surface of the trench 24 by this method. As shown in FIG. 4, a broad halo pattern is observed, confirming that the silicon layer formed on the side surface of the trench 24 is amorphous.

[0038] Furthermore, performing CVD under these conditions can reduce the surface roughness of the amorphous silicon layer 42. For example, the flow rates of SiH4 gas and N2 gas can be controlled to 250 sccm and 230 sccm, respectively. Here, the film formation time is adjusted to form the amorphous silicon layer 42 so that the thickness of the amorphous silicon layer 42 on the side surface 24a is 6 nm or less.

[0039] 3(c), a gate insulating film formation process is carried out. Here, a low-pressure CVD apparatus is used to form a silicon oxide layer 44 on the surface of the amorphous silicon layer 42. That is, the silicon oxide layer 44 is formed on the upper surface 12a and in the trenches 24.

[0040] Next, nitrogen termination is performed. In nitrogen termination, the SiC substrate 12 is heated to a temperature of 1200°C or higher (e.g., 1250°C) in nitrogen gas (i.e., N2 gas) or nitrogen oxide gas (e.g., NO gas, N2O gas, NO2 gas, etc.). This nitrogen-terminates the SiC crystal.

[0041] In conventional manufacturing methods, the surface of the SiC substrate may be oxidized during the gate insulating film formation process. Furthermore, in conventional manufacturing methods, the surface of the SiC substrate may be oxidized during the nitrogen termination process. For example, when nitrogen oxide gas is used during the nitrogen termination process, the surface of the SiC substrate may be oxidized by oxygen atoms in the nitrogen oxide gas. Even when nitrogen gas is used during the nitrogen termination process, the surface of the SiC substrate may be oxidized by a trace amount of oxidizing gas mixed into the chamber. Oxidation of the surface of the SiC substrate during the gate insulating film formation process and the nitrogen termination process generates carbon defects on the surface of the SiC substrate. In contrast, in this embodiment, the amorphous silicon layer 42 is oxidized instead of the SiC substrate 12 during the gate insulating film formation process and the nitrogen termination process shown in FIG. 3( c). The silicon oxide layer 42 a formed by oxidation of the amorphous silicon layer 42 is integrated with the silicon oxide layer 44 formed by CVD. This results in the formation of the gate insulating film 14. Furthermore, oxidation of the amorphous silicon layer 42 instead of the SiC substrate 12 suppresses oxidation of the surface of the SiC substrate 12. Therefore, carbon defects are unlikely to be generated on the surface of the SiC substrate 12 (i.e., the interface between the SiC substrate 12 and the gate insulating film 14). This makes it possible to reduce the interface state density on the surface of the SiC substrate 12. Due to this effect and the effect of nitrogen-terminating the SiC crystal by the nitrogen termination treatment, it is possible to significantly reduce the interface state density on the interface between the SiC substrate 12 and the gate insulating film 14. In particular, in this embodiment, since the amorphous silicon layer 42 can be formed on the side surface 24a of the trench 24, it is possible to significantly reduce the interface state density on the side surface 24a (i.e., the interface between the SiC substrate 12 and the gate insulating film 14).

[0042] 3(d), a gate electrode 16 is formed in the trench 24. An interlayer insulating film 18 is also formed on the gate electrode 16. This completes the trench gate structure.

[0043] 1, the gate insulating film 14 on the upper surface 12a is selectively removed to form a contact hole 20a. Next, a source electrode 20 is formed to cover the upper surface 12a of the SiC substrate 12. Next, a drain electrode 22 is formed to cover the lower surface 12b of the SiC substrate 12. Through the above steps, the MOS transistor 10 shown in FIG. 1 is completed.

[0044] According to the manufacturing method of the embodiment, carbon defects present on the side surface 24a of the trench 24 can be removed by high-temperature hydrogen etching. According to the manufacturing method of the embodiment, the amorphous silicon layer 42 is oxidized in the gate insulating film forming step and the nitrogen termination treatment step, thereby suppressing oxidation of the SiC substrate 12 and suppressing the generation of carbon defects on the side surface 24a of the trench 24. According to the manufacturing method of the embodiment, the nitrogen termination treatment can reduce the interface state density at the interface between the SiC substrate 12 and the gate insulating film 14. Therefore, a MOS transistor 10 having a low interface state density on the side surface 24a (i.e., the interface between the body region 34 and the gate insulating film 14) can be manufactured. Therefore, according to this manufacturing method, the channel resistance of the MOS transistor 10 can be reduced. That is, according to this manufacturing method, a MOS transistor 10 having a low on-resistance can be manufactured.

[0045] When the characteristics of a MOS transistor 10 manufactured by the manufacturing method of the embodiment (hereinafter referred to as the embodiment prototype) and a MOS transistor manufactured by a conventional manufacturing method (hereinafter referred to as the conventional product) were evaluated, it was confirmed that the embodiment prototype could achieve a higher channel mobility than the conventional product. Furthermore, while the conventional product's channel mobility decreased as the temperature decreased, the embodiment prototype's channel mobility increased as the temperature decreased. This is thought to be because the embodiment prototype's interface state density was reduced, thereby reducing the influence of Coulomb scattering at low temperatures. Furthermore, the embodiment prototype was confirmed to have a lower on-resistance than the conventional product. This is thought to be because the embodiment prototype's channel resistance was reduced due to the increased channel mobility. It was also confirmed that the embodiment prototype could achieve a breakdown voltage equivalent to that of the conventional product.

[0046] 5 to 7 show cross sections along a direction perpendicular to the extension direction of the trench 24 on the upper surface 12a and along the thickness direction of the SiC substrate 12. FIGS. 5 and 6 show enlarged photographs of the boundary (hereinafter referred to as the shoulder) between the side surface 24a and the upper surface 12a when the gate insulating film 14 is formed by the manufacturing method of the embodiment. More specifically, FIG. 5 shows the shape of the shoulder when high-temperature hydrogen etching is performed for 15 minutes without performing the sacrificial oxide film formation step and the sacrificial oxide film removal step. FIG. 5 corresponds to a MOS transistor 10 (hereinafter referred to as the example prototype) manufactured by the manufacturing method of the embodiment. FIG. 6 shows the shape of the shoulder when high-temperature hydrogen etching is performed for 30 minutes without performing the sacrificial oxide film formation step and the sacrificial oxide film removal step. Furthermore, FIG. 7 shows an enlarged photograph of the shoulder when the gate insulating film 14 is formed by the manufacturing method of the comparative example. More specifically, FIG. 7 shows the shape of the shoulder when the sacrificial oxide film formation step and the sacrificial oxide film removal step are performed and argon etching is performed instead of high-temperature hydrogen etching.

[0047] In argon etching, the etching rates of the upper surface 12a and the side surface 24a differ significantly, and etching of the upper surface 12a proceeds faster than etching of the side surface 24a. Therefore, as shown in FIG. 7, a sloped portion 100 is formed at the shoulder, gradually displacing downward as it approaches the trench. Furthermore, in a portion 102 between the sloped portion 100 and the side surface 24a, the surface of the SiC substrate 12 bends with a small radius of curvature. That is, in FIG. 7, the radius of curvature of the shoulder is smallest at portion 102, and its value is 47 nm. Furthermore, the dashed line 200 in FIG. 7 represents the shoulder connecting the upper surface 12a and the side surface 24a as an elliptical arc. The oblateness of the ellipse constituting the elliptical arc 200 is 0.40. The oblateness f is a value expressed by f=1-b / a, where a is the major axis of the ellipse and b is the minor axis. In argon etching, the etching rate of the top surface 12a is faster than that of the side surface 24a, so the oblateness of the elliptical arc 200 is increased.

[0048] On the other hand, high-temperature hydrogen etching etches the top surface 12a and the side surface 24a more uniformly than argon etching. Therefore, as shown in FIGS. 5 and 6, a locally small portion of the radius of curvature (such as portion 102 in FIG. 7) is not formed at the shoulder between the top surface 12a and the side surface 24a. Therefore, high-temperature hydrogen etching increases the minimum radius of curvature at the shoulder. For example, the minimum radius of curvature at the shoulder is 53 nm in FIG. 5, and 71 nm in FIG. 6. The dashed lines 202 and 204 in FIGS. 5 and 6 represent the shoulder connecting the top surface 12a and the side surface 24a as an elliptical arc. In FIG. 5, the oblateness of the elliptical arc 202 is 0.29, while in FIG. 6, the oblateness of the elliptical arc 204 is 0.25. That is, the oblateness of the elliptical arc is smaller in FIGS. 5 and 6 than in FIG. 7. That is, the elliptical arc in FIGS. 5 and 6 is closer to a perfect circle than in FIG. 7. High-temperature hydrogen etching etches the top surface 12a and the side surface 24a more uniformly than argon etching, so that the oblateness of the elliptical arcs 202 and 204 can be reduced.

[0049] FIG. 8 shows the results of evaluating the breakdown voltage of the gate insulating film 14 at the shoulder position. The horizontal axis of FIG. 8 represents the voltage applied to the gate insulating film 14, and the vertical axis of FIG. 8 represents the leakage current flowing through the gate insulating film 14. In FIG. 8, graphs G5, G6, and G7 represent the results for the MOS transistors of FIGS. 5, 6, and 7, respectively. As shown in FIG. 8, graphs G5 and G6 achieve a higher breakdown voltage than graph G7. FIG. 8 shows that when the minimum radius of curvature of the shoulder is 53 nm or greater and the flattening ratio of the elliptical arc of the shoulder is 0.29 or less, the breakdown voltage is stable at a high value. As such, high-temperature hydrogen etching can form a smoother curved shoulder, thereby enabling a higher breakdown voltage.

[0050] In the above embodiment, a method for manufacturing a trench MOS transistor has been described. However, the techniques disclosed in this specification may also be applied to the manufacture of a MOS transistor having a planar gate structure. In this case, the techniques disclosed in this specification can be used to form a gate insulating film so as to cover the main surface (e.g., the upper surface) of the SiC substrate.

[0051] The configurations of the techniques disclosed in this specification are listed below. (Configuration 1) A method for manufacturing a MOS transistor, comprising: Etching the surface of the SiC substrate with hydrogen gas while heating the SiC substrate to a temperature of 1200°C or higher; forming an amorphous silicon layer on the surface of the SiC substrate after performing the etching with hydrogen gas; forming a gate insulating film made of silicon oxide on the surface of the amorphous silicon layer by chemical vapor deposition; performing a nitrogen termination process on the SiC substrate after forming the gate insulating film; A manufacturing method comprising the steps of: (Configuration 2) a trench is provided in a main surface of the SiC substrate, In the step of etching the surface of the SiC substrate, the side surface of the trench is etched with hydrogen gas; In the step of forming the amorphous silicon layer, the amorphous silicon layer is formed on the side surface of the trench; In the step of forming the gate insulating film, the gate insulating film is formed on the surface of the amorphous silicon layer covering the side surface of the trench. The manufacturing method according to configuration 1. (Configuration 3) The etching with hydrogen gas etches the side surface of the trench and the main surface of the SiC substrate; In the step of forming the amorphous silicon layer, the amorphous silicon layer is formed on the side surface of the trench and on the main surface of the SiC substrate; In the step of forming the gate insulating film, the gate insulating film is formed on the surface of the amorphous silicon layer in an area covering the side surface of the trench and the main surface of the SiC substrate. The manufacturing method according to configuration 2. (Configuration 4) 4. The manufacturing method according to any one of aspects 1 to 3, wherein the amorphous silicon layer is formed by chemical vapor deposition. (Configuration 5) 5. The manufacturing method according to claim 4, wherein the amorphous silicon layer is formed in a nitrogen atmosphere by chemical vapor deposition while the SiC substrate is heated to a temperature of 400° C. or higher and 550° C. or lower. (Configuration 6) 5. The manufacturing method according to claim 4, wherein the amorphous silicon layer is formed by chemical vapor deposition in a state where the SiC substrate is placed under a pressure of 0.3 Torr or more and 1.0 Torr or less. (Configuration 7) 4. The manufacturing method according to any one of aspects 1 to 3, wherein the amorphous silicon layer has a thickness of 6 nm or less. (Configuration 8) 4. The manufacturing method according to any one of aspects 1 to 3, wherein the main surface of the SiC substrate is a surface of an epitaxial layer. (Configuration 9) 4. The manufacturing method according to any one of configurations 1 to 3, wherein the nitrogen termination treatment involves heating the SiC substrate to a temperature of 1200° C. or higher in nitrogen gas or nitrogen oxide gas. (Configuration 10) 4. The manufacturing method according to claim 2, wherein after the gate insulating film is formed, in a cross section of the main surface of the SiC substrate along a direction perpendicular to the trench and a thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the trench are connected by an arc having a minimum radius of curvature of 53 nm or more. (Configuration 11) 4. The manufacturing method according to claim 2, wherein after the gate insulating film is formed, in a cross section of the main surface of the SiC substrate along a direction perpendicular to the trench and a thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the trench are connected by an elliptical arc or a circular arc having an oblateness of 0.29 or less. (Configuration 12) A trench gate MOS transistor, a SiC substrate having a trench formed on its main surface; a gate insulating film covering a side surface of the trench; a gate electrode provided in the trench; and A MOS transistor, wherein in a cross section of the main surface along a direction perpendicular to the trench and along a thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the trench are connected by an arc having a minimum radius of curvature of 53 nm or more. (Configuration 13) A trench gate MOS transistor, a SiC substrate having a trench formed on its main surface; a gate insulating film covering a side surface of the trench; a gate electrode provided in the trench; and In a cross section of the main surface along a direction perpendicular to the trench and a thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the trench are connected by an elliptical arc or a circular arc having a flattening ratio of 0.29 or less.

[0052] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0053] 10: MOS transistor, 12: SiC substrate, 14: gate insulating film, 16: gate electrode, 40: sacrificial oxide film, 42: amorphous silicon layer, 44: silicon oxide layer

Claims

1. A method for manufacturing a MOS transistor, comprising: Etching a surface of the SiC substrate with hydrogen gas while the SiC substrate is heated to a temperature of 1200°C or higher; forming an amorphous silicon layer on the surface of the SiC substrate after performing the etching with hydrogen gas; forming a gate insulating film made of silicon oxide on the surface of the amorphous silicon layer by chemical vapor deposition; performing a nitrogen termination treatment on the SiC substrate after forming the gate insulating film; A manufacturing method comprising the steps of:

2. a trench is provided in a main surface of the SiC substrate; In the step of etching the surface of the SiC substrate, a side surface of the trench is etched with hydrogen gas; In the step of forming the amorphous silicon layer, the amorphous silicon layer is formed on the side surface of the trench; In the step of forming the gate insulating film, the gate insulating film is formed on the surface of the amorphous silicon layer covering the side surface of the trench. The method of claim 1.

3. The etching with hydrogen gas etches the side surface of the trench and the main surface of the SiC substrate; In the step of forming the amorphous silicon layer, the amorphous silicon layer is formed on the side surface of the trench and on the main surface of the SiC substrate; In the step of forming the gate insulating film, the gate insulating film is formed on the surface of the amorphous silicon layer in an area covering the side surface of the trench and the main surface of the SiC substrate. The method of claim 2.

4. The manufacturing method according to any one of claims 1 to 3, wherein the amorphous silicon layer is formed by chemical vapor deposition.

5. 5. The manufacturing method according to claim 4, wherein the amorphous silicon layer is formed by chemical vapor deposition in a nitrogen atmosphere while the SiC substrate is heated to a temperature of 400° C. or higher and 550° C. or lower.

6. The manufacturing method according to claim 4 , wherein the amorphous silicon layer is formed by chemical vapor deposition in a state where the SiC substrate is placed under a pressure of 0.3 Torr or more and 1.0 Torr or less.

7. The manufacturing method according to any one of claims 1 to 3, wherein the amorphous silicon layer has a thickness of 6 nm or less.

8. The manufacturing method according to any one of claims 1 to 3, wherein the main surface of the SiC substrate is a surface of an epitaxial layer.

9. 4. The manufacturing method according to claim 1, wherein the nitrogen termination treatment comprises heating the SiC substrate to a temperature of 1200° C. or higher in nitrogen gas or nitrogen oxide gas.

10. 4. The manufacturing method according to claim 2, wherein, after the gate insulating film is formed, in a cross section of the main surface of the SiC substrate taken along a direction perpendicular to the trench and a thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the trench are connected by an arc having a minimum radius of curvature of 53 nm or more.

11. 4. The manufacturing method according to claim 2, wherein after the gate insulating film is formed, in a cross section of the main surface of the SiC substrate along a direction perpendicular to the trench and a thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the trench are connected by an elliptical arc or a circular arc having an oblateness of 0.29 or less.

12. A trench gate MOS transistor, a SiC substrate having a trench formed on a main surface; a gate insulating film covering a side surface of the trench; a gate electrode provided in the trench; and a MOS transistor, wherein in a cross section of the main surface along a direction perpendicular to the trench and along a thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the trench are connected by an arc having a minimum radius of curvature of 53 nm or more.

13. A trench gate MOS transistor, a SiC substrate having a trench formed on a main surface; a gate insulating film covering a side surface of the trench; a gate electrode provided in the trench; and a MOS transistor, wherein in a cross section of the main surface along a direction perpendicular to the trench and along a thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the trench are connected by an elliptical arc or a circular arc having a flattening ratio of 0.29 or less.

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