Information processing device

Abstract

To make similarity determination on a larger amount of data quickly and accurately by CIM.SOLUTION: An information processing device includes a cluster division unit that distributes a plurality of first data sets equally to two or more clusters while allowing duplications of some of the first data sets, and repeats the allocation into new two or more clusters until the number of first data sets included in each cluster becomes equal to or less than a predetermined limit number, a centroidal value calculation unit that calculates a centroidal value of each of the clusters finally obtained by the allocation by the cluster division unit, a first determination unit that compares the centroid of each of the clusters with second data, and determines, as a search cluster, a cluster having a centroid value that is the most similar to the second data, and a selection unit that compares each of the first data sets included in the search cluster with the second data, and selects a prescribed number, which is one or more, of the first data sets that are similar to the second data.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] An embodiment of the present invention relates to an information processing device. [Background technology]

[0002] In vector data search, data is represented as vectors to find data similar to a given search query, and the similarity between the vectors is calculated. The similarity calculation is usually performed by a host device or a central processing unit (CPU) after reading the data from a storage device.

[0003] By performing similarity calculations using CIM (Computing In Memory), the cost of transferring data to the host device or CPU can be reduced, and the processing load on the host device or CPU can be alleviated. Because CIM performs calculations using a memory cell array, to maximize calculation efficiency, it is desirable to match the number of parallel data processing to the number of bit lines in the memory cell array. If the total number of data is greater than the number of bit lines, the data must be divided into multiple clusters.

[0004] The k-means method is generally used for cluster division. However, since the cluster size is not constant in the k-means method, if the cluster division is performed so that each cluster size is equal to or smaller than the total number of bit lines, some clusters will be smaller than the total number of bit lines, which reduces the calculation efficiency of the CIM. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent Publication No. 2021 / 0064928 Summary of the Invention [Problem to be solved by the invention]

[0006] Therefore, one embodiment of the present invention provides an information processing device that can quickly and accurately perform analogy judgments on large amounts of data using CIM. [Means for solving the problem]

[0007] In order to solve the above problem, according to one embodiment of the present invention, a cluster dividing unit divides a plurality of first data items into two or more clusters while overlapping some of the first data items, and repeats the division into two or more new clusters until the number of the first data items included in each of the divided clusters becomes equal to or less than a predetermined limit number; a centroid calculation unit that calculates a centroid value of each of the plurality of clusters finally allocated by the cluster division unit; a first determination unit that compares the centroids of the plurality of clusters with second data and determines a cluster having the centroid value that is most similar to the second data as a search cluster; a selection unit that compares each of the plurality of first data included in the search cluster with the second data, and selects one or more predetermined number of the first data similar to the second data, An information processing device is provided. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration of an information processing apparatus according to an embodiment. [Figure 2] Functional block diagram of the controller. [Figure 3] FIG. 2 is a block diagram showing a specific configuration of the storage unit in FIG. 1. [Figure 4] 10A and 10B are diagrams for explaining bit-by-bit multiplication and product-sum calculations that add up the results of the multiplications performed in a storage unit. [Figure 5] FIG. 10 is a circuit diagram showing an example of a memory unit in which a plurality of strings are connected to one bit line. [Figure 6] 6 is a diagram showing the relationship between the gate voltage and the threshold voltage of the transistor in each string of FIG. 5. [Figure 7]4 is a flowchart showing a processing operation of the information processing device according to the present embodiment. [Figure 8] FIG. 8 is a diagram for explaining the process of step S2 in FIG. 7. [Figure 9] FIG. 10 is a diagram for explaining an example in which a cluster division unit performs soft clustering using PCA. [Figure 10] FIG. 2 is a perspective view schematically showing memory cells, bit lines, and word lines included in a memory cell array in a cross-point memory. [Figure 11] FIG. 11 is a diagram schematically showing an example of a circuit configuration of the memory cell array shown in FIG. [Figure 12] FIG. 12 is a diagram showing an example of driving the word line WL1 in FIG. [Figure 13] FIG. 12 is a diagram showing an example of driving the word line WL2 in FIG. [Figure 14] FIG. 12 is a diagram showing an example of driving the word line WL3 in FIG. [Figure 15] FIG. 12 is a diagram showing an example of driving the word line WL4 in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of an information processing device will be described with reference to the drawings. The following description will focus on the main components of the information processing device, but the information processing device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0010] 1 is a block diagram showing a schematic configuration of an information processing device 1 according to an embodiment. As shown in FIG. 1, the information processing device 1 according to an embodiment includes a storage unit 2 and a controller 3.

[0011] The storage unit 2 is, for example, a nonvolatile memory. The nonvolatile memory is, for example, a NAND flash memory. Note that any type of nonvolatile memory can be used as the storage unit 2, and therefore a cross-point memory or the like may be used. Examples of cross-point memories include a resistive random access memory (ReRAM) that uses a resistance change element in the memory cell, a magnetoresistive random access memory (MRAM) that uses a magnetoresistive element, and a phase change memory, and any of these can be applied to the storage unit 2 according to this embodiment. Alternatively, the storage unit 2 may be a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0012] The controller 3 controls writing and reading of data to and from the storage unit 2. The controller 3 also has the function of a clustering device 4. As will be described later, the clustering device 4 performs an analogy determination to determine whether a plurality of first data are similar to the second data in accordance with instructions from the host device 5. The controller 3 (clustering device 4) transmits the result of the analogy determination to the host device 5.

[0013] The host device 5 supplies the above-mentioned plurality of first data and second data to the controller 3 to instruct the controller 3 to make an analogy judgment, and receives the result of the analogy judgment by the controller 3. In FIG. 1, the host device 5 is provided outside the information processing device 1, but the host device 5 may also be provided inside the information processing device 1.

[0014] In this embodiment, both the first data and the second data are multidimensional data and can be represented as vectors. In this specification, the first data consisting of multidimensional data is sometimes referred to as a first vector having many elements, and the second data consisting of multidimensional data is sometimes referred to as a second vector having many elements. The number of elements in the first vector is equal to the number of elements in the second vector. The similarity between the first data and the second data can be determined by the dot product value of the first vector and the second vector. The larger the dot product value, the higher the similarity.

[0015] When searching for first data that has a high similarity to second data from among multiple first data, the information processing device 1 of this embodiment classifies the multiple first data into multiple clusters that group similar data together, determines the cluster that is most similar to the second data from among the multiple first data as the search cluster, determines the similarity between all of the first data and the second data in the search cluster, for example, using the dot product value described above, and searches for first data that is similar to the second data.

[0016] 2 is a functional block diagram of the controller 3 and the host device 5, and shows the block configuration of the clustering device 4. The clustering device 4 included in the controller 3 includes a cluster division unit 11, a center of gravity calculation unit 12, a first determination unit 13, and a selection unit 14. The host device 5 includes a second determination unit 15.

[0017] The cluster division unit 11 equally allocates some of the multiple first data K to two or more clusters while overlapping the first data K, and repeats this allocation to new two or more clusters until the number of first data K included in each allocated cluster becomes equal to or less than a predetermined limit. In this specification, the first data K may be referred to as key data or key vector data. A cluster is a collection of one or more key data, and each cluster includes multiple similar key data.

[0018] The cluster dividing unit 11 may equally divide the plurality of first data K into three or more clusters, but the following describes an example in which the cluster dividing unit 11 equally divides the plurality of first data K into two clusters while overlapping some of the first data K. Both of the two clusters have some of the first data K overlapping.

[0019] In this way, the cluster dividing unit 11 repeats the process of dividing all the first data K in one cluster into two clusters while allowing overlaps for each cluster, so that the number of first data K included in one cluster is ultimately equal to or less than a predetermined limit number. The predetermined limit number is a number according to the number of first wirings (e.g., bit lines), as will be described later, and more specifically, is the number of data equal to or less than the page size.

[0020] The centroid calculation unit 12 calculates the centroid value of each of the multiple clusters finally allocated by the cluster division unit 11. The centroid value is the average value of all the first data K in the corresponding cluster. More specifically, the average value of each bit of all the first data K is calculated. This is equivalent to calculating the average value for each element of all the first vectors.

[0021] The first determination unit 13 compares the centroid values ​​of each of the plurality of clusters with the second data Q, and determines the cluster having the centroid value most similar to the second data Q as the search cluster.

[0022] The selection unit 14 compares each of the multiple first data K included in the search cluster with the second data Q, and selects a predetermined number (one or more) of first data K that are similar to the second data Q. As will be described later, each first data K is identified by a label. The selection unit 14 selects the first data K and the corresponding label. The first data K selected by the selection unit 14 and the corresponding label are sent from the controller 3 to the host device 5.

[0023] The second determination unit 15 in the host device 5 determines a label similar to the second data Q from among the labels corresponding to the predetermined number of first data K selected by the selection unit .

[0024] Fig. 3 is a block diagram showing a specific configuration of the storage unit 2 of Fig. 1. As shown in Fig. 3, the storage unit 2 has a plurality of memory cells MC arranged in a first direction (hereinafter referred to as row direction) X and a second direction (hereinafter referred to as column direction) Y, a plurality of first wirings (hereinafter referred to as bit lines) BL1 to BLm each extending in the column direction Y and arranged at predetermined intervals in the row direction X, a plurality of second wirings (hereinafter referred to as word lines) WL1 to WLn each extending in the row direction X and arranged at predetermined intervals in the column direction Y, and a plurality of sense amplifiers SA1 to SAm connected to one end of each of the plurality of bit lines BL1 to BLm.

[0025] The storage unit 2 according to this embodiment performs a product-sum operation, which multiplies each bit (each dimension) of the first data K by the corresponding bit (each dimension) of the second data Q and adds them together. This product-sum operation is equivalent to calculating the inner product of each element of the first vector and the corresponding element of the second vector. The above-mentioned multiplication (calculation of the inner product) is performed in each memory cell MC, and the above-mentioned product-sum operation is performed on each bit line.

[0026] Each of the plurality of memory cells MC stores first data K (key data, first vector). As described above, the first data K is multidimensional data and has a plurality of elements. The storage unit 2 stores all elements of one first data K in a plurality of memory cells MC (framed by dashed lines in FIG. 3) arranged in a column direction Y. In the example of FIG. 3, m pieces of first data K arranged in a row direction X are stored in the plurality of memory cells MC.

[0027] The number of dimensions (number of elements of the second vector) n of the second data Q matches the number of dimensions (number of elements of the first vector) n of the first data K. In the example of Fig. 3, n word lines WL1 to WLn that transmit the second data Q are arranged in the column direction Y, and each word line WL1 to WLn is connected to a corresponding memory cell MC among the multiple memory cells MC arranged in the column direction Y.

[0028] Each bit of the first data K (each element of the first vector) is supplied to n memory cells MC connected to the corresponding bit line via the corresponding bit line. Thus, each dimension of the m pieces of first data K is stored in m×n memory cells MC via m bit lines BL1 to BLm.

[0029] The n memory cells MC arranged in the column direction Y are connected to a common bit line BL, and the m memory cells MC arranged in the row direction X are connected to a common word line WL.

[0030] A plurality of (m×n) memory cells MC perform parallel multiplication of each bit of the first data K (each element of the first vector) with a corresponding bit of the second data Q (corresponding element of the second vector) to indicate whether or not they match, and set a plurality of bit lines BL1 to BLm to a voltage corresponding to the sum (inner product value) of the multiplication results of each bit. The voltages of the plurality of bit lines BL1 to BLm are sensed by a plurality of sense amplifiers SA1 to SAm.

[0031] Each of m bit lines BL1 to BLm arranged in the row direction X is connected to n memory cells MC arranged in the column direction Y. Therefore, each bit line supplies a voltage corresponding to a signal obtained by wired-ORing the results of multiplication of the bits of the corresponding n memory cells MC to the sense amplifier SA. In this way, each bit line BL1 to BLm becomes a voltage corresponding to a signal obtained by wired-ORing the results of multiplication of the bits of the n memory cells MC arranged in the column direction Y, and these voltages are sensed by the sense amplifiers SA1 to SAm.

[0032] 3, m pieces of first data K are defined as K={(k11, k12, ... k1n), ..., (ki1, ki2, ... kin), ..., (km1, km2, ... kmn)}, and second data Q is defined as Q=(q1, ..., qi, ..., qn). In this case, bit line BL1 has a voltage corresponding to the inner product of k11×q1+k12×q2+ ...+k1n×qn. Similarly, bit lines BL2 to BLm have voltages corresponding to the inner product of each element of the corresponding first data and second data.

[0033] Alternatively, a plurality of word lines WL1 to WLn arranged in the column direction Y may be sequentially driven to sequentially transmit the multiplication results of the bits for each row over m bit lines BL1 to BLm. In this case, a holding circuit for temporarily holding the multiplication results of the bits may be provided between the plurality of memory cells MC and the corresponding bit lines.

[0034] 4 is a diagram illustrating the multiplication of bits and the sum-of-products operation of adding the results of the multiplication performed in the memory unit 2. FIG. 4 shows a plurality of memory cells MC1 to MCn (hereinafter, sometimes collectively referred to as memory cells MC) connected to one bit line. In FIG. 3, the direction in which each bit line extends is the vertical direction on the paper, but in FIG. 4, for convenience, the direction in which the bit line extends is the horizontal direction on the paper.

[0035] As shown in FIG. 3, n (n is an integer equal to or greater than 2) memory cells MC1 to MCn are connected to one bit line. Each of these memory cells MC calculates the similarity between the first data K and the second data Q, and draws a current corresponding to the similarity from the bit line to the memory cell MC. The higher the similarity, the more current is drawn from the bit line to the memory cell MC, and the more the voltage on the bit line drops. Thus, in the circuit of FIG. 4, a current corresponding to the similarity between the first data K and the second data Q flows through the bit line, changing the voltage on the bit line.

[0036] The sense amplifier SA senses the voltage of the bit line, and therefore the similarity between the first data K and the second data Q can be detected based on the voltage of the bit line.

[0037] 3 and 4 vary depending on the type of memory constituting the storage unit 2. For example, in the case of a NAND flash memory, each memory cell MC shown in FIGS. 3 and 4 is configured as a string in which multiple memory cell transistors are connected in series.

[0038] FIG. 5 is a circuit diagram showing an example of a memory unit 2 in which multiple strings SR1 to SRn are connected to one bit line. Each of the strings SR1 to SRn is composed of multiple memory cell transistors connected in series. The strings SR1 to SRn in FIG. 5 correspond to, for example, the multiple memory cells within one dashed line in FIG. 3. Hereinafter, the memory cell transistors will be simply referred to as transistors. A different word line is connected to each gate of the multiple transistors in the string SR. Note that in a typical memory cell array, multiple word lines WL1 to WLn are generally connected in common to the multiple strings SR1 to SRn. FIG. 5 shows an example in which word line WL1 is connected to the gate of transistor Q1 in string SR1, word line WLi is connected to the gate of transistor Q1 in string SRi, and word line WLn is connected to the gate of transistor Q1 in string SRn. In FIG. 5, the voltages of word lines WL1 to WLn connected to the gates of transistors Q1 in strings SR1 to SRn are all Vcgr. Vcgr is a voltage according to the value of each element of the second vector corresponding to the second data Q.

[0039] 5, the threshold voltages Vth(k1_s), . . . , Vth(ki_s), . . . Vth(kn_s) of the transistors Q1 in the strings SR1 to SRn are set by the values ​​of the elements of the first vector corresponding to the first data K.

[0040] In addition to the transistor Q1, multiple transistors Q2 are connected in series to each of the strings SR1 to SRn. The gates of these transistors Q2 are set to a predetermined fixed voltage Vread. The threshold voltages of the transistors Q2 are set to predetermined voltages Vth(k1_u1), Vth(k1_u2), ..., Vth(ki_u1), Vth(ki_u2), ..., Vth(kn_u1), Vth(kn_u2).

[0041] By applying a gate voltage Vread having a voltage level significantly higher than the threshold voltage of each of the transistors Q2 in the strings SR1 to SRn, each of the transistors Q2 can be turned on.

[0042] In this embodiment, of the multiple transistors Q1 and Q2 connected in series in each of the strings SR1 to SRn, the transistor Q2 is set to be always on. Also, the transistor Q1 of each string SR passes a current corresponding to the product of corresponding elements of the first data (first vector) K and the second data (second vector) Q from the bit line BL to the corresponding string SR.

[0043] Figure 6 is a diagram showing the relationship between the gate voltage and threshold voltage of transistors Q1 and Q2 in each string SR in Figure 5. As shown in Figure 6, in order from the largest voltage level, they are Vread, the threshold voltage VthB of transistor Q1 when first data K=0, the gate voltage VcgrH of transistor Q1 when second data Q=1, the threshold voltage VthA of transistor Q1 when first data K=1, and the gate voltage VcgrL of transistor Q1 when second data Q=0.

[0044] Therefore, for example, when the first data K=1 and the second data Q=1, a current flows through the transistor Q1, whereas when the first data K=0 and the second data Q=0, no current flows through the transistor Q1.

[0045] The sum of the currents flowing through the multiple strings SR1 to SRn is a current corresponding to the dot product value of the first vector K and the second vector Q, and this current flows through the bit line BL. Therefore, the current flowing through the bit line BL changes according to the dot product value of the first vector K and the second vector Q. The larger the dot product value, the larger the sum of the currents flowing through the multiple strings SR1 to SRn and the current flowing through the bit line BL become, and the larger the voltage level of the bit line BL drops.

[0046] The storage unit 2 in FIG. 5 can calculate the dot product of a first vector K corresponding to first data K and a second vector Q corresponding to second data Q. Each of the strings SR1 to SRn passes a current corresponding to the product of corresponding elements of the first vector K and the second vector Q. Therefore, the sum of the currents passing through each of the strings SR1 to SRn passes through the bit line, and the voltage of the bit line decreases according to this sum. The current passing through the bit line and the voltage of the bit line are values ​​corresponding to the dot product of the first vector K and the second vector Q.

[0047] Fig. 7 is a flowchart showing the processing operation of the information processing device 1 according to this embodiment. The processing of the flowchart in Fig. 7 is performed by the controller 3 using the storage unit 2 in response to instructions from the host device 5 in Fig. 1. In this way, the information processing device 1 according to this embodiment is characterized in that the analogy judgment of the above-mentioned multidimensional data is performed by a hardware circuit consisting of a CIM.

[0048] First, the host device 5 sends a plurality of first data K (key data) to the controller 3. The controller 3 stores the plurality of first data K from the host device 5 in the storage unit 2 (step S1).

[0049] Next, the cluster division unit 11 in the controller 3 performs clustering to divide the plurality of first data K evenly into two clusters while allowing some of the first data K to overlap, and stores the first data K and the corresponding labels for each cluster in the storage unit 2 (step S2). Dividing evenly means making the number of first data K included in each cluster equal. If the total number of first data K in each cluster after division exceeds a predetermined limit, the first data K in each cluster after division is divided evenly into two new clusters while allowing some of the first data K to overlap. This division process into two clusters is repeated until the total number of first data K in each cluster is finally equal to or less than the predetermined limit.

[0050] Next, the centroid calculation unit 12 in the controller 3 calculates the centroid value of each of the multiple clusters finally obtained in step S2. The centroid value is multidimensional data like the first data K, and is stored in the storage unit 2 (step S3). In the process of processing step S2, multiple clusters are generated hierarchically, and in step S3, the centroid values ​​of the multiple clusters in the lowest hierarchy are calculated. As described above, the centroid calculation unit 12 calculates the average value of each bit (each element) of each first data K included in each cluster as the centroid value.

[0051] Next, the first determination unit 13 and the storage unit 2 in the controller 3 compare the centroid values ​​of each cluster calculated in step S3 with the second data Q (query data) to determine a search cluster (step S4). The comparison process in step S4 may be performed by the storage unit 2. As shown in FIGS. 4 and 5, the storage unit 2 stores the centroid values ​​as key data in each string SR. The second data Q is input to each string SR via a word line. The current flowing through the bit line and the voltage on the bit line change depending on the similarity between the centroid value of each cluster and the second data Q. The first determination unit 13 determines the cluster having the centroid value with the highest similarity as the search cluster based on the bit line voltage detected by the sense amplifier SA.

[0052] Next, the selection unit 14 in the controller 3 compares each of the multiple first data K (key data) included in the search cluster with the second data Q (query data) and selects a predetermined number (one or more) of first data K that are similar to the second data Q (step S5). The process of step S5 can be performed by the storage unit 2. In this case, the selection unit 14 uses the multiple first data K included in the search cluster stored in the storage unit 2 and inputs the second data Q via the word line to detect the similarity based on the voltage of the bit line, as shown in FIGS. 4 and 5. Alternatively, the process of step S5 can be performed by the host device 5. In this case, the controller 3 reads the multiple first data K included in the search cluster from the storage unit 2 and sends them to the host device 5. The host device 5 performs an analogy judgment between the multiple first data K included in the search cluster and the second data Q and selects the predetermined number of first data K in descending order of similarity. When selecting the predetermined number of first data K, the selection unit 14 selects labels corresponding to the predetermined number of first data K.

[0053] Next, the second determination unit 15 in the host device 5 determines a label similar to the second data Q from among the labels corresponding to the predetermined number of first data K selected by the selection unit 14 by majority vote.

[0054] 8 is a diagram illustrating the processing of step S2 in FIG. 7. The cluster division unit 11 divides the vectors V1 and V2 into two clusters CL1 and CL2, for example, by NMF (Non-negative Matrix Factorization). NMF is a data conversion method using unsupervised learning. The cluster division unit 11 uses NMF to equally divide multiple elements present in the region between two vectors V1 and V2 into two clusters CL1 and CL2 while overlapping some elements. Cluster CL1 includes first data only in cluster CL1 and first data that overlaps with cluster CL2. Similarly, cluster CL2 includes first data only in cluster CL2 and first data that overlaps with cluster CL1.

[0055] If the number of first data items included in each of the two clusters CL1 and CL2 exceeds a predetermined limit, the cluster division unit 11 divides the cluster CL1 equally into two new clusters CL3 and CL4 while overlapping some of the multiple first data items included in cluster CL1, and similarly divides the cluster CL2 equally into two new clusters CL5 and CL6 while overlapping some of the multiple first data items included in cluster CL2. This type of clustering, in which the two divided clusters have some overlapping elements, is called soft clustering.

[0056] In this embodiment, when clustering a plurality of first data K, soft clustering is performed using, for example, NMF, in which the first data K are divided equally into two clusters while overlapping some of the first data K. If the number of first data K included in each cluster after division exceeds a predetermined limit, each cluster after division is further divided equally into two clusters while overlapping some of the first data K, as shown in Fig. 8. By repeating this type of clustering, it is possible to ultimately make the number of first data K included in each cluster after division equal to or less than the predetermined limit.

[0057] The predetermined limit number is a number according to the number of bit lines in the memory unit 2. In a more specific example, the predetermined limit number is the number of data items equal to or less than a page size determined according to the number of bit lines in the memory unit 2. The page size is a unit for writing to and reading from a plurality of memory cells MC in the memory unit 2. By setting the number of first data items K included in the final cluster to be equal to or less than the page size, analogy determination between the plurality of first data items K and second data items Q included in the final cluster can be performed in parallel, and the analogy determination can be performed efficiently in a short time.

[0058] To effectively utilize the storage unit 2, it is desirable that the clusters that are finally divided contain the number of first data K as close as possible to the page size.

[0059] The first determination unit 13 determines the cluster having the centroid value most similar to the second data Q as the search cluster from among a plurality of clusters (dashed frame in FIG. 8) in which the number of first data K is equal to or less than a predetermined limit number.

[0060] The method by which the cluster division unit 11 performs soft clustering is not necessarily limited to NMF, and soft clustering may be performed by any other method.

[0061] 9 is a diagram illustrating an example in which the cluster division unit 11 performs soft clustering using PCA (Principal Component Analysis). In PCA, principal component analysis is performed on all first data K, and the data is divided into two clusters CL1 and CL2 according to the magnitude (coefficient) of the first principal component V1. At this time, the two clusters CL1 and CL2 hold some of the first data K in duplicate. If the number of first data K included in each of the clusters CL1 and CL2 after division exceeds a predetermined limit, principal component analysis is performed on each of the clusters CL1 and CL2 after division, and two new clusters are allocated according to the coefficient of the first principal component, and this process is repeated until the number of first data K included in each cluster is equal to or less than the predetermined limit.

[0062] Using either the NMF in FIG. 8 or the PCA in FIG. 9, a portion of the first data K can be divided into two clusters with overlapping.

[0063] 3 to 5, an example has been described in which the inner product value of the first data K and the second data Q is calculated using a string SR that uses NAND memory cells MC, but the inner product value may also be calculated using a nonvolatile memory other than a NAND memory. Below, an example will be described in which the inner product value is calculated using a resistance change type memory (also called a cross-point type memory).

[0064] FIG. 10 is a perspective view schematically showing memory cells MC, bit lines BL, and word lines WL included in a memory cell array MCA in a cross-point memory.

[0065] 10, for example, a plurality of bit lines BL extend in the same direction at intervals, and above them, a plurality of word lines WL extend at intervals in a direction perpendicular to the direction in which the bit lines BL extend. A plurality of memory cells MC are arranged at the intersections of the plurality of bit lines BL and the plurality of word lines WL. This forms a cross-point memory cell array MCA in which the plurality of memory cells MC are arranged in a matrix in a plan view.

[0066] FIG. 10 shows an example in which bit lines BL and word lines WL are arranged in one layer each, with one layer of memory cells MC arranged between them, but this is not limiting. It is also possible to increase the number of layers in which memory cells MC are arranged, and correspondingly increase the number of layers of bit lines BL and / or word lines WL. For example, a plurality of bit lines BL1 may be provided above the plurality of word lines WL in FIG. 10, extending at intervals in a direction perpendicular to the direction in which the word lines WL extend, and a plurality of memory cells MC may be arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL above them. In this case, there are two layers of memory cells MC, and three layers of wiring layers (layers of bit lines BL and layer of word lines WL). It is also possible to interchange the bit lines BL and word lines WL.

[0067] 11 is a diagram schematically illustrating an example of a circuit configuration of the memory cell array MCA shown in FIG. 10. Each memory cell MC is connected between a corresponding word line WL and a corresponding bit line BL. The memory cell MC includes, for example, a resistance change element VR and a switch element SE. Note that the memory cell MC is not limited to a resistance change element.

[0068] The switch element SE functions as a rectifying element having a rectifying function, and may be a bidirectional rectifying element.

[0069] In the cross-point memory, the plurality of word lines WL1 to WLn that supply second data Q (query data) are driven one by one so that the voltage of the word line does not affect the other word lines.

[0070] The resistance change element VR can be in a low resistance state and a high resistance state. The resistance change element VR holds one bit of data by utilizing the difference between the low resistance state and the high resistance state. In the example of FIG. 11, four first data (key data) K=(K1, K2, K3, K4) are stored in each memory cell MC via bit lines BL1 to BL4, and a current corresponding to the result of a bit-by-bit comparison with second data (query data) Q=(q1, q2, q3, q4) supplied via word lines WL1 to WL4 is passed through the bit lines BL1 to BL4. Each key data K consists of four bits, and each bit is stored in four memory cells MC arranged in a column direction. In the example of Figure 11, the bits of key data K1 are (k11, k12, k13, k14) from the least significant side, the bits of key data K2 are (k21, k22, k23, k24) from the least significant side, the bits of key data K3 are (k31, k32, k33, k34) from the least significant side, and the bits of key data K4 are (k41, k42, k43, k44) from the least significant side.

[0071] Each memory cell MC has a low resistance when the corresponding bit of the key data is 1, and a high resistance when the corresponding bit is 0. The relationship between the value of the bit of the key data and the resistance state of the memory cell MC is arbitrary.

[0072] The word lines WL1 to WL4 are sequentially driven to Vhigh. If the query data corresponding to the word line driven to Vhigh is 1, the bit lines BL1 to BL4 will be at a voltage indicating the match detection result for each bit of the key data and query data. On the other hand, if the query data corresponding to the word line driven to Vhigh is 0, the bit lines BL1 to BL4 will be at a voltage that is the inverse of the match detection result for each bit of the key data and query data. Therefore, by sensing the voltage of the bit lines BL1 to BL4 and checking the query data of the word line driven to Vhigh, a similarity search can be performed between the first data K and the second data Q.

[0073] 12 to 15 are diagrams illustrating an example of calculating the similarity between a plurality of first data K (key data) and second data Q (query data) supplied via a word line using a cross-point memory.

[0074] FIG. 12 shows an example of driving the word line WL1. In this case, a high-level voltage Vhigh is applied to the word line WL1. Of the four memory cells MC connected to the word line WL1, a current flows through the memory cell MC whose resistance change element is in a low-resistance state, causing the corresponding bit line to go high. In the example of FIG. 12, the least significant bits of the first data K1 to K4 are (1, 0, 1, 1), respectively, so the logic of the bit lines BL0 to BL3 is (H, L, H, H). As such, in FIG. 12, an analogy judgment is performed between the least significant bits of the multiple first data K and the least significant bit of the second data Q, and the result of this analogy judgment is output to the bit lines BL0 to BL3. Among the bit lines BL0 to BL3, a bit line that goes high (H) indicates that the corresponding bits of the first data K and the second data Q match, and a bit line that goes low (L) indicates that the corresponding bits of the first data K and the second data Q do not match. In the example of FIG. 12, the least significant bit b0 of the first data K1, K3, and K4 matches the least significant bit b1 data q1 of the second data Q.

[0075] After the word line WL1 is driven, the word line WL2 is driven as shown in FIG. 13. In this case, a high-level voltage Vhigh is applied to the word line WL2. In the example of FIG. 13, the bits b1 of the first data K1 to K4 are (0, 1, 0, 0), respectively, so the logic of the bit lines BL0 to BL3 is (L, H, L, L). Therefore, the bit b1 of the first data K2 matches the bit b1 of the second data Q, and the other bits b1 of the first data K1, K3, and K4 do not match the bit b1 of the second data Q.

[0076] After the word line WL2 is driven, the word line WL3 is driven as shown in FIG. 14. In this case, a high-level voltage Vhigh is applied to the word line WL3. In the example of FIG. 14, bit b2 of the first data K1 to K4 is (0, 1, 1, 1), respectively, so the logic of the bit lines BL0 to BL3 is (L, H, H, H). On the other hand, bit b2 of the second data Q is 0, so the inverted logic of the bit lines BL0 to BL3 (H, L, L, L) represents the result of the analogy judgment between the bits b2 of the first data K and the second data Q. In this way, in the example of FIG. 14, bit b2 of the first data K1 matches bit b2 of the second data Q, and the other bits b2 of the first data K2 to K4 do not match bit b2 of the second data Q.

[0077] After the word line WL3 is driven, the word line WL4 is driven as shown in FIG. 15. In this case, a high-level voltage Vhigh is applied to the word line WL4. In the example of FIG. 15, bit b1 of the first data K1 to K4 is (1, 0, 0, 1), respectively, so the logic of the bit lines BL0 to BL3 is (H, L, L, H). Therefore, bit b3 of the first data K1 and K4 matches bit b3 of the second data Q, and the other bits b3 of the first data K2 and K3 do not match bit b3 of the second data Q.

[0078] 12 to 15, the first data K1 to K4 and the second data Q are compared bit by bit, and the similarity is determined based on the number of matching bits. For example, the first data K1 matches the second data Q in three out of four bits, so the similarity is 3. The first data K2 and K3 both have a similarity of 1, and the first data K4 has a similarity of 2. Therefore, in the examples of FIGS. 12 to 15, the results show that the first data K1 is most similar to the second data Q.

[0079] The cross-point memories shown in FIGS. 10 to 15 can be used for the processing of at least one of the first determination unit 13 and the selection unit 14 in FIGS.

[0080] As described above, in this embodiment, the process of dividing multidimensional first data K into two clusters while overlapping some of the first data K is repeated until one cluster finally contains a predetermined number of first data K or less. In this state, the centroid values ​​of the multiple clusters are compared with the second data Q, and the cluster having the centroid value most similar to the second data Q is determined as the search cluster. Then, all of the first data K in the search cluster are compared with the second data Q, a predetermined number of first data K with high similarity are selected, and from among them, the first data K similar to the second data Q is determined. This allows for rapid and accurate similarity determination between multiple first data K and the second data Q.

[0081] In this embodiment, the comparison of the center of gravity values ​​of the plurality of clusters with the second data Q, and the analogy determination between all the first data K in the search cluster and the second data Q can be performed by the CIM using the storage unit 2. In particular, by making the number of all the first data K in the search cluster equal to or less than the page size of the storage unit 2, the voltages of the plurality of bit lines BL1 to BLm can be varied according to the similarity between the plurality of first data K and the second data Q. Therefore, by sensing the voltages of the plurality of bit lines BL1 to BLm with the sense amplifier SA, the analogy determination between the plurality of first data K and the second data Q can be performed quickly.

[0082] [Note] [Item 1] a cluster dividing unit that divides the plurality of first data items into two or more clusters while overlapping some of the first data items, and repeats the division into two or more new clusters until the number of the first data items included in each of the divided clusters becomes equal to or less than a predetermined limit number; a centroid calculation unit that calculates a centroid value of each of the plurality of clusters finally allocated by the cluster division unit; a first determination unit that compares the centroids of the plurality of clusters with second data and determines a cluster having the centroid value that is most similar to the second data as a search cluster; a selection unit that compares each of the plurality of first data included in the search cluster with the second data, and selects one or more predetermined number of the first data similar to the second data, Information processing device. [Item 2] a second determination unit that determines first data similar to the second data from the predetermined number of first data selected by the selection unit; Item 1. An information processing device according to item 1. [Item 3] a plurality of labels are provided to identify each of the plurality of first data; the second determination unit determines a label similar to the second data based on a majority vote of the number of labels determined to be similar to the second data among the predetermined number of the first data. Item 2. An information processing device according to item 2. [Item 4] a storage unit that stores the plurality of first data and the plurality of labels in association with each other; performing a comparison process between the predetermined number of first data and the second data inside the storage unit; Item 3. An information processing device according to item 3. [Item 5] The storage unit a plurality of memory cells for storing respective bits of the first data; a plurality of first wirings connected to the plurality of memory cells and transmitting the plurality of first data included in the search cluster; a plurality of second wirings connected to the plurality of memory cells and transmitting the second data consisting of a plurality of bits; the plurality of first wirings are at a voltage level according to the degree of similarity between each of the plurality of first data and the second data; Item 5. An information processing device according to item 4. [Item 6] the predetermined limit number is a number corresponding to the number of the plurality of first wirings; Item 5. An information processing device according to item 5. [Item 7] the storage unit writes and reads data to and from the memory cells using a page size determined according to the number of the first wirings and the number of the second wirings; the predetermined limit number is the number of data items equal to or smaller than the page size; Item 7. The information processing device according to item 5 or 6. [Item 8] the plurality of first wirings are set to a voltage according to a similarity between each bit in each of the plurality of first data and a corresponding bit in the second data; 8. The information processing device according to any one of items 5 to 7. [Item 9] the selection unit selects the predetermined number of the first data based on voltages of the plurality of first wirings. Item 9. An information processing device according to item 8. [Item 10] a controller that controls storage of the plurality of first data in the storage unit; the controller performs the processes of the cluster division unit, the centroid calculation unit, the first determination unit, the selection unit, and the second determination unit. 10. The information processing device according to any one of items 5 to 9. [Item 11] a plurality of memory strings connected to the plurality of first wirings and the plurality of second wirings, each of which has two or more of the memory cells connected in series; the plurality of memory strings pass a current according to a degree of similarity between each bit in each of the plurality of first data and a corresponding bit in the second data; 11. The information processing device according to any one of items 5 to 10. [Item 12] The memory strings are connected to each of the plurality of first wirings in a number equal to the number of bits of the plurality of first data, and each memory string passes a current according to a comparison result between a corresponding bit of the first data and a corresponding bit of the second data. Item 12. The information processing device according to item 11. [Item 13] the storage unit compares each of the plurality of first data with the second data in parallel; Item 13. The information processing device according to item 11 or 12. [Item 14] The memory cells are NAND flash memory cells. 14. The information processing device according to any one of items 11 to 13. [Item 15] Each of the plurality of memory cells stores a corresponding bit of the first data by a change in resistance value. 11. The information processing device according to any one of items 5 to 10. [Item 16] By driving each of the plurality of second wirings at a time staggered in accordance with the second data, a current corresponding to an inner product value of each bit of each of the plurality of first data and a corresponding bit of the second data flows through the plurality of first wirings. Item 16. An information processing device according to item 15. [Item 17] The storage unit is a cross-point memory. Item 17. The information processing device according to item 15 or 16. [Item 18] the cluster division unit repeats a process of dividing the plurality of first data into two clusters by soft clustering using NMF (Non-negative Matrix Factorization); 18. The information processing device according to any one of items 1 to 17. [Item 19] the cluster division unit generates one cluster using PCA (Principal Component Analysis) and repeats a process of dividing the plurality of first data into two clusters; 18. The information processing device according to any one of items 1 to 17. [Item 20] A host device that performs the processing of the second determination unit is provided. Item 18. An information processing device according to any one of items 2 to 17. [Item 21] The host device performs the processing of the selection unit. Item 21. An information processing device according to item 20.

[0083] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0084] REFERENCE SIGNS LIST 1 information processing device, 2 storage unit, 3 controller, 4 clustering device, 5 host device, 11 cluster division unit, 12 centroid calculation unit, 13 first determination unit, 14 selection unit, 15 second determination unit

Claims

1. a cluster dividing unit that divides the plurality of first data items into two or more clusters while overlapping some of the first data items, and repeats the division into two or more new clusters until the number of the first data items included in each of the divided clusters becomes equal to or less than a predetermined limit number; a centroid calculation unit that calculates a centroid value of each of the plurality of clusters finally allocated by the cluster division unit; a first determination unit that compares the centroids of the plurality of clusters with second data and determines a cluster having the centroid value that is most similar to the second data as a search cluster; a selection unit that compares each of the plurality of first data included in the search cluster with the second data, and selects one or more predetermined number of the first data similar to the second data, Information processing device.

2. a second determination unit that determines first data similar to the second data from the predetermined number of first data selected by the selection unit; The information processing device according to claim 1 .

3. a plurality of labels are provided to identify the plurality of first data, the second determination unit determines a label similar to the second data based on a majority vote of the number of labels determined to be similar to the second data among the predetermined number of the first data. The information processing device according to claim 2 .

4. a storage unit that stores the plurality of first data and the plurality of labels in association with each other; performing a comparison process between the predetermined number of first data and the second data within the storage unit; The information processing device according to claim 3 .

5. The storage unit a plurality of memory cells for storing respective bits of the first data; a plurality of first wirings connected to the plurality of memory cells and transmitting the plurality of first data included in the search cluster; a plurality of second wirings connected to the plurality of memory cells and transmitting the second data consisting of a plurality of bits; the plurality of first wirings are at a voltage level according to the degree of similarity between each of the plurality of first data and the second data; The information processing device according to claim 4 .

6. the predetermined limit number is a number corresponding to the number of the plurality of first wirings; The information processing device according to claim 5 .

7. the storage unit writes and reads data to and from the memory cells using a page size determined according to the number of the first wirings and the number of the second wirings; the predetermined limit number is the number of data items equal to or smaller than the page size; The information processing device according to claim 5 .

8. the plurality of first wirings are set to voltages according to the similarity between each bit in each of the plurality of first data and a corresponding bit in the second data; The information processing device according to claim 5 .

9. the selection unit selects the predetermined number of the first data based on voltages of the plurality of first wirings. The information processing device according to claim 8 .

10. a controller that controls storage of the plurality of first data in the storage unit; the controller performs the processes of the cluster division unit, the centroid calculation unit, the first determination unit, the selection unit, and the second determination unit. The information processing device according to claim 5 .

11. a plurality of memory strings connected to the plurality of first wirings and the plurality of second wirings, each of which has two or more of the memory cells connected in series; the plurality of memory strings pass a current according to a degree of similarity between each bit in each of the plurality of first data and a corresponding bit in the second data; The information processing device according to claim 5 .

12. the memory strings are connected to each of the plurality of first wirings in a number equal to the number of bits of the plurality of first data, and each memory string passes a current according to a comparison result between a corresponding bit of the first data and a corresponding bit of the second data; The information processing device according to claim 11.

13. the storage unit compares each of the plurality of first data with the second data in parallel; The information processing device according to claim 11.

14. The memory cells are NAND flash memory cells. The information processing device according to claim 11.

15. Each of the plurality of memory cells stores a corresponding bit of the first data by a change in resistance value. The information processing device according to claim 5 .

16. By driving each of the plurality of second wirings at a time staggered in accordance with the second data, a current corresponding to an inner product value of each bit of each of the plurality of first data and a corresponding bit of the second data flows through the plurality of first wirings. The information processing device according to claim 15.

17. The storage unit is a cross-point memory. The information processing device according to claim 15.

18. the cluster division unit repeats a process of dividing the plurality of first data into two clusters by soft clustering using NMF (Non-negative Matrix Factorization). The information processing device according to claim 1 .

19. the cluster division unit generates one cluster using PCA (Principal Component Analysis), and repeats a process of allocating the plurality of first data to two clusters; The information processing device according to claim 1 .

20. a host device that performs the processing of the second determination unit; The information processing device according to claim 2 .

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