Semiconductor device

Abstract

To provide a programmable logic device (PLD) having a less number of switches and high reliability.SOLUTION: A PLD includes: first to third columns each having a plurality of logic elements (LE); a plurality of first to third wiring lines to which a signal output from LE of the first to third columns are respectively given; a plurality of fourth wiring lines to which a signal inputted to LE on the second column are respectively given; a plurality of groups each of which has at least a first switch and a second switch for selecting a conduction state or a non-conduction state according to a potential of a node to which a signal is given through the first switch; a fifth wiring line to which a predetermined potential is given; and a third switch for controlling electrical connection between the plurality of fourth wiring lines and the fifth wiring line. The plurality of first to third wiring lines are respectively provided between the first column and the second column or between the second column and the third column, and in one group of the plurality of groups selected according to the signal, and when the second switch becomes a conduction state, one of the plurality of first to third wiring lines is connected to one of the plurality of fourth wiring lines.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, relating to the manufacture or composition of matter, especially The present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, and a driving method thereof. In particular, one aspect of the present invention relates to a method for manufacturing the same by changing the hardware configuration. A programmable logic device that can be changed and the programmable logic device The present invention relates to a semiconductor device using a vice. [Background technology]

[0002] Programmable Logic Device (PLD) A logic circuit is composed of logic elements (basic blocks) of an appropriate size. The functions of each logic element and the connection structure between the logic elements are verified after manufacturing. Specifically, the PLD can be configured to change the logic elements. The logic elements have interconnect resources for controlling connections between the logic elements, and registers. The above registers are logic elements that are configured by the functions of each logic element and the wiring resources. Data for defining the connection structure between the network elements (configuration data) is stored.

[0003] The registers for storing configuration data are The storage of configuration data in the configuration memory is called The storage of data is called a configuration. The new storage of configuration data is called reconfiguration. Be found out.

[0004] By the way, there is a technique called dynamic reconfiguration that PLDs that allow the reconfiguration of logic circuits are said to be more area efficient than regular PLDs. The multi-context approach has the advantage that it can be applied to logic elements or routing resources. The configuration memory is then written to the corresponding memory element. This is a method to realize dynamic reconfiguration by storing configuration data. The two-context method transfers configuration data from memory elements to logic elements in order. to the configuration memory corresponding to the block element or routing resource. Compared to the configuration information distribution method that realizes dynamic reconfiguration by can be done.

[0005] The following Patent Document 1 describes a DRAM (Dynamic Random Access Memory) The configuration data sent from the memory is stored in the SRAM (Static RAM). Configuration memory consisting of a A programmable LSI that can be reconfigured in a short time by storing the data in memory. It describes: [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 10-285014 Summary of the Invention [Problem to be solved by the invention]

[0007] By the way, the PLD using the multi-context method mentioned above has a memory element as well as a context element. Since it is necessary to provide a configuration memory, dynamic reconfiguration such as the configuration information delivery method is not possible. Compared to other methods of achieving this, the memory elements and configuration memory The advantage of dynamic reconfiguration is that it occupies a large area in the PLD of memory devices such as In particular, SRAM has a large number of elements per memory cell, so It is difficult to keep the area of ​​the device small. Also, the number of elements per memory cell is small. Since the amount of data is smaller than that of SRAM, it is advantageous for keeping the area of ​​the memory device small. It is difficult to reduce power consumption because of the need for a filter.

[0008] In addition, increasing the degree of freedom in designing programmable logic devices reduces wiring resources. The number of switches included in the routing resource tends to increase. The selection of the non-conducting state (switching) is determined by the configuration data. Therefore, when the number of switches increases, the circuit scale of the programmable logic device increases. Therefore, the capacity of the configuration data corresponding to one circuit configuration becomes large. This reduces the time required to transfer configuration data to the configuration memory. In addition, as the number of switches increases, memory elements with large storage capacities or Configuration memory is required, making it difficult to keep the memory area small. In addition, as the number of switches increases, the number of As a result, signal delays through the switch become significant, and the high performance of programmable logic devices Rapid movement is hindered.

[0009] In addition, various wirings connected to the wiring resource switches are After powering off the device, its potential may be in an undefined state. Depending on the configuration of the storage elements used in the application memory, the switches included in the wiring resources may The configuration data that determines the switching of the programmable logic devices For example, in the case of the processor described in Patent Document 1, the data may be lost when the power to the device is turned off. In programmable LSIs, the configuration memory is made up of SRAM. Therefore, when the programmable logic device is powered down, the configuration data is lost. If the potential of the wiring becomes unstable, the configuration data will be lost. If the communication data is lost, the wiring that is electrically isolated during normal operation After powering on the programmable logic device, the switch is turned on. In this case, if the potentials differ between the above wirings, a large amount of current flowing through the programmable logic device may cause damage to the programmable logic device. There is.

[0010] In light of the above-mentioned technical background, one aspect of the present invention is to provide a logic circuit that can be used in a variety of applications while increasing the degree of freedom in design. A programmable logic circuit that can reduce the number of switches that control the connections between network elements. Another object of the present invention is to provide a highly reliable logic device. One of the objectives is to provide a programmable logic device that can

[0011] Furthermore, the present invention provides a programmable logic device that can operate at high speed or One of the objects of the present invention is to provide a semiconductor device that can achieve high reliability.

[0012] In addition, as the circuit scale of programmable logic devices increases, larger memory capacities become possible. This requires a configuration memory with a programmable logic device. It becomes difficult to keep the area of ​​the nozzle small.

[0013] Therefore, one aspect of the present invention is to keep the layout area small even if the circuit scale increases. One of the goals is to provide a programmable logic device that can

[0014] Furthermore, one embodiment of the present invention is a programmable logic circuit that can reduce the area of ​​a memory device. Another object of the present invention is to provide a logic device. It is a programmable device that can be configured at high speed and has a small memory area. Another object of the present invention is to provide a logic device. Configuration can be performed quickly, the area of ​​the storage device can be kept small, and high-speed operation can be achieved. One of the objectives of the present invention is to provide a programmable logic device that can realize

[0015] Furthermore, one embodiment of the present invention is a method for miniaturizing a semiconductor device by using the programmable logic device. Another object of the present invention is to provide a semiconductor device that can achieve high performance.

[0016] Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like. The description of these problems does not preclude the existence of other problems. It is not necessary to solve all of these problems. It is obvious from the description, drawings, claims, etc. It is possible to extract other issues from the description of the claims, etc. [Means for solving the problem]

[0017] In the first aspect of the present invention, a switch circuit included in a wiring resource is configured to maintain its conductive state. Specifically, the switch circuit is configured to have a function as a memory device. a first transistor acting as a first switch, which controls the electrical connection of the The amount of charge determined by the configuration data is transferred to the gate of the first transistor. a second transistor acting as a second switch for supplying, holding, and discharging the Then, according to the configuration data, the plurality of sets are When the first transistor in one of the sets is turned on, the plurality of wirings and logic A connection structure between the input terminals of the elements is determined via the switch circuits.

[0018] A semiconductor film with a wider band gap than silicon and a lower intrinsic carrier density than silicon In addition, transistors with a channel formation region are typically made of semiconductors such as silicon or germanium. The off-state current can be made extremely small compared to a transistor having a channel formation region in a conductor. It has a wider band gap than silicon and a higher intrinsic carrier density than silicon. Examples of semiconductors that can be made lower include silicon, which has a band gap twice as large as that of silicon. Examples of suitable materials include oxide semiconductors, silicon carbide, and gallium nitride.

[0019] The second transistor prevents the charge held in the gate of the first transistor from leaking. To prevent this, it is desirable that the off-state current is extremely small. The semiconductor film has a wider band gap than silicon and a lower intrinsic carrier density than silicon. A transistor having a channel forming region is suitable for use as the second transistor. .

[0020] In the switch circuit having the above configuration, the wiring or The conduction state of the first transistor that controls the electrical connection between the terminals is determined, and the off-state The second transistor, which has a significantly smaller current, maintains the conductive state. In a programmable logic device according to one aspect of the present invention, a switch circuit is configured It has both the function of a positioning memory and the function of a memory element. In addition, the number of elements in each set is smaller than that of SRAM, so the configuration memory and memory Compared to conventional programmable logic devices that have both memory elements and This allows the area of ​​the storage device required to store configuration data to be kept small. Cut.

[0021] The off-state current of the second transistor is a transistor having a channel forming region in a silicon film. Since it is smaller than a DRAM, the data retention time in the switch circuit is longer than that of a DRAM. Therefore, the frequency of data rewriting can be reduced, which reduces data loss. Power consumption can be kept low.

[0022] Furthermore, the programmable logic device according to the first aspect of the present invention includes a plurality of first logic a column having a plurality of second logic elements; a column having a plurality of third logic elements; and a column having logic elements. The programmable logic device includes a plurality of first logic elements each having an output. A plurality of first wirings and a plurality of second logic elements are electrically connected to the terminals. a plurality of second wirings electrically connected to an output terminal having the second wiring and a plurality of third logic elements; and a plurality of third wirings electrically connected to the output terminals of the respective inputs. The first wiring and the second wiring are connected to a plurality of first logic elements and a plurality of second logic elements. The third wiring is provided between the plurality of first logic elements and the plurality of second logic elements. The logic elements are arranged between the plurality of second logic elements and the plurality of third logic elements. It is provided between the lock elements.

[0023] In addition, in a first aspect of the present invention, a first wiring, a second wiring, and a third wiring, and the plurality of second wirings The electrical connections of the input terminals of the logic elements are made by a plurality of the switch circuits. Specifically, in each switch circuit, the configuration The first transistor in one of the plurality of sets is turned on in accordance with the scan data. , the first wiring, the second wiring, and the third wiring, and the plurality of second logic elements An electrical connection structure is defined between the input terminals having the same.

[0024] In the first aspect of the present invention, with the above configuration, one second logic element and one second logic The electrical connections of the clock elements can be controlled by a single switch circuit. The electrical connection between one first logic element and one second logic element is established by one switch. The second logic element and the third logic element can be controlled by a switch circuit. The electrical connections of the logic elements can be controlled by a single switch circuit. Therefore, in one aspect of the present invention, the degree of freedom in designing a programmable logic device is increased. This allows the number of switch circuits included in the wiring resources to be reduced while increasing the bandwidth.

[0025] In a second aspect of the present invention, a switch circuit included in the wiring resource includes a first switch and an upper switch. A node to which a signal including configuration data is given via the first switch and a second switch that controls the electrical connection between the wirings according to the potential. Then, according to the configuration data, When the second switch is in a conductive state in one of the sets, the plurality of logic elements One of the multiple wirings connected to the output terminals of each logic element and the input terminal of one logic element. A connection structure is defined with one of the wires electrically connected to the terminal via a switch circuit.

[0026] Furthermore, the programmable logic device according to the second aspect of the present invention includes a plurality of first logic a column having a plurality of second logic elements; a column having a plurality of third logic elements; and a column having logic elements. The plurality of wirings electrically connected to the output terminals of the elements are referred to as first wirings. a plurality of wirings electrically connected to output terminals of the plurality of second logic elements, are used as second wirings, and are electrically connected to the output terminals of the plurality of third logic elements. In one aspect of the present invention, when the plurality of connected wirings are referred to as third wirings, the plurality of first wirings and the plurality of The second wiring is connected to a column having a plurality of first logic elements and a column having a plurality of second logic elements. The third wirings are provided between the columns having the first logic elements. a column having a plurality of first logic elements and a column having a plurality of second logic elements; A column having a plurality of third logic elements and a column having a plurality of second logic elements. It is assumed that

[0027] and a second logic element connected to the input terminals of the second logic elements. In one embodiment of the present invention, when the plurality of wirings are referred to as fourth wirings, the plurality of first wirings, the plurality of second wirings, , and the electrical connection between the plurality of third wirings and the plurality of fourth wirings is made by the plurality of switch circuits. Specifically, each switch is controlled according to the configuration data. When the second switch in one of the plurality of sets of circuits is turned on, any one of the wiring, the plurality of second wirings, and the plurality of third wirings, and any one of the plurality of fourth wirings An electrical connection structure with one of the electrodes is defined.

[0028] In a second aspect of the present invention, with the above configuration, one second logic element and another first logic element are connected to each other. The electrical connection between two logic elements can be controlled by one switch circuit. In addition, the electrical connection between one first logic element and one second logic element is The first logic element and the second logic element can be controlled by a single switch circuit. The electrical connection of the third logic element can be controlled by a single switch circuit. Therefore, one aspect of the present invention is to provide a method for automatically designing programmable logic devices. This makes it possible to reduce the number of switch circuits included in the wiring resources while increasing the degree of flexibility.

[0029] Furthermore, the programmable logic device according to the second aspect of the present invention includes first to third logic circuits. a wiring electrically connected to an input terminal of one of the logic elements; A switch is provided to control the electrical connection with the wiring to which a potential is applied. In one aspect, the above configuration allows the potential of the wiring electrically connected to the input terminal to be set to a predetermined value. Therefore, the programmable logic device After the power supply is turned off, the potential of the wiring electrically connected to the input terminal becomes unstable. This can also result in the loss of configuration data, which can lead to power-on issues. Then, the wiring electrically connected to the input terminal and a plurality of wirings electrically connected to the output terminal are connected to each other. Even if the wires are in a conductive state, the current flowing between the wires is transmitted from the input terminal to the logic element. This prevents the current from flowing into the programmable logic device. This prevents damage from occurring. Immediately after power is applied, the input terminals of the logic element are at high and low levels. The intermediate potential may be applied to the input terminal of the logic element. When this occurs, a shoot-through current tends to occur in the CMOS circuitry of the logic element. However, in one aspect of the present invention, the above configuration prevents the input terminal from being interrupted after the power is turned on. Since it is possible to prevent the potential from becoming equal to the potential of the first electrode, it is possible to prevent the occurrence of the above-mentioned through current.

[0030] In addition to the switch for initialization, the programmer according to the second aspect of the present invention may also include a In a power logic device, the potential of the wiring electrically connected to the input terminal is changed from high level to low level. A latch having a function of keeping the signal at either a low level or a low level may be provided. In one aspect, the above configuration allows the potential of the input terminal to be changed from a high level to a low level after the power is turned on. This prevents the occurrence of the above-mentioned through current. can.

[0031] In addition, in a third aspect of the present invention, a configuration included in a logic element The memory receives configuration data through the first switch. a first wiring to which a first potential is applied in accordance with a potential of a first node to which a first signal is applied; a second switch for controlling an electrical connection with the second wiring; a third switch; a second node to which a second signal having an inverted polarity relative to the first signal is applied via a switch; a third wiring to which a second potential lower than the first potential is applied in accordance with the potential of the second wiring; The fourth switch controls the electrical connection with the wire, and the second switch controls the output of the potential of the second wire to the fourth wire. The fifth switch controls the first and second switches. The logical operations performed by the logic elements are defined according to the data.

[0032] In the third aspect of the present invention, the above-mentioned configuration allows the The first or second potential can be applied to the fourth wiring. Before reading the configuration data from the configuration memory, the fourth line is precharged. Therefore, the configuration data can be read accurately without having to Therefore, a circuit for precharging is provided in the drive circuit of the configuration memory. This eliminates the need for a programmable logic device, thereby reducing the area of ​​the programmable logic device.

[0033] In a fourth aspect of the present invention, the above-mentioned configuration memory is A plurality of logic elements each having a plurality of logic elements are arranged in a row, The configuration memories included in each are arranged in a matrix. Furthermore, in the fourth aspect of the present invention, a plurality of switch circuits included in the wiring resource are also They are arranged in rows.

[0034] In the third embodiment, the configuration memory is configured with a first switch and a second switch. The part consisting of the third switch and the fourth switch is the second mode switch. The part consisting of the first switch and the second switch in the switch circuit and the connection of each switch Therefore, in the fourth aspect of the present invention, the configuration memory By arranging the memory and the switch circuit in a matrix, the operation of the configuration memory and Therefore, it is possible to control the operation of the switch circuit with the same drive circuit. When the driver circuit for the switch circuit and the driver circuit for the configuration memory are provided separately In comparison with the above, the area of ​​the programmable logic device can be reduced. [Effects of the Invention]

[0035] According to one embodiment of the present invention, a programmable logic device capable of reducing the area of ​​a memory device can be provided. Furthermore, according to one embodiment of the present invention, a logic circuit can be reconfigured at high speed. This allows the area of ​​the memory device to be kept small. Furthermore, according to one embodiment of the present invention, a logic circuit can be reconfigured at high speed. This allows the area of ​​the memory device to be kept small and allows high-speed operation. In addition, in one aspect of the present invention, a programmable logic device can be provided. By using a logic device, miniaturization and high functionality can be achieved. A semiconductor device can be provided.

[0036] According to one aspect of the present invention, it is possible to control connections between logic elements while increasing the degree of freedom in design. It is possible to provide a programmable logic device that can reduce the number of switches required. Furthermore, one aspect of the present invention provides a highly reliable programmable logic device. Furthermore, one aspect of the present invention makes it possible to achieve high-speed operation or high reliability. It is possible to provide a semiconductor device.

[0037] Furthermore, according to one embodiment of the present invention, even if the circuit scale increases, the layout area can be kept small. In addition, according to one aspect of the present invention, a programmable logic device can be provided. This makes it possible to provide a miniaturized semiconductor device. [Brief explanation of the drawings]

[0038] [Figure 1] FIG. 2 is a diagram showing the configuration of a PLD and a switch circuit. [Figure 2] FIG. 2 is a diagram showing the configuration of a switch circuit. [Figure 3] FIG. 2 is a diagram showing the configuration of a switch circuit. [Figure 4] FIG. 2 is a diagram showing the configuration of a switch circuit. [Figure 5] Timing chart. [Figure 6]FIG. 2 is a diagram showing the configuration of a switch circuit. [Figure 7] Timing chart. [Figure 8] FIG. 2 is a diagram showing the configuration of a switch circuit. [Figure 9] FIG. 2 is a diagram showing the configuration of a switch circuit. [Figure 10] FIG. 2 is a diagram showing the configuration of a switch circuit. [Figure 11] Timing chart. [Figure 12] FIG. 2 is a diagram showing the configuration of a switch circuit. [Figure 13] FIG. 1 is a diagram showing the configuration of a cell. [Figure 14] FIG. 2 is a diagram showing the configuration of a latch. [Figure 15] FIG. 1 is a diagram showing the configuration of a PLD. [Figure 16] FIG. 2 is a diagram showing the configuration of a logic element. [Figure 17] Top view of the PLD. [Figure 18] FIG. 2 is a diagram showing the configuration of an LUT. [Figure 19] Cross section of the cell. [Figure 20] FIG. 1 is a cross-sectional view of a transistor. [Figure 21] 1A and 1B illustrate a stacked structure of a transistor. [Figure 22] 1A and 1B illustrate a stacked structure of a transistor. [Figure 23] 1A and 1B illustrate a stacked structure of a transistor. [Figure 24] Schematic diagram of the configuration memory. [Figure 25] FIG. 2 is a diagram showing an example of the configuration of a logic element. [Figure 26] A diagram showing an example of an IO configuration. [Figure 27] Circuit diagram of a tristate buffer. [Figure 28] PLD mask drawing. [Figure 29] FIG. 1 is a diagram showing an example of the configuration of a PLD. [Figure 30] Cell circuit diagram and timing chart. [Figure 31]FIG. 10 is a diagram showing the relationship between the overdrive voltage and the delay time. [Figure 32] Micrograph of PLD. [Figure 33] FIG. 1 is a graph showing changes in oscillation frequency over time in a ring oscillator. [Figure 34] Electronic equipment illustration. DETAILED DESCRIPTION OF THE INVENTION

[0039] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and the embodiments and aspects thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0040] The programmable logic device of the present invention may be a microprocessor, an image processing circuit, or the like. , controllers for semiconductor display devices, DSP (Digital Signal Processing) Various semiconductor integrated circuits using semiconductor elements, such as semiconductor devices, microcontrollers, etc. The semiconductor device of the present invention includes an RF tag using the semiconductor integrated circuit. This category includes various devices such as semiconductor display devices. , a light-emitting device in which each pixel is provided with a light-emitting element, such as an organic light-emitting diode (OLED), an electronic page Par, DMD(Digital Micromirror Device), PDP(P lasma Display Panel), FED(Field Emission Display) and other semiconductor display devices having semiconductor elements in their drive circuits, It falls into that category.

[0041] <PLD configuration example> In a PLD according to one aspect of the present invention, a column having a plurality of LEs (logic elements) is Between each row, a plurality of wirings and a plurality of switch circuits are arranged. 1(A) illustrates a portion of a PLD 100 according to one embodiment of the present invention.

[0042] In FIG. 1A, a first column 102-1 having a plurality of LEs 101 and a second column 102-2 having a plurality of LEs 101 are shown. A second column 102-2 having a plurality of LEs 101 and a third column 102-3 having a plurality of LEs 101 are arranged in a PL In FIG. 1A, from the left side of the drawing, the first column 1 When the first column 102-1, the second column 102-2, and the third column 102-3 are arranged in parallel, is shown as an example.

[0043] In addition, in FIG. 1A, a plurality of wirings 103, a plurality of wirings 104, and a plurality of wirings 105 are , a plurality of wirings 106, a plurality of wirings 107, a plurality of wirings 108, and a plurality of wirings 109. is provided in the PLD100.

[0044] The first output terminals of the LEs 101 in the first column 102-1 are connected to a plurality of wirings 103. Each of the LEs 101 included in the first column 102-1 is connected to one of the LEs 101. The second output terminals are connected to any one of the plurality of wirings 104.

[0045] The first output terminal of each LE 101 in the second column 102-2 is connected to one of the plurality of wirings 106. The second column 102-2 has each LE 101 connected to one of the LEs 101. The second output terminals are connected to any one of the plurality of wirings 107.

[0046] The first output terminal of each LE 101 in the third column 102-3 is connected to one of the plurality of wirings 105. The third column 102-3 has each LE 101 connected to one of the LEs 101. The second output terminals are connected to any one of the plurality of wirings 109 .

[0047] The number of first output terminals and the number of second output terminals that each LE101 has are not necessarily one. However, it is not limited to the above, and either one may be plural, or both may be plural. Even if there are multiple first output terminals or multiple second output terminals, one wiring must That is, the number of LEs 101 in the column 102 is Y (Y is a natural number), then the PLD100 has Y wires connected to the first output terminal. , and Y wires connected to the second output terminal.

[0048] In this specification, connection means electrical connection, and a current, a voltage, or a potential Therefore, the connected state corresponds to the state in which the signal is directly connected. It does not necessarily refer to the state of being connected, but rather to the state in which a current, voltage, or potential is available or is transmitted through circuit elements such as wires, resistors, diodes, and transistors. This also includes situations where the connection is indirectly made via a direct connection.

[0049] The first column 102-1 is disposed between the plurality of wirings 103 and the plurality of wirings 104. The second column 102-2 is disposed between the plurality of wirings 106 and the plurality of wirings 107. The third column 102-3 is disposed between the plurality of wirings 105 and the plurality of wirings 109. .

[0050] Furthermore, a plurality of wirings connected to the first output terminals of the LEs 101 of the second column 102-2 are The line 106 is between the first column 102-1 and the second column 102-2, and between the first column 102-1 and The column of LEs 101 (see FIG. 1A) is located on the left side of the first column 102-1. The third column 102-3 has a plurality of LEs 101-1 and 101-2. The plurality of wirings 105 connected to the first output terminals of the first column 102-1 and the second column 10 2-2 and between the second row 102-2 and the third row 102-3. In addition, each L arranged on the right side of the third row 102-3 in the drawing of FIG. A plurality of wirings 108 connected to the first output terminal of E101 (not shown) are connected to the second column 10 Between 2-2 and the third column 102-3, and between the third column 102-3 and the right side of the third column 102-3 The LE 101 is arranged so as to straddle the rows (not shown) of the LE 101.

[0051] That is, when focusing on the Nth column (N is a natural number of 3 or more), each LE101 in the column The plurality of wirings connected to the first output terminals are connected between the Nth column and the (N-1)th column and between the (N It is arranged so as to straddle between the (N-1)th column and the (N-2)th column. In this case, the wirings connected to the first output terminals of the LEs 101 in the second column are The first row is arranged so as to straddle the I / O element (IO) and the second row. The above IOs are used to input signals from outside the PLD to LE101, or to receive signals from LE101. It functions as an interface that controls the output of signals to the outside of the PLD.

[0052] The positional relationship between the column 102 having the LE 101 shown in FIG. 1(A) and the various wirings is as follows: In one embodiment of the present invention, the LE101 is an example. It is sufficient that the columns 102 and a plurality of various wirings are arranged in parallel.

[0053] In one aspect of the present invention, when focusing on the (N-1)th column (N is a natural number of 3 or more), a plurality of wirings connected to the first output terminals of the LEs 101 in the Nth column; A plurality of wirings connected to the first output terminals of the LEs 101 and each L in the (N-2)th column A plurality of wires connected to the second output terminal of E101 are connected to the first output terminal of E102 via the switch circuit 110. The (N-1) columns are connected to the plurality of input terminals of the LEs 101.

[0054] Specifically, in the case of FIG. 1A, for example, the first LE 101 of each of the second columns 102-2 A plurality of wirings 106 connected to the output terminals and each of the LEs 101 in the third column 102-3 A plurality of wirings 105 connected to the first output terminal and each LE 10 included in the first column 102-1 The first output terminal is connected to a plurality of wirings 104 via a switch circuit 110. The input terminals of the LEs 101 in the second column 102-2 are connected to the input terminals of the LEs 101 in the second column 102-2.

[0055] FIG. 1B shows a diagram of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 shown in FIG. Connection between the wiring 106 and the input terminals of each LE 101 of the second column 102-2 1B is a circuit diagram of a switch circuit 110 for controlling the The wiring 111 is connected to a plurality of input terminals of one LE 101 in the second column 102-2. The switch circuit 110 has a plurality of switch circuits 120. FIG. 1C shows a more specific example of the configuration of the switch circuit 110 shown in FIG. 1B. The switch circuit 110 shown in FIG. 1B is a switch circuit 110 shown in FIG. 1C. Three switch circuits are shown as switch circuit 20-1, switch circuit 120-2, and switch circuit 120-3. It has a path 120.

[0056] Note that FIG. 1C illustrates an example of a switch circuit 110 corresponding to three wirings 111. Therefore, the switch circuit 110 includes the switch circuit 120-1, the switch circuit 120-2, and The switch circuit 120-3 is shown as having three switch circuits 120. The number of switch circuits 120 included in the switch circuit 110 is determined based on the number of inputs included in the LE 101. It can be determined according to the number of terminals.

[0057] In addition, in FIGS. 1B and 1C, a plurality of wirings 104, a plurality of wirings 105, and a plurality of wirings 106 are provided. The wiring 106 is connected to a plurality of wirings 111 through a switch circuit 110. However, in FIG. 1(A), a switch circuit 1 that controls the connection between a plurality of wirings is 10 shall have a similar configuration.

[0058] Next, a more specific configuration example of the switch circuit 110 shown in FIG. 1C is shown in FIG. In FIG. 2, a plurality of wirings 104, a plurality of wirings 105, a plurality of wirings 106, and a switch circuit 2, the connection relationship between each switch circuit and the corresponding circuit 110 is more clearly shown. 120 is a circuit diagram of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106, 111.

[0059] Specifically, in FIG. 2, the plurality of wirings 104 are wirings 104-1, 104-2, 104-3, 104-4, 104-5, 104-6, 104-7, 104-8, 104-9, 104-10, 104-11, 104-12, 104-13, 104-14, 104-15, 104-16, 104-17, 104-18, 104-19, 104-20, 104-21, 104-22, 104-23, 104-24, 104-25, 104-26, 104-27, 104-28, 104-29, 104-21, 104 4-3, and the plurality of wirings 105 are wirings 105-1, 105-2, 105-3 The plurality of wirings 106 includes wirings 106-1, 106-2, and 106-3. 2, the plurality of wirings 111 are shown as wirings 111-1, wirings 111-2, wirings 111-3, wirings 111-4, wirings 111-5, wirings 111-6, wirings 111-7, wirings 111-8, wirings 111-9, wirings 111-10, wirings 111-11, wirings 111-12, wiring 11-2 and wiring 111-3.

[0060] 2, the switch circuit 120-1 is connected to a plurality of wirings 104, a plurality of wirings 105, and controls the connection between all of the plurality of wirings 106 and the wiring 111-1. The switch circuit 120-1 includes a plurality of wirings 104, a plurality of wirings 105, and a plurality of wirings 106. One of the wirings is selected according to the configuration data, and the selected wiring It has the function of connecting the wiring to the wiring 111-1.

[0061] The switch circuit 120-2 is connected to a plurality of wirings 104, a plurality of wirings 105, and a plurality of wirings 106. The switch circuit controls the connection between all of the lines 106 and the wiring 111-2. 120-2 is one of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106. The wiring is selected according to the configuration data, and the selected wiring and the wiring 111-2.

[0062] The switch circuit 120-3 is connected to a plurality of wirings 104, a plurality of wirings 105, and a plurality of wirings 106. The switch circuit controls the connection between all of the lines 106 and the wiring 111-3. 120-3 is one of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106. The wiring is selected according to the configuration data, and the selected wiring and the wiring 111-3.

[0063] <Switch circuit configuration example> Next, a configuration example of the switch circuit 120 will be described. The following is an example of the configuration of the switch circuit 120. The switch circuit 120 includes a switch 131 and a switch In FIG. 3, each of the above-mentioned groups is referred to as a cell 14. 3, the switch circuit 120 is shown as cells 140-1 to 140-0. 1 illustrates a case where there are a plurality of cells 140 indicated by n (n is a natural number).

[0064] The switch 131 sends a packet containing configuration data to the node FD in the cell 140. Specifically, when the switch 131 is in a conducting state, When the signal is ON, the signal including the configuration data is applied to the wiring 121. The potential of the switch 131 is supplied to the node FD. When the potential of the node FD is high, the potential of the node FD is maintained.

[0065] The selection of the conductive or non-conductive state of the switch 131 is determined by the signal applied to the wiring 122. In FIG. 3, the switching is performed in the cells 140-1 to 140-n. The selection of the conductive state or non-conductive state of the switch 131 is performed by the wirings 122-1 to 122-n. The case where the signal is applied to each of the wirings 122 is represented by Illustrated.

[0066] The switch 130 electrically connects the wiring 123 and the wiring 111 in accordance with the potential of the node FD. Specifically, when the switch 130 is in a conductive state, the wiring 12 3 is electrically connected to the wiring 111. When the switch 130 is in a non-conducting state, 3, the wiring 123 and the wiring 111 are electrically isolated from each other. In the cells 140-1 to 140-n, the switch 130 connects the wiring 123-1 to the wiring 123-n. 111. The electrical connections between the wirings 123 shown in FIG. Illustrated.

[0067] The wiring 123 is electrically connected to the output terminals of the LE and IO, and the wiring 111 is It is electrically connected to the input terminals of LE and IO. In accordance with the data, in at least one of the cells 140-1 to 140-n, the switch 13 When the wiring 123-1 to the wiring 123-n are turned on, the wiring 123-2 to the wiring 123-n are turned on. At least one of the 23, i.e., at least one of the output terminals of LE or IO is a switch The selected output terminal selected by the circuit 120 is connected to the wiring 111, i.e., LE or It will be electrically connected to the input terminal of the IO.

[0068] In this specification, an input terminal refers to a node such as a wiring to which an input signal is applied. The potential, voltage, current, etc. of the input signal are applied to the circuit via the node. The wiring electrically connected to the input terminals can also be considered as part of the input terminals. In this specification, the output terminal means a node such as a wiring to which an output signal is applied. The potential, voltage, current, etc. of the output signal are output from the circuit via this node. The wiring electrically connected to the terminal can also be considered to be part of the output terminal.

[0069] Furthermore, in the PLD 100 according to one embodiment of the present invention, a wiring 111 and a wiring to which a predetermined potential is applied are connected. A switch 126 is provided to control the electrical connection with the wiring 125. The switch 126 performs switching in accordance with the signal INIT. When the potential of the wiring 125 is applied to the wiring 111, the switch 126 is in a non-conducting state. When this condition is met, the potential of the wiring 125 is not applied to the wiring 111 .

[0070] In one embodiment of the present invention, the potential of the wiring 111 is set to a predetermined value by turning on the switch 126. The potential of the wiring 111 and the wiring 123 can be initialized to a height of P The LD100 is prone to becoming unstable after power is turned off. After the configuration memory is written, the configuration may be changed depending on the configuration of the storage elements in the configuration memory. In this case, the PLD will lose its distribution data when power is applied. The line 111 and the plurality of wirings 123 are brought into a conductive state via the switch circuit 120, and the wiring 11 If the potentials of the wirings 123 and 124 are different, a large amount of current may flow through these wirings. However, in one embodiment of the present invention, the potential of the wiring 111 is initialized as described above. Therefore, it is possible to prevent a large amount of current from flowing between the wiring 111 and the plurality of wirings 123. This can prevent damage to the PLD.

[0071] Immediately after power is applied to the PLD100, the input terminal of LE101 is set to high level. The intermediate potential may be the intermediate potential between the low and high levels. If the voltage is applied to the CMOS circuit of LE101, a through current is likely to occur. In one embodiment of the present invention, the potential of the wiring 111 can be initialized as described above. Therefore, it is necessary to prevent the input terminal of LE101 from reaching the intermediate potential immediately after power is turned on. This makes it possible to prevent the occurrence of the above-mentioned through current.

[0072] Furthermore, in the PLD 100 according to one aspect of the present invention, when the power is turned on to the PLD 100, After initializing the potential of 111, all the cells 140 included in the switch circuit 120 are switched. The configuration data that causes the switch 130 to be in a non-conducting state is With the above configuration, the wiring 111 and the plurality of wirings Since the wiring 111 and the plurality of wirings 123 can be electrically separated, When the potentials are different, a large amount of current flows through these wirings via the switch circuit 120. This can prevent damage to the PLD100. can.

[0073] The switch circuit 120 shown in FIG. 3 is used as the switch circuit 120-1 shown in FIG. In this case, the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 shown in FIG. 2 are 2 corresponds to the wiring 123-1 to the wiring 123-n shown in FIG. 3. This corresponds to the wiring 111 shown in FIG.

[0074] 2. Also, the switch circuit 120 shown in FIG. 3 is used as the switch circuit 120-2 shown in FIG. In this case, the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 shown in FIG. 2 are 2 corresponds to the wiring 123-1 to the wiring 123-n shown in FIG. 3. This corresponds to the wiring 111 shown in FIG.

[0075] 2. Also, the switch circuit 120 shown in FIG. 3 is used as the switch circuit 120-3 shown in FIG. In this case, the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 shown in FIG. 2 are 2 corresponds to the wiring 123-1 to the wiring 123-n shown in FIG. 3. This corresponds to the wiring 111 shown in FIG.

[0076] As described above, in one embodiment of the present invention, the wiring electrically connected to the output terminal of the LE 101 One of the multiple wirings such as wiring 104, wiring 105, and wiring 106 is configured. Select the appropriate wiring according to the application data, and connect it to the input terminal of the LE101. The switch circuit 120 electrically switches between the first wiring and the second wiring, such as the wiring 111 electrically connected to the first wiring. In one embodiment of the present invention, a switch circuit including the switch circuit 120 having the above configuration is connected. A switch circuit 110 and the various wirings whose electrical connections are controlled by the switch circuit 110. and the LE101 in the first column 102-1, the second column 102-2, the third column 102-3, etc. By providing the second column 102 between the columns including the first column 102 in the PLD 100 shown in FIG. The electric current of one LE 101 included in the first column 102-2 and the electric current of another LE 101 included in the second column 102-2 The individual connections can be controlled by a single switch circuit 120. The electrical connection between one LE 101 in the first column 102-1 and one LE 101 in the second column 102-2 The connection can be controlled by a single switch circuit 120. Electrical connection between one LE 101 in the second column and one LE 101 in the third column 102-3 can be controlled by one switch circuit 120. Therefore, in one embodiment of the present invention, While increasing the design freedom of the PLD100, the switch circuit included in the routing resources The number of can be reduced.

[0077] <Example 1 of a specific switch circuit configuration> Next, a specific example of the configuration of the switch circuit 120 shown in Fig. 3 will be described. The circuit configuration of the switch circuit 120 is shown as an example. A transistor 130t that controls the electrical connection between the elements, and a configuration device The amount of charge determined by the data is supplied and held at the gate of transistor 130t. , and a transistor 131t having an extremely low off-state current for discharging.

[0078] In Fig. 4, each of the above groups is illustrated as a cell 140. The switch circuit 120 shown in Fig. 4 has , the cells corresponding to the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106, respectively. 2, a plurality of wirings 104, a plurality of wirings 105, and Since the total number of the wirings 106 is nine, the wirings shown in FIG. 4 do not match the configuration shown in FIG. In addition, the switch circuit 120 switches the nine cells 140-1 to 140-9. 40, and wirings corresponding to the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106. An example will be given in which there are nine lines 123 (wires 123-1 to 123-9).

[0079] Each cell 140 includes a transistor 130t and a transistor 131t, as well as a transistor The transistor 130t has a capacitance element 132 connected to the gate of the transistor 130t. 32 has the function of retaining the charge accumulated in the gate of the transistor 130t. The gate of the transistor 130t is kept floating, and the change in the potential of the wiring 127 is It has the function of adding to the potential of the gate of 130t.

[0080] Specifically, one of the source and drain of the transistor 130t is connected to the wiring 111. The other is connected to one of the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106. The transistor 131t is connected to one wiring 123 corresponding to one wiring. One of the source and drain is connected to the gate of the transistor 130t, and the other is connected to the wiring 1 21. The gate of the transistor 131t is connected to a plurality of wirings 122 (wirings 12 The pair of electrodes of the capacitor 132 are connected to one of the wirings 122-1 to 122-9. One of the electrodes is connected to one of the plurality of wirings 127 (wirings 127-1 to 127-9). The other end is connected to the gate of transistor 130t.

[0081] The source of a transistor is a source region that is a part of the semiconductor film that functions as an active layer. The source electrode electrically connected to the semiconductor film is also called a transistor. The drain of a transistor is the drain region, which is a part of the semiconductor film that functions as the active layer. The gate electrode is a gate electrode electrically connected to the semiconductor film. means.

[0082] The source and drain of a transistor are determined by the channel type of the transistor and the characteristics given to each terminal. The name changes depending on the level of the potential applied. Generally, n-channel transistors are In a transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. Also, in a p-channel transistor, the terminal to which a low potential is applied is called The terminal to which a high potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. Assuming that the source and drain are fixed, explain the connection relationship of the transistor. However, in reality, the names of source and drain are changed according to the above potential relationship. Replace.

[0083] The cell 140 may include a transistor, a diode, a resistor, a capacitor, an inductor, etc., as needed. It may also include other circuit elements such as a converter.

[0084] Next, an example of the operation of the switch circuit 120 shown in FIG. 4 will be explained with reference to the timing chart shown in FIG. The timing chart shown in Figure 5 will be used to explain this. 13 shows an example in which the transistors 130t and 131t are n-channel types.

[0085] First, the first conversion of the configuration data is performed from time T1 to time T6. The writing will be described. From time T1 to time T6, the wiring 127 is supplied with the ground potential G Assume that ND is given.

[0086] Between time T1 and time T2, the wiring 122-1 of the plurality of wirings 122 is set to a ground potential. A high-level potential VDD higher than GND is applied, and the other wiring 122 is applied with the ground potential GND. A low-level potential VSS that is lower than the potential VSS is applied to the wiring 121. By the above operation, the gate (FD1) of the transistor 130t of the cell 140-1 has Therefore, the cell 140-1 is supplied with a potential VSS, which corresponds to a digital value of "0". The configuration data is stored.

[0087] Between time T3 and time T4, a high level is applied to the wiring 122-2 of the plurality of wirings 122. A potential VDD is applied to the wiring 121, and a low level potential VSS is applied to the other wiring 122. A high level potential VDD is applied to the cell 121. By the above operation, the transistor of the cell 140-2 The gate (FD2) of the transistor 130t is supplied with a potential VDD. 40-2 stores the configuration data corresponding to the digital value of "1". do.

[0088] Between time T5 and time T6, a high level is applied to the wiring 122-3 of the plurality of wirings 122. A potential VDD is applied to the wiring 121, and a low level potential VSS is applied to the other wiring 122. By the above operation, the potential VSS is applied to the transistor 121 of the cell 140-3. The gate (FD3) of cell 30t is supplied with the potential VSS. , configuration data corresponding to a digital value of "0" is stored.

[0089] In the timing chart shown in FIG. 5, the signals to the cells 140-1 to 140-3 are Only the first write of configuration data is shown, cell 140-4 The first write of configuration data to cell 140-9 is performed in the same manner. However, among the cells 140-1 to 140-9, the data "1" is written to There is only one cell 140 in which configuration data corresponding to the digital value is stored. is.

[0090] Next, the configuration data stored in the cell 140 by the first write is The switching of the first logic circuit that is performed in this manner will now be described.

[0091] Between time T7 and time T8, a high-level potential VDD is applied to the wiring 127. Between time T7 and time T8, in cell 140-1, transistor 130t is in a non-conductive state. In cell 140-2, transistor 130t is in a conducting state, and in cell 140-3, transistor Therefore, the wiring 123-2 and the wiring 111 are in a conductive state. Therefore, the potential of the wiring 123-2 is applied to the wiring 111. Specifically, in the timing shown in FIG. The chart illustrates an example in which the potential VDD is applied to the wiring 111.

[0092] Next, the first processing of the configuration data is performed from time T8 to time T13. The writing of 2 will be described. Between time T8 and time T13, the wiring 127 is connected to the ground. It is assumed that the potential GND is given.

[0093] Between time T8 and time T9, a high level is applied to the wiring 122-1 of the plurality of wirings 122. A potential VDD is applied to the wiring 121, and a low level potential VSS is applied to the other wiring 122. A high level potential VDD is applied to the cell 121. By the above operation, the transistor of the cell 140-1 The gate (FD1) of the transistor 130t is supplied with a potential VDD. 40-1 stores the configuration data corresponding to the digital value of "1". do.

[0094] Between time T10 and time T11, among the multiple wirings 122, a high level is applied to the wiring 122-2. A potential VDD is applied to the bell, and a low-level potential VSS is applied to the other wiring 122. A potential VSS is applied to the wiring 121. By the above operation, the transistor of the cell 140-2 The gate (FD2) of the cell 130t is supplied with the potential VSS. stores configuration data corresponding to a digital value of "0."

[0095] Between time T12 and time T13, among the multiple wirings 122, a high level is applied to the wiring 122-3. A potential VDD is applied to the bell, and a low-level potential VSS is applied to the other wiring 122. A potential VSS is applied to the wiring 121. By the above operation, the transistor of the cell 140-3 The gate (FD3) of the cell 130t is supplied with the potential VSS. stores configuration data corresponding to a digital value of "0."

[0096] In the timing chart shown in FIG. 5, the signals to the cells 140-1 to 140-3 are Only the second write of configuration data is shown, cell 140-4 The second write of configuration data to cell 140-9 is performed in the same manner. However, among the cells 140-1 to 140-9, the data "1" is written in the second write. There is only one cell 140 in which configuration data corresponding to the digital value is stored. is.

[0097] Then, a second write is performed to the configuration data stored in the cell 140. The switching of the second logic circuit that is performed accordingly will now be described.

[0098] Between time T14 and time T15, a high-level potential VDD is applied to the wiring 127. Between time T14 and time T15, the transistor 130t in the cell 140-1 is turned on. In cell 140-2, transistor 130t is in a non-conducting state, and in cell 140-3, transistor 130t is in a non-conducting state. Therefore, the wiring 123-1 and the wiring 111 are not electrically connected. The potential of the wiring 123-1 is applied to the wiring 111. Specifically, in the timing diagram shown in FIG. The timing chart illustrates the case where the ground potential GND is applied to the wiring 111.

[0099] When writing the configuration data, the wirings 123-1 to 123- It is desirable to keep the potential of -9 and the potential of the wiring 111 at the same level. During the writing of the configuration data, the transistor 130t is turned on. However, an excessive current flows through the wirings 123-1 to 123-9 via the transistor 130t. and the wiring 111.

[0100] In addition, it is preferable that the potential of the wiring 111 be maintained at a predetermined level by a latch circuit or the like. With the above configuration, the potential of the wiring 111 can be prevented from being in a floating state, and the potential of the wiring 111 can be prevented from being in a floating state. This can prevent excessive current from occurring in the LE where the potential is applied to the input terminal. Cut.

[0101] As described above, the switch circuit 120 has When any one of the plurality of cells 140 is brought into a conductive state, Thus, the connection structure between one of the plurality of wirings 123 and the wiring 111 is determined.

[0102] In one embodiment of the present invention, the above-described configuration allows the PLD 100 shown in FIG. The first column 102-2 has one LE101, and the second column 102-2 has another LE1 The electrical connection of the first and second switches 120 can be controlled by a single switch circuit 120. One LE 101 in the first column 102-1 and one LE 101 in the second column 102-2 The electrical connection of the first and second electrodes can be controlled by a single switch circuit 120. The power of one LE 101 in the column 102-2 and the power of one LE 101 in the third column 102-3 The electrical connection can be controlled by a single switch circuit 120. In one embodiment, the degree of freedom in designing the PLD 100 is increased while the number of switches included in the wiring resources is increased. The number of switch circuits can be reduced.

[0103] The transistor 131t, which has a significantly small off-state current, is made of a material having a band gap rather than silicon. A channel formation region is formed in a semiconductor film with a wide gap and a lower intrinsic carrier density than silicon. Such semiconductors are characterized by being made of, for example, silicon or more than twice the Examples of semiconductors with large band gaps include oxide semiconductors, silicon carbide, and gallium nitride. The transistors using the above semiconductors are made of ordinary semiconductors such as silicon and germanium. The off-state current can be made extremely small compared to a transistor formed using a silicon dioxide film. By using the transistor 131t having the above configuration, the voltage between the wirings or terminals can be reduced. The charge held on the gate of transistor 130t, which controls the electrical connection, leaks away. This can prevent this.

[0104] In the switch circuit 120 having the above configuration, the The conduction state of transistor 130t, which controls the electrical connection between the lines or terminals, is determined. The conductive state is maintained by the transistor 131t having an extremely small off-state current. Therefore, in one aspect of the present invention, the switch circuit 110 is It functions as both a memory element and a memory cell. The number of 0 elements is smaller than that of SRAM. Therefore, it is Compared to conventional PLDs that have both a configuration data and a memory element, This allows the area of ​​the storage device for storing the data to be kept small.

[0105] The off-state current of the transistor 131t is Since it is smaller than a transistor, the data retention time in the switch circuit 110 is M. This reduces the frequency of data rewriting. Power consumption can be further reduced.

[0106] <Example 2 of a specific switch circuit configuration> Next, a specific example of the configuration of the switch circuit 120 shown in FIG. The switch circuit 120 includes a transistor 131t that functions as a switch 131 and a A transistor 130t functions as a switch 130, and a gate of the transistor 130t is connected to the transistor 130t. The device has a plurality of cells 140 each having a capacitor element 132 electrically connected thereto. Then, n cells 140 indicated as cells 140-1 to 140-n are connected to a switch circuit 120 has.

[0107] Specifically, the gate of the transistor 131t is electrically connected to the wiring 122. One of the source and drain of the transistor 131t is electrically connected to the wiring 121. The other end is electrically connected to the gate of transistor 130t. One of the source and drain of 130t is electrically connected to the wiring 123, and the other is electrically connected to the wiring 1 11 is electrically connected to

[0108] One of the pair of electrodes of the capacitor 132 is electrically connected to the gate of the transistor 130t. The other end is connected to a plurality of wirings 127-1 to 127-n. 7. The capacitor 132 is electrically connected to one of the nodes FD and FD. In addition to the function of maintaining the potential of the wiring 127, the node FD is kept floating. It has the function of adding to the potential of the FD.

[0109] The cell 140 may include a transistor, a diode, a resistor, a capacitor, an inductor, etc., as needed. It may also include other circuit elements such as a converter.

[0110] <Switch circuit operation example> Next, an example of the operation of the switch circuit 120 shown in FIG. 6 will be explained with reference to the timing chart shown in FIG. The timing chart shown in Figure 7 will be used to explain this. 131t and the transistor 130t are n-channel type. The wiring 125 is supplied with a low-level potential VSS that is lower than the ground potential GND. Let's say.

[0111] First, after powering on the PLD, the wiring 111 is turned on at time T1 to time T8. The initialization of the potential of node FD will be described below.

[0112] Before time T1, the PLD is powered on immediately, so the multiple wirings 123 and the wiring The potential of the node FD of each cell 140 is also in an uncertain state. In FIG. 7, the period when the potential is in an unstable state is indicated by diagonal lines.

[0113] At times T1 to T8, the signal INI input to the gate of the transistor 126t The potential of T becomes high level, and the transistor 126t becomes conductive. A potential VSS is applied to the wiring 111 via a resistor 126t. At the same time as the power is turned on, the potential of the signal INIT is set to high level, so that the potential of the wiring 111 In one embodiment of the present invention, the wiring 111 is provided with a potential By applying VSS, the potential of the wiring 111 can be initialized. The element does not become unstable, and the CMOS circuit with LE can prevent through current. This prevents the PLD from being damaged. At times T1 to T8, a ground potential GND is applied to the wiring 127, thereby disabling the wiring 123 and the wiring 127. Therefore, even if the potentials of the wiring 123 and the wiring 111 are different, the wiring 1 This can prevent a large amount of current from flowing between 23 and the wiring 111.

[0114] During the period from time T1 to time T8, the potential VSS is applied to the wiring 111. 7, the potentials of the nodes FD of all the cells 140 are initialized. Between time T2 and time T3, the wiring 122-1 of the plurality of wirings 122 is supplied with a ground potential G A high-level potential VDD higher than ND is applied, and the other wiring 122 is applied with a potential VSS. Further, the potential VSS is applied to the wiring 121. By the above operation, the cell 140 At -1, the potential VSS is applied to the node FD1, so that the transistor 130t is non-conductive. This is the state.

[0115] Next, from time T4 to time T5, among the multiple wirings 122, the wiring 122-2 is A high-level potential VDD higher than the ground potential GND is applied, and the other wiring 122 is The potential VSS is applied to the wiring 121. In the cell 140-2, the potential VSS is applied to the node FD2, so that the transistor 130 t is in a non-conducting state.

[0116] Next, from time T6 to time T7, among the multiple wirings 122, the wiring 122-3 is A high-level potential VDD higher than the ground potential GND is applied, and the other wiring 122 is The potential VSS is applied to the wiring 121. In the cell 140-3, the potential VSS is applied to the node FD3, so that the transistor 130 t is in a non-conducting state.

[0117] In the timing chart shown in FIG. 7, the cells 140-1 to 140-3 Although only the initialization of the potential of the node FD is shown, the cells 140-4 to 140- The potential of node FD in n is also initialized in the same way. At 140, the potential of node FD is initialized, and transistor 130t is in a non-conductive state. become.

[0118] Next, at time T8, the potential of the signal INIT becomes low, and the transistor 12 6t is in a non-conductive state.

[0119] Next, the writing of the configuration data is performed from time T9 to time T15. Between time T9 and time T15, the wiring 127 is supplied with the ground potential G ND is given. Also, from time T9 to time T15, the signal INI The potential of T remains low, and transistor 126t remains non-conductive.

[0120] First, from time T9 to time T10, among the plurality of wirings 122, the wiring 122-1 is connected to the A high-level potential VDD is applied to the other wiring 122, and a low-level potential VSS is applied to the other wiring 122. Also, a high-level potential VDD is applied to the wiring 121. In the cell 140-1, the potential VDD is applied to the node FD1. , the configuration data corresponding to the digital value of "1" is stored. It can be said that.

[0121] Next, from time T11 to time T12, among the plurality of wirings 122, the wiring 122-2 A high-level potential VDD is applied to the wiring 121, and a low-level potential VSS is applied to the other wiring 122. In addition, a low-level potential VSS is applied to the wiring 121. In the cell 140-2, the potential VSS is applied to the node FD2. 2 is the state where the configuration data corresponding to the digital value of "0" is stored. It can be said that there is.

[0122] Next, from time T13 to time T14, among the multiple wirings 122, the wiring 122-3 A high-level potential VDD is applied to the wiring 121, and a low-level potential VSS is applied to the other wiring 122. In addition, a low-level potential VSS is applied to the wiring 121. In the cell 140-3, the potential VSS is applied to the node FD3. 3 is the state where the configuration data corresponding to the digital value of "0" is stored. It can be said that there is.

[0123] In the timing chart shown in FIG. 7, the signals to the cells 140-1 to 140-3 are Although only the writing of configuration data is shown, cells 140-4 to 140-6 are The configuration data is written to the cell 140-n in the same manner. Among cells 140-1 to 140-n, the one corresponding to the digital value of "1" is written. There is only one cell 140 in which configuration data is stored.

[0124] Then, according to the configuration data stored in the cell 140 by writing The switching of the logic circuit that is performed will now be described.

[0125] Between time T15 and time T16, a high-level potential VDD is applied to the wiring 127. Then, the potential difference between the ground potential GND and the potential VDD is added to the node FD of each cell 140. Therefore, from time T9 to time T15, the configuration corresponding to the digital value of "1" Only in the cell 140 where the information data is stored, the potential of the node FD becomes sufficiently high. Specifically, in the timing chart shown in FIG. In this case, the cell 140-1 is set to a digital value of "1" from time T9 to time T15. Since the configuration data is stored, the voltage of the wiring 123-1 and the wiring 111 is The transistor 130t that controls the electrical connection is turned on, and the potential of the wiring 123-1 is The signal is applied to the wiring 111 via the transistor 130t.

[0126] As described above, the switch circuit 120 has When any one of the plurality of cells 140 is brought into a conductive state, Thus, the connection structure between one of the plurality of wirings 123 and the wiring 111 is determined.

[0127] 7 illustrates an example in which the potential of the node FD is initialized for each cell 140 in turn. However, the potentials of the nodes FD in all the cells 140 may be initialized simultaneously.

[0128] <Switch circuit specific configuration example 3> Next, a specific example of the configuration of the switch circuit 120 shown in FIG. 3, which is different from that shown in FIG. 4, will be described. I will explain.

[0129] 8 shows an example of the circuit configuration of the switch circuit 120. The switch circuit 120 is Alternatively, a transistor 130t that controls the electrical connection between the terminals and a configuration The amount of charge determined by the application data is provided at the gate of transistor 130t. A transistor 131t having an extremely small off-state current for supplying, holding, and discharging The circuit has a plurality of pairs of transistors 130t and 133t connected in series to each other.

[0130] In this specification, the state in which transistors are connected in series means, for example, Only one of the source or drain of one transistor is connected to the source or drain of the second transistor. means that only one of the drains is connected. The state of being connected means that either the source or the drain of the first transistor is connected to the second transistor. the source or drain of the first transistor; The other of the drains is connected to the other of the source or drain of the second transistor. It means attitude.

[0131] In Fig. 8, each of the above groups is illustrated as a cell 140. The switch circuit 120 shown in Fig. 8 has: Cells 1 corresponding to the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106, respectively 2, a plurality of wirings 104, a plurality of wirings 105, and a plurality of wirings 106 are provided. 8 shows an example in which the total number of wirings 106 is nine, and therefore, in FIG. 8, the wirings 106 are not matched to the configuration in FIG. The switch circuit 120 selects nine cells 140-1 to 140-9. 0, and wirings corresponding to the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106 Here is an example where there are nine 123s.

[0132] Specifically, one of the source and drain of the transistor 133t is connected to the wiring 111. The other terminal is connected to one of the source and drain of the transistor 130t. The other of the source and the drain of the transistor 130t is connected to a plurality of wirings 123 ( The transistor 131t is connected to one of the wirings 123-1 to 123-9. The source and drain of the transistor 130t are connected to the gate of the transistor 130t, and the other are connected to the wiring 121. The gate of the transistor 131t is connected to a plurality of wirings 122 ( The transistor 133t is connected to one of the wirings 122-1 to 122-9. The gate is connected to one of a plurality of wirings 128 (wirings 128-1 to 128-9). There are.

[0133] The cell 140 may include a transistor, a diode, a resistor, a capacitor, an inductor, etc., as needed. It may also include other circuit elements such as a converter.

[0134] The operation of the switch circuit 120 shown in FIG. 8 can be understood by referring to the timing chart shown in FIG. However, in the timing chart shown in FIG. This corresponds to the case where the transistor 131t and the transistor 133t are n-channel transistors.

[0135] <Switch circuit specific configuration example 4> Next, a configuration example of the switch circuit 120 shown in FIG. 3 that is different from that shown in FIG. 6 will be described. The switch circuit 120 shown in FIG. 9 includes a transistor 131t, a transistor 130t, 9, the cell 140 includes a plurality of transistors 133t. The switch circuit 120 activates n cells 140 indicated as 140-1 to 140-n. This example shows a case where

[0136] Transistor 131t is connected to node FD via a signal including configuration data. The transistor 130t has a function of controlling the supply of a potential. The transistor 133t is turned on or off by the signal line 128. The transistor 130t is turned on or off depending on the potential. and the transistor 133t are connected in series, and together It has the function of controlling electrical connections.

[0137] Specifically, the gate of the transistor 131t is electrically connected to the wiring 122. One of the source and drain of the transistor 131t is electrically connected to the wiring 121. The other end is electrically connected to the gate of transistor 130t. One of the source and drain of 130t is electrically connected to the wiring 123, and the other is connected to the transistor. The transistor 133t is electrically connected to one of the source and drain of the transistor 133t. The other of the source and drain of the transistor 33t is electrically connected to the wiring 111. The gate of the starter 133t is electrically connected to the wiring 128.

[0138] The cell 140 may include a transistor, a diode, a resistor, a capacitor, an inductor, etc., as needed. It may also include other circuit elements such as a converter.

[0139] <Switch circuit specific configuration example 5> Next, taking the circuit configuration of the switch circuit 120 shown in FIG. 2 as an example, A specific example of the configuration different from that shown in FIG. 4 will be described.

[0140] 10 shows an example of the circuit configuration of the switch circuit 120. The switch circuit shown in FIG. 120 is an electrical connection between wirings or terminals, similar to the switch circuit 120 shown in FIG. The transistor 130t controls the connection and the for supplying, holding, and discharging a certain amount of charge at the gate of transistor 130t. A transistor 131t with a very small current is connected in series with the transistor 130t. 10, the transistor 133t includes a plurality of pairs of wirings 104, In the case where two sets are provided for the plurality of wirings 105 and the plurality of wirings 106, This example illustrates the case.

[0141] In FIG. 10, each of the above groups is illustrated as a cell 140. are two wirings corresponding to the plurality of wirings 104, the plurality of wirings 105, and the plurality of wirings 106, respectively. In FIG. 2, a plurality of wirings 104 and a plurality of wirings 10 10 shows an example in which the total number of wirings 106 is 9. In accordance with this configuration, the switch circuit 120 is configured to include cells 140-1 to 140-18. The cell 140 includes 18 cells 140, a plurality of wirings 104, a plurality of wirings 105, and a plurality of wirings 106. 6, there are nine wires 123.

[0142] In addition, the wirings 104, 105, and 106 correspond to the wirings 104, 105, and 106, respectively. The number of cells 140 is not limited to two. The wirings 104, the plurality of wirings 105, and the plurality of wirings 106 may correspond to each other.

[0143] Specifically, in FIG. 10, two of the plurality of cells 140 are connected to the plurality of wirings 123. For example, in the case of cell 140-1 and cell 140-2, two The other of the source and drain of the transistor 130t is connected to the wiring 123-1. are.

[0144] The cell 140 may include a transistor, a diode, a resistor, a capacitor, an inductor, etc., as needed. It may also include other circuit elements such as a converter.

[0145] 8 and 10, the transistor 133t has the same structure as the transistor 130t. In this example, one of the source and drain is electrically connected to the wiring 111. The transistor 133t has the other of the source and drain of the transistor 130t. and one of the plurality of wirings 123 may be electrically connected to each other.

[0146] Next, an example of the operation of the switch circuit 120 shown in FIG. 10 will be explained with reference to the timing diagram shown in FIG. The timing chart shown in Figure 11 is used to explain this. The transistor 130t, the transistor 131t, and the transistor 133t are n-channel. This example illustrates a case where

[0147] First, the configuration data writing process, which is performed from time T1 to time T8, At times T1 to T8, the plurality of wirings 128 are supplied with a ground potential G ND is given, and the transistors 133t of all the cells 140 are in a non-conducting state. It shall be.

[0148] Between time T1 and time T2, a high level is applied to the wiring 122-1 of the plurality of wirings 122. A potential VDD is applied to the wiring 121, and a low level potential VSS is applied to the other wiring 122. By the above operation, the voltage VDD is applied to the transistor 121 of the cell 140-1. The gate (FD1) of cell 30t is supplied with a potential VDD. , the first configuration data corresponding to the digital value of "1" is stored.

[0149] Between time T3 and time T4, a high level is applied to the wiring 122-2 of the plurality of wirings 122. A potential VDD is applied to the wiring 121, and a low level potential VSS is applied to the other wiring 122. By the above operation, the potential VSS is applied to the transistor 121 of the cell 140-2. The gate (FD2) of cell 30t is supplied with the potential VSS. , the second configuration data corresponding to the digital value of "0" is stored.

[0150] Between time T5 and time T6, a high level is applied to the wiring 122-3 of the plurality of wirings 122. A potential VDD is applied to the wiring 121, and a low level potential VSS is applied to the other wiring 122. By the above operation, the potential VSS is applied to the transistor 121 of the cell 140-3. The gate (FD3) of cell 30t is supplied with the potential VSS. , the first configuration data corresponding to the digital value of "0" is stored.

[0151] Between time T7 and time T8, a high level is applied to the wiring 122-4 of the plurality of wirings 122. A potential VDD is applied to the wiring 121, and a low level potential VSS is applied to the other wiring 122. By the above operation, the voltage VDD is applied to the transistor 121 of the cell 140-4. The gate (FD4) of cell 30t is supplied with a potential VDD. , the second configuration data corresponding to the digital value of "1" is stored.

[0152] In the timing chart shown in FIG. 11, the first signals to the cells 140-1 to 140-4 are For writing 1st or 2nd configuration data Although only the first configuration data is shown for cells 140-5 to 140-18, The writing of the configuration data or the second configuration data is also performed in the same manner. However, multiple cells represented by cells 140-M (where M is a natural number and an odd number less than or equal to 18) Among the cells 140, the digital value "1" is written by writing the first configuration data. There is only one cell 140 in which configuration data corresponding to the rule value is stored. In addition, the compound cell 140-L (where L is a natural number and an even number less than or equal to 18) Of the cells 140, the data of “1” is written by writing the second configuration data. There is only one cell 140 in which configuration data corresponding to the digital value is stored. is.

[0153] Next, switching of the first logic circuit is performed in accordance with the first configuration data. We will explain the process.

[0154] Between time T9 and time T10, a plurality of wirings 128 represented by wirings 128-M are connected to the high A potential VDD of the level is applied to the plurality of wirings 128 represented by wirings 128-L. The ground potential GND is then applied. Then, from time T9 to time T10, cell 1 Among the multiple cells 140 represented by 40-M, cell 140-1 is in a conductive state, and the other cells Therefore, the wiring 123-1 and the wiring 111 are in a conductive state. As a result, the potential of the wiring 123-1 is applied to the wiring 111. Specifically, in the timing shown in FIG. The timing chart illustrates an example in which the ground potential GND is applied to the wiring 111.

[0155] Next, switching of the second logic circuit is performed in accordance with the second configuration data. We will explain the process.

[0156] Between time T11 and time T12, the wirings 128 represented by the wirings 128-L are connected to the A potential VDD of the high level is applied to the plurality of wirings 128 represented by wirings 128-M. The ground potential GND is applied. Then, from time T11 to time T12, the cell 140 Among the multiple cells 140 represented by -L, cell 140-4 is in a conducting state, and the other cells 1 40 is in a non-conductive state. Therefore, the wiring 123-2 and the wiring 111 are in a conductive state. The potential of the wiring 123-2 is applied to the wiring 111. Specifically, at the timing shown in FIG. The chart illustrates an example in which the potential VDD is applied to the wiring 111.

[0157] In addition, the first configuration data or the second configuration data When writing, the potentials of the wirings 123-1 to 123-18 and the potential of the wiring 111 are set to It is desirable to keep the height the same. During the writing of the second configuration data, transistor 130t is in a conducting state. Even if the transistor 130t is in the ON state, an excessive current flows through the wirings 123-1 to 123-2. 3-18 and the wiring 111.

[0158] In addition, it is preferable that the potential of the wiring 111 be maintained at a predetermined level by a latch circuit or the like. With the above configuration, the potential of the wiring 111 can be prevented from being in a floating state, and the potential of the wiring 111 can be prevented from being in a floating state. This can prevent excessive current from occurring in the LE where the potential is applied to the input terminal. Cut.

[0159] In the case of the switch circuit 120 shown in FIG. 10, a plurality of configuration data The configuration data used for the configuration is stored in Therefore, it is possible to freely select the data for one configuration data. While the PLD with the specified logic circuit is operating, other configuration devices The data can be rewritten.

[0160] <Example 6 of a specific switch circuit configuration> Next, a configuration example of the switch circuit 120 shown in FIG. 3 that is different from that shown in FIG. 6 will be described. The switch circuit 120 shown in FIG. 12 is similar to the switch circuit 120 shown in FIG. A cell 140 having a transistor 131t, a transistor 130t, and a transistor 133t. However, in FIG. 12, each of the plurality of wirings 123 is shared by two cells 140. 1 illustrates the configuration of the switch circuit 120.

[0161] Specifically, in FIG. 12, 2n cells 140-1 to 140-2n are shown. 40 in the switch circuit 120. Among them, cell 140-i and cell 140-i+1 (i is a natural number equal to or less than 2n-1) are allocated. Among the lines 123-1 to 123-n, one line 123 is shared.

[0162] The number of cells 140 sharing each of the multiple wirings 123 is not limited to two. A plurality of cells 140 may share a plurality of wirings 123 .

[0163] Specifically, in FIG. 12, the source and drain of the transistor 130t of the cell 140-1 are One of the inputs and one of the source and drain of the transistor 130t of the cell 140-2. 12 illustrates a case where both are electrically connected to the wiring 123-1.

[0164] The cell 140 may include a transistor, a diode, a resistor, a capacitor, an inductor, etc., as needed. It may also include other circuit elements such as a converter.

[0165] 9 and 12, the transistor 133t has the same structure as the transistor 130t. 11. In this example, the other of the source and drain is electrically connected to the wiring 111. The transistor 133t has one of the source and drain of the transistor 130t. Alternatively, the wiring 123 may be electrically connected to one of the wirings 123 .

[0166] In the switch circuit 120 shown in FIG. 12, a plurality of The cell 140 stores configuration data corresponding to a plurality of circuit configurations. The logic circuits that are executed according to the configuration data can then be stored. The path switching is performed by storing configuration data corresponding to one circuit configuration. In the cell 140, the transistor 133t is turned on, and the other circuit configurations are In the cell 140 in which the configuration data is stored, the transistor 13 This can be done by making 3t non-conductive.

[0167] Therefore, in the case of the switch circuit 120 shown in FIG. 12, a plurality of configuration data The configuration data is stored and used for configuration. Data can be freely selected. Therefore, one configuration data While the PLD with the logic circuit defined by the The data can be rewritten.

[0168] In the case of the above-mentioned Patent Document 1, the configuration is To switch the configuration data, the configuration data must be read from the DRAM. The configuration data must be read using a sense amplifier. In one aspect of the present invention shown in FIG. 10 or FIG. 12, in a multi-context system, To switch the configuration data, the configuration data is retrieved from DRAM, etc. There is no need to read the data from the memory, and therefore no need to use a sense amplifier. This reduces the time required to switch configuration data, This allows the logic circuit in the programmable logic device to be reconfigured at high speed. Cut.

[0169] In the switch circuit 120, the transistor 131t holds the potential of the node FD. Therefore, it is desirable that the transistor has an extremely low off-state current. A semiconductor with a wider bandgap than silicon and a lower intrinsic carrier density than silicon. A transistor having a channel formation region formed in a film has a significantly low off-state current. Since the semiconductor is very small, it is suitable for use as the transistor 131t. Examples of such materials include oxide semiconductors, which have a band gap twice as large as that of silicon, gallium nitride, etc. Transistors using the above semiconductors are not the same as ordinary silicon or Compared to transistors made of semiconductors such as germanium, the off-state current is extremely small. Therefore, by using the transistor 131t having the above structure, This can prevent the charge held in the board FD from leaking.

[0170] In the switch circuit 120 having the above configuration, the The conductive or non-conductive state of the transistor 130t that controls the electrical connection between the lines is When the transistor 131t is selected and turned off, the node FD The potential of the signal including the configuration data is maintained in the In one embodiment, the switch circuit 120 included in the wiring resource is configured to have its conductive state or non-conductive state. It has the added function of functioning as a configuration memory that holds information on state selection. In addition, since the number of elements in each cell 140 is smaller than that of an SRAM, the configuration Compared to conventional PLDs that have both configuration memory and switches, This allows the area of ​​the application memory to be kept small.

[0171] In particular, multi-context PLDs have a configuration function that supports multiple circuit configurations. Dynamic reconfiguration is realized by storing configuration data in the configuration memory. Therefore, the multi-context PLD is not suitable for dynamic reconfiguration such as configuration information distribution. Compared to other configuration methods, the PLD area occupied by the configuration memory is However, the switching circuit 120 having the configuration shown in FIG. 10 or FIG. In the case of a PLD according to one aspect of the present invention, even if it is a multi-context system, As described above, the area of ​​the configuration memory can be reduced.

[0172] In addition, impurities such as water or hydrogen, which act as electron donors (donors), are reduced, and the acid Highly purified oxide semiconductor (purified OS) due to reduced electron vacancies is an i-type (intrinsic semiconductor) or is as close to i-type as possible. A transistor having a channel formation region in the semiconductor film has a significantly small off-state current and is highly reliable. Therefore, the above transistor is used as the transistor 131t of the switch circuit 120. This allows for a longer data retention period.

[0173] Specifically, the present invention relates to an oxide semiconductor film having a highly purified oxide semiconductor film as a channel formation region. The small fringe current can be proven by various experiments. For example, 0 6 Even in a device with a channel length of 10 μm, the voltage between the source and drain electrodes In the drain voltage range of 1V to 10V, the off-state current was measured by the semiconductor parameter analyzer. Below the riser measurement limit, i.e., 1×10 -13 It can achieve a characteristic of A or below. In this case, the off-state current normalized by the transistor channel width is 100 zA / μm or less. In addition, by connecting the capacitor and the transistor, Off-state current is measured using a circuit that controls the charge flowing out of the capacitor with the transistor. In the measurement, a highly purified oxide semiconductor film was used as a channel of the transistor. The on / off state of the transistor is determined based on the change in the amount of charge per unit time of the capacitor element. The current was measured. As a result, the voltage between the source and drain electrodes of the transistor was 3V. In this case, it was found that an even smaller off-state current of several tens of yA / μm could be obtained. Therefore, a transistor using a highly purified oxide semiconductor film for a channel formation region has an off-state current The current is significantly smaller than that of a transistor using crystalline silicon.

[0174] In addition, oxide semiconductors such as In-Ga-Zn oxides and In-Sn-Zn oxides Unlike silicon carbide, gallium nitride, or gallium oxide, The wet method allows for the fabrication of transistors with excellent electrical characteristics, making it suitable for mass production. In addition, silicon carbide, gallium nitride, or gallium oxide In contrast, the oxide semiconductor (In-Ga-Zn oxide) is deposited on a glass substrate or silicon. It is possible to fabricate transistors with excellent electrical characteristics on an integrated circuit using silicon. It is also possible to accommodate larger substrates.

[0175] The oxide semiconductor contains at least indium (In) or zinc (Zn). In addition, it is preferable to prevent variations in electrical characteristics of transistors using the oxide semiconductor. In addition to these, gallium (Ga) can be added as a stabilizer to reduce It is preferable to have tin (Sn) as a stabilizer. It is preferable to have hafnium (Hf) as a stabilizer. It is preferable that the stabilizer contains aluminum (Al). It is preferable that the metal contains zirconium (Zr).

[0176] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Tetrium) (Lu).

[0177] For example, oxide semiconductors include indium oxide, gallium oxide, tin oxide, zinc oxide, and I n-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, S n-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, I n-Hf-Zn oxide, In-La-Zn oxide, In-Pr-Zn oxide, In -Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In- Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-H Oxide based on Zn, In-Er-Zn, In-Tm-Zn, In-Yb -Zn-based oxides, In-Lu-Zn-based oxides, In-Sn-Ga-Zn-based oxides, In- Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide It is possible.

[0178] For example, an In-Ga-Zn oxide means an oxide containing In, Ga, and Zn. The ratio of In, Ga, and Zn is not important. In-Ga-Zn oxides have a sufficiently high resistance in the absence of an electric field, and The flow can be made sufficiently small and the mobility is high.

[0179] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In-Sn-Zn oxide having an atomic ratio or an oxide having a composition close to that.

[0180] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, even in In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0181] The structure of the oxide semiconductor film will be described below.

[0182] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. refers to the state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This includes cases where the angle is between 85° and 95°.

[0183] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0184] Oxide semiconductor films are roughly classified into single-crystal oxide semiconductor films and non-single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film includes an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, and a polycrystalline oxide semiconductor film. Physical semiconductor film, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor films, etc.

[0185] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and is an oxide film that does not contain a crystalline component. The film is a compound semiconductor film. It does not have any crystalline parts even in the microscopic areas, and the entire film has a completely amorphous structure. A typical example is an oxide semiconductor film.

[0186] The microcrystalline oxide semiconductor film is made up of, for example, microcrystals (nanocrystals) having a size of 1 nm or more and less than 10 nm. Therefore, the microcrystalline oxide semiconductor film has a lower atomic number than the amorphous oxide semiconductor film. Therefore, the microcrystalline oxide semiconductor film has a higher order of molecular arrangement than the amorphous oxide semiconductor film. The defect level density is also low.

[0187] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is so large that it fits inside a cube with a side length of less than 100 nm. The crystals contained in the S film are cubic with sides of less than 10 nm, 5 nm, or 3 nm. The CAAC-OS film has a smaller defect density than the microcrystalline oxide semiconductor film. The CAAC-OS film has a low density of recessed states. .

[0188] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a crystalline microscope, clear boundaries between the crystals, i.e., crystal boundaries, are clearly visible. It is not possible to confirm the grain boundary. It can be said that the AC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0189] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). ) It can be confirmed that the metal atoms are arranged in layers in the crystalline part. Each layer has a surface on which the CAAC-OS film is formed (also referred to as a surface on which the CAAC-OS film is formed) or an uneven surface on which the CAAC-OS film is formed. The shape reflects this and is aligned parallel to the surface on which the CAAC-OS film is formed or the top surface.

[0190] On the other hand, the CAAC-OS film was observed by TEM from a direction approximately perpendicular to the sample surface (planar TEM). When observed, it was found that the metal atoms were arranged in triangular or hexagonal shapes in the crystals. However, there is no regularity in the arrangement of metal atoms between different crystal parts. stomach.

[0191] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It turns out that there are.

[0192] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was found by structural analysis using the device. In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0193] On the other hand, in-pl X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0194] From the above, it is concluded that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. Although it is regular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. Therefore, the layered arrangement confirmed by the cross-sectional TEM observation mentioned above is consistent with the above. Each layer of aligned metal atoms is a plane parallel to the ab plane of the crystal.

[0195] The crystalline part is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed or the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0196] The crystallinity of the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The area near the surface may have a higher degree of crystallinity than the area near the surface to be formed. When impurities are added to a C-OS film, the crystallinity of the region where the impurities are added changes, resulting in partial In some cases, regions of different crystallinity may be formed.

[0197] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ around 31°, a peak also appeared at 2θ around 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferable that the peak is exhibited at 2θ of around 36° and that the peak is not exhibited at 2θ of around 36°.

[0198] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0199] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a CA The AC-OS film may be a laminated film having two or more kinds of films.

[0200] The CAAC-OS film can be formed by sputtering a polycrystalline oxide semiconductor target. The sputtering target is used to form a film by sputtering. Upon impact, the crystalline regions contained in the sputtering target cleave from the ab plane, forming a -b Peels off as flat or pellet-shaped sputtered particles with surfaces parallel to the plane In this case, the plate-like sputtered particles may be transferred to the substrate while maintaining their crystalline state. By reaching the plate, a CAAC-OS film can be formed.

[0201] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0202] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas at a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0203] In addition, by increasing the substrate heating temperature during film formation, the migration of sputtered particles after they reach the substrate is reduced. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably The film is formed at a temperature between 200°C and 500°C. When a plate-shaped sputtering particle reaches the substrate, migration occurs on the substrate, The flat surface of the sputtered particle adheres to the substrate.

[0204] In addition, increasing the oxygen ratio in the deposition gas and optimizing the power reduces plasma damage during deposition. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0205] As an example of a sputtering target, an In-Ga-Zn oxide target is The following is a summary:

[0206] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified number of moles and then pressurized. By heat treatment at a temperature between 1000℃ and 1500℃, polycrystalline In-Ga -Zn-based oxide target, where X, Y, and Z are any positive numbers. The predetermined molar ratio is, for example, InO X powder, GaO Y Powder and ZnO Z Powder, 2: 2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2. The type of powder and the molar ratio of the powder to be mixed depend on the sputtering target to be prepared. This can be changed as appropriate depending on the case.

[0207] The semiconductor film is formed using metal oxide targets having different atomic ratios of metals. A plurality of oxide semiconductor films may be stacked. The atomic ratio of the first oxide semiconductor film is In:Ga:Zn=1:1:1, and the second oxide semiconductor film is In:Ga:Zn=1:1:1. The compound semiconductor film may be formed so that the composition is In:Ga:Zn=3:1:2. The atomic ratio of the target is In:Ga:Zn=1:3:2 for the first oxide semiconductor film, and The first oxide semiconductor film is In:Ga:Zn=3:1:2, and the third oxide semiconductor film is In: It may be formed so that Ga:Zn=1:1:1.

[0208] Alternatively, the semiconductor film may be formed by using a plurality of metal oxide targets containing different metals. The oxide semiconductor film may have a stacked structure.

[0209] The transistor 130t or the transistor 133t may be amorphous, microcrystalline, polycrystalline, or The semiconductor film has a channel forming region in a single crystal semiconductor film such as silicon or germanium. A transistor may be used, and similar to the transistor 131t, a silicon The band gap is wider than that of silicon, and the intrinsic carrier density is lower than that of silicon. A transistor having a silicon-based structure may be used. Amorphous silicon, amorphous silicon, produced by vapor phase growth methods such as the D method or sputtering method Polycrystalline silicon, which is made by crystallizing silicon through processes such as laser annealing, and single-crystal silicon It is possible to use single crystal silicon, etc., which has been exfoliated by implanting hydrogen ions into a silicon wafer. can.

[0210] <Example of cell configuration> Next, another example of the configuration of the switch circuit 120 shown in FIG. 13A shows an example of the cell 140 included in the switch circuit 120. 40 is a transistor 13, similar to the cell 140 included in the switch circuit 120 shown in FIG. 1t, transistor 130t, and transistor 133t. The cell 140 shown in A) includes an inverter 180 for maintaining the potential of the node FD and an inverter 181 for maintaining the potential of the node FD. The configuration differs from that of the cell 140 shown in FIG. 9 in that a converter 181 is provided.

[0211] Specifically, in FIG. 13A, the input terminal of the inverter 180 and the output terminal of the inverter 181 The terminal is electrically connected to the node FD, and the output terminal of the inverter 180 and the inverter The input terminal of the cell 140 shown in FIG. With the above configuration, the potential of the node FD is maintained by the inverter 180 and the inverter 181. It can be held.

[0212] In addition, the cell 140 shown in FIG. 13A has a configuration in which two cells share the wiring 123. An example is shown in FIG. 13B. In FIG. 13B, two cells 140 are connected to the wiring 123. Although the example shows a case where the wiring 123 is shared, in one embodiment of the present invention, the wiring 123 may be shared by three or more Several cells 140 may be shared.

[0213] The cell 140 shown in FIGS. 13(A) and 13(B) may include transistors, diodes, etc. as needed. It may further include other circuit elements such as diodes, resistors, capacitors, and inductors. That's fine.

[0214] 13A and 13B, the transistor 133t is the transistor 13 The other of the source and drain of the transistor 0t is electrically connected to the wiring 111. The transistor 133t has a source and a drain of the transistor 130t. The line 123 may be electrically connected to one of the drain and the gate.

[0215] <Preventing through current by latching> In the PLD according to one aspect of the present invention, the wiring 11 electrically connected to the input terminal of the LE A latch may be electrically connected to the switch 126 for initialization. In addition, the latch 182 is electrically connected to the wiring 111 as shown in FIG. The latch 182 shown in FIG. 14A has a wiring 111 electrically connected to the input terminal of the LE. The potential of the transistor 10 is maintained at either a high level or a low level.

[0216] FIG. 14B shows an example of the configuration of the latch 182. The inverter 2 includes an inverter 183 and a p-channel transistor 184. The input terminal of the inverter 183 is electrically connected to the wiring 111, and the output terminal of the inverter 183 is The source and drain of the transistor 184 are electrically connected to the gate of the transistor 184. One end of the drain is electrically connected to the wiring 185, which is given a higher potential than the wiring 125. The other end is electrically connected to the wiring 111 .

[0217] In one embodiment of the present invention, the latch 182 having the above structure is electrically connected to the wiring 111. By this, after the power supply to the PLD is turned on, the potential of the wiring 111 is set to a high level or a low level. Since the potential can be maintained at either one of the two levels, an intermediate potential can be applied to the wiring 111. This makes it possible to prevent a through current from occurring in the LE whose input terminal is connected to the wiring 111. Cut.

[0218] <Connection structure between IO and logic elements> Next, the connection structure between the IO and logic elements in the PLD 100 will be explained. Figure 15 illustrates a portion of a PLD 100 according to one embodiment of the present invention.

[0219] In FIG. 15, a column 102 having a plurality of LEs 101 and a column 151 having a plurality of IOs 150 are shown. In FIG. 15, from the left side of the drawing, 51 and column 102 are arranged in parallel.

[0220] In addition, in FIG. 15, a plurality of wirings 152, a plurality of wirings 153, a plurality of wirings 154, and a plurality of wirings A number of wirings 155 and a plurality of wirings 156 are provided on the PLD 100.

[0221] The first output terminal of each LE 101 in the column 102 is connected to a plurality of wirings 152 and a plurality of The second output terminal of each LE 101 in the column 102 is connected to the wiring 156. , and are connected to a plurality of wirings 153. The output terminals of the IOs 150 of the column 151 are The terminals are respectively connected to a plurality of wirings 155. The plurality of wirings 154 are connected to the wirings 155 shown in FIG. The first output of each of the plurality of LEs 101 (not shown) arranged on the right side of the column 102 when facing the direction of the arrow. are connected to the output terminals, respectively.

[0222] The number of output terminals that each IO 150 has is not necessarily one, and may be multiple. However, even if there are multiple output terminals, one output terminal must be connected to one wiring. That is, the number of IOs 150 in the column 151 is Y (Y is a natural number). If so, the PLD 100 can provide at least Y wires 155 electrically connected to the output terminals. At least have.

[0223] Then, a plurality of wirings 152, a plurality of wirings 154, a plurality of wirings 155, and a plurality of wirings 1 Column 156 is disposed between column 151 and column 102. Column 102 is also provided with a plurality of wirings 1 52 and a plurality of wirings 153.

[0224] In addition, in FIG. 15, a plurality of wirings 152, a plurality of wirings 154, and a plurality of wirings 155 are The input terminals of each LE 101 in the column 102 are electrically connected to each other through a switch circuit 110. In FIG. 15, a plurality of wirings 156 are connected to the column 151 are electrically connected to the input terminals of the IOs 150.

[0225] The switch 157 has one switch circuit 120 having the above-described configuration. The switch circuit 120 of the switch 157 is configured to connect one of the plurality of wirings 156 to the Select according to the configuration data, and connect the selected wiring to the input of each IO150. It has the function of connecting to the output terminal.

[0226] In addition, in FIG. 1(A) and FIG. 15, the LE 101 is connected to the column through a plurality of wirings provided between the columns. This shows an example in which LEs 101 belonging to the same column are connected to each other. The wiring that directly connects the LE101 in one column is provided in the PLD100. is also good.

[0227] <LE configuration example> FIG. 16(A) shows an example of the LE 101. The LE 101 shown in FIG. UT (Look-up table) 160, flip-flop 161, and configuration The configuration memory 162 includes a memory element. It has the function of storing the configuration data sent from the LUT. 160 receives the configuration data from the configuration memory 162. The logic circuit that is defined varies depending on the contents of the configuration data. When the input data is determined, the LUT 160 calculates the sum of the input signals applied to the input terminal 163. One output value is determined for each input value. Then, the LUT 160 outputs a value including the output value. The flip-flop 161 holds the signal output from the LUT 160. Then, in synchronization with the clock signal CLK, an output signal corresponding to the signal is output from the first output terminal 164 and output from the second output terminal 165.

[0228] In addition, the LE101 further has a multiplexer circuit, and the multiplexer circuit , it is possible to select whether the output signal from the LUT 160 passes through the flip-flop 161 or not. You can do it like this.

[0229] Also, the type of flip-flop 161 can be defined by the configuration data. Specifically, the flip Flop 161 is a D-type flip-flop, a T-type flip-flop, and a JK-type flip-flop. The flip-flop may have the function of either a flip-flop or an RS flip-flop.

[0230] 16(B) shows another example of the LE 101. 01 has a configuration in which an AND circuit 166 is added to the LE 101 shown in FIG. 16(A). The AND circuit 166 receives the signal from the flip-flop 161 as a positive logic input. The signal INIT for initializing the potential of the wiring 111 shown in FIG. With the above configuration, the voltage of the wiring 111 is controlled in accordance with the signal INIT. When the potential is initialized, the output signal from the LE 101 is set to the same potential as the wiring 125. Therefore, the plurality of wirings 1 to which the output signal from LE 101 is given as shown in FIG. This can prevent a large amount of current from flowing between the wiring 23 and the wiring 111. , it is possible to prevent damage to the PLD from occurring.

[0231] 16(C) shows another example of the LE 101. 01 is a LE 101 shown in FIG. 16(A) with a multiplexer 168 and a configuration In FIG. 16(C), a multiplication memory 169 is added. The lexer 168 receives the output signal from the LUT 160 and the output signal from the flip-flop 161. The multiplexer 168 then inputs the configuration memory. The two output signals are generated according to the configuration data stored in the The multiplexer 168 has a function of selecting and outputting either one of the signals. is output from the first output terminal 164 and the second output terminal 165.

[0232] <PLD top view> FIG. 17 shows a top view of a PLD 100 as an example.

[0233] In FIG. 17, the PLD 100 includes a logic array 170, an IO 150, and a PLL (phase locked loop). The arithmetic unit 170 includes a logic circuit (lock loop) 172, a RAM 173, and a multiplier 174. .

[0234] The logic array 170 includes a plurality of LEs 101 and wiring and The PLL 172 includes a wiring resource 175 including a switch. The RAM 173 has a function to store data used in logical operations. The multiplier 174 corresponds to a logic circuit dedicated to multiplication. If a multiplication function is included, the multiplier 174 does not necessarily have to be provided.

[0235] In FIG. 17, the configuration data defining the logic circuit of each LE 101 is This example shows a case where the data is stored in a memory element provided outside the PLD 100. However, the memory element may be provided in the PLD 100.

[0236] <LUT configuration example> In this embodiment, a configuration example of the LUT 160 included in the LE 101 will be described. 160 can be configured with multiple multiplexers. The configuration data is input to either the input terminal or the control terminal of the lexer. The configuration can be such that:

[0237] FIG. 18A shows one aspect of the LUT 160 included in the LE 101.

[0238] In FIG. 18(A), the LUT 160 has seven 2-input multiplexers (multiplexers). multiplexer 31, multiplexer 32, multiplexer 33, multiplexer 34, multiplexer The multiplexer 35, the multiplexer 36, and the multiplexer 37 are used. The input terminals of the multiplexer 31 to the multiplexer 34 are connected to the input terminals M1 to M8 of the LUT 160. is equivalent to

[0239] The control terminals of the multiplexers 31 to 34 are electrically connected to each other. The control terminal corresponds to the input terminal IN3 of the LUT 160. The output terminal of the multiplexer 32 is electrically connected to the two input terminals of the multiplexer 35. The output terminals of the multiplexers 33 and 34 are connected in series. The multiplexer 35 and the multiplexer 36 are electrically connected to each other. The control terminals of the LUT and the multiplexer 36 are electrically connected to each other. 160. The output terminal of the multiplexer 35 and the The output terminal of the multiplexer 36 is electrically connected to two input terminals of the multiplexer 37 . The control terminal of the multiplexer 37 corresponds to the input terminal IN1 of the LUT 160. The output terminal of the lexer 37 corresponds to the output terminal OUT of the LUT 160 .

[0240] The configuration is input from the configuration memory to the input terminals M1 to M8. The output signal corresponds to the configuration data stored in the simulation memory. By inputting the value, the type of logical operation performed by the LUT 160 can be determined. do.

[0241] For example, in the LUT 160 of FIG. 18A, the input terminals M1 to M8 are connected to the From the configuration memory, the digital values ​​are "0", "1", "0", "1", "0". , "1", "1", "1" are stored in the configuration memory. When the output signals corresponding to the configuration data are input, the The function of the equivalent circuit can be realized.

[0242] FIG. 18B shows another aspect of the LUT 160 included in the LE 101.

[0243] In FIG. 18(B), the LUT 160 has three 2-input multiplexers (multiplexers). A multiplexer 41, a multiplexer 42, a multiplexer 43, and a two-input OR circuit 44 are used. It is composed of:

[0244] The output terminal of the multiplexer 41 and the output terminal of the multiplexer 42 are connected to the multiplexer The output terminal of the OR circuit 44 is electrically connected to the two input terminals of the multiplexer 43. The output terminal of the multiplexer 43 is electrically connected to the control terminal of the LUT. This corresponds to the output terminal OUT of 160.

[0245] The control terminal A1, input terminal A2 and input terminal A3 of the multiplexer 41 The control terminal A6, the input terminal A4 and the input terminal A5 of the lexer 42, and the input terminal A of the OR circuit 44 The configuration memory is then connected to either input terminal A7 or input terminal A8. The output signal corresponds to the configuration data stored in the simulation memory. By inputting the value, the type of logical operation performed by the LUT 160 can be determined. do.

[0246] For example, in the LUT 160 of FIG. 18B, the input terminal A2, the input terminal A4, the input terminal A5, control terminal A6, and input terminal A8 receive digital values ​​from the configuration memory. The configuration memory is set to "0", "1", "0", "0", "0". When the output signals corresponding to the stored configuration data are input, The function of the equivalent circuit shown in FIG. 18(C) can be realized. The input terminal A1, input terminal A3, and input terminal A7 are the input terminals IN1, IN2, and This corresponds to input terminal IN3.

[0247] In addition, in Fig. 18(A) and Fig. 18(B), the L Although the example of UT160 is shown, it is possible to use a LUT1 with more input multiplexers. It could be 60.

[0248] In addition to the multiplexer, the LUT 160 may also include diodes, resistors, and logic circuits (or The circuit may further include any one or all of a logic circuit (or a logic element) and a switch. are logic elements), buffers, inverters, NAND circuits, NOR circuits, three-stage A clock buffer, a clocked inverter, etc. can be used as a switch. For example, an analog switch, a transistor, etc. can be used.

[0249] In addition, by using the LUT 160 shown in FIG. 18(A) or FIG. 18(B), Although the example shows a case where a logical operation with three inputs and one output is performed, this is not limited to this. By appropriately defining the configuration data to be input, more input is possible. , it is possible to realize logical operations of many outputs.

[0250] <Example of cell cross-sectional structure> 19 shows the transistor 130t and the transistor 130t included in the cell 140 shown in FIG. The cross-sectional structures of the capacitor 132 and the transistor 1t are shown as examples.

[0251] In this embodiment, the transistor 13 having a channel formation region in an oxide semiconductor film The transistor 111 and the capacitor element 132 are formed on a single crystal silicon substrate having a channel forming region. 1 shows an example in which the resistor 130t is formed.

[0252] The transistor 130t is made of amorphous, microcrystalline, polycrystalline, or single-crystalline silicon. Alternatively, a semiconductor film such as germanium can be used for the active layer. The active layer of the transistor 130t may be made of an oxide semiconductor. When a conductor is used for the active layer, the transistor 131t is stacked on the transistor 130t. The transistors 131t and 130t may not be formed in the same layer. It may be formed.

[0253] When forming the transistor 130t using thin-film silicon, a method such as plasma CVD is used. Amorphous silicon produced by vapor phase growth or sputtering, and amorphous silicon laser Polycrystalline silicon and single crystal silicon wafers are crystallized by laser annealing and other processes. It is possible to use single crystal silicon or the like in which hydrogen ions or the like are implanted to peel off the surface layer.

[0254] The semiconductor substrate 400 on which the transistor 130t is formed may be, for example, an n-type or p-type conductive substrate. Silicon substrates with molds, germanium substrates, silicon germanium substrates, compound semiconductors Substrates (GaAs substrate, InP substrate, GaN substrate, SiC substrate, GaP substrate, GaInAs In FIG. 19, a substrate having n-type conductivity (e.g., a P substrate, a ZnSe substrate, etc.) can be used. A case where a single crystal silicon substrate is used is shown as an example.

[0255] The transistor 130t is separated from other transistors by an insulating film 401 for element isolation. The insulating film 401 for element isolation is formed by a selective oxidation method (LOCOS). (Local Oxidation of Silicon) method) or trench isolation method etc. can be used.

[0256] Specifically, the transistor 130t has a source region or The impurity region 402 and the impurity region 403 functioning as a drain region, and the gate electrode 40 4, and a gate insulating film 405 provided between the semiconductor substrate 400 and the gate electrode 404. The gate electrode 404 is connected to the impurity region 402 with a gate insulating film 405 sandwiched therebetween. The channel forming region is formed between the solid regions 403 .

[0257] An insulating film 409 is provided over the transistor 130t. The insulating film 409 has an opening. In the opening, impurity regions 402 and 403 are formed. The wiring 410 and the wiring 411 are electrically connected to the gate electrode 404. A line 412 is formed.

[0258] The wiring 410 is electrically connected to a wiring 415 formed on the insulating film 409. The wiring 411 is electrically connected to a wiring 416 formed on the insulating film 409. The wiring 412 is electrically connected to a wiring 417 formed on the insulating film 409 .

[0259] An insulating film 420 and an insulating film 440 are stacked in this order over the wirings 415 to 417. An opening is formed in the insulating film 420 and the insulating film 440. In the portion, a wiring 421 electrically connected to the wiring 417 is formed.

[0260] 19, the transistor 131t and the capacitor 132 are formed over the insulating film 440. It has been done.

[0261] The transistor 131t has a semiconductor film 430 including an oxide semiconductor and a semiconductor film 430 including a semiconductor A conductive film 432 and a conductive film 433 functioning as a source electrode or a drain electrode are formed on the conductive film 430. a semiconductor film 430, a conductive film 432, and a gate insulating film 431 on the conductive film 433; , which is located on the gate insulating film 431 and between the conductive film 432 and the conductive film 433, The conductive film 433 has a gate electrode 434 overlapping with the wiring 421. is electrically connected to

[0262] A conductive film 435 is provided over the gate insulating film 431 so as to overlap with the conductive film 433. The conductive film 433 and the conductive film 435 are overlapped with each other with the gate insulating film 431 interposed therebetween. The portion functions as a capacitance element 132.

[0263] In FIG. 19, the capacitor element 132 is provided on the insulating film 440 together with the transistor 131t. The capacitor 132, together with the transistor 130t, It may be provided under the insulating film 440 .

[0264] Then, an insulating film 441 and an insulating film 442 are formed over the transistor 131t and the capacitor 132. The insulating film 441 and the insulating film 442 are stacked in this order. The conductive film 443 in contact with the gate electrode 434 in the opening is formed on the insulating film 441. is placed above.

[0265] 19, the transistor 131t has a gate electrode 434 formed on the semiconductor film 430. It is sufficient if it is provided on at least one side, but it is also possible to provide a pair of semiconductor films 430 sandwiched between them. The gate electrode may be formed of:

[0266] The transistor 131t has a pair of gate electrodes sandwiching a semiconductor film 430 therebetween. When the gate electrode is connected to the transistor, a signal is applied to one of the gate electrodes to control whether the transistor is in a conducting or non-conducting state. The other gate electrode may be in a state where a potential is applied from another source. In this case, the pair of gate electrodes may be given the same potential, or the other gate electrode A fixed potential such as a ground potential may be applied only to the other gate electrode. By controlling the level, the threshold voltage of the transistor can be controlled.

[0267] 19, the transistor 131t has one channel corresponding to one gate electrode 434. The example shows a single gate structure having a transistor formation region. The transistor 131t has a plurality of gate electrodes electrically connected to each other, so that the transistor 131t has a plurality of gate electrodes electrically connected to each other. A multi-gate structure having a plurality of channel forming regions may also be used.

[0268] <Transistor configuration example> Next, a structure example of a transistor having a channel formation region in an oxide semiconductor film will be described. I will explain.

[0269] A transistor 601 shown in FIG. 20 includes a conductive film 602, a conductive film 603, and a conductive film 604 over an insulating surface. The gate electrode 604 is located between the conductive film 602 and the conductive film 603. The transistor 601 is formed by a conductive film 602 and a conductive film 603 provided on an insulating surface. 603 and a gate electrode 604. An insulating film 605 is located between the gate electrode 603 and the gate electrode 604.

[0270] The transistor 601 has an island-shaped insulating film on the gate electrode 604 and the insulating film 605. 606 and an island-shaped oxide semiconductor film 607 located over the insulating film 606. The transistor 601 includes a conductive film 602, a source electrode 608 over an oxide semiconductor film 607, and a , and a drain electrode 609 over the conductive film 603 and the oxide semiconductor film 607 .

[0271] The transistor 601 includes an oxide semiconductor film 607, a source electrode 608, and a drain electrode 609. An insulating film 610 is provided on the electrode 609 .

[0272] The source electrode 608 and the drain electrode 609 have a thickness that gradually decreases at their ends. Alternatively, the source electrode 608 and the drain electrode 609 are With the above configuration, the thickness of the source electrode 608 and the drain electrode 609 may be continuously reduced. The insulating film 610 provided on the source electrode 609 is connected to the source electrode 608 and the drain electrode 60 The coverage at the edge of the 9 can be improved.

[0273] The transistor 601 has a gate electrode 611 provided over the insulating film 610. The gate electrode 611 overlaps with the oxide semiconductor film 607 with an insulating film 610 interposed therebetween. do.

[0274] In FIG. 20, the transistor 601 is arranged so as to cover the gate electrode 611 and the insulating film 610. 6 illustrates an example in which an insulating film 612 is provided as shown in FIG.

[0275] 21, a transistor 630 having a channel formation region in a single crystal silicon substrate is The state in which the transistor 601 shown in FIG. 20 is stacked is shown in a cross-sectional view.

[0276] As shown in Figure 21, the transistor 630 is formed on a semiconductor substrate 631. The substrate 631 may be, for example, a single crystal silicon substrate having n-type or p-type conductivity, a compound semiconductor, or the like. Conductor substrates (GaAs substrates, InP substrates, GaN substrates, SiC substrates, GaP substrates, GaIn In FIG. 21, a substrate having n-type conductivity can be used. This example shows the case where a single crystal silicon substrate is used.

[0277] The transistor 630 is separated from other transistors by an insulating film 632 for element isolation. The insulating film 632 for element isolation is electrically isolated from the semiconductor element. LOCOS (Local Oxidation of Silicon) method or Trench isolation or the like can be used.

[0278] The region where the n-channel transistor 630 is formed is given p-type conductivity. By selectively introducing an impurity element, a p-well 633 is formed. When a p-channel transistor is formed using a semiconductor substrate having electrical conductivity, In the region where the N-type transistor is formed, an impurity element that gives n-type conductivity is selected. By selectively introducing ions, a region called an n-well is formed.

[0279] Specifically, transistor 630 includes a source region or drain region formed in a semiconductor substrate 631. The impurity regions 634 and 635 functioning as drain regions, and the semiconductor substrate 631 and a gate insulating film 637 provided between the gate electrode 636. is formed between the impurity region 634 and the impurity region 635 with the gate insulating film 637 interposed therebetween. The channel forming region overlaps the channel forming region.

[0280] An insulating film 638 is provided over the transistor 630. The insulating film 638 has an opening. In the opening, an impurity region 634, an impurity region 635, and a gate electrode are formed. Wiring 639 and wiring 640 are formed in contact with 636, respectively.

[0281] The wiring 639 is connected to a wiring 641 formed on the insulating film 638. 640 is connected to wiring 642 formed on the insulating film 638 .

[0282] An insulating film 643 is formed on the wiring 641 and the wiring 642 .

[0283] 21, the transistor 601 is formed over the insulating film 643. O3 is connected to the gate electrode of transistor 630.

[0284] FIG. 22 shows a layer in which the transistor 630 is formed and a layer in which the transistor 601 is stacked. 1 shows a cross-sectional view of another wiring layer formed between two adjacent layers.

[0285] In FIG. 22, wiring 645 is formed on the insulating film 643. An insulating film 646 is formed on the wiring 645. An opening is formed in the insulating film 646. In the opening, a wiring 647 connected to the wiring 645 is formed. On the insulating film 646, a wiring 648 connected to the wiring 647 is formed. An insulating film 649 is formed on the wiring 648. An opening is formed in the insulating film 649. In the opening, a wiring 650 connected to the wiring 648 is formed. A transistor 601 is formed on the film 649, and a wiring 650 is connected to the conductive film 603. It continues.

[0286] In FIG. 23, another wiring layer is formed on the layer on which the transistor 601 is formed. The situation is shown in a cross-sectional view.

[0287] In FIG. 23, an insulating film 651 is formed over a transistor 601. The wiring 652 is formed on the film 651, and the wiring 652 is connected to the insulating film 651 and the insulating film 61. 0, and in an opening formed in the insulating film 612, An insulating film 653 is formed on the insulating film 651 and the wiring 652. The wiring 654 is formed on the insulating film 53 through an opening formed in the insulating film 653. In the portion, the insulating film 653 is connected to the wiring 652. In addition, a wiring 656 is formed on the insulating film 655. The element 56 is connected to the wiring 654 through an opening formed in the insulating film 655 .

[0288] <Configuration memory configuration example> Next, FIG. 24 shows the circuit configuration of the memory cells in the configuration memory. Here is an example.

[0289] In one embodiment of the present invention, the memory cell 200 includes at least two switches 201 to 205. 24, the memory cell 200 includes a capacitor 206 and A capacitor element 207 may be included.

[0290] Although FIG. 24 shows an example in which one transistor is used as a switch, A plurality of transistors may be used as a switch.

[0291] Switch 201 connects the configuration device to node FD1 in memory cell 200. Specifically, the switch 20 has a function of controlling the supply of the potential of the first signal including the data. When 1 is in a conductive state (ON), the configuration data provided on the wiring 210 The potential of the first signal including the potential of the switch 201 is supplied to the node FD1. When the node F is in the OFF state, the potential of the node FD1 is maintained. It is electrically connected to D1 and has a function of holding the potential of the node FD1.

[0292] The selection of the conductive or non-conductive state of the switch 201 is determined by a signal applied to the wiring 212. This is done according to the potential of the signal.

[0293] The switch 202 electrically connects the wiring 208 and the wiring 209 in accordance with the potential of the node FD1. Specifically, when the switch 202 is in a conductive state, the wiring 2 08 and the wiring 209 are electrically connected. When this occurs, the wiring 208 and the wiring 209 are electrically isolated from each other.

[0294] Also, the switch 203 is connected to the node FD2 in the memory cell 200. Specifically, the switch has a function of controlling the supply of the potential of the second signal including the application data. When the switch 203 is in a conductive state (ON), the configuration data provided to the wiring 211 is The potential of the second signal including the data is supplied to the node FD2. When the capacitor 207 is in a non-conducting state (off), the potential of the node FD2 is held. The transistor FD1 is electrically connected to the node FD2 and has a function of holding the potential of the node FD2.

[0295] The selection of the conductive or non-conductive state of the switch 203 is determined by a signal applied to the wiring 212. This is done according to the potential of the signal.

[0296] The switch 204 electrically connects the wiring 214 and the wiring 209 in accordance with the potential of the node FD2. Specifically, when the switch 204 is in a conductive state, the wiring 2 14 is electrically connected to the wiring 209. When the switch 204 is in a non-conducting state, When this occurs, the wiring 214 and the wiring 209 are electrically isolated from each other.

[0297] The wiring 208 is supplied with a high-level potential VDD, and the wiring 214 is supplied with a low-level potential VDD. The potential VSS is applied to the memory cell. When writing to the register 200, the potential of the first signal and the potential of the second signal are inverted in polarity. Therefore, the logic level of the switch 202 is inverted. When one of the switches 204 is in a conducting state, the other is in a non-conducting state. Which of switch 202 and switch 204 is in a conducting state and which is in a non-conducting state? The potential of the first signal and the second signal, i.e., the configuration data, determines whether the Therefore, the potential applied to the wiring 209 is determined by the configuration data. , it is determined whether the potential is a high level potential VDD or a low level potential VSS.

[0298] The switch 205 has a function of controlling the electrical connection between the wiring 209 and the wiring 215. Specifically, when the switch 205 is in a conductive state, the wiring 209 and the wiring 215 The potential of the wiring 209 is applied to the wiring 215. When 5 is in a non-conductive state, the wiring 209 and the wiring 215 are electrically isolated.

[0299] In the configuration memory shown in FIG. 24, the switch 201 and the switch The transistor used in the transistor 203 holds the potentials of the nodes FD1 and FD2. Therefore, it is desirable that the transistor has an extremely small off-state current. A semiconductor film with a wider band gap than silicon and a lower intrinsic carrier density than silicon A transistor characterized by having a channel formation region has a significantly small off-state current. Therefore, it is suitable for use in the switches 201 and 203. As the material, for example, oxide semiconductors with a band gap twice as large as that of silicon are used. The transistors using the above semiconductors are generally silicon-based. Compared to transistors made of semiconductors such as silicon or germanium, Therefore, the transistor having the above configuration can be used as the switch 201 and the By using the switch 203, the charges held at the nodes FD1 and FD2 are This can prevent leaks.

[0300] In a configuration memory according to one aspect of the present invention, configuration data is According to the data, the wiring 215 is set to either a low level potential VSS or a high level potential VDD. Therefore, the wiring that outputs the configuration data 215, a controller that reads configuration data by applying or not applying a voltage to the Unlike configuration memory, the configuration data is stored in memory cells The configuration can be performed correctly without precharging the line 215 before reading from 00. Therefore, the configuration memory drive There is no need to provide a circuit for precharging in the circuit, and the programmable logic device The area of ​​the vise can be kept small.

[0301] After the PLD is powered on, the configuration data is lost and the node F Even if D1 and node FD2 are in an unstable state, the potential of the first signal and the potential of the second signal are By setting both the wirings 208 and 214 to a low potential, the wiring 208 and the wiring 214 are electrically connected to each other. This can prevent the formation of cavities.

[0302] In addition, in FIG. 24, the switch 20 is turned on in only one of the two memory cells 200. 5 is turned on, the configurations stored in the two memory cells 200 are One of the configuration data is read from one wiring 215. However, in one aspect of the present invention, In the configuration memory according to the present invention, the configuration stored in the plurality of memory cells 200 is The configuration data is read out from different wirings 215. That's fine.

[0303] In addition to the above configuration, the potential of the wiring 215 can be set to either a high level or a low level. A latch 182 having a function of keeping the latch 182 electrically connected to the wiring 215 is provided. In one aspect of the present invention, with the above configuration, after the power is turned on, the wiring 21 The potential of 5 can be kept at either high or low level, so when the power is turned on After this, a through current occurs in the circuits such as the LUT and multiplexer connected to the wiring 215. This can prevent this from happening.

[0304] When the potential VDD of the wiring 210 is applied to the node FD1 through the switch 201, In reality, the node FD1 has a potential of 0V, which is equal to the threshold voltage of the transistor used in the switch 201. Therefore, even if the switch 205 is in a conductive state, the wiring 21 It is difficult to raise the potential of the latch 1 to the same potential VDD as the wiring 208. By providing 82, the potential of the wiring 215 can be raised to the potential VDD. 15 can be prevented from becoming an intermediate potential between the potential VSS and the potential VDD. When the potential VSS of 210 is applied to the node FD1 through the switch 201, the node F The potential of D1 is dropped by the threshold voltage of the transistor used in switch 201. Similarly, the potential VSS of the wiring 211 is applied to the node FD2 via the switch 203. When the potential of the node FD2 is equal to or higher than the threshold voltage of the transistor used in the switch 203, Therefore, the switch 202 or the switch 204 is not dropped by a certain amount. In fact, the switch 202 or the switch 204 can be turned off. No through current flows.

[0305] As described above, when an n-channel transistor is used for the switch 201, It is easy to set the node FD1 to the potential VSS, but it is difficult to set the node FD1 to the potential VDD. It is difficult to do this when the threshold voltage of the transistor is taken into consideration. If a p-channel transistor is used, the switch 202 is completely turned off. This makes it difficult to achieve this, and a through current tends to flow through the switch 202. When an n-channel transistor is used for the switch 201, the switch 202 has It is preferable to use an n-channel transistor to prevent shoot-through current. The same can be said for switch 203 and switch 204. That is, switch 203 has n switches. When n-channel transistors are used, the switch 204 is The use of a resistor is desirable to prevent shoot-through current.

[0306] When a p-channel transistor is used for the switch 201, the node FD1 is It is easy to set the node FD1 to the potential VDD, but setting the node FD1 to the potential VSS is This is difficult when the threshold voltage of the transistor is taken into consideration. When a transistor is used, it is difficult to make the switch 202 completely non-conductive. This makes it easier for a through current to flow through switch 202. When a p-channel transistor is used, the switch 202 is It is preferable to use a transistor to prevent a through current. The same can be said for the switch 204. That is, if the switch 203 is a p-channel transistor, When a transistor is used, a p-channel transistor is used for the switch 204. This is desirable to prevent shoot-through current.

[0307] In addition to the above configuration, a wiring 216 to which a predetermined potential is applied, and a wiring 216 and a wiring A switch 217 may be provided to control the electrical connection with the sensor 215. In one embodiment, the potential of the wiring 215 is initialized to a predetermined level by the above configuration. Therefore, after the programmable logic device is powered off, the wiring Even if the potential of 215 becomes unstable, the configuration data is lost. Even if the power is turned on, it is possible to prevent the LUT and multiplexer in the LE from malfunctioning. can be done.

[0308] In addition, in the configuration memory, the wiring 210 and the wiring 211 are connected to the LE and the switch. The wiring 212 and the wiring 213 are arranged along the direction in which the rows of the cells of the switch circuit are arranged. When placing the wires in a direction intersecting the above direction, the wires are placed on one wiring 215 in a multi-context manner. Even if the number of corresponding memory cells 200 increases, the wiring 210 or the wiring 211 and the wiring 21 5, i.e., the distance between the switch circuit and LE, can be prevented from becoming long. Therefore, in the multi-context method, multiple switch circuits and LEs are electrically connected. This can suppress the increase in the load of the parasitic resistance and capacitance of the wiring that connects the switch circuit. This can prevent the noise from increasing.

[0309] Next, the two memory cells 200, the latch 182, and the switch 217 shown in FIG. , 216 and 220. FIG. 25 shows an example of the connection configuration of the set 220 within the logic element.

[0310] The LE 221 shown in FIG. 25 is a configuration memory configured of a plurality of sets 220. 162, a configuration memory 169 consisting of a plurality of sets 220, and a logic The sensor 225 and the latch 224 are connected to the sensor 226.

[0311] The logic cell 225 includes an LUT, a multiplexer, a flip-flop, etc. The configuration memory 162 stores the configuration data to be input to the LUT of the logic cell 225. The configuration memory 169 stores logic The configuration data that is input to the multiplexer of cell 225 is stored.

[0312] Furthermore, a signal including data given to the wiring 223 is input to the LUT of the logic cell 225. A latch 224 for holding data is connected to the wiring 223.

[0313] A signal INIT for controlling the switching of the switch 217 is input to the wiring 222. can be.

[0314] In one embodiment of the present invention, the LEs 221 are arranged in a row, so that the configuration The matrix memory 162 and the configuration memory 169 also have the matrix ( Mem), they are arranged in a matrix. The PLD 162 and the configuration memory 169 can be densely arranged. The layout area can be reduced.

[0315] Next, an example of the configuration of an IO in which a plurality of the above-described sets 220 are provided will be described with reference to FIG. The IO 230 shown in FIG. 26 includes a set 220a to a set 220d, a latch 224, and an Ex An OR circuit 231a, an ExOR circuit 231b, a tri-state buffer 232, and an The circuit has a converter 233, a buffer 234, and a terminal 236.

[0316] The output signal of the set 220a, specifically the signal having the potential applied to the wiring 215 in FIG. , and are input to the ExOR circuit 231a. The signal including data is input from the ExOR circuit 231a. The output signal of the ExOR circuit 231a is The signal is input as signal A to the tri-state buffer 232 .

[0317] Also, the output signal of the set 220b, specifically, the potential applied to the wiring 215 in FIG. The signal is input to the ExOR circuit 231b. The signal including data is input from the EXOR circuit 231b. The signal EN determines whether the state buffer 232 is set to high impedance. The data is input to the state buffer 232 .

[0318] The ExOR circuit 231a and the ExOR circuit 231b are stored in the sets 220a and 220b. The polarity of the signals on the wiring 213a and the wiring 213b is determined according to the entered configuration data. In this way, the input An ExOR circuit 231a and an ExOR circuit 231b are provided in the IO to invert the polarity of the input signal. By doing so, it is possible to realize the desired arithmetic circuit with a small number of LEs, and as a result, the PLD It is possible to configure a large-scale circuit as a whole. Also, it is possible to configure a desired arithmetic circuit with a small number of LEs. Therefore, the power supply to the LEs not used in the arithmetic circuit is stopped, and the LEs Since the operation of E can be stopped, the power consumption of the PLD can also be reduced. Similarly, on the input side of LE, there are an ExOR circuit 231a and an E An xOR circuit 231b may be provided.

[0319] 24. In addition, the output signal of the set 220d, specifically, the potential applied to the wiring 215 in FIG. The signal is inverted in polarity in inverter 233 and then output to Tris as signal OD. The output signal of the set 220d is input to the tri-state buffer 232. It has a function of controlling whether the output of the buffer 232 is open drain or not. That is, when the potential of the output signal of the set 220d is at a low level, the tri-state buffer 232 It operates as a normal tri-state buffer. The potential of the signal A is at a low level, and the potential of the signal EN is at a high level. When the tri-state buffer 232 is in the low-level potential, the output terminal of the tri-state buffer 232 is in the low-level potential. In addition, the potential of the output signal of the set 220d is at a high level, but the potentials of the signals A and EN are When the combination is different from the above, that is, when the potential of signal A is at a low level, and Except when the potential of the signal EN is at a high level, the tri-state buffer 232 becomes impedance.

[0320] If a pull-up resistor is added to the outside of the tri-state buffer 232, Even when the state buffer 232 is in a high impedance state, the tri-state buffer 23 The potential of the output signal from the tri-state buffer 23 can be set to a high level. By using IO230, which has a configuration in which a pull-up resistor is added externally to IO2, Semiconductor devices with different voltages can be electrically connected via the IO 230.

[0321] FIG. 27 shows an example of the circuit configuration of the tri-state buffer 232. The state buffer 232 is a NAND gate to which the signals OD, EN, and A are input. circuit 501, an inverter 502 to which the output signal of the NAND circuit 501 is input, and an inverter An inverter 503 receives the output signal of the inverter 502, and an output signal of the inverter 503 is The tri-state buffer 504 also has a p-channel transistor 508. 232 is an inverter 504 to which a signal EN is input, an output signal of the inverter 504, and A NOR circuit 505 receives the signal A and the output signal of the NOR circuit 505. an inverter 506; an inverter 507 to which the output signal of the inverter 506 is input; and an n-channel transistor 509 to which the output signal of the inverter 507 is input.

[0322] The p-channel transistor 508 and the n-channel transistor 509 are connected to each other's drains. The potential of the drain is output as an output signal Y to the tri-state buffer 2. It is output from 32.

[0323] In addition, the drains of the p-channel transistor 508 and the n-channel transistor 509 are connected to The output terminal of the inverter 510 and the input terminal of the inverter 511 are connected. The input terminal of the inverter 510 is connected to the output terminal of the inverter 511. .

[0324] The inverters 502 and 503 function as buffers and are not necessarily It is not necessary to provide it in the state buffer 232. 07 functions as a buffer and does not necessarily need to be provided in the tri-state buffer 232. There's no need.

[0325] The output signal of tri-state buffer 232 is provided to terminal 236 .

[0326] In addition, the signal input from the terminal 236 to the IO 230 is switched via the buffer 234. is input to the circuit.

[0327] In addition, FIG. 26 illustrates a case where the set 220c is provided as a dummy in the IO 230. By providing the set 220c, it is possible to add functions to the set 220 by slight mask modification. In addition, the mask layout of the set 220 is easier than when the set 220c is not provided. When the periodicity of the mask is low, the periodicity of the mask can be increased. In the photolithography process, interference of light emitted from the exposure device can cause flashes. The width of conductive films, insulating films, semiconductor films, etc. formed by photolithography is narrowed in parts. However, in FIG. 26, by providing the set 220c, , the periodicity in the layout of the masks in set 220 can be increased, thereby Prevents defects in the shape of conductive, insulating, and semiconductor films after lithography processes It is possible.

[0328] <Explanation of PLD mask drawing> Next, a mask drawing of a PLD according to one embodiment of the present invention is shown in FIG. A row of logic elements (denoted by LE) is provided between rows of switch circuits (denoted by sw). Also, there are switches between the rows of IO elements (denoted as I / O) and the rows of logic elements. A row of switch circuits is provided.

[0329] Also, in FIG. 28, a plurality of configuration memories, such as those shown in FIG. 16(C), are used. A logic element having a plurality of configurations is used. The memory is also arranged in a matrix (denoted Mem). In the example shown in FIG. 1, logic elements, IO elements, and switch circuits are arranged in rows. Therefore, the configuration memory included in the logic elements is also arranged in a matrix. Therefore, in a PLD according to one aspect of the present invention, as shown in FIG. The driver circuits (bd, wd) control the operation of the switch circuit and the configuration memory. The area where the logic elements, IO elements, and switch circuits are located is shown. Configuration memory and switches can be grouped together around the periphery of the area. When the circuit is regarded as a memory cell array, the area in which the memory cell array is arranged is can be considered to overlap with the area where the LE is arranged. The above configuration can reduce the layout area of ​​the PLD. In the mask drawing, Pad corresponds to a terminal, and cc corresponds to the operation of the drive circuit bd, drive circuit wd, etc. It corresponds to the controller that controls the

[0330] Note that the configuration memory is not arranged in a matrix as shown in Figure 28. In this case, the level of the wiring that electrically connects the driver circuit and the configuration memory is In addition, multiple drivers are required for each small area of ​​the configuration memory. In this case, the level of wiring for supplying control signals to each drive circuit is The layout becomes complicated.

[0331] 29 shows the connection between the LE 101 and the switch circuits 120a to 120c. An example of the structure is shown in Figure 29. The electrical connection between the output terminal of LE101 and the input terminal of LE101 is The switch circuit 120 that controls the connection is shown as a switch circuit 120a. A switch circuit that controls the electrical connection between the output terminal of the LE101 (not shown) and the input terminal of the LE101 120 is shown as a switch circuit 120b. The switch circuit 120 controls the electrical connection of the input terminals (not shown) Shown as c.

[0332] Also, as shown in FIG. 29, in one embodiment of the present invention, the output signal of each LE 101 is given The wiring 195 and the wiring 196 are arranged between the adjacent LEs 101. This allows the wiring length from each LE 101 to the switch circuit 120 to be kept short. Therefore, the current supply capacity of the buffer on the output side of LE101 can be small, The size of the buffer can be kept small.

[0333] In addition, wiring is provided to supply output signals to adjacent LEs without going through a switch circuit. These wirings are used when configuring shift registers, adders, subtractors, etc. with multiple LEs. Furthermore, by adding a half adder and a full adder for 1 bit to the LE, Addition and subtraction circuits that consist of several LEs can be constructed with one LE. Therefore, a desired arithmetic circuit can be realized with a small number of LEs.

[0334] In addition, the LEs are arranged in a row, and adjacent LEs are connected without a switch circuit. If the PLD is connected to the PLD, the PLD is similar to that disclosed in U.S. Pat. No. 4,870,302. are different, and the wiring between LEs can be shortened.

[0335] <Cell Comparison> Next, a cell having a transistor using an OS film and a cell having a transistor using a silicon (Si) film were fabricated. The difference in operation between a cell having a transistor and a pair of inverters will now be described.

[0336] FIG. 30 shows a cell 140a having a transistor using an OS film and a silicon (Si) film. 1 and 2. A circuit diagram of a cell 140b having a pair of inverters and transistors used is shown. FIG. 30 shows the timing diagram of the potentials of the nodes FD in the cells 140a and 140b. and the voltage of the signal IN containing the configuration data, which is applied to the wiring 121. 10 shows a timing chart of the same.

[0337] In the cells 140a and 140b, the conductive or non-conductive state of the transistor 131t is controlled by the potential of the wiring 122, and the configuration data is supplied from the wiring 121. The potential corresponding to the voltage at the node FD is maintained, and the transistor 130t is turned on or off. The timing chart shown in FIG. 30 is for when the transistor 130t is an n-channel transistor. This shows an example of a panel type.

[0338] In the cell 140b, the inverter 180 and the inverter 181 cause the potential of the node FD to On the other hand, in the cell 140a, the transistor 131t using the OS film is turned off. The current is so small that the potential at node FD is maintained. When the transistor 131t is in a non-conductive state, the node FD is connected to other electrodes and wirings. Therefore, the floating electrodes between the cells 140a and 140b have extremely high insulating properties. 40a is capable of holding the potential of the node FD with a smaller number of transistors. do.

[0339] In addition, in the cell 140a, when the transistor 131t is in a non-conductive state, the node FD floats. Since the cell is in a free state, the boosting effect described below can be expected. In 140a, when the node FD is in a floating state, the potential of the signal IN changes from a low level to a high level. As the voltage changes, a capacitance is formed between the source and gate of transistor 130t. The potential of node FD rises due to Cgs. The rise in the potential of node FD is The logic level of the configuration data input to the gate of transistor 130t Specifically, the configuration data written to cell 140a When the data is "0", the transistor 130t is in weak inversion mode, so the potential of the node FD The capacitance Cgs that contributes to the increase in the Specifically, the capacitance Cos includes the capacitance between the gate electrode and the source region. The overlap capacitance formed in the overlapping region and the capacitance formed between the gate electrode and the source electrode On the other hand, the configuration written in the cell 140a includes the parasitic capacitance. When the data is "1", the transistor 130t is in strong inversion mode, so the node FD The capacitance Cgs that contributes to the increase in the potential of the gate electrode and the gate The capacitance Cod formed between the drain electrode and the channel forming region and the gate electrode Therefore, the configuration data is In the case of ", the capacitance Cgs of the transistor 130t that contributes to the increase in the potential of the node FD is Therefore, the value of cell 14 is larger than that of the case where the configuration data is "0". In 0a, the configuration data is "1" and the configuration is When the data is "0", the potential of the node FD increases more with the change in the potential of the signal IN. This can achieve the boosting effect of raising the speed higher. As a result, the switching speed of the cell 140a is increased when the configuration data is "1". When the configuration data is "0", the transistor 130 t is in a non-conducting state.

[0340] The switches included in the routing resources of a typical PLD are designed to improve integration density. However, in the above switch, there is a problem that the threshold voltage This occurs when the potential of the signal passing through the gate of an n-channel transistor drops. The problem is that the switching speed is reduced. A method using overdrive, in which a high potential is applied to the gate of a transistor, has also been proposed. However, in this case, the reliability of the n-channel transistor used in the switch is reduced. However, in one aspect of the present invention, the above-mentioned boosting effect can Even without using bar drive, the switching speed of cell 140a can be increased by configuring The switching speed can be improved when the application data is "1". There is no need to sacrifice reliability for this purpose.

[0341] In the case of the cell 140b, the potential of the node FD also rises due to the boosting effect. However, the inverter 180 and the inverter 181 instantly return the potential of the node FD to the original potential. Therefore, it is possible to benefit from the boosting effect to improve switching speed. I can't.

[0342] Also, in Reference 1 (K.C. Chun, P.Jain, J.H.Lee, and C. H.Kim,”A 3T Gain Cell Embedded DRAM Util izing Preferential Boosting for High Den sity and Low Power On-Die Caches”IEEE Jo urnal of Solid-State Circuits, vol.46, n o.6, pp.1495-1505, June. 2011), Reference 2 (F. Es lami and M. Sima,”Capacitive Boosting fo r FPGA Interconnection Networks” Int. Co nf. on Field Programmable Logic and Appl ications, 2011, pp. 453-458.) Unlike cell 140 Further effects can be expected in a.

[0343] In Reference 1, since DRAM is assumed, there are many memory cells, and the output of the memory cells The connected read bit line (RBL) has a high parasitic capacitance. On the other hand, in the cell 140a, the signal OUT is supplied to the gate of the CMOS. The parasitic capacitance on the output side of a is smaller than that in the case of Reference 1. Therefore, As the potential of the node FD rises due to the capacitance Cgs of The capacitance Cod acts as a secondary booster to increase the potential of the signal OUT. That is, the cell 140a is used as a switch circuit that controls the connection between the wires. When used as a switching element, the secondary boosting effect mentioned above can further improve switching speed. In addition, the cell 140a requires fewer transistors than the cell 140a in the case of Reference 2. The resistor can maintain the increased potential of the node FD.

[0344] To verify the boosting effect described above, the output terminal of each stage is connected to cell 140a or ,Two types of TEGs of 101-stage ring oscillator (RO) circuits in which cell 140b is arranged. The delay time of cell 140a or cell 140b was evaluated based on the oscillation frequency. The n-channel and p-channel transistors of the inverter that constitutes the TEG of the RO circuit The channel widths W of the transistors were set to 16 μm and 32 μm, respectively. The channel width W of the transistor 130t in the cell 140a is 16 μm. The channel width W of the transistor 131t in the cell 140b is 4 μm. The channel width W of the cell 131t is set to 8 μm. The inverter 181 has an n-channel transistor and a p-channel transistor. The channel widths W were set to 4 μm and 8 μm, respectively. The channel length L of all the transistors and p-channel transistors was set to 0.5 μm. The transistor 131t of the cell 140a is made of a CAA containing an In-Ga-Zn oxide. The C-OS film was used, and the channel length L was set to 1 μm. The semiconductor layer was laminated on a transistor using a silicon film.

[0345] Next, the power supply voltage (VDD RO ) and the inverter of cell 140b The power supply voltage (VDD MEM ) is the overdrive voltage Overdrive Voltage and RO1 for the overdrive voltage The delay time per stage was measured. The potential difference between the low level and low level is VDD MEM is equivalent to

[0346] The measurement results of the delay time are shown in Figure 31. In Figure 31, the horizontal axis represents the overdrive voltage (mV ), and the vertical axis indicates the delay time per RO stage. In FIG. 31, the delay time on the vertical axis is DD RO The relative value to the measured delay time when the overdrive voltage is 2.00V and the overdrive voltage is 0V. Also, in Figure 31, VDD RO The solid line indicates the delay time when the voltage is 2.00V, and the 2.2 The delay time at 5V is shown by a dashed line, and the delay time at 2.50V is shown by a dotted line.

[0347] As shown in FIG. 31, the RO circuit with the cell 140a added is more efficient than the RO circuit with the cell 140b added. The delay time is shorter than that of the RO circuit, and the delay time is determined by the configuration of cells 140a and 140b. It was confirmed that they were different.

[0348] As shown in FIG. 31, the overdrive voltage of the cell 140b is increased. The overdrive effect, which improves switching speed by RO The lower the However, in cell 140b, VDD RO More than 0.2 times the amount Even when a bar drive voltage was applied, the switching speed of cell 140a was not reached. In cell 140a, when configuration data is written, the transistor The potential of node FD drops due to the threshold voltage of 131t, so the potential of node FD becomes V DD MEM Nevertheless, the sensor that does not provide an overdrive voltage The cell 140a has a faster switching speed than the cell 140b to which an overdrive voltage is applied. It is noteworthy that the results were high.

[0349] In addition, when the overdrive voltage is the same, the RO circuit with the cell 140a added has a higher cell It was confirmed that the power consumption was smaller than that of the RO circuit with the filter 140b added.

[0350] Furthermore, from the SPICE simulation corresponding to the TEG of the RO circuit, cell 140 In the RO circuit with a added, the potential of node FD increases with the increase in the potential of signal IN. In the calculation, VDD RO As a result of the calculation, the voltage of the signal IN is As the voltage level rises, the voltage is 0.75V when the configuration data is "1" and 0.75V when the configuration data is "0". In this case, it was confirmed that the potential of node FD increased by 0.07V.

[0351] Therefore, in the semiconductor device having the cell 140a, a single Even when using a power supply voltage of 100 V, high performance is achieved, such as reduced power consumption and improved switching speed. It was shown that this can be done.

[0352] Figure 32 shows a micrograph of the prototype PLD. The driver circuit (Bit Driver, Word Driver) that controls the operation of the configuration memory The routing resources (Routing Fabric) include switch circuits and wiring. ic), IO element (User IO), and controller (Configurat ion Controller) and PLE (Programmable Logic Element), the corresponding area is shown enclosed in a rectangle.

[0353] The prototype PLD is a transistor using a CAAC-OS film containing In-Ga-Zn oxide. The prototype PLD has a switch The circuit includes a cell 140a, and the transistor 131t included in the cell 140a is an In-G A CAAC-OS film containing a-Zn-based oxide is used.

[0354] In the PLD shown in FIG. 32, there are 20 PLEs and the configuration memory has The number of memory cells is 7520, the number of IO terminals is 20, and the PLE has standard functions. The transistors using the CAAC-OS film were The n-channel transistor and p-channel transistor were stacked on the silicon film. All the transistors had a channel length of 0.5 μm. The transistor using the CAAC-OS film containing oxide has a channel length L of 1 μm. Ta.

[0355] For comparison, we used SRAM for the configuration memory and A PLD with cell 140b was also fabricated. Compared to D, the layout area of ​​the switch circuit is reduced by 60%, the area of ​​the routing resources is reduced by 52%, and the PL The overall area of ​​D was reduced by approximately 22%.

[0356] The PLD prototyped using cell 140a includes a count-up / down circuit, a shift circuit, For various circuit configurations, for example, with a single power supply voltage of 2.5V and a frequency of 50MHz, It was confirmed that the cell 140a operated normally. Data retention operation: The necessary data is saved in the storage device, and the power supply is intermittently cut off. Normally-off operation was also confirmed.

[0357] FIG. 33 shows a PLD prototyped using cell 140a, which has 13 stages of link circuits, each stage being a PLE. The figure shows the change in oscillation frequency over time when a ring oscillator is configured. In the evaluation, no significant decrease in the oscillation frequency was observed. In the prototype PLD, the configuration memory has good data retention characteristics. It was suggested that this is the case.

[0358] <Examples of electronic devices> The semiconductor device or the programmable logic device according to one embodiment of the present invention may be used in a display device, Personal computers, image playback devices equipped with recording media (typically DVDs: Digital A device that can play recording media such as a Versatile Disc and display the images. In addition, the semiconductor device according to one embodiment of the present invention can be used in a device having a display. As an electronic device that can use a programmable logic device, a mobile phone mobile phones, game consoles including portable ones, personal digital assistants, e-books, video cameras, digital still cameras Cameras such as mobile cameras, goggle-type displays (head-mounted displays), navigation systems audio systems, audio playback devices (car audio, digital audio players, etc.) , copiers, facsimiles, printers, printer-combined machines, automated teller machines (A TM), vending machines, etc. Specific examples of these electronic devices are shown in Figure 34.

[0359] FIG. 34A shows a portable game machine, which includes a housing 5001, a housing 5002, a display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, The portable game machine shown in FIG. 34(A) has two displays. The portable game machine has a display unit 5003 and a display unit 5004. This is not limited to this.

[0360] FIG. 34B shows a portable information terminal, which includes a first housing 5601, a second housing 5602, a first display unit, and a 5603, a second display unit 5604, a connection unit 5605, operation keys 5606, etc. Table 1 The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected by a connection portion 56 5605, and the angle between the first housing 5601 and the second housing 5602 is The image on the first display unit 5603 can be changed by the connection unit 5605. The configuration is such that the switching is performed according to the angle between the first housing 5601 and the second housing 5602 in the In addition, at least one of the first display unit 5603 and the second display unit 5604 may have a position A display device with a function as a position input device may be used. The function as a touch device can be added by providing a touch panel to the display device. Alternatively, the function of the position input device may be realized by using a photoelectric conversion element, also called a photosensor, on a display device. It can also be added by providing it in the pixel portion of the device.

[0361] FIG. 34C shows a notebook personal computer, which includes a housing 5401 and a display portion 5402. , a keyboard 5403, a pointing device 5404, and the like.

[0362] FIG. 34(D) shows an electric refrigerator-freezer, which includes a housing 5301, a refrigerator door 5302, and a freezer door. 5303 etc.

[0363] FIG. 34(E) shows a video camera, which includes a first housing 5801, a second housing 5802, and a display unit 58 03, operation keys 5804, a lens 5805, a connection part 5806, etc. The lens 5805 is provided in the first housing 5801, and the display unit 5803 is provided in the second housing. The first housing 5801 and the second housing 5802 are connected by a connection part. The first housing 5801 and the second housing 5802 are connected by a The image on the display unit 5803 can be changed by the connection unit 5806. The switch is configured to switch according to the angle between the first housing 5801 and the second housing 5802. That's fine.

[0364] FIG. 34(F) shows a standard automobile, which includes a body 5101, wheels 5102, and a dashboard 510. 3, Light 5104, etc. [Explanation of symbols]

[0365] 31 Multiplexer 32 Multiplexer 33 Multiplexer 34 Multiplexer 35 Multiplexer 36 Multiplexer 37 Multiplexer 41 Multiplexer 42 Multiplexer 43 Multiplexer 44 OR Circuit 100 PLD 101 LE 102 columns Column 102-1 Row 102-2 Row 102-3 103 Wiring 104 Wiring 104-1 Wiring 104-2 Wiring 104-3 Wiring 105 Wiring 105-1 Wiring 105-2 Wiring 105-3 Wiring 106 Wiring 106-1 Wiring 106-2 Wiring 106-3 Wiring 107 Wiring 108 Wiring 109 Wiring 110 Switch Circuit 111 Wiring 111-1 Wiring 111-2 Wiring 111-3 Wiring 120 Switch Circuit 120-1 Switch circuit 120-2 Switch circuit 120-3 Switch circuit 120a switch circuit 120b Switch circuit 120c switch circuit 121 Wiring 122 Wiring 122-1 Wiring 122-2 Wiring 122-3 Wiring 122-n wiring 123 Wiring 123-1 Wiring 123-n wiring 125 Wiring 126 Switch 126t transistor 127 Wiring 128 Wiring 131 Switch 131t transistor 130 Switch 130t transistor 132 Capacitor element 133t transistor 140 cells 140-1 Cell 140-2 Cell 140-3 Cell 140-4 Cell 140-n cell 150 IO Column 151 152 Wiring 153 Wiring 154 Wiring 155 Wiring 156 Wiring 157 Switch 160 LUT 161 Flip-Flop 162 configuration memory 163 Input terminal 164 output terminal 165 output terminal 166 AND Circuit 168 Multiplexer 169 Configuration Memory 170 Logic Array 172 PLL 173 RAM 174 Multiplier 175 Routing Resources 180 inverter 181 Inverter 182 Latch 183 Inverter 184 transistors 185 Wiring 195 Wiring 196 Wiring 200 memory cells 201 Switch 202 Switch 203 Switch 204 Switch 205 Switch 206 Capacitor 207 Capacitor 208 Wiring 209 Wiring 210 Wiring 211 Wiring 212 Wiring 213 Wiring 213a wiring 213b Wiring 214 Wiring 215 Wiring 216 Wiring 217 Switch 220 pairs 220a group 220b group 220c group 220d group 221 LE 222 Wiring 223 Wiring 224 Latch 225 logic cells 230 IO 231a ExOR circuit 231b ExOR circuit 232 Tristate Buffer 233 Inverter 234 buffers 236 terminals 400 Semiconductor Substrates 401 Element isolation insulating film 402 Impurity region 403 Impurity region 404 gate electrode 405 Gate insulating film 409 Insulating Film 410 Wiring 411 Wiring 412 Wiring 415 Wiring 416 Wiring 417 Wiring 420 insulating film 421 Wiring 430 Semiconductor Film 431 Gate insulating film 432 Conductive film 433 Conductive Film 434 Gate electrode 435 Conductive Film 440 insulating film 441 Insulating Film 442 insulating film 443 Conductive Film 501 NAND circuit 502 Inverter 503 Inverter 504 Inverter 505 NOR circuit 506 Inverter 507 Inverter 508 p-channel transistor 509 n-channel transistor 510 Inverter 511 Inverter 601 Transistor 602 Conductive film 603 Conductive film 604 gate electrode 605 Insulating film 606 Insulating film 607 Oxide semiconductor film 608 Source Electrode 609 Drain electrode 610 Insulating film 611 Gate electrode 612 insulating film 630 Transistor 631 Semiconductor substrate 632 Element isolation insulating film 633 p-well 634 Impurity region 635 Impurity region 636 Gate electrode 637 Gate insulating film 638 Insulating Film 639 Wiring 640 Wiring 641 Wiring 642 Wiring 643 Insulating Film 645 Wiring 646 Insulating Film 647 Wiring 648 Wiring 649 Insulating Film 650 Wiring 651 Insulating film 652 Wiring 653 Insulating film 654 Wiring 655 insulating film 656 Wiring 5001 Case 5002 Case 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5101 Car body 5102 Wheel 5103 Dashboard 5104 Light 5301 Housing 5302 Refrigerator door 5303 Freezer door 5401 Housing 5402 Display section 5403 Keyboard 5404 Pointing Device 5601 Housing 5602 Housing 5603 Display section 5604 Display section 5605 Connection 5606 Operation Key 5801 Housing 5802 Housing 5803 Display section 5804 Operation key 5805 Lens 5806 Connection

Claims

1. a first transistor including silicon in a channel formation region; a second transistor having a channel formation region in an oxide semiconductor film, a channel formation region of the first transistor having a region disposed below a first insulating film; the oxide semiconductor film has a region disposed above the first insulating film, a semiconductor device in which one of a source and a drain of the second transistor is always electrically connected to a gate of the first transistor, a first conductive film having a region located above a channel formation region of the first transistor and a region located below the first insulating film, the first conductive film functioning as a gate of the first transistor; a second conductive film having a region located below the oxide semiconductor film and functioning as a first gate of the second transistor; a third conductive film having a region disposed above the first insulating film and always electrically connected to the other of the source and drain of the second transistor; a fourth conductive film having a region located above the oxide semiconductor film and functioning as a second gate of the second transistor; a fifth conductive film having a region located above the oxide semiconductor film and always in electrical conduction with one of a source and a drain of the second transistor; a sixth conductive film having a region disposed above the oxide semiconductor film and always electrically connected to the other of the source and the drain of the second transistor; the sixth conductive film has a region in contact with an upper surface of the third conductive film; Semiconductor device.

2. a first transistor including silicon in a channel formation region; a second transistor having a channel formation region in an oxide semiconductor film, a channel formation region of the first transistor having a region disposed below a first insulating film; the oxide semiconductor film has a region disposed above the first insulating film, a semiconductor device in which one of a source and a drain of the second transistor is always electrically connected to a gate of the first transistor, a first conductive film having a region located above a channel formation region of the first transistor and a region located below the first insulating film, the first conductive film functioning as a gate of the first transistor; a second conductive film having a region located below the oxide semiconductor film and functioning as a first gate of the second transistor; a third conductive film having a region disposed above the first insulating film and always electrically connected to the other of the source and drain of the second transistor; a fourth conductive film having a region located above the oxide semiconductor film and functioning as a second gate of the second transistor; a fifth conductive film having a region located above the oxide semiconductor film and always in electrical conduction with one of a source and a drain of the second transistor; a sixth conductive film having a region disposed above the oxide semiconductor film and always electrically connected to the other of the source and the drain of the second transistor; the sixth conductive film has a region in contact with an upper surface of the third conductive film, the third conductive film does not overlap with the fourth conductive film in a cross-sectional view of the second transistor in a channel length direction; Semiconductor device.

3. a first transistor including silicon in a channel formation region; a second transistor having a channel formation region in an oxide semiconductor film, a channel formation region of the first transistor having a region disposed below a first insulating film; the oxide semiconductor film has a region disposed above the first insulating film, a semiconductor device in which one of a source and a drain of the second transistor is always electrically connected to a gate of the first transistor, a first conductive film having a region located above a channel formation region of the first transistor and a region located below the first insulating film, the first conductive film functioning as a gate of the first transistor; a second conductive film having a region located below the oxide semiconductor film and functioning as a first gate of the second transistor; a third conductive film having a region disposed above the first insulating film and always electrically connected to the other of the source and drain of the second transistor; a fourth conductive film having a region located above the oxide semiconductor film and functioning as a second gate of the second transistor; a fifth conductive film having a region located above the oxide semiconductor film and always in electrical conduction with one of a source and a drain of the second transistor; a sixth conductive film having a region disposed above the oxide semiconductor film and always electrically connected to the other of the source and the drain of the second transistor; the sixth conductive film has a region in contact with a top surface of the third conductive film in a region where the sixth conductive film does not overlap with the oxide semiconductor film; Semiconductor device.

4. a first transistor including silicon in a channel formation region; a second transistor having a channel formation region in an oxide semiconductor film, a channel formation region of the first transistor having a region disposed below a first insulating film; the oxide semiconductor film has a region disposed above the first insulating film, a semiconductor device in which one of a source and a drain of the second transistor is always electrically connected to a gate of the first transistor, a first conductive film having a region located above a channel formation region of the first transistor and a region located below the first insulating film, the first conductive film functioning as a gate of the first transistor; a second conductive film having a region located below the oxide semiconductor film and functioning as a first gate of the second transistor; a third conductive film having a region disposed above the first insulating film and always electrically connected to the other of the source and drain of the second transistor; a fourth conductive film having a region located above the oxide semiconductor film and functioning as a second gate of the second transistor; a fifth conductive film having a region located above the oxide semiconductor film and always in electrical conduction with one of a source and a drain of the second transistor; a sixth conductive film having a region disposed above the oxide semiconductor film and always electrically connected to the other of the source and the drain of the second transistor; the sixth conductive film has a region that does not overlap with the oxide semiconductor film and is in contact with a top surface of the third conductive film; the third conductive film does not overlap with the fourth conductive film in a cross-sectional view of the second transistor in a channel length direction; Semiconductor device.

5. In any one of claims 1 to 4, the oxide semiconductor film contains indium oxide; Semiconductor device.

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