Control device, electronic instrument and control method

Abstract

To provide a control device, an electronic instrument and a control method which can reduce output terminals of a processor that executes data communication with an integrated circuit.SOLUTION: A control device 6 comprises: a CPU 30 that has an output terminal 31 that outputs a clock signal X1 and executes data communication with an image processing circuit 5; and an additional relay circuit 40 that outputs a reset signal X3 in response to input of the clock signal X1 whose duty ratio is equal to a first value, following input of a clock signal X2 to the image processing circuit 5, and stops outputting a reset signal X3 in response to switching of the duty ratio of the clock signal X1 from the first value to a second value lower than the first value.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a control device, an electronic device, and a control method. [Background technology]

[0002] Electronic devices such as printers include a processor such as a CPU (see, for example, Patent Document 1). In such electronic devices, data communication is performed between the processor and an integrated circuit such as an image processing circuit. For example, when data communication is performed with the integrated circuit, the processor inputs a clock signal to the integrated circuit, and inputs a reset signal to the integrated circuit after the clock signal has stabilized. Furthermore, after data communication with the integrated circuit is completed, the processor stops inputting the reset signal to the integrated circuit, and then stops inputting the clock signal to the integrated circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-156574 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in conventional electronic devices, in order to realize data communication between the processor and the integrated circuit, it is necessary to provide the processor with separate output terminals for outputting the clock signal and the reset signal.

[0005] An object of the present invention is to provide a control device, electronic equipment, and control method that can reduce the number of output terminals of a processor that performs data communication with an integrated circuit. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a control device including a processor and a signal output circuit. The processor has an output terminal for outputting a clock signal and performs data communication with an integrated circuit. The signal output circuit outputs a reset signal used to reset the integrated circuit in response to input of the clock signal having a predetermined first duty ratio after the clock signal is input to the integrated circuit, and stops outputting the reset signal in response to switching of the duty ratio of the clock signal from the first value to a second value lower than the first value.

[0007] An electronic device according to another aspect of the present invention includes the control device and the integrated circuit.

[0008] A control method according to another aspect of the present invention is executed by a control device including a processor having an output terminal that outputs a clock signal and that executes data communication with an integrated circuit, and a signal output circuit that outputs a reset signal used to reset the integrated circuit in response to input of the clock signal having a predetermined first duty ratio after the clock signal is input to the integrated circuit, and stops outputting the reset signal in response to switching of the duty ratio of the clock signal from the first value to a second value lower than the first value, and includes an output step and a switching step. In the output step, the clock signal having the first duty ratio is output from the output terminal when the data communication is executed. In the switching step, the duty ratio of the clock signal output from the output terminal is switched from the first value to the second value after the data communication is completed. [Effects of the Invention]

[0009] According to the present invention, it is possible to reduce the number of output terminals of a processor that performs data communication with an integrated circuit. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a cross-sectional view showing the configuration of an image forming apparatus according to an embodiment of the present invention. [Figure 2] FIG. 2 is a block diagram showing the configuration of the control unit according to the embodiment of the present invention. [Figure 3] FIG. 3 is a circuit diagram showing the configuration of an additional relay circuit of the control unit according to the embodiment of the present invention. [Figure 4] FIG. 4 is a flowchart showing an example of a communication control process executed by the CPU of the control unit according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. Note that the following embodiment is an example of the present invention, and does not limit the technical scope of the present invention.

[0012] [Configuration of image forming apparatus 100] First, the configuration of an image forming apparatus 100 according to an embodiment of the present invention will be described with reference to FIGS.

[0013] The image forming apparatus 100 is a multifunction peripheral that has multiple functions, such as a scanning function for reading an image from a document, a printing function for forming an image based on image data, a facsimile function, and a copy function. The image forming apparatus 100 is an example of an electronic device of the present invention. The present invention may also be applied to electronic devices such as scanners, printers, fax machines, copy machines, personal computers, laptop computers, televisions, microwave ovens, and refrigerators.

[0014] As shown in Fig. 1, image forming apparatus 100 includes an ADF (Auto Document Feeder) 1, an image reading unit 2, an image forming unit 3, and a paper feeding unit 4. Image forming apparatus 100 also includes an image processing circuit 5 and a control unit 6 shown in Fig. 2. Control unit 6 is an example of a control device of the present invention.

[0015] The ADF 1 transports documents to be scanned by the scanning function, and includes a document setting unit, a plurality of document transport rollers, a document holder, and a paper ejection unit.

[0016] The image reading unit 2 realizes the scanning function and includes a document table, a light source, a plurality of mirrors, an optical lens, and a CCD (Charge Coupled Device).

[0017] The image forming unit 3 realizes the printing function. As shown in Fig. 1, the image forming unit 3 includes a photosensitive drum 11, a charging roller 12, an optical scanning device 13, a developing device 14, a toner container 15, a transfer roller 16, a cleaning device 17, a fixing device 18, and a paper output tray 19.

[0018] The photosensitive drum 11 is rotatably mounted. The charging roller 12 is provided in contact with the surface of the photosensitive drum 11 and charges the surface of the photosensitive drum 11.

[0019] The optical scanning device 13 irradiates the surface of the photosensitive drum 11, which has been charged by the charging roller 12, with light based on image data. An electrostatic latent image is formed on the surface of the photosensitive drum 11 by the optical scanning device 13.

[0020] The developing device 14 uses toner to develop the electrostatic latent image formed on the surface of the photosensitive drum 11. The toner container 15 supplies the toner to the developing device 14.

[0021] The transfer roller 16 transfers the electrostatic latent image (toner image) developed by the developing device 14 onto a sheet supplied by the paper feed unit 4. The cleaning device 17 cleans the surface of the photosensitive drum 11 after the toner image has been transferred by the transfer roller 16.

[0022] The fixing device 18 fixes the toner image transferred onto the sheet by the transfer roller 16. The sheet onto which the toner image has been fixed by the fixing device 18 is discharged to a paper discharge tray 19.

[0023] The paper feed unit 4 supplies sheets to the image forming unit 3. As shown in FIG. 1, the paper feed unit 4 includes a paper feed cassette 21, a pickup roller 22, a paper feed roller 23, a plurality of sheet transport rollers 24, and a registration roller 25.

[0024] The paper feed cassette 21 is detachably provided in the housing of the image forming apparatus 100, and holds sheets to be supplied to the image forming unit 3. The pickup roller 22 picks up the top sheet from the paper feed cassette 21 among the multiple sheets stacked in the paper feed cassette 21.

[0025] The paper feed roller 23 conveys the sheet picked up from the paper feed cassette 21 by the pickup roller 22 to a sheet supply path leading to the image forming unit 3. A plurality of sheet conveying rollers 24 are provided in the sheet supply path and convey the sheet to the image forming unit 3.

[0026] The registration rollers 25 are provided at the most downstream portion of the sheet supply path, and supply the sheet to the image forming unit 3 at a predetermined timing.

[0027] The image processing circuit 5 executes predetermined image processing on image data to be printed. For example, the image processing circuit 5 is an ASIC (Application Specific Integrated Circuit), a DSP (Digital Signal Processor), or an FPGA (Field-Programmable Gate Array). The image processing circuit 5 is an example of the integrated circuit of the present invention. The integrated circuit of the present invention may be a storage device such as a flash memory. The integrated circuit of the present invention may also be an engine control unit that controls the image forming unit 3 and the paper feed unit 4.

[0028] The control unit 6 performs overall control of the image forming apparatus 100. The control unit 6 may be the engine control unit.

[0029] As shown in FIG. 2, the control unit 6 includes a CPU 30.

[0030] The CPU 30 is a processor that executes various types of arithmetic processing. The CPU 30 executes data communication with the image processing circuit 5 using a data transmission path (not shown). The CPU 30 is an example of a processor of the present invention.

[0031] In image forming apparatus 100, when data communication between image processing circuit 5 and CPU 30 is started, clock signal X2 (see FIG. 2) is input to image processing circuit 5, and then reset signal X3 (see FIG. 2) is input to image processing circuit 5. After data communication between image processing circuit 5 and CPU 30 is completed, input of reset signal X3 to image processing circuit 5 is stopped, and then input of clock signal X2 to image processing circuit 5 is stopped.

[0032] In conventional electronic devices, in order to realize data communication between the CPU 30 and the image processing circuit 5, it is necessary to provide the CPU 30 with separate output terminals for outputting the clock signal X2 and the reset signal X3.

[0033] In contrast to this, in the image forming apparatus 100 according to the embodiment of the present invention, the number of output terminals of the CPU 30 that executes data communication with the image processing circuit 5 can be reduced, as will be described below.

[0034] Specifically, the CPU 30 includes an output terminal 31 (see FIG. 2) that outputs a clock signal X1 (see FIG. 2).

[0035] The control unit 6 also includes an additional relay circuit 40 shown in FIGS.

[0036] 2. Specifically, the CPU 30 functions as each of the above-mentioned processing units by executing a control program stored in advance in a ROM (not shown).

[0037] [Configuration of additional relay circuit 40] Next, the configuration of the additional relay circuit 40 will be described with reference to FIGS.

[0038] As shown in FIG. 3, the additional relay circuit 40 includes a clock signal output circuit 41 and a reset signal output circuit 42.

[0039] In response to an input of a clock signal X1, the clock signal output circuit 41 generates and outputs a clock signal X2 that is identical to the clock signal X1.

[0040] As shown in FIG. 3, the clock signal output circuit 41 includes resistors R1 to R3 and a transistor Q1.

[0041] The transistor Q1 is a PNP transistor. The emitter terminal of the transistor Q1 is connected to a power supply Vcc (see FIG. 3) via a resistor R1. The emitter terminal of the transistor Q1 is also connected to an input terminal 51 (see FIG. 2) of the image processing circuit 5. A clock signal X2 is input to the input terminal 51. The base terminal of the transistor Q1 is connected to an output terminal 31 (see FIG. 2) of the CPU 30 via a resistor R2. The base terminal of the transistor Q1 is also connected to ground via a resistor R3. The collector terminal of the transistor Q1 is connected to ground.

[0042] In the clock signal output circuit 41, the transistor Q1 is in an on state when the clock signal X1 is not output from the output terminal 31 (see FIG. 2) of the CPU 30. When the transistor Q1 is in an on state, the input terminal 51 (see FIG. 2) of the image processing circuit 5 is connected to ground. In other words, when the clock signal X1 is not output from the output terminal 31 of the CPU 30, the clock signal output circuit 41 does not generate the clock signal X2.

[0043] In the clock signal output circuit 41, the transistor Q1 is in an off state when the clock signal X1 is output from the output terminal 31 (see FIG. 2) of the CPU 30 and the signal level of the clock signal X1 is high. When the transistor Q1 is in an off state, the input terminal 51 (see FIG. 2) of the image processing circuit 5 is connected to the power supply Vcc via the resistor R1. As a result, a high-level signal constituting the clock signal X2 is output. Also, in the clock signal output circuit 41, the transistor Q1 is in an on state when the clock signal X1 is output from the output terminal 31 of the CPU 30 and the signal level of the clock signal X1 is low. When the transistor Q1 is in an on state, the input terminal 51 of the image processing circuit 5 is connected to ground. As a result, a low-level signal constituting the clock signal X2 is output.

[0044] In response to input of clock signal X1 having a predetermined first duty ratio, reset signal output circuit 42 outputs reset signal X3 after input of clock signal X2 to image processing circuit 5. In addition, reset signal output circuit 42 stops output of reset signal X3 in response to switching of the duty ratio of clock signal X1 from the first value to a second value lower than the first value. Reset signal output circuit 42 is an example of a signal output circuit of the present invention.

[0045] As shown in FIG. 3, the reset signal output circuit 42 includes resistors R4 to R10, transistors Q2 to Q3, and capacitors C1 to C2.

[0046] The transistor Q2 is an NPN transistor. The collector terminal of the transistor Q2 is connected to the power supply Vcc via a resistor R4. The base terminal of the transistor Q2 is connected to the output terminal 31 of the CPU 30 (see FIG. 2) via a resistor R5. The emitter terminal of the transistor Q2 is connected to ground via a resistor R6. The emitter terminal of the transistor Q2 is also connected to ground via a capacitor C1.

[0047] The transistor Q3 is a PNP transistor. The emitter terminal of the transistor Q3 is connected to the power supply Vcc via a resistor R7. The emitter terminal of the transistor Q3 is also connected to an input terminal 52 (see FIG. 2) of the image processing circuit 5. A reset signal X3 is input to the input terminal 52. The base terminal of the transistor Q3 is connected to the emitter terminal of the transistor Q2 via a resistor R8. The base terminal of the transistor Q3 is also connected to ground via a resistor R9. The collector terminal of the transistor Q3 is connected to ground.

[0048] The emitter terminal of the transistor Q3 is connected to ground via a capacitor C2 and a resistor R10.

[0049] In the reset signal output circuit 42, the transistor Q2 is in an off state when the clock signal X1 is not output from the output terminal 31 of the CPU 30 (see FIG. 2). In other words, no voltage is applied to the base terminal of the transistor Q3. Therefore, the transistor Q3 is in an on state when the clock signal X1 is not output from the output terminal 31 of the CPU 30. When the transistor Q3 is in an on state, the input terminal 52 of the image processing circuit 5 (see FIG. 2) is connected to ground. In other words, the reset signal output circuit 42 does not generate the reset signal X3 when the clock signal X1 is not output from the output terminal 31 of the CPU 30.

[0050] In the reset signal output circuit 42, the transistor Q2 is in an ON state when the clock signal X1 is output from the output terminal 31 (see FIG. 2) of the CPU 30 and the signal level of the clock signal X1 is high. When the transistor Q2 is in an ON state, the capacitor C1 is connected to the power supply Vcc via the resistor R4. This charges the capacitor C1, gradually increasing the voltage applied to the base terminal of the transistor Q3, and the transistor Q3 switches from an ON state to an OFF state. When the transistor Q3 is in an OFF state, the capacitor C2 is connected to the power supply Vcc via the resistor R7. This charges the capacitor C2, gradually increasing the voltage applied to the input terminal 52 (see FIG. 2) of the image processing circuit 5.

[0051] In the reset signal output circuit 42, the transistor Q2 is in an off state when the clock signal X1 is output from the output terminal 31 (see FIG. 2) of the CPU 30 and the signal level of the clock signal X1 is low. When the transistor Q2 is in an off state, the capacitor C1 discharges. As a result, the transistor Q3 remains in an off state for a while.

[0052] Here, the higher the duty ratio of the clock signal X1, the longer the charging time of the capacitor C1 and the shorter the discharging time of the capacitor C1. In other words, if the duty ratio of the clock signal X1 is sufficiently high, it is possible to maintain the transistor Q3 in the off state regardless of the switching of the signal level of the clock signal X1. Therefore, it is possible to increase the voltage applied to the input terminal 52 (see FIG. 2) of the image processing circuit 5 to the signal level of the reset signal X3.

[0053] Specifically, in the reset signal output circuit 42, when the duty ratio of the clock signal X1 is equal to or greater than a third value, the transistor Q3 can be maintained in an off state regardless of the switching of the signal level of the clock signal X1. Also, the first value is a value set within a range equal to or greater than the third value.

[0054] On the other hand, the lower the duty ratio of the clock signal X1, the shorter the charging time of the capacitor C1 and the longer the discharging time of the capacitor C1. In other words, if the duty ratio of the clock signal X1 is sufficiently low, the transistor Q3 switches from the off state to the on state during the period when the signal level of the clock signal X1 is low, and the capacitor C2 discharges. If the amount of discharge of the capacitor C2 exceeds the amount of charge of the capacitor C2, the voltage applied to the input terminal 52 (see FIG. 2) of the image processing circuit 5 gradually decreases. In this case, the output of the reset signal X3 stops.

[0055] Specifically, in the reset signal output circuit 42, when the duty ratio of the clock signal X1 is equal to or less than a fourth value that is lower than the third value, the discharge amount of the capacitor C2 exceeds the charge amount of the capacitor C2. Also, the second value is a value set within a range equal to or less than the fourth value.

[0056] [Functions of each processing unit included in CPU 30] Next, the function of each processing unit included in the CPU 30 will be described with reference to FIG.

[0057] When data communication is performed between the CPU 30 and the image processing circuit 5, the output processing unit 32 causes the output terminal 31 to output the clock signal X1 whose duty ratio is the first value.

[0058] After the data communication between the CPU 30 and the image processing circuit 5 is completed, the switching processing unit 33 switches the duty ratio of the clock signal X1 output from the output terminal 31 from the first value to the second value.

[0059] The stop processing unit 34 stops the output of the clock signal X1 from the output terminal 31 after the data communication between the CPU 30 and the image processing circuit 5 has ended and the output of the reset signal X3 from the reset signal output circuit 42 has stopped.

[0060] [Communication control processing] 4, the control method of the present invention will be described below along with an example of the procedure of communication control processing executed by the CPU 30 in the image forming apparatus 100. Here, steps S11, S12, etc. represent the numbers of the processing procedures (steps) executed by the CPU 30. The communication control processing is executed when data communication is executed between the CPU 30 and the image processing circuit 5.

[0061] <Step S11> First, in step S11, the CPU 30 outputs a clock signal X1 having a duty ratio of the first value from the output terminal 31. The process of step S11 is an example of an output step of the present invention, and is executed by the output processing unit 32 of the CPU 30.

[0062] By executing the process of step S11, the clock signal X1 having the duty ratio of the first value is input to the additional relay circuit 40 (see FIG. 2). As a result, the clock signal X2 is output from the clock signal output circuit 41. Furthermore, after the clock signal X2 is input to the image processing circuit 5, the reset signal X3 is output from the reset signal output circuit 42.

[0063] <Step S12> In step S12, the CPU 30 determines whether the reset signal output circuit 42 has output the reset signal X3.

[0064] For example, the CPU 30 determines that the reset signal X3 has been output from the reset signal output circuit 42 when a predetermined first time has elapsed since the execution of the process of step S11.

[0065] Here, if the CPU 30 determines that the reset signal X3 has been output from the reset signal output circuit 42 (Yes in S12), it shifts the process to step S13. On the other hand, if the reset signal X3 has not been output from the reset signal output circuit 42 (No in S12), the CPU 30 waits for the reset signal X3 to be output from the reset signal output circuit 42 in step S12.

[0066] <Step S13> In step S13, the CPU 30 starts data communication with the image processing circuit 5.

[0067] <Step S14> In step S14, the CPU 30 determines whether or not data communication with the image processing circuit 5 has ended.

[0068] Here, when the CPU 30 determines that the data communication with the image processing circuit 5 has ended (Yes in S14), it shifts the process to step S15. On the other hand, if the data communication with the image processing circuit 5 has not ended (No in S14), the CPU 30 waits for the end of the data communication with the image processing circuit 5 in step S14.

[0069] <Step S15> In step S15, the CPU 30 switches the duty ratio of the clock signal X1 output from the output terminal 31 from the first value to the second value. The process of step S15 is an example of a switching step of the present invention, and is executed by the switching processing unit 33 of the CPU 30.

[0070] By executing the process of step S15, the clock signal X1 having the second duty ratio is input to the additional relay circuit 40 (see FIG. 2). As a result, the clock signal X2 is output from the clock signal output circuit 41. Also, the output of the reset signal X3 from the reset signal output circuit 42 is stopped.

[0071] <Step S16> In step S16, the CPU 30 determines whether or not the output of the reset signal X3 from the reset signal output circuit 42 has stopped.

[0072] For example, the CPU 30 determines that the output of the reset signal X3 from the reset signal output circuit 42 has stopped when a predetermined second time has elapsed since the execution of the process of step S15.

[0073] Here, if the CPU 30 determines that the output of the reset signal X3 from the reset signal output circuit 42 has stopped (Yes in S16), it shifts the process to step S17. On the other hand, if the output of the reset signal X3 from the reset signal output circuit 42 has not stopped (No in S16), the CPU 30 waits in step S16 for the output of the reset signal X3 from the reset signal output circuit 42 to stop.

[0074] <Step S17> In step S17, the CPU 30 stops the output of the clock signal X1 from the output terminal 31. The process of step S17 is executed by the stop processing unit 34 of the CPU 30.

[0075] This makes it possible to reduce power consumption and suppress the occurrence of electromagnetic interference due to the output of the clock signal X1, compared to a configuration in which the CPU 30 always outputs the clock signal X1.

[0076] As described above, the control unit 6 includes a reset signal output circuit 42 that outputs the reset signal X3 to the image processing circuit 5 after the clock signal X2 is input in response to the input of the clock signal X1 whose duty ratio has the first value, and stops outputting the reset signal X3 in response to the duty ratio of the clock signal X1 switching to the second value. This makes it possible to output the reset signal X3 without providing an output terminal for the reset signal X3 in the CPU 30. This makes it possible to reduce the number of output terminals of the CPU 30 that perform data communication with the image processing circuit 5.

[0077] [Notes on the Invention] The following is a summary of the invention extracted from the above-described embodiment. Note that the configurations and processing functions described in the following supplementary notes can be selected and combined as desired.

[0078] <Appendix 1> A control device comprising: a processor having an output terminal that outputs a clock signal and that performs data communication with an integrated circuit; and a signal output circuit that outputs a reset signal used to reset the integrated circuit in response to input of the clock signal having a duty ratio of a predetermined first value after the clock signal is input to the integrated circuit, and stops outputting the reset signal in response to switching of the duty ratio of the clock signal from the first value to a second value lower than the first value.

[0079] <Appendix 2> The control device described in Appendix 1, wherein the processor outputs the clock signal having a duty ratio of the first value from the output terminal when the data communication is performed, and switches the duty ratio of the clock signal output from the output terminal from the first value to the second value after the data communication is completed.

[0080] <Appendix 3> The control device described in Appendix 2, wherein the processor stops outputting the clock signal from the output terminal after the data communication ends and output of the reset signal from the signal output circuit stops.

[0081] <Appendix 4> An electronic device comprising the control device according to any one of Supplementary Notes 1 to 3 and the integrated circuit.

[0082] <Appendix 5> A control method executed by a control device comprising: a processor having an output terminal that outputs a clock signal and that performs data communication with an integrated circuit; and a signal output circuit that outputs a reset signal used to reset the integrated circuit in response to input of the clock signal having a duty ratio of a predetermined first value after the clock signal is input to the integrated circuit, and stops outputting the reset signal in response to switching of the duty ratio of the clock signal from the first value to a second value lower than the first value, the control method including: an output step of outputting the clock signal having a duty ratio of the first value from the output terminal when the data communication is performed; and a switching step of switching the duty ratio of the clock signal output from the output terminal from the first value to the second value after the data communication is completed. [Explanation of symbols]

[0083] 1 ADF 2 Image reading unit 3 Image forming unit 4 Paper feed section 5 Image processing circuit 6 Control Unit 30 CPU 31 Output terminal 32 Output Processing Section 33 Switching processing section 34 Stop processing section 40 Additional relay circuit 41 Clock signal output circuit 42 Reset signal output circuit 100 Image forming device

Claims

1. a processor having an output terminal for outputting a clock signal and for performing data communication with the integrated circuit; a signal output circuit that outputs a reset signal used to reset the integrated circuit after the clock signal is input to the integrated circuit in response to an input of the clock signal having a duty ratio of a predetermined first value, and stops outputting the reset signal in response to a change in the duty ratio of the clock signal from the first value to a second value lower than the first value; A control device comprising:

2. the processor outputs the clock signal having a duty ratio of the first value from the output terminal when the data communication is performed, and switches the duty ratio of the clock signal output from the output terminal from the first value to the second value after the data communication is completed. The control device according to claim 1 .

3. the processor stops outputting the clock signal from the output terminal after the data communication ends and after the signal output circuit stops outputting the reset signal; The control device according to claim 2 .

4. A control device according to any one of claims 1 to 3; the integrated circuit; An electronic device comprising:

5. A control method executed by a control device including: a processor having an output terminal that outputs a clock signal and that executes data communication with an integrated circuit; and a signal output circuit that outputs a reset signal used to reset the integrated circuit in response to input of the clock signal having a duty ratio of a predetermined first value after the clock signal is input to the integrated circuit, and stops output of the reset signal in response to switching of the duty ratio of the clock signal from the first value to a second value lower than the first value, an output step of outputting the clock signal having the first duty ratio from the output terminal when the data communication is being performed; a switching step of switching the duty ratio of the clock signal output from the output terminal from the first value to the second value after the data communication is completed; A control method comprising:

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