Wafer test device

Abstract

To provide a wafer test device which can conduct a high-temperature inspection without increasing leakage current.SOLUTION: The wafer test device according to the present disclosure includes: a test stage on which a wafer having a plurality of semiconductor chips is mounted; and a probe card for inspecting the plurality of semiconductor chips. The test stage includes a temperature control mechanism configured to adjust the temperature of a part of the wafer, and the temperature control mechanism includes a plurality of first heaters separated from each other and independently controlled.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a wafer testing apparatus that tests semiconductor devices in a wafer state. [Background technology]

[0002] When testing semiconductor chips to see if they meet product specifications, accelerated testing is often used, in which the temperature of the semiconductor chip is increased to shorten the test time. For example, power semiconductor devices are often tested at temperatures between 25°C and 200°C.

[0003] Patent Document 1 discloses an inspection device for semiconductor devices that can locally adjust the wafer temperature by irradiating light onto semiconductor devices in a wafer state for accelerated testing. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-030909 Summary of the Invention [Problem to be solved by the invention]

[0005] In Patent Document 1, when raising the temperature of a portion of a semiconductor device in wafer form, the temperature is raised by irradiating the section to be heated with light. However, when using a method of irradiating light to inspect the characteristics of a power semiconductor device, there are problems such as an increase in leakage current due to light energy, and it is difficult to raise the temperature to a high temperature such as 200°C by irradiating light.

[0006] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a wafer testing device that is capable of performing testing at high temperatures without increasing leakage current. [Means for solving the problem]

[0007] The wafer testing apparatus according to the present disclosure comprises an inspection stage on which a wafer having a plurality of semiconductor chips is mounted, and a probe card for inspecting the plurality of semiconductor chips, the inspection stage having a temperature adjustment mechanism capable of adjusting the temperature of a portion of the wafer, and the temperature adjustment mechanism including a plurality of first heaters that are separate from each other and independently controlled. [Effects of the Invention]

[0008] According to the wafer testing device of the present disclosure, the semiconductor chip to be measured can be heated in a concentrated manner by the multiple first heaters, and the leakage current does not increase due to light energy as in the case of heating due to light irradiation, and the temperature can be raised to a high temperature such as 200°C in a short time, thereby shortening the inspection time. Furthermore, by heating the semiconductor chip to be measured in a concentrated manner, the semiconductor chip is prevented from reaching a high temperature for a long time, and an accelerated test can be performed while preventing Ni precipitation from the electrode portion of the laminated structure. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a plan view illustrating a configuration of an inspection stage of a wafer testing apparatus according to a first embodiment of the present disclosure. [Figure 2] 1 is a cross-sectional view illustrating a configuration of an inspection stage of a wafer testing apparatus according to a first embodiment of the present disclosure. [Figure 3] FIG. 2 is a plan view showing the inspection stage before a wafer is mounted thereon. [Figure 4] 1 is a plan view schematically showing a state in which the temperature of a semiconductor chip to be measured is raised in a concentrated manner on the inspection stage of the wafer testing apparatus according to the first embodiment of the present disclosure. FIG. [Figure 5] 1 is a cross-sectional view schematically showing a state in which the temperature of a semiconductor chip to be measured is raised in a concentrated manner on the inspection stage of the wafer testing apparatus according to the first embodiment of the present disclosure. [Figure 6]FIG. 10 is a plan view schematically illustrating the function of a temperature adjustment mechanism on an inspection stage of a wafer testing apparatus according to a second embodiment of the present disclosure. [Figure 7] FIG. 10 is a plan view schematically illustrating the function of a temperature adjustment mechanism on an inspection stage of a wafer testing apparatus according to a second embodiment of the present disclosure. [Figure 8] FIG. 10 is a cross-sectional view illustrating the configuration of a wafer testing device according to a third embodiment of the present disclosure. [Figure 9] FIG. 10 is a cross-sectional view illustrating the configuration of a wafer testing device according to a third embodiment of the present disclosure. [Figure 10] FIG. 10 is a cross-sectional view illustrating the configuration of a wafer testing device according to a fourth embodiment of the present disclosure. [Figure 11] FIG. 11 is a plan view of a probe card of a wafer testing apparatus according to a fourth embodiment of the present disclosure, viewed from the bottom side. [Figure 12] FIG. 10 is a cross-sectional view illustrating the configuration of a wafer testing device according to a fifth embodiment of the present disclosure. [Figure 13] FIG. 10 is a cross-sectional view illustrating the configuration of a wafer testing device according to a fifth embodiment of the present disclosure. [Figure 14] FIG. 11 is a plan view of a probe card of a wafer testing apparatus according to a fifth embodiment of the present disclosure, viewed from the bottom side. [Figure 15] FIG. 13 is a plan view illustrating the configuration of a wafer testing device according to a sixth embodiment of the present disclosure. [Figure 16] FIG. 13 is a cross-sectional view illustrating the configuration of a wafer testing device according to a sixth embodiment of the present disclosure. [Figure 17] FIG. 13 is a diagram showing a wafer test using a wafer test apparatus according to a sixth embodiment of the present disclosure. [Figure 18] FIG. 13 is a diagram showing a wafer test using a wafer test apparatus according to a sixth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] <Introduction> The drawings are schematic illustrations, and the relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. In the following description, similar components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

[0011] In addition, in the following description, terms that indicate specific positions and directions, such as "top," "bottom," "side," "front," and "back," may be used. However, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and are not related to the directions in which the embodiments are actually implemented.

[0012] <First Embodiment> A wafer testing device according to a first embodiment of the present disclosure will be described with reference to FIGS.

[0013] FIG. 1 is a plan view illustrating the configuration of an inspection stage 2 of a wafer testing apparatus 100 according to the first embodiment, and FIG. 2 is a cross-sectional view taken along line AA in FIG.

[0014] As shown in FIG. 1, a wafer 1 on which a plurality of semiconductor chips 3 are fabricated is mounted on an inspection stage 2. As shown in FIG. 2, a temperature adjustment mechanism 11 is provided inside the inspection stage 2. The temperature adjustment mechanism 11 is composed of, for example, a plurality of heaters 11a (first heaters), and the plurality of heaters 11a are separated from one another and independently controlled so that only an arbitrarily selected portion of the wafer 1 can be heated rather than the entire wafer 1. Note that although a probe card having probes for testing the semiconductor chips 3 is not shown in FIGS. 1 and 2, a conventional cantilever-type probe card or a vertical-type probe card can be used as the probe card.

[0015] FIG. 3 is a plan view showing the inspection stage 2 and the wafer 1 before the wafer 1 is mounted. For convenience, the area on the lower inspection stage 2 where the wafer 1 is mounted is omitted. As shown in FIG. 3, multiple heaters 11a are arranged with their heating surfaces facing the backside of the wafer 1, and each heater 11a can be turned on and off individually. As a result, by concentrating the temperature rise on the semiconductor chip 3 to be measured rather than the entire wafer 1, the time it takes for each semiconductor chip 3 to reach a high temperature can be shortened. Note that while FIG. 3 shows a configuration in which multiple heaters 11a are arranged to divide a circular area, this is not limiting, and multiple heaters 11a can also be arranged to divide a square.

[0016] The heater 11a is provided inside the inspection stage 2 and has no part that comes into direct contact with the wafer 1, so a metal heater such as a nichrome wire heater can be used.

[0017] 4 and 5 are diagrams schematically illustrating a state in which the temperature of the semiconductor chips 3 to be measured is increased in a concentrated manner on the inspection stage 2 of the first embodiment, with FIG. 4 being a plan view corresponding to FIG. 1 and FIG. 5 being a cross-sectional view corresponding to FIG. 2. The region RM indicated by a dashed line in FIG. 4 indicates the temperature increase region, which includes three semiconductor chips 3. FIG. 5 illustrates, with hatching, the state in which the heaters 11a included in the region RM are generating heat, with the three heaters 11a generating heat and increasing the temperatures of the three semiconductor chips 3 above them. After the temperatures of the three semiconductor chips 3 to be measured have been increased and measurement using the probe card has been completed, the temperature increase of the next three semiconductor chips 3 to be measured begins. By repeating this process, all of the semiconductor chips 3 included in the wafer 1 are measured.

[0018] 5 shows an example in which three heaters 11a are controlled, the number of heaters to be controlled is not limited to this, and it is sufficient to control at least one heater 11a. Using fewer heaters 11a can reduce the thermal impact on the surrounding semiconductor chips 3.

[0019] For power semiconductor devices, screening tests are sometimes conducted for quality assurance purposes, and accelerated testing is performed to shorten the inspection time by heating the semiconductor chip to a higher temperature than that during actual use. However, if the semiconductor chip is heated to a high temperature for a long period of time, nickel (Ni) will precipitate on the gold (Au) layer on the chip surface, which may cause poor bonding when the chip is mounted in a package.

[0020] That is, in SiC chips that use silicon carbide (SiC) substrates, the electrode portion, etc., has a layered structure in which, for example, a titanium (Ti) barrier metal, an aluminum silicon (AlSi) layer, a nickel phosphorus (NiP) layer, and an Au layer are stacked on the SiC substrate, but when the SiC chip is heated to high temperatures for a long time, Ni may precipitate from the NiP layer onto the surface of the Au layer. If this precipitated Ni oxidizes and forms an oxide film, for example, it may cause poor bonding when wire bonding to the Au layer.

[0021] In particular, in wafer testing, individual chips remain at high temperatures for longer periods than in chip testing, which limits the temperature conditions and increases the testing time. For example, if a test takes 10 seconds to be performed on one chip, the chip test only heats up the individual chip, so the high-temperature period is only 10 seconds. However, in wafer testing, the entire wafer is heated, so the high-temperature period is 10 x the number of chips per wafer [seconds]. Therefore, if a wafer contains 100 chips, the individual chips remain at high temperatures for 100 times longer in wafer testing than in chip testing.

[0022] Although accelerated testing can be performed by raising the wafer temperature, shortening the test time, the higher the temperature, the more likely Ni is to precipitate. For this reason, in wafer testing, the wafer remains in a high-temperature state for a longer period of time than in chip testing, and as a result, the temperature of the measurement conditions cannot be raised, resulting in a longer test time.

[0023] On the other hand, in the inspection stage 2 of the first embodiment, the temperature of the semiconductor chip 3 to be measured is raised in a concentrated manner, so that an accelerated test can be performed while preventing Ni precipitation, thereby shortening the inspection time. In particular, since SiC chips have many crystal defects, a large number of screening items must be performed, which tends to lengthen the inspection time, so accelerated testing at high temperatures is effective. Here, high temperature refers to a temperature higher than room temperature (25°C). For example, if the guaranteed temperature of the chip is 150°C, performing the screening test at 150°C can shorten the test time the most. Furthermore, since the temperature is raised by the heater 11a, the target temperature can be reached in a relatively short time.

[0024] <Embodiment 2> A wafer testing apparatus according to a second embodiment of the present disclosure will be described with reference to Figures 6 and 7. Figures 6 and 7 are plan views schematically showing the function of a temperature adjustment mechanism on the inspection stage 2 of the wafer testing apparatus 200 according to the second embodiment.

[0025] In the inspection stage 2 of the wafer testing apparatus 100 of the first embodiment, the temperature adjustment mechanism 11 has a structure in which multiple heaters 11a are separated from one another and controlled independently so that only a portion of the wafer 1 can be heated, and the temperature of the semiconductor chip 3 to be measured is raised in a concentrated manner, and after the measurement using the probe card is completed, the temperature of the next semiconductor chip 3 to be measured is started. By repeating this process, all of the semiconductor chips 3 included in the wafer 1 are measured.

[0026] In contrast, in the inspection stage 2 of the wafer testing apparatus 200 of the second embodiment, the inspection order of the semiconductor chips 3 to be inspected is set, and the temperature adjustment mechanism 11 is controlled to adjust the temperature of the portion of the wafer 1 corresponding to the set inspection order.

[0027] For example, Fig. 6 shows an example in which the heater 11a is controlled to turn on and off so as to raise the temperature of one or more semiconductor chips 3 to be measured along the inspection paths indicated by the arrows from left to right, from top to bottom, and from right to left. In the example of Fig. 6, the inspection paths indicated by the arrows in the left and right directions are spaced apart by the width of one semiconductor chip 3, so that the temperature rise along one inspection path indicated by an arrow does not affect the surrounding chips.

[0028] 7 shows an example in which the heater 11a is controlled to turn on and off so that the temperature of the semiconductor chips 3 to be measured is increased one by one or in units of multiple chips along the inspection paths indicated by the arrows, from the upper left to the lower right. In the example of FIG. 7, the inspection paths indicated by the four arrows are numbered A to D, and the temperature of the semiconductor chips 3 to be measured is increased in the order of inspection paths A, B, C, and D. The order of temperature increase is set so that the temperature increase along one inspection path indicated by the arrows does not affect the surrounding chips.

[0029] That is, even if the multiple heaters 11a are separated and controlled independently to locally raise the temperature of the inspection stage 2, the inspection stages 2 themselves are connected, so that the chips around the semiconductor chip 3 being measured also rise in temperature due to heat conduction. As a result, there will be semiconductor chips 3 whose temperature is continuously raised while the influence of the temperature rise of the semiconductor chip 3 being measured remains. However, as shown in Figures 6 and 7, by setting the inspection order of the semiconductor chips 3 to be inspected and adjusting the temperature of the parts of the wafer 1 corresponding to the set order, it is possible to reduce, even if only slightly, the time that the semiconductor chips 3 continuously reach high temperatures.

[0030] <Third Embodiment> A wafer testing apparatus according to a third embodiment of the present disclosure will be described with reference to Figures 8 and 9. Figures 8 and 9 are cross-sectional views illustrating the configuration of a wafer testing apparatus 300 according to the third embodiment.

[0031] 8 shows a state in which a probe card 6 is placed above a wafer 1 mounted on an inspection stage 2, and is a cross-sectional view of the probe card 6. The cross-sectional configuration of the inspection stage 2 is the same as that of the inspection stage 2 shown in FIG. 2, and although not shown, multiple heaters 11a have temperature adjustment mechanisms 11 that are separated from each other and controlled independently.

[0032] The probe card 6 is a probe card having cantilever-type probes 4, but can also be a spring probe type, and has a plurality of heater holes 62 for accommodating heaters 5 (second heaters) in an outer wall 61 outside the area where the probes 4 are arranged. The heater holes 62 are provided so as to extend in the height direction (vertical direction) from the bottom surface of the outer wall 61, and are provided inside with elastic wiring 63 that is connected to the heaters 5, supplies power to heat the heaters 5, and suspends the heaters 5 from the bottom of the holes. The wiring 63 has elasticity so as to urge the heaters 5 in the vertical direction, and when the probe card 6 is placed above the wafer 1 as shown in FIG. 8, the heaters 5 are suspended from the wiring 63, and the wiring 63 is in an extended state.

[0033] 9 shows a state in which the probes 4 of the probe card 6 are in contact with the wafer 1, and the end face of the heater 5 is also in contact with the wafer 1. In this state, part of the heater 5 is housed in the heater hole 62, the wiring 63 is compressed between the heater 5 and the bottom of the hole, and the end face of the heater 5 is pressed strongly against the wafer 1 by the repulsive force of the wiring 63.

[0034] For convenience, Figures 8 and 9 show only a part of the probe card, i.e., the housing portion that houses the probes 4. In reality, the housing portion includes a probe card substrate including wiring, but this is not shown.

[0035] When the probes 4 of the probe card 6 contact the wafer 1 and the heater 5 is energized with its end face pressed against the wafer 1, the heat generated by the heater 5 causes the temperature of the semiconductor chip 3 to be measured to rise from the top side, as shown in Fig. 9. The temperature of the semiconductor chip 3 is also raised from the bottom side by the temperature adjustment mechanism 11 in the inspection stage 2. In Fig. 9, the area of ​​the semiconductor chip 3 where the temperature is rising is indicated by hatching.

[0036] In this way, the temperature rise time can be shortened by raising the temperature of the semiconductor chip 3 from the top side as well as the bottom side. In the sense of raising the temperature of the semiconductor chip 3, the heater 5 can also be said to be a temperature adjustment mechanism.

[0037] Furthermore, by preheating the probe 4 with the heater 5, the work involved in preheating can be simplified.

[0038] Preheating the probe 4 is a process of warming the probe 4 before performing high-temperature measurements. The probe 4 is generally made of metal, which undergoes thermal expansion. If a non-preheated probe 4 is brought into contact with a high-temperature semiconductor chip 3 when measuring the chip, heat will be transferred to the probe 4 during the characteristics measurement, and thermal expansion may cause the needle of the probe 4 to sink into the semiconductor chip 3.

[0039] Conventionally, before measuring electrical characteristics, the probes were preheated by bringing them close to a stage heated to a high temperature for a certain period of time. However, in the wafer testing device 300 of embodiment 3, the probes 4 are preheated using a heater 5 provided on the probe card 6, and then the semiconductor chip 3 is heated using a temperature adjustment mechanism 11 in the inspection stage 2, thereby simplifying the work involved in preheating.

[0040] The number of heaters 5 to be arranged is not particularly limited, but from the viewpoint of uniformly raising the temperature of the semiconductor chip 3, the more the better, and as an example, 4 to 8 heaters can be arranged.

[0041] <Fourth Embodiment> A wafer testing apparatus according to a fourth embodiment of the present disclosure will be described with reference to Figures 10 and 11. Figure 10 is a cross-sectional view illustrating the configuration of a wafer testing apparatus 400 according to the fourth embodiment, showing a state in which a probe card 6A is placed on a wafer 1 mounted on an inspection stage 2. Figure 11 is a plan view of the probe card 6A as seen from the bottom side, and the cross section taken along line BB in Figure 11 corresponds to the cross section in Figure 10. In the probe card 6A in Figure 10, the same components as those in the probe card 6 shown in Figure 8 are designated by the same reference numerals, and redundant explanations will be omitted.

[0042] The probe card 6A shown in Figure 10 has an outer wall 61 outside the area where the probes 4 are arranged, which has multiple heater holes 62 for accommodating heaters 5, as well as sensor holes 64 for accommodating temperature sensors 7 such as resistance thermometers and thermocouples.

[0043] As an example of a resistance temperature detector, a platinum resistance temperature detector can be used, which measures temperature by measuring the resistivity of platinum, taking advantage of the fact that the resistivity of platinum changes depending on the temperature.

[0044] The sensor hole 64 is provided so as to extend in the height direction (vertical direction) from the bottom surface of the outer wall 61, and inside is provided a resilient wiring 65 that is connected to the sensor 7, detects the output signal of the sensor 7, and suspends the sensor 7 from the bottom of the hole. The wiring 65 has resilience so as to urge the sensor 7 in the vertical direction, and when the probe 4 of the probe card 6 is placed so as to contact the wafer 1 as shown in Figure 10, the end face of the sensor 7 also comes into contact with the wafer 1. In this state, a part of the sensor 7 is housed in the sensor hole 64, the wiring 65 is compressed between the sensor 7 and the bottom of the hole, and the end face of the sensor 7 is pressed strongly against the wafer 1 by the repulsive force of the wiring 65.

[0045] 11, the sensors 7 are provided at four locations outside the area where the probes 4 are arranged. The heaters 5 are also provided at four locations in the area where the probes 4 are not arranged. In this way, the probe card 6A has the sensors 7, and when the semiconductor chip 3 to be measured is inspected, the sensors 7 come into contact with the semiconductor chip 3, so that the temperature of the semiconductor chip 3 can be measured directly.

[0046] Conventionally, in wafer-level testing, the temperature of the chip being measured is not measured directly, but is instead measured by monitoring the temperature of the stage. However, because the temperature of the stage varies across its surface, for example, the temperature at the edges is lower than that at the center, monitoring the stage temperature can result in the chip temperature not being measured accurately.

[0047] However, in the wafer testing apparatus 400 of the fourth embodiment, the temperature of the semiconductor chip 3 can be measured directly, and an accurate temperature can be obtained, so that the characteristic values ​​of the semiconductor chip 3 can be corrected by temperature, and the characteristics of the semiconductor chip 3 can be obtained in more detail.

[0048] Furthermore, by using a resistance temperature detector, a thermocouple, or the like as the temperature sensor 7, the temperature sensor 7 can have a relatively simple structure.

[0049] <Fifth Embodiment> A wafer testing apparatus according to a fifth embodiment of the present disclosure will be described with reference to Figures 12 to 14. Figures 12 and 13 are cross-sectional views illustrating the configuration of a wafer testing apparatus 500 according to the fifth embodiment, and Figure 14 is a plan view of a probe card 6B viewed from the bottom side, with the cross section taken along line CC in Figure 14 corresponding to the cross sections of Figures 12 and 13.

[0050] 12 shows a state in which the probe card 6B is placed above the wafer 1 mounted on the inspection stage 2, and the probe card 6B is shown in cross section. In the probe card 6B in FIG. 12, the same components as those in the probe card 6 shown in FIG. 8 are denoted by the same reference numerals, and redundant explanations will be omitted.

[0051] The probe card 6B shown in FIG. 12 is provided with a heater 5 on an outer wall 61 outside the area where the probes 4 are arranged, as well as a nozzle 9 of a blower (not shown) that blows hot and cold air onto the semiconductor chip 3. It also has a pressure wall 8 that seals the space between the probe card 6B and the semiconductor chip 3 to be measured. The pressure wall 8 is provided so as to surround the outer wall 61 of the probe card 6B and is fixed to the outer wall 61 of the probe card 6B. The pressure wall 8 can be made of the same material as the outer wall 61, or can be made of a different material. If the pressure wall 8 is made of the same material as the outer wall 61, it can be made into an integral structure with the outer wall 61.

[0052] 14, the nozzles 9 are provided at four locations outside the area where the probes 4 are arranged. The heaters 5 are provided at four locations in the area where the probes 4 are not arranged. The number of nozzles 9 to be arranged is not particularly limited, but from the viewpoint of uniformly raising or lowering the temperature of the semiconductor chip 3, the more the better, and as an example, two to four nozzles can be arranged.

[0053] 13 shows a state in which the probes 4 of the probe card 6B are in contact with the wafer 1, and the end face of the heater 5 is also in contact with the wafer 1. In this state, a part of the heater 5 is housed in the heater hole 62, the wiring 63 is compressed between the heater 5 and the bottom of the hole, the end face of the heater 5 is strongly pressed against the wafer 1 by the repulsive force of the wiring 63, and the pressure wall 8 is in contact with the wafer 1, sealing the space between the probe card 6B and the semiconductor chip 3 to be measured.

[0054] When the heater 5 is energized in this state, the heat generated by the heater 5 raises the temperature of the semiconductor chip 3 to be measured from the top side, and the temperature is also raised from the bottom side of the semiconductor chip 3 by the temperature adjustment mechanism 11 inside the inspection stage 2. Furthermore, by operating the blower device to emit hot air from the nozzle 9, the temperature of the semiconductor chip 3 can be raised rapidly from the top side.

[0055] In this way, by heating the semiconductor chip 3 from the top side as well as the bottom side, the temperature rise time can be shortened. In the sense of heating the semiconductor chip 3, the blowing device including the nozzle 9 can also be said to be a temperature adjustment mechanism. In this case, the hot air is at a temperature higher than room temperature (25°C) and is set to the temperature at which the semiconductor chip 3 to be measured will be inspected. The gas to be blown is not limited to air, and inert gases such as nitrogen, argon, and neon can also be used. However, if Paschen's law, which will be described later, is used, the discharge suppression effect varies depending on the type of gas to be blown, so the gas to be used should be selected taking this into consideration.

[0056] Furthermore, by blowing cool air at a temperature lower than room temperature (25°C), the temperature of the semiconductor chip 3 can be rapidly reduced, and by manipulating the temperature of the semiconductor chip 3, the time that the semiconductor chip 3 is in a high temperature state can be shortened.

[0057] Furthermore, by blowing gas onto the semiconductor chip 3 in the space sealed by the pressure wall 8, the space is pressurized, making it possible to prevent discharge.

[0058] That is, according to Paschen's law, the voltage that causes a spark discharge increases as the pressure approaches a vacuum or increases, so discharge at 1200V to 6500V, which is the withstand voltage of power semiconductor devices, can be suppressed by setting the pressure at about 200kPa (about 2 atmospheres) to 500kPa (about 5 atmospheres). Therefore, by filling the space sealed by pressure wall 8 with gas at this pressure, discharge during testing can be prevented.

[0059] <Sixth Embodiment> A wafer testing apparatus according to a sixth embodiment of the present disclosure will be described with reference to Figures 15 to 18. Figure 15 is a plan view illustrating the configuration of an inspection stage 2 of a wafer testing apparatus 600 according to the sixth embodiment, and Figure 16 is a cross-sectional view taken along line DD in Figure 15.

[0060] As shown in Fig. 15, a wafer 1 on which a plurality of semiconductor chips 3 are fabricated is mounted on an inspection stage 2. A movable stage 10 is provided inside the inspection stage 2, as shown in Fig. 16. The movable stage 10 has an internal heater 11a that comes into contact with at least the backside of the semiconductor chip 3 to be inspected on the wafer 1 mounted on the wafer mounting table 21 of the inspection stage 2, and heats at least the semiconductor chip 3 to be measured. In Figs. 15 and 16, the semiconductor chips 3 to be measured are shown surrounded by dashed lines, and in this example, three semiconductor chips 3 are being measured, but the number of measurement targets is not limited to this.

[0061] When testing the semiconductor chip 3, the movable stage 10 moves to directly below the semiconductor chip 3 to be measured and comes into contact with the back surface of the semiconductor chip 3 to be measured, allowing the temperature to be raised in a concentrated manner on the semiconductor chip 3 to be measured rather than on the entire wafer 1. Therefore, compared to the inspection stage 2 of embodiment 1 in which the inspection stage 2 is in contact with the entire wafer 1, heat is less likely to diffuse on the inspection stage 2, and the temperature rise time can be shortened.

[0062] The movable mechanism of the movable stage 10, not shown, is arranged so that the movable stage 10 can cover the entire wafer 1 below the wafer mounting table 21, and is also a mechanism that can heat the semiconductor chip 3 at the edge of the wafer 1.

[0063] 17 and 18 are diagrams showing wafer testing using a wafer testing apparatus 600, where FIG. 17 shows an example of testing three semiconductor chips 3 simultaneously, and FIG. 18 shows an example of testing semiconductor chips 3 one by one.

[0064] In the example shown in Figure 17, the movable stage 10 heats up three semiconductor chips 3, and the probes 4 extending from the three test circuits TB1, TB2 and TB3 of the probe card 6 respectively contact the three semiconductor chips 3 to be measured and test them simultaneously.When the testing of the three semiconductor chips 3 is completed, the movable stage 10 moves under the next semiconductor chip 3 to be measured.

[0065] In the example shown in FIG. 18, the movable stage 10 heats three semiconductor chips 3A, 3B, and 3C, and the probes 4 extending from the test circuit TB1 of the probe card 6 contact the semiconductor chip 3A to be tested. After the test of the semiconductor chip 3A is completed, the probe card 6 moves, and the probes 4 extending from the test circuit TB1 contact the semiconductor chip 3B to test it. After the test of the semiconductor chip 3B is completed, the probe card 6 moves, and the probes 4 extending from the test circuit TB1 contact the semiconductor chip 3C to test it. After the test of the semiconductor chips 3A to 3C is completed, the movable stage 10 moves to below the next semiconductor chip 3 to be tested.

[0066] It should be noted that, within the scope of the present disclosure, the embodiments can be freely combined, modified, or omitted as appropriate.

[0067] The present disclosure described above will be summarized as an appendix.

[0068] (Appendix 1) an inspection stage on which a wafer having a plurality of semiconductor chips is mounted; a probe card for testing the plurality of semiconductor chips; The inspection stage includes: a temperature control mechanism capable of adjusting the temperature of a portion of the wafer; The temperature adjustment mechanism includes: A wafer testing apparatus including a plurality of first heaters that are isolated from one another and independently controlled.

[0069] (Appendix 2) The temperature adjustment mechanism includes: 2. The wafer testing apparatus according to claim 1, wherein the plurality of first heaters are controlled to raise the temperature of at least one semiconductor chip among the plurality of semiconductor chips.

[0070] (Appendix 3) The plurality of first heaters include: 2. The wafer testing device according to claim 1, which is provided inside the inspection stage.

[0071] (Appendix 4) The temperature adjustment mechanism includes: 4. The wafer testing apparatus according to claim 1, wherein the plurality of first heaters are controlled to raise the temperature of corresponding portions of the wafer in accordance with a predetermined testing order of the plurality of semiconductor chips.

[0072] (Appendix 5) The inspection order of the plurality of semiconductor chips is a plurality of inspection paths are set based on the arrangement of the plurality of semiconductor chips; 5. The wafer testing apparatus according to claim 4, wherein the plurality of inspection paths are set to leave a gap for at least one semiconductor chip.

[0073] (Appendix 6) The probe card comprises: Located above the inspection stage, 2. A wafer testing apparatus according to claim 1, further comprising a second heater that contacts a surface of a semiconductor chip to be measured by bringing a probe into contact with the semiconductor chip to be measured among the plurality of semiconductor chips.

[0074] (Appendix 7) The probe card comprises: 7. The wafer testing apparatus according to claim 6, further comprising a temperature sensor that contacts a surface of the semiconductor chip to be measured by bringing the probe into contact with the semiconductor chip to be measured.

[0075] (Appendix 8) The temperature sensor 8. The wafer testing device of claim 7, comprising a resistance temperature detector or a thermocouple.

[0076] (Appendix 9) The probe card comprises: 7. The wafer testing apparatus according to claim 6, further comprising a nozzle of a blowing device that blows hot or cold air onto the semiconductor chip to be measured while the probe is in contact with the semiconductor chip to be measured.

[0077] (Appendix 10) The probe card comprises: 10. The wafer testing apparatus according to claim 9, further comprising a pressure wall that seals a space between the probe and the semiconductor chip under test while the probe is in contact with the semiconductor chip under test.

[0078] (Appendix 11) The inspection stage includes: a movable stage that partially contacts the wafer when the wafer is mounted thereon, The movable stage is 2. A wafer testing apparatus according to claim 1, which is controlled to contact a surface of a semiconductor chip to be measured among the plurality of semiconductor chips, raise the temperature of the semiconductor chip to be measured, and move when measurement of the semiconductor chip to be measured is completed. [Explanation of symbols]

[0079] 1 wafer, 2 inspection stage, 3 semiconductor chip, 5,11a heater, 6 probe card, 7 temperature sensor, 8 pressure wall, 9 nozzle, 10 movable stage, 11 temperature control mechanism.

Claims

1. an inspection stage on which a wafer having a plurality of semiconductor chips is mounted; a probe card for testing the plurality of semiconductor chips; The inspection stage includes: a temperature control mechanism capable of adjusting the temperature of a portion of the wafer; The temperature adjustment mechanism includes: A wafer testing apparatus including a plurality of first heaters that are isolated from one another and independently controlled.

2. The temperature adjustment mechanism includes:

2. The wafer testing device according to claim 1, wherein said plurality of first heaters are controlled so as to raise the temperature of at least one semiconductor chip among said plurality of semiconductor chips.

3. The plurality of first heaters include:

2. The wafer testing device according to claim 1, wherein the wafer testing device is provided inside the inspection stage.

4. The temperature adjustment mechanism includes:

4. The wafer testing device according to claim 1, wherein the plurality of first heaters are controlled to raise the temperature of corresponding portions of the wafer in accordance with a predetermined testing order of the plurality of semiconductor chips.

5. The inspection order of the plurality of semiconductor chips is a plurality of inspection paths are set based on the arrangement of the plurality of semiconductor chips; 5. The wafer testing device according to claim 4, wherein the plurality of testing paths are set so as to leave a gap of at least one semiconductor chip therebetween.

6. The probe card comprises: Located above the inspection stage, 2. The wafer testing device according to claim 1, further comprising a second heater that contacts a surface of a semiconductor chip to be measured by bringing a probe into contact with the semiconductor chip to be measured among the plurality of semiconductor chips.

7. The probe card comprises:

7. The wafer testing device according to claim 6, further comprising a temperature sensor that contacts the surface of the semiconductor chip to be measured by bringing the probe into contact with the semiconductor chip to be measured.

8. The temperature sensor 8. The wafer testing device according to claim 7, which is comprised of a resistance temperature detector or a thermocouple.

9. The probe card comprises:

7. The wafer testing device according to claim 6, further comprising a nozzle of a blowing device for blowing hot or cold air onto said semiconductor chip to be measured while said probe is in contact with said semiconductor chip to be measured.

10. The probe card comprises:

10. The wafer testing device according to claim 9, further comprising a pressure wall for sealing a space between the probe and the semiconductor chip under test while the probe is in contact with the semiconductor chip under test.

11. The inspection stage includes: a movable stage that partially contacts the wafer when the wafer is mounted thereon, The movable stage is 2. The wafer testing device according to claim 1, which is controlled to contact a surface of a semiconductor chip to be measured among the plurality of semiconductor chips, to heat the semiconductor chip to be measured, and to move when measurement of the semiconductor chip to be measured is completed.

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