Manufacturing method of multilayer wiring board and the multilayer wiring board

Abstract

To provide a manufacturing method of a multilayer wiring board and the multilayer wiring board capable of improving both heat dissipation and manufacturing efficiency.SOLUTION: A manufacturing method for a multilayer wiring board 1 includes: a step of stacking an insulating layer 14 on an insulating layer 13; a step of forming a plurality of non-through holes 34 penetrating the insulating layer 13 and the insulating layer 14; a step of filling the plurality of non-through holes 34 with a plurality of conductors 24; a step of stacking the insulating layer 15 on the insulating layer 14; a step of forming a plurality of non-through holes 35 penetrating the insulating layer 14 and the insulating layer 15; and a step of filling the plurality of non-through holes 35 with the plurality of conductors 25. In the step of forming the plurality of non-through holes 34, the plurality of non-through holes 34 are formed at intervals in an X-axis direction. In the step of forming the plurality of non-through holes 35, the plurality of non-through holes 35 are formed between the plurality of non-through holes 34 so that the plurality of non-through holes 35 do not overlap the plurality of non-through holes 34 when viewed along a Z-axis direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a multilayer wiring board and a multilayer wiring board. [Background technology]

[0002] High-density modules are used in small devices such as smartphones to achieve high functionality and miniaturization. In high-density modules, electronic components are densely mounted in a small area, so there is a demand for improved heat dissipation for heat generated by the electronic components. Methods described in Patent Documents 1 to 4 are known as examples of methods for improving the heat dissipation of printed wiring boards for modules. For example, Patent Document 1 describes a method for manufacturing a printed wiring board in which a process of forming blind holes in an insulating substrate constituting the printed wiring board and filling the holes with conductive plating is repeated multiple times to arrange via holes at a high density. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-119057 [Patent Document 2] Japanese Patent Application Laid-Open No. 2010-263003 [Patent Document 3] Japanese Patent Application Laid-Open No. 2013-211502 [Patent Document 4] Japanese Patent Application Publication No. 2019-029610 Summary of the Invention [Problem to be solved by the invention]

[0004] When manufacturing a multilayer wiring board, heat dissipation can be improved by forming thermal vias at a high density based on, for example, the technology described in Patent Document 1. However, as the thermal via density increases, the number of times that holes are drilled and conductors are filled to form the thermal vias increases, which may reduce the manufacturing efficiency of the multilayer wiring board.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method for manufacturing a multilayer wiring board and a multilayer wiring board that can improve both heat dissipation and manufacturing efficiency. [Means for solving the problem]

[0006] The method for manufacturing a multilayer wiring board of the present invention is [1] "a method for manufacturing a multilayer wiring board, comprising: a step of stacking a second insulating layer on a first insulating layer in a first direction; a step of forming a plurality of first non-through holes that penetrate the first insulating layer and the second insulating layer in the first direction; a step of filling each of the first non-through holes with a plurality of first conductors; a step of stacking a third insulating layer on the second insulating layer in the first direction; a step of forming a plurality of second non-through holes that penetrate the second insulating layer and the third insulating layer in the first direction; and a step of filling each of the second non-through holes with a plurality of second conductors, wherein in the step of forming the plurality of first non-through holes, the plurality of first non-through holes are formed to be spaced apart from each other in a second direction perpendicular to the first direction; and in the step of forming the plurality of second non-through holes, the plurality of second non-through holes are formed between the plurality of first non-through holes so that the plurality of second non-through holes do not overlap with the plurality of first non-through holes when viewed from the first direction."

[0007] In the method for manufacturing a multilayer wiring board described in [1], a second insulating layer is laminated on a first insulating layer, and then a plurality of first non-through holes are formed penetrating the first and second insulating layers, and a plurality of first conductors are respectively filled into the plurality of first non-through holes. Furthermore, a third insulating layer is laminated on the second insulating layer, and then a plurality of second non-through holes are formed penetrating the second and third insulating layers, and a plurality of second conductors are respectively filled into the plurality of second non-through holes. This reduces the number of times non-through holes are formed and filled with conductors compared to forming non-through holes and filling with conductors individually in each layer. Furthermore, in this manufacturing method, the plurality of first non-through holes are formed spaced apart from each other in the second direction, and the plurality of second non-through holes are formed between the plurality of first non-through holes so that the plurality of second non-through holes do not overlap with the plurality of first non-through holes when viewed from the first direction. This allows for a high density of non-through holes filled with conductors, and allows for a high density arrangement of conductors in the manufactured multilayer wiring board. Therefore, according to this method for manufacturing a multilayer wiring board, it is possible to improve both the heat dissipation properties of the multilayer wiring board and the manufacturing efficiency.

[0008] The method for manufacturing a multilayer wiring board of the present invention may be [2] "the method for manufacturing a multilayer wiring board according to [1], wherein in the step of forming the plurality of first non-through holes, the plurality of first non-through holes are formed so that the length along a third direction perpendicular to the first and second directions of each of the plurality of first non-through holes is longer than the length along the second direction of each of the plurality of first non-through holes, and in the step of forming the plurality of second non-through holes, the plurality of second non-through holes are formed so that the length along the third direction of each of the plurality of second non-through holes is longer than the length along the second direction of each of the plurality of second non-through holes." In this case, the number of times non-through holes are formed and filled with conductors can be reduced compared to when non-through holes whose length along the third direction is equal to the length along the second direction are repeatedly formed in the third direction. Furthermore, the conductors can be arranged at a higher density in the third direction. This further improves the heat dissipation and manufacturing efficiency of the multilayer wiring board.

[0009] The method for manufacturing a multilayer wiring board of the present invention may be [3] "the method for manufacturing a multilayer wiring board according to [2], wherein in the step of forming the plurality of first non-through holes, the plurality of first non-through holes are formed such that, for each of the plurality of first non-through holes, the ratio of the depth in the first direction to the length in the second direction is 1.2 or more and 2.0 or less, and the ratio of the depth in the first direction to the length in the third direction is 0.6 or more and 1.2 or less." In this case, in the step of filling the first non-through holes with the first conductor, it is possible to improve the embeddability of the first conductor and suppress the occurrence of voids.

[0010] The method for manufacturing a multilayer wiring board of the present invention may be [4] "the method for manufacturing a multilayer wiring board according to either [2] or [3], wherein in the step of forming the plurality of second non-through holes, the plurality of second non-through holes are formed such that, for each of the plurality of second non-through holes, the ratio of the depth in the first direction to the length in the second direction is 1.2 to 2.0, and the ratio of the depth in the first direction to the length in the third direction is 0.6 to 1.2." In this case, in the step of filling the second non-through holes with the second conductor, it is possible to improve the embeddability of the second conductor and suppress the occurrence of voids.

[0011] The method for manufacturing a multilayer wiring board of the present invention may be [5] "the method for manufacturing a multilayer wiring board according to any one of [1] to [4], wherein each of the plurality of first conductors and the plurality of second conductors is copper." In this case, the heat dissipation of the multilayer wiring board can be further improved.

[0012] The method for manufacturing a multilayer wiring board of the present invention may be [6] "the method for manufacturing a multilayer wiring board according to any one of [1] to [5], further comprising the steps of forming a plurality of third non-through holes that penetrate the third insulating layer in the first direction and filling the third non-through holes with a plurality of third conductors, wherein in the step of forming the third non-through holes, the third non-through holes are formed between the second non-through holes so that, when viewed from the first direction, the third non-through holes overlap with the first non-through holes but do not overlap with the second non-through holes." In this case, conductors can be arranged more densely in the multilayer wiring board, further improving the heat dissipation of the multilayer wiring board.

[0013] The multilayer wiring board of the present invention is a multilayer wiring board [7] comprising: a laminate having a first insulating layer, a second insulating layer, and a third insulating layer in that order in a first direction; and a plurality of first conductors and a plurality of second conductors disposed within the laminate, wherein the laminate has a plurality of first non-through holes penetrating the first insulating layer and the second insulating layer in the first direction and a plurality of second non-through holes penetrating the second insulating layer and the third insulating layer in the first direction, the plurality of first non-through holes being spaced apart from one another in a second direction perpendicular to the first direction, the plurality of second non-through holes being formed between the plurality of first non-through holes so as not to overlap with the plurality of first non-through holes when viewed from the first direction, the plurality of first conductors being filled in the plurality of first non-through holes, and the plurality of second conductors being filled in the plurality of second non-through holes, respectively. This multilayer wiring board can improve both heat dissipation and manufacturing efficiency for the reasons described above.

[0014] The multilayer wiring board of the present invention may be [8] "the multilayer wiring board according to [7], wherein the length of each of the plurality of first non-through holes along a third direction perpendicular to the first and second directions is longer than the length along the second direction, and the length of each of the plurality of second non-through holes along the third direction is longer than the length along the second direction." In this case, the heat dissipation and manufacturing efficiency of the multilayer wiring board can be further improved. [Effects of the Invention]

[0015] According to the present invention, it is possible to provide a method for manufacturing a multilayer wiring board and a multilayer wiring board that can improve both heat dissipation and manufacturing efficiency. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a cross-sectional view showing an example of a multilayer wiring board according to a first embodiment. [Figure 2] 2 is a cross-sectional view of the multilayer wiring board taken along line A1-A1 shown in FIG. [Figure 3] 2A to 2C are diagrams for explaining a method for manufacturing a multilayer wiring board according to the first embodiment. [Figure 4] 2A to 2C are diagrams for explaining a method for manufacturing a multilayer wiring board according to the first embodiment. [Figure 5] 2A to 2C are diagrams for explaining a method for manufacturing a multilayer wiring board according to the first embodiment. [Figure 6] 2A to 2C are diagrams for explaining a method for manufacturing a multilayer wiring board according to the first embodiment. [Figure 7] 2A to 2C are diagrams for explaining a method for manufacturing a multilayer wiring board according to the first embodiment. [Figure 8] 2A to 2C are diagrams for explaining a method for manufacturing a multilayer wiring board according to the first embodiment. [Figure 9] 2A to 2C are diagrams for explaining a method for manufacturing a multilayer wiring board according to the first embodiment. [Figure 10] 2A to 2C are diagrams for explaining a method for manufacturing a multilayer wiring board according to the first embodiment. [Figure 11]2A to 2C are diagrams for explaining a method for manufacturing a multilayer wiring board according to the first embodiment. [Figure 12] 2A to 2C are diagrams for explaining a method for manufacturing a multilayer wiring board according to the first embodiment. [Figure 13] FIG. 10 is a cross-sectional view showing an example of a multilayer wiring board according to a second embodiment. [Figure 14] 10A to 10C are diagrams for explaining a method for manufacturing a multilayer wiring board according to a second embodiment. [Figure 15] 10A to 10C are diagrams for explaining a method for manufacturing a multilayer wiring board according to a second embodiment. [Figure 16] 10 is a table showing the embedding of a conductor into a non-through hole and the occurrence of voids. [Figure 17] 1 is a table for explaining the effects of the methods for manufacturing a multilayer wiring board according to the first and second embodiments. [Figure 18] 1 is a cross-sectional view showing a multilayer wiring board manufactured by a manufacturing method according to Comparative Example 1. FIG. [Figure 19] 19 is a cross-sectional view of the multilayer wiring board taken along line A2-A2 shown in FIG. 18. [Figure 20] 10A and 10B are diagrams for explaining a method for manufacturing a multilayer wiring board according to Comparative Example 1. [Figure 21] 10A and 10B are diagrams for explaining a method for manufacturing a multilayer wiring board according to Comparative Example 1. [Figure 22] 10A and 10B are diagrams for explaining a method for manufacturing a multilayer wiring board according to Comparative Example 1. [Figure 23] 10 is a cross-sectional view showing a multilayer wiring board manufactured by a manufacturing method according to Comparative Example 2. FIG. [Figure 24] 24 is a cross-sectional view of the multilayer wiring board taken along line A3-A3 shown in FIG. 23. [Figure 25] 10A and 10B are diagrams for explaining a method for manufacturing a multilayer wiring board according to Comparative Example 2. [Figure 26] 10A and 10B are diagrams for explaining a method for manufacturing a multilayer wiring board according to Comparative Example 2. [Figure 27] 10A and 10B are diagrams for explaining a method for manufacturing a multilayer wiring board according to Comparative Example 2. [Figure 28]10A and 10B are diagrams for explaining a method for manufacturing a multilayer wiring board according to Comparative Example 2. [Figure 29] 10A and 10B are diagrams for explaining a method for manufacturing a multilayer wiring board according to Comparative Example 2. [Figure 30] 10A and 10B are diagrams for explaining a method for manufacturing a multilayer wiring board according to Comparative Example 2. [Figure 31] 10 is a cross-sectional view showing a multilayer wiring board manufactured by a manufacturing method according to Comparative Example 3. FIG. [Figure 32] 32 is a cross-sectional view of the multilayer wiring board taken along line A3-A3 shown in FIG. 31. [Figure 33] 10A and 10B are diagrams for explaining a method for manufacturing a multilayer wiring board according to Comparative Example 3. [Figure 34] 10A and 10B are diagrams for explaining a method for manufacturing a multilayer wiring board according to Comparative Example 3. [Figure 35] 10A and 10B are diagrams for explaining a method for manufacturing a multilayer wiring board according to Comparative Example 3. DETAILED DESCRIPTION OF THE INVENTION

[0017] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same or equivalent elements are designated by the same reference numerals, and redundant description will be omitted.

[0018] [Multilayer wiring board configuration] FIG. 1 is a cross-sectional view showing an example of a multilayer wiring board 1 according to a first embodiment. The multilayer wiring board 1 includes a laminate 10 having insulating layers 11-15, a plurality of conductors 21-25 arranged within the laminate 10, copper foils 41-46, and metal layers 51-55. In the laminate 10, insulating layer 11, insulating layer 12, insulating layer 13 (first insulating layer), insulating layer 14 (second insulating layer), and insulating layer 15 (third insulating layer) are stacked in this order. Hereinafter, the stacking direction of the insulating layers 11-15 is referred to as the Z-axis direction (first direction), a direction perpendicular to the Z-axis direction is referred to as the X-axis direction (second direction), and a direction perpendicular to the Z-axis direction and the X-axis direction is referred to as the Y-axis direction (third direction). In this example, the multilayer wiring board 1 is a six-layer build-up wiring board.

[0019] The insulating layers 11-15 are formed of, for example, prepreg. Prepreg is a sheet-like material in which fibers such as glass cloth or carbon fiber are impregnated with resin (for example, thermosetting resin such as epoxy, phenol, or polyimide). The insulating layers 11-15 may have a thickness of about 20 μm. The multiple conductors 21-25 are made of a thermally conductive metal, and in this example, are made of copper. The multiple conductors 21-25 function as thermal via blocks in the multilayer wiring board 1. A thermal via block is a collection of multiple conductors formed on the multilayer wiring board, and is used to control the conduction of heat from modules and the like mounted on the multilayer wiring board.

[0020] Insulating layer 11 and insulating layer 12 have a plurality of non-through holes 31 formed therein that penetrate insulating layer 11 and insulating layer 12 in the Z-axis direction. Non-through holes are holes that do not penetrate the entire multilayer wiring board, and are holes formed in some of the insulating layers included in the multilayer wiring board. Hereinafter, holes formed across multiple insulating layers, such as non-through holes 31, may be referred to as "skip holes." A plurality of conductors 21 are filled in each of the non-through holes 31. The conductors 21 are arranged from insulating layer 11 to insulating layer 12. In other words, the portion of the conductor 21 located within insulating layer 11 is integrated with the portion of the conductor 21 located within insulating layer 12.

[0021] The insulating layer 12 has a plurality of non-through holes 32 formed therein that penetrate the insulating layer 12 in the Z-axis direction. The plurality of conductors 22 are filled in the plurality of non-through holes 32, respectively. The insulating layer 13 has a plurality of non-through holes 33 formed therein that penetrate the insulating layer 13 in the Z-axis direction. The plurality of conductors 23 are filled in the plurality of non-through holes 33, respectively.

[0022] The insulating layer 13 and the insulating layer 14 have a plurality of non-through holes 34 (a plurality of first non-through holes) formed therein, which penetrate the insulating layer 13 and the insulating layer 14 in the Z-axis direction. The non-through holes 34 are skip-type holes. A plurality of conductors 24 (a plurality of first conductors) are filled in the plurality of non-through holes 34, respectively. The conductors 24 are arranged from the insulating layer 13 to the insulating layer 14. That is, the portion of the conductor 24 located in the insulating layer 13 is integral with the portion of the conductor 24 located in the insulating layer 14.

[0023] The insulating layer 14 and the insulating layer 15 have a plurality of non-through holes 35 (a plurality of second non-through holes) formed therein, which penetrate the insulating layer 14 and the insulating layer 15 in the Z-axis direction. The non-through holes 35 are skip-type holes. A plurality of conductors 25 (a plurality of second conductors) are filled in each of the non-through holes 35. The conductors 25 are arranged from the insulating layer 14 to the insulating layer 15. In other words, the portion of the conductor 25 located in the insulating layer 14 is integral with the portion of the conductor 25 located in the insulating layer 15.

[0024] Copper foil 41 and metal layer 51 are formed on the surface of insulating layer 11 opposite to insulating layer 12. Metal layer 51 is formed integrally with conductor 21. Copper foil 41 and metal layer 51 form a circuit on the first layer (L1 layer) of multilayer wiring board 1. Copper foil 42 and metal layer 52 are formed between insulating layer 11 and insulating layer 12. Metal layer 52 is formed integrally with conductor 22. Copper foil 42 and metal layer 52 form a circuit on the second layer (L2 layer) of multilayer wiring board 1.

[0025] Copper foil 43 and metal layer 53 are formed between insulating layer 12 and insulating layer 13. Metal layer 53 is formed integrally with conductor 23. Copper foil 43 and metal layer 53 form a circuit on the third layer (L3 layer) of multilayer wiring board 1. Copper foil 44 is formed between insulating layer 13 and insulating layer 14. Copper foil 44 forms a circuit on the fourth layer (L4 layer) of multilayer wiring board 1.

[0026] Copper foil 45 and metal layer 54 are formed between insulating layer 14 and insulating layer 15. Metal layer 54 is formed integrally with conductor 24. Copper foil 45 and metal layer 54 form a circuit on the fifth layer (L5 layer) of multilayer wiring board 1. Copper foil 46 and metal layer 55 are formed on the surface of insulating layer 15 opposite insulating layer 14. Metal layer 55 is formed integrally with conductor 25. Copper foil 46 and metal layer 55 form a circuit on the sixth layer (L6 layer) of multilayer wiring board 1.

[0027] Here, the configuration of the plurality of conductors 21-25 and the plurality of non-through holes 31-35 will be described in more detail with reference to Fig. 2. Fig. 2 is a cross-sectional view of the multilayer wiring board 1 taken along line A1-A1 shown in Fig. 1. Fig. 2 shows cross sections of the insulating layer 14 taken along the X-axis direction and the Y-axis direction. When viewed from the Z-axis direction, each of the plurality of non-through holes 34 and the plurality of non-through holes 35 has an elongated hole shape. More specifically, each of the non-through holes 34 and the non-through holes 35 has a rectangular shape with rounded corners.

[0028] Each of the non-through holes 34 has a length L1 along the X-axis direction and a length L2 along the Y-axis direction. Length L2 is longer than length L1. Length L1 may be, for example, 30 μm or more and 150 μm or less. Length L2 may be, for example, 30 μm or more and 1000 μm or less. A plurality of conductors 24 are filled in each of the non-through holes 34. When viewed from the Z-axis direction, the outer edge shape of the conductors 24 matches the shape of the non-through holes 34. Therefore, the length of the conductors 24 along the X-axis direction matches length L1, and the length of the conductors 24 along the Y-axis direction matches length L2.

[0029] Each of the non-through holes 35 has a length L3 along the X-axis direction and a length L4 along the Y-axis direction. Length L4 is longer than length L3. Length L3 may be, for example, 30 μm or more and 150 μm or less. Length L4 may be, for example, 30 μm or more and 1000 μm or less. A plurality of conductors 25 are filled in each of the non-through holes 35. When viewed from the Z-axis direction, the outer edge shape of the conductors 25 matches the shape of the non-through holes 35. Therefore, the length of the conductors 25 along the X-axis direction matches length L3, and the length of the conductors 25 along the Y-axis direction matches length L4.

[0030] The plurality of non-through holes 34 are formed at intervals from one another in the X-axis direction. The plurality of non-through holes 35 are formed at intervals from one another in the X-axis direction. When viewed from the Z-axis direction, the plurality of non-through holes 35 are formed between the plurality of non-through holes 34 so as not to overlap with the plurality of non-through holes 34. In other words, the non-through holes 34 and the non-through holes 35 are formed alternately in the X-axis direction.

[0031] The plurality of conductors 24 are arranged spaced apart from one another in the X-axis direction. The plurality of conductors 25 are arranged spaced apart from one another in the X-axis direction. When viewed from the Z-axis direction, the plurality of conductors 25 are arranged between the plurality of conductors 24 so as not to overlap with each other. In other words, the conductors 24 and the conductors 25 are arranged alternately in the X-axis direction.

[0032] When viewed from the Z-axis direction, the shape and position of the non-through hole 31 are the same as the shape and position of the non-through hole 34. That is, the non-through hole 31 overlaps with the non-through hole 34 in the Z-axis direction. When viewed from the Z-axis direction, the shape and position of the conductor 21 are the same as the shape and position of the conductor 24. That is, the conductor 21 overlaps with the conductor 24 in the Z-axis direction.

[0033] When viewed from the Z direction, the shape and position of the non-through holes 32 and 33 are the same as the shape and position of the non-through hole 35. That is, the non-through holes 32 and 33 overlap with the non-through hole 35 in the Z-axis direction. When viewed from the Z direction, the shape and position of the conductors 22 and 23 are the same as the shape and position of the conductor 25. That is, the conductors 22 and 23 overlap with the conductor 25 in the Z-axis direction.

[0034] As shown in FIG. 1 , each of the non-through holes 34 has a depth D1 along the Z-axis direction. The depth D1 may be, for example, about 60 μm. The depth D1 may be defined as the distance in the Z-axis direction from the surface of the insulating layer 13 opposite the insulating layer 14 to the surface of the insulating layer 14 opposite the insulating layer 13, or as the sum of the thicknesses of the insulating layers 13 and 14 and the thicknesses of the circuits of the fourth layer (L4 layer) and the fifth layer (L5 layer). Each of the non-through holes 35 has a depth D2 along the Z-axis direction. The depth D2 may be, for example, about 60 μm. The depth D2 may be defined as the distance in the Z-axis direction from the surface of the insulating layer 14 opposite the insulating layer 15 to the surface of the insulating layer 15 opposite the insulating layer 14, or as the sum of the thicknesses of the insulating layers 14 and 15 and the thicknesses of the circuits of the fifth layer (L5 layer) and the sixth layer (L6 layer).

[0035] In each of the plurality of non-through holes 34, the ratio of the depth D1 to the length L1 (depth D1 / length L1) may be 1.2 or more and 2.0 or less, and the ratio of the depth D1 to the length L2 (depth D1 / length L2) may be 0.6 or more and 1.2 or less. In each of the plurality of non-through holes 35, the ratio of the depth D2 to the length L3 (depth D2 / length L3) may be 1.2 or more and 2.0 or less, and the ratio of the depth D2 to the length L4 (depth D2 / length L4) may be 0.6 or more and 1.2 or less. In each of the plurality of non-through holes 31, the ratios of the depth to the length along the X-axis direction and the length along the Y-axis direction may be the same as those of the non-through holes 34.

[0036] [Manufacturing method for multilayer wiring boards] Next, an example of a method for manufacturing multilayer wiring board 1 will be described with reference to Figures 1 to 12. First, a member corresponding to insulating layer 13 with conductor 23 disposed therein is formed by a coreless method. The coreless method is a method for manufacturing a multilayer wiring board using a support substrate (hereinafter also referred to as a dummy core) that does not constitute the multilayer wiring board itself that will be the product.

[0037] First, as shown in FIG. 3 , a laminate is prepared, including a dummy core 60 and a pair of prepregs 410 laminated on corresponding main surfaces of the dummy core 60. Each of the pair of prepregs 410 will be used as an insulating layer 13 in a later process. A copper foil 44 is formed on the surface of each prepreg 410 facing the dummy core 60, and a copper foil 43 is formed on the surface of each prepreg 410 opposite the dummy core 60. The size of the copper foil 44 is smaller than the copper foil 43 and the prepreg 410. The size of the copper foil is the area of ​​the copper foil when viewed from the thickness direction of the copper foil (in this example, the area along the X-axis and Y-axis directions). Similarly, the size of the prepreg is the area of ​​the prepreg when viewed from the thickness direction of the prepreg (in this example, the area along the X-axis and Y-axis directions). The dummy core 60 includes an insulating layer 61 and a pair of copper foils 62 laminated on both sides of the insulating layer 61. The dummy core 60 may be a copper-clad laminate. An end portion of the prepreg 410 in a direction perpendicular to the thickness direction is bonded to the copper foil 62 of the dummy core 60. In this example, the dummy core 60 and the prepreg 410 are formed in a rectangular plate shape. When viewed from the Z-axis direction, the edge portions along the outer edges (four sides) of the prepreg 410 are bonded to the dummy core 60.

[0038] Next, the prepreg 410 is cured to form a plurality of non-through holes 33 in the prepreg 410. The non-through holes 33 may be formed using, for example, a CO2 laser. At this time, the plurality of non-through holes 33 are formed at intervals from one another in the X-axis direction. The non-through holes 33 are formed so that the length along the Y-axis direction of each of the plurality of non-through holes 33 is longer than the length along the X-axis direction.

[0039] Next, as shown in FIG. 4, the non-through holes 33 are filled with the conductors 23, respectively. Specifically, first, smears (residues) on the inner surfaces of the non-through holes 33 and on the surface of the copper foil 44 exposed from the non-through holes 33 are removed by a desmear process. Next, base plating is applied to the inner surfaces of the non-through holes 33 and on the surface of the copper foil 44 exposed from the non-through holes 33. The base plating may be electroless copper plating. Next, the conductors 23 are embedded in the non-through holes 33 by a filling plating process. In this example, the conductors 23 are formed by a copper plating process. At this time, a metal layer 53 is also formed on the copper foil 43 by the copper plating process.

[0040] 5, the end of the laminate of the dummy core 60 and the pair of prepregs 410 is cut and removed to separate the prepregs 410 from the dummy core 60. Specifically, the portion of the prepregs 410 that is bonded to the dummy core 60 is removed. Because the copper foils 62 and 44 are not bonded to each other, the copper foils 62 and 44 are naturally separated from each other (separated without using a dedicated jig or device, etc.). This results in a member corresponding to the insulating layer 13 with the conductor 23 disposed therein.

[0041] 6, a circuit is formed on the insulating layer 13 by removing portions of the copper foils 43, 44 and the metal layer 53. At this time, portions of the copper foil 44 are removed that correspond to positions where non-through holes 34 (see FIG. 8) will be formed in a later step.

[0042] 7, insulating layer 12 and insulating layer 14 are laminated in the Z-axis direction on insulating layer 13. These layers are arranged so that insulating layer 12, insulating layer 13, and insulating layer 14 are laminated in this order in the Z-axis direction. Insulating layer 12 and insulating layer 14 are, for example, prepreg. Copper foil 42 is formed on the surface of insulating layer 12 opposite to insulating layer 13, and copper foil 45 is formed on the surface of insulating layer 14 opposite to insulating layer 13.

[0043] 8, a plurality of non-through holes 32 are formed in the insulating layer 12, and a plurality of non-through holes 34 are formed in the insulating layers 13 and 14. The non-through holes 32 and 34 may be formed using, for example, a CO2 laser. The plurality of non-through holes 32 are formed at intervals from one another in the X-axis direction. The plurality of non-through holes 32 are formed so that the plurality of non-through holes 32 overlap with the plurality of non-through holes 33 when viewed from the Z direction. The plurality of non-through holes 32 are formed so that the length along the Y-axis direction of each of the plurality of non-through holes 32 is longer than the length along the X-axis direction.

[0044] A plurality of non-through holes 34 are formed at intervals from one another in the X-axis direction. The non-through holes 34 are defined by the surfaces of the insulating layers 13 and 14 and the surfaces of the conductors 23. The plurality of non-through holes 34 are formed so that they do not overlap with the plurality of non-through holes 33 when viewed from the Z direction. The non-through holes 34 are formed so that the length L2 of each of the non-through holes 34 along the Y-axis direction is longer than the length L1 of each of the non-through holes 34 along the X-axis direction. The non-through holes 34 are formed so that the ratio of the depth D1 to the length L1 of each of the non-through holes 34 is 1.2 or more and 2.0 or less, and the ratio of the depth D1 to the length L2 of each of the non-through holes 34 is 0.6 or more and 1.2 or less.

[0045] Next, as shown in FIG. 8 , the non-through holes 32 are filled with the conductors 22, respectively. Specifically, first, smears on the inner surfaces of the non-through holes 32 and on the surface of the metal layer 53 exposed from the non-through holes 32 are removed by a desmearing process. Next, base plating is applied to the inner surfaces of the non-through holes 32 and on the surface of the metal layer 53 exposed from the non-through holes 32. The base plating may be electroless copper plating. Next, the conductors 22 are embedded in the non-through holes 32 by a filling plating process. In this example, the conductors 22 are formed by a copper plating process. At this time, the metal layer 52 is also formed on the copper foil 42 by the copper plating process.

[0046] 8, a plurality of conductors 24 are filled into a plurality of non-through holes 34. Specifically, first, smears on the inner surfaces of the non-through holes 34 and on the surface of the copper foil 43 exposed from the non-through holes 34 are removed by a desmearing process. Next, base plating is applied to the inner surfaces of the non-through holes 34 and on the surface of the copper foil 43 exposed from the non-through holes 34. The base plating may be electroless copper plating. Next, the conductors 24 are embedded in the non-through holes 34 by a filling plating process. In this example, the conductors 24 are formed by a copper plating process. At this time, a metal layer 54 is also formed on the copper foil 45 by the copper plating process.

[0047] 9, a circuit is formed on the insulating layer 12 by removing a portion of the copper foil 42 and the metal layer 52. At this time, portions of the copper foil 42 and the metal layer 52 corresponding to positions where non-through holes 31 (see FIG. 11) will be formed in a later step are removed. Also, a circuit is formed on the insulating layer 14 by removing a portion of the copper foil 45 and the metal layer 54. At this time, portions of the copper foil 45 and the metal layer 54 corresponding to positions where non-through holes 35 (see FIG. 11) will be formed in a later step are removed.

[0048] 10, insulating layer 11 is laminated on insulating layer 12 in the Z-axis direction, and insulating layer 15 is laminated on insulating layer 14 in the Z-axis direction. These layers are arranged so that insulating layer 11, insulating layer 12, insulating layer 13, insulating layer 14, and insulating layer 15 are laminated in this order in the Z-axis direction. Insulating layer 11 and insulating layer 15 are made of, for example, prepreg. Copper foil 41 is formed on the surface of insulating layer 11 opposite to insulating layer 12, and copper foil 46 is formed on the surface of insulating layer 15 opposite to insulating layer 14.

[0049] Next, as shown in FIG. 11 , a plurality of non-through holes 31 are formed in the insulating layers 11 and 12, and a plurality of non-through holes 35 are formed in the insulating layers 14 and 15. The non-through holes 31 are defined by the surfaces of the insulating layers 11 and 12 and the surface of the conductor 22. The non-through holes 35 are defined by the surfaces of the insulating layers 14 and 15 and the surface of the conductor 24. The non-through holes 31 and 35 may be formed using, for example, a CO laser. The plurality of non-through holes 31 are formed at intervals from each other in the X-axis direction. The plurality of non-through holes 31 are formed so that the plurality of non-through holes 31 do not overlap with the plurality of non-through holes 32 when viewed from the Z-axis direction. The non-through holes 31 are formed so that the length of each of the plurality of non-through holes 31 along the Y-axis direction is longer than the length along the X-axis direction.

[0050] The non-through holes 35 are formed at intervals from one another in the X-axis direction. The non-through holes 35 are formed so that the non-through holes 35 do not overlap the non-through holes 34 when viewed from the Z direction. The non-through holes 35 are formed so that the length L4 along the Y-axis direction is longer than the length L3 along the X-axis direction for each of the non-through holes 35. The non-through holes 35 are formed so that the ratio of the depth D2 to the length L3 for each of the non-through holes 35 is 1.2 or more and 2.0 or less, and the ratio of the depth D2 to the length L4 for each of the non-through holes 35 is 0.6 or more and 1.2 or less.

[0051] Next, as shown in FIG. 12 , the non-through holes 31 are filled with the conductors 21, respectively. Specifically, first, smears on the inner surfaces of the non-through holes 31 and on the surface of the metal layer 53 exposed from the non-through holes 31 are removed by a desmearing process. Next, base plating is applied to the inner surfaces of the non-through holes 31 and on the surface of the metal layer 53 exposed from the non-through holes 31. The base plating may be electroless copper plating. Next, the conductors 21 are embedded in the non-through holes 31 by a filling plating process. In this example, the conductors 21 are formed by a copper plating process. At this time, the metal layer 51 is also formed on the copper foil 41 by the copper plating process.

[0052] 12, a plurality of conductors 25 are filled into a plurality of non-through holes 35. Specifically, first, smears on the inner surface of the non-through holes 35 and on the surface of the copper foil 44 exposed from the non-through holes 35 are removed by a desmearing process. Next, base plating is applied to the inner surface of the non-through holes 35 and on the surface of the copper foil 44 exposed from the non-through holes 35. The base plating may be electroless copper plating. Next, the conductors 25 are embedded in the non-through holes 35 by a filling plating process. In this example, the conductors 25 are formed by a copper plating process. At this time, a metal layer 55 is also formed on the copper foil 46 by the copper plating process.

[0053] 1, a circuit is formed on insulating layer 11 by removing a portion of copper foil 41 and metal layer 51. A circuit is also formed on insulating layer 15 by removing a portion of copper foil 46 and metal layer 55. In this manner, multilayer wiring board 1 is obtained.

[0054] In the manufacturing method of the multilayer wiring board 1 according to the present embodiment, after laminating an insulating layer 14 on an insulating layer 13, a plurality of non-through holes 34 are formed penetrating the insulating layers 13 and 14, and a plurality of conductors 24 are respectively filled into the plurality of non-through holes 34. Furthermore, after laminating an insulating layer 15 on the insulating layer 14, a plurality of non-through holes 35 are formed penetrating the insulating layers 14 and 15, and a plurality of conductors 25 are respectively filled into the plurality of non-through holes 35. This reduces the number of times that non-through holes are formed and filled with conductors compared to when non-through holes are formed and filled with conductors individually in each layer. Furthermore, in the manufacturing method according to the present embodiment, the plurality of non-through holes 34 are formed spaced apart from one another in the X-axis direction, and the plurality of non-through holes 35 are formed between the plurality of non-through holes 34 so that they do not overlap with each other when viewed from the Z-axis direction. This allows the non-through holes filled with conductors to be formed at a high density, and the conductors can be arranged at a high density in the manufactured multilayer wiring board 1. Therefore, according to this method for manufacturing multilayer wiring board 1, it is possible to improve both the heat dissipation properties of multilayer wiring board 1 and manufacturing efficiency.

[0055] In the process of forming the non-through holes 34, the non-through holes 34 are formed so that the length L2 along the Y-axis direction of each of the non-through holes 34 is longer than the length L1 along the X-axis direction. In the process of forming the non-through holes 35, the non-through holes 35 are formed so that the length L4 along the Y-axis direction of each of the non-through holes 35 is longer than the length L3 along the X-axis direction. This reduces the number of times the non-through holes are formed and filled with conductors compared to when non-through holes whose lengths along the Y-axis direction are equal to the lengths along the X-axis direction are repeatedly formed in the Y-axis direction. Furthermore, the conductors can be arranged with higher density in the Y-axis direction. This further improves the heat dissipation and manufacturing efficiency of the multilayer wiring board 1.

[0056] In the step of forming the non-through holes 34, the non-through holes 34 are formed so that the ratio of the depth D1 along the Z-axis direction to the length L1 along the X-axis direction is 1.2 or more and 2.0 or less, and the ratio of the depth D2 along the Z-axis direction to the length L2 along the Y-axis direction is 0.6 or more and 1.2 or less, in each of the non-through holes 34. This makes it possible to improve the embedding of the conductor 24 and suppress the occurrence of voids in the step of filling the non-through holes 34 with the conductor 24.

[0057] In the step of forming the non-through holes 35, the non-through holes 35 are formed so that the ratio of the depth D2 along the Z-axis direction to the length L3 along the X-axis direction is 1.2 or more and 2.0 or less, and the ratio of the depth D2 along the Z-axis direction to the length L4 along the Y-axis direction is 0.6 or more and 1.2 or less, in each of the non-through holes 35. This makes it possible to improve the embedding of the conductor 25 and to suppress the occurrence of voids in the step of filling the non-through holes 35 with the conductor 25.

[0058] Each of the plurality of conductors 24 and the plurality of conductors 25 is made of copper, which can further improve the heat dissipation properties of the multilayer wiring board 1.

[0059] [Second embodiment] Next, a multilayer wiring board 1A according to a second embodiment will be described. In the following description, differences from the multilayer wiring board 1 will be mainly described, and commonalities may be omitted. FIG. 13 is a cross-sectional view showing an example of the multilayer wiring board 1A according to the second embodiment. The multilayer wiring board 1A differs from the multilayer wiring board 1 in that it further includes a plurality of conductors 26, 27 and metal layers 56, 57. The plurality of conductors 26, 27 are arranged within the laminate 10.

[0060] In the insulating layer 11 according to this embodiment, a plurality of non-through holes 36 are formed which penetrate the insulating layer 11 in the Z-axis direction. A plurality of conductors 26 are filled in each of the plurality of non-through holes 36. A metal layer 56 is formed on the metal layer 51. The metal layer 56 is formed integrally with the conductors 26, and together with the copper foil 41 and the metal layer 51, constitutes a circuit on the first layer (L1 layer) of the multilayer wiring board 1A.

[0061] The non-through holes 36 are spaced apart from one another in the X-axis direction. When viewed from the Z-axis direction, the non-through holes 36 are formed between the non-through holes 31 so as not to overlap with the non-through holes 31. In other words, the non-through holes 31 and the non-through holes 36 are alternately formed in the X-axis direction.

[0062] The plurality of conductors 26 are arranged spaced apart from one another in the X-axis direction. When viewed from the Z-axis direction, the plurality of conductors 26 are arranged between the plurality of conductors 21 so as not to overlap with the plurality of conductors 21. In other words, the conductors 21 and the conductors 26 are arranged alternately in the X-axis direction.

[0063] When viewed from the Z-axis direction, the shape and position of the non-through holes 36 are the same as the shape and position of the non-through holes 35. That is, the non-through holes 36 overlap with the non-through holes 35 in the Z-axis direction. When viewed from the Z-axis direction, the shape and position of the conductors 26 are the same as the shape and position of the conductors 25. That is, the conductors 26 overlap with the conductors 25 in the Z-axis direction.

[0064] Insulating layer 15 according to this embodiment has a plurality of non-through holes 37 (a plurality of third non-through holes) formed therein that penetrate insulating layer 15 in the Z-axis direction. A plurality of conductors 27 (a plurality of third conductors) are filled in each of the plurality of non-through holes 37. Metal layer 57 is formed on metal layer 55. Metal layer 57 is formed integrally with conductor 27, and together with copper foil 46 and metal layer 55, constitutes a circuit on the sixth layer (L6 layer) of multilayer wiring board 1A.

[0065] The non-through holes 37 are formed at intervals in the X-axis direction. When viewed from the Z-axis direction, the non-through holes 37 are formed between the non-through holes 35 so as not to overlap with the non-through holes 35. In other words, the non-through holes 35 and the non-through holes 37 are formed alternately in the X-axis direction.

[0066] The plurality of conductors 27 are arranged spaced apart from one another in the X-axis direction. When viewed from the Z-axis direction, the plurality of conductors 27 are arranged between the plurality of conductors 25 so as not to overlap with the plurality of conductors 25. In other words, the conductors 25 and the conductors 27 are arranged alternately in the X-axis direction.

[0067] When viewed from the Z-axis direction, the shape and position of the non-through hole 37 are the same as the shape and position of the non-through hole 34. That is, the non-through hole 37 overlaps with the non-through hole 34 in the Z-axis direction. When viewed from the Z-axis direction, the shape and position of the conductor 27 are the same as the shape and position of the conductor 24. That is, the conductor 27 overlaps with the conductor 24 in the Z-axis direction.

[0068] Next, an example of a method for manufacturing multilayer wiring board 1A will be described with reference to Figures 13 to 15. First, of the method for manufacturing multilayer wiring board 1 described above, the steps up to the step described with reference to Figure 12 (the step of filling conductors 21, 25 and forming metal layers 51, 55) are performed.

[0069] Next, the thickness of the metal layers 51, 56 is reduced by half etching. The metal layers 51, 56 may be thinned so that they each have a thickness approximately equal to that of the copper foils 41, 46 (for example, 2 μm or more and 5 μm or less). Next, as shown in FIG. 14, a plurality of non-through holes 36 are formed in the insulating layer 11, and a plurality of non-through holes 37 are formed in the insulating layer 15. The non-through holes 36 are defined by the surface of the insulating layer 11 and the surface of the conductor 21. The non-through holes 37 are defined by the surface of the insulating layer 15 and the surface of the conductor 25. The non-through holes 36, 37 may be formed using, for example, a CO laser.

[0070] The non-through holes 36 are formed at intervals from one another in the X-axis direction. The non-through holes 36 are formed so that, when viewed from the Z direction, the non-through holes 36 do not overlap with the non-through holes 31. The non-through holes 36 are formed so that the length along the Y-axis direction of each of the non-through holes 36 is longer than the length along the X-axis direction.

[0071] The non-through holes 37 are formed at intervals in the X-axis direction. The non-through holes 37 are formed so that, when viewed from the Z direction, the non-through holes 37 do not overlap with the non-through holes 35. The non-through holes 37 are formed so that the length of each of the non-through holes 37 along the Y-axis direction is longer than the length along the X-axis direction.

[0072] Next, as shown in FIG. 15 , the non-through holes 36 are filled with the conductors 26, respectively. Specifically, first, smears on the inner surfaces of the non-through holes 36 and on the surface of the metal layer 52 exposed from the non-through holes 36 are removed by a desmearing process. Next, base plating is applied to the inner surfaces of the non-through holes 36 and on the surface of the metal layer 52 exposed from the non-through holes 36. The base plating may be electroless copper plating. Next, the conductors 26 are embedded in the non-through holes 36 by a filling plating process. In this example, the conductors 26 are formed by a copper plating process. At this time, a metal layer 56 is also formed on the metal layer 51 by the copper plating process.

[0073] 15, a plurality of conductors 27 are filled into a plurality of non-through holes 37. Specifically, first, smears on the inner surfaces of the non-through holes 37 and on the surface of the metal layer 54 exposed from the non-through holes 37 are removed by a desmearing process. Next, base plating is applied to the inner surfaces of the non-through holes 37 and on the surface of the metal layer 54 exposed from the non-through holes 37. The base plating may be electroless copper plating. Next, the conductors 27 are embedded in the non-through holes 37 by a filling plating process. In this example, the conductors 27 are formed by a copper plating process. At this time, the metal layer 57 is also formed on the metal layer 55 by the copper plating process.

[0074] 13, a circuit is formed on insulating layer 11 by removing portions of copper foil 41 and metal layers 51 and 56. Also, a circuit is formed on insulating layer 15 by removing portions of copper foil 46 and metal layers 55 and 57. In this manner, multilayer wiring board 1A is obtained.

[0075] The method for manufacturing multilayer wiring board 1A according to this embodiment includes the steps of forming a plurality of non-through holes 37 that penetrate insulating layer 15 in the Z-axis direction, and filling each of non-through holes 37 with a plurality of conductors 27. In the step of forming non-through holes 37, non-through holes 37 are formed between non-through holes 35 so that, when viewed from the Z-axis direction, non-through holes 37 overlap with non-through holes 34 but do not overlap with non-through holes 35. This allows conductors to be arranged more densely in multilayer wiring board 1A, further improving the heat dissipation of multilayer wiring board 1A.

[0076] [Example] The present invention will be described in more detail below with reference to examples, but the present invention is not limited to these examples.

[0077] FIG. 16 is a table showing the embeddability of conductors in non-through holes and the occurrence of voids. The embeddability of conductors and the occurrence of voids were examined for multiple non-through holes of different sizes. Non-through holes penetrating two insulating layers (e.g., non-through holes having a configuration similar to that of non-through hole 34 in the above embodiment) were prepared, and conductors were embedded (filled) in the non-through holes by a filling plating process. Copper was used as the plating material. The "minor diameter" in the table corresponds to the length along the short side of the non-through hole (e.g., the length L1 of non-through hole 34 in FIG. 2), and the "minor diameter aspect ratio" corresponds to the ratio of the depth of the non-through hole to the minor diameter. Here, each layer constituting the build-up wiring board is assumed to be composed of an insulating layer having a thickness of 20 μm and a circuit having a thickness of 10 μm, and the depth of the non-through hole is defined as the thickness of two layers (60 μm). In addition, the "long diameter" in the table corresponds to the length along the longitudinal direction of the non-through hole (for example, the length L2 of the non-through hole 34 in Figure 2), and the "long diameter aspect ratio" corresponds to the ratio of the depth of the non-through hole to the long diameter.

[0078] The results for conductor fillability are shown to the left of the / , and the results for void occurrence are shown to the right of the / . Regarding the fillability results, the symbol "A" indicates that the depression in the cross section of the filled conductor was between 0 μm and 4 μm, the symbol "B" indicates that the depression was between 4 μm and 8 μm, and the symbol "C" indicates that the depression was greater than 8 μm. Regarding void occurrence results, the symbol "A" indicates that no voids occurred in the filled conductor, and the symbol "B" indicates that voids occurred.

[0079] 16, when the minor axis aspect ratio was 2.00 and the major axis aspect ratio was 2.00, 1.20, 0.86, 0.60, or 0.12, and when the minor axis aspect ratio was 1.20 and the major axis aspect ratio was 2.00, 1.20, 0.86, 0.60, or 0.12, the embeddability was rated "A" (the depression was 4 μm or less). Furthermore, when the minor axis aspect ratio was 2.00 and the major axis aspect ratio was 1.20, 0.86, or 0.60, and when the minor axis aspect ratio was 1.20 and the major axis aspect ratio was 2.00, 1.20, 0.86, 0.60, or 0.12, the void occurrence was rated "A" (no voids occurred). Therefore, it was confirmed that when the minor axis aspect ratio is 2.00 and the major axis aspect ratio is 1.20, 0.86, or 0.60, and when the minor axis aspect ratio is 1.20 and the major axis aspect ratio is 2.00, 1.20, 0.86, 0.60, or 0.12, both the embeddability and void occurrence are rated "A" (the depression is 4 μm or less and no voids occur).

[0080] 17 is a table illustrating the effects of the manufacturing methods for multilayer wiring boards according to the first and second embodiments. The table in FIG. 17 shows simulation results for the performance and manufacturing costs of multilayer wiring boards manufactured by the manufacturing methods according to Examples 1 and 2 and Comparative Examples 1 to 3, as well as the number of steps. A six-layer multilayer wiring board (build-up wiring board) having thermal via blocks was formed by the manufacturing methods according to Examples 1 and 2 and Comparative Examples 1 to 3. The thickness of each insulating layer was 20 μm, the thickness of each circuit was 10 μm, and the overall thickness of the multilayer wiring board was 160 μm. The simulation was performed assuming the formation of a thermal via block with a width of 500 μm along the X-axis, a length of 500 μm along the Y-axis, and a thickness of 160 μm along the Z-axis.

[0081] Example 1 corresponds to the manufacturing method of multilayer wiring board 1 according to the first embodiment. In the manufacturing method according to Example 1, the spacing (pitch) between conductors 21 in the X-axis direction, the spacing between conductors 22, the spacing between conductors 23, the spacing between conductors 24, and the spacing between conductors 25 were each set to 100 μm. The spacing between conductors in a predetermined direction is, for example, the distance from the center of one conductor to the center of another conductor in the predetermined direction. Furthermore, the length of each conductor and each non-through hole along the X-axis direction was set to 50 μm, and the length along the Y-axis direction was set to 500 μm. Furthermore, conductors 21 to 25 were formed from copper.

[0082] Example 2 corresponds to the manufacturing method of multilayer wiring board 1A according to the second embodiment. That is, in the manufacturing method of Example 2, in addition to the manufacturing method of Example 1, a step of forming conductors 26 and 27 on the outermost layers (insulating layer 11 and insulating layer 15) is performed. In the manufacturing method of Example 2, the distance between conductors 21, the distance between conductors 22, the distance between conductors 23, the distance between conductors 24, the distance between conductors 25, the distance between conductors 26, and the distance between conductors 27 in the X-axis direction were each set to 100 μm. Furthermore, the length of each conductor and each non-through hole along the X-axis direction was set to 50 μm, and the length along the Y-axis direction was set to 500 μm. Furthermore, conductors 21 to 26 were formed of copper.

[0083] Next, comparative examples 1 to 3 will be described. First, the configuration of a multilayer wiring board 2A manufactured by a manufacturing method according to comparative example 1 will be described with reference to FIGS. 18 and 19. FIG. 18 is a cross-sectional view showing a multilayer wiring board 2A manufactured by a manufacturing method according to comparative example 1. FIG. 19 is a cross-sectional view of the multilayer wiring board 2A taken along line A2-A2 in FIG. 18. The multilayer wiring board 2A includes a laminate 101 having insulating layers 111, 121, 131, 141, and 151 (hereinafter sometimes referred to as "insulating layers 111 to 151"), and a plurality of conductors 211, 221, 231, 241, and 251 (hereinafter sometimes referred to as "conductors 211 to 251"). In the laminate 101, the insulating layer 111, the insulating layer 121, the insulating layer 131, the insulating layer 141, and the insulating layer 151 are stacked in this order in the Z-axis direction.

[0084] The insulating layers 111-151 are made of prepreg. The conductors 211-251 are made of copper. A collection of the conductors 211-251 functions as a thermal via block in the multilayer wiring board 2A. The insulating layer 111 has a plurality of non-through holes 311 formed therein that penetrate the insulating layer 111 in the Z-axis direction. The conductors 211 are filled in the non-through holes 311, respectively. Similarly, the insulating layers 121, 131, 141, and 151 have a plurality of non-through holes 321, 331, 341, and 351 formed therein that penetrate the corresponding insulating layers in the Z-axis direction. The conductors 221, 231, 241, and 251 are filled in the corresponding non-through holes 321, 331, 341, and 351, respectively. That is, in multilayer wiring board 2A, each conductor is located within a corresponding insulating layer (for example, conductor 211 is located within insulating layer 111), and no conductors are located across multiple different insulating layers.

[0085] 19 shows cross sections of insulating layer 111 along the X-axis and Y-axis directions. When viewed from the Z-axis direction, each of the non-through holes 311 has an elongated hole shape. More specifically, non-through holes 311 have a rectangular shape with rounded corners. The length of each of the non-through holes 311 along the X-axis direction is 50 μm, and the length of each of the non-through holes 311 along the Y-axis direction is 500 μm. The spacing between each of the non-through holes 311 (conductors 211) in the X-axis direction is 100 μm.

[0086] When viewed from the Z-axis direction, the shapes and positions of the non-through holes 321, 331, 341, and 351 are the same as the shape and position of the non-through hole 311. That is, the non-through holes 321, 331, 341, and 351 overlap with the non-through hole 311 in the Z-axis direction. When viewed from the Z-axis direction, the shapes and positions of the conductors 221, 231, 241, and 251 are the same as the shape and position of the conductor 211. That is, the conductors 221, 231, 241, and 251 overlap with the conductor 211 in the Z-axis direction.

[0087] 20 to 22, a method for manufacturing multilayer wiring board 2A will be described. First, as shown in Fig. 20, insulating layer 131 having a plurality of conductors 231 arranged thereon is formed. The process for forming insulating layer 131 is the same as the process for forming insulating layer 13 described with reference to Figs. 3 to 6, and therefore a description thereof will be omitted.

[0088] 20, insulating layer 121 and insulating layer 141 are stacked in the Z-axis direction on insulating layer 131. These layers are arranged so that insulating layer 121, insulating layer 131, and insulating layer 141 are stacked in this order in the Z-axis direction. Copper foil 421 is formed on the surface of insulating layer 121 opposite to insulating layer 131, and copper foil 451 is formed on the surface of insulating layer 141 opposite to insulating layer 131.

[0089] 21, a CO2 laser is used to form a plurality of non-through holes 321 in the insulating layer 121, and a plurality of non-through holes 341 in the insulating layer 141. The plurality of non-through holes 321, 341 are formed at intervals in the X-axis direction. The plurality of non-through holes 321, 341 are formed so that the plurality of non-through holes 321, 341 overlap with the plurality of non-through holes 331 when viewed from the Z direction.

[0090] Next, as shown in FIG. 21 , the non-through holes 321 are filled with the conductors 221, respectively. Specifically, first, smears inside the non-through holes 321 are removed by a desmearing process, and then base plating is applied. Next, the conductors 221 are formed by a filling plating process (copper plating process). At this time, a metal layer 521 is also formed on the copper foil 421 by the copper plating process. Furthermore, the non-through holes 341 are filled with the conductors 241, respectively. Specifically, the conductors 241 are formed by the copper plating process. At this time, a metal layer 541 is also formed on the copper foil 451 by the copper plating process.

[0091] 22, a circuit is formed on insulating layer 121 by removing a portion of copper foil 421 and metal layer 521, and a circuit is formed on insulating layer 141 by removing a portion of copper foil 451 and metal layer 541. Thereafter, similar steps such as laminating insulating layers, forming blind holes, and filling conductors are repeated to obtain multilayer wiring board 2A shown in FIG.

[0092] Next, the configuration of a multilayer wiring board 2B manufactured by the manufacturing method of Comparative Example 2 will be described with reference to Figures 23 and 24. Figure 23 is a cross-sectional view showing multilayer wiring board 2B manufactured by the manufacturing method of Comparative Example 2. Figure 24 is a cross-sectional view of multilayer wiring board 2B taken along line A3-A3 shown in Figure 23. Multilayer wiring board 2B includes laminate 102 having insulating layers 112, 122, 132, 142, and 152 (hereinafter sometimes referred to as "insulating layers 112-152"), a plurality of conductors 212A, 222A, 232A, 242A, and 252A (hereinafter sometimes referred to as "conductors 212A-252A"), and a plurality of conductors 212B-252B (hereinafter sometimes referred to as "conductors 212B-252B"). In the laminate 101, an insulating layer 112, an insulating layer 122, an insulating layer 132, an insulating layer 142, and an insulating layer 152 are laminated in this order in the Z-axis direction.

[0093] The insulating layers 112 to 152 are made of prepreg. The plurality of conductors 212A to 252A and 212B to 252B are made of copper. A collection of the plurality of conductors 212A to 252A and 212B to 252B functions as a thermal via block in the multilayer wiring board 2B. The insulating layer 112 is formed with a plurality of non-through holes 312A that penetrate the insulating layer 112 in the Z-axis direction. The plurality of conductors 212A are filled in the plurality of non-through holes 312A. Similarly, the insulating layers 122, 132, 142, and 152 are formed with a plurality of non-through holes 322A, 332A, 342A, and 352A that penetrate the corresponding insulating layers in the Z-axis direction, respectively. The plurality of conductors 222A, 232A, 242A, and 252A are filled in the corresponding plurality of blind holes 322A, 332A, 342A, and 352A, respectively.

[0094] Furthermore, insulating layer 112 has a plurality of non-through holes 312B formed therein that penetrate insulating layer 112 in the Z-axis direction. Conductors 212B are filled in each of the non-through holes 312B. Similarly, insulating layers 122, 132, 142, and 152 have a plurality of non-through holes 322B, 332B, 342B, and 352B formed therein that penetrate the corresponding insulating layer in the Z-axis direction. Conductors 222B, 232B, 242B, and 252B are filled in the corresponding non-through holes 322B, 332B, 342B, and 352B, respectively. That is, in multilayer wiring board 2B, each conductor is located within the corresponding insulating layer (for example, conductor 212A is located within insulating layer 112), and no conductors are located across different insulating layers.

[0095] 24 shows cross sections of insulating layer 122 along the X-axis and Y-axis directions. When viewed from the Z-axis direction, each of non-through holes 312A, 312B has an elongated hole shape. More specifically, non-through holes 312A, 312B have a rectangular shape with rounded corners. The length of non-through holes 312A, 312B along the X-axis direction is 50 μm, and the length of non-through holes 312A, 312B along the Y-axis direction is 500 μm. The spacing between non-through holes 312A in the X-axis direction is 100 μm, and the spacing between non-through holes 312B in the X-axis direction is 100 μm.

[0096] When viewed from the Z-axis direction, the shapes and positions of the non-through holes 322A, 332A, 342A, and 352A are the same as those of the non-through hole 312A. That is, the non-through holes 322A, 332A, 342A, and 352A overlap with the non-through hole 312A in the Z-axis direction. When viewed from the Z-axis direction, the shapes and positions of the conductors 222A, 232A, 242A, and 252A are the same as those of the conductor 212A. That is, the conductors 222A, 232A, 242A, and 252A overlap with the conductor 212A in the Z-axis direction.

[0097] When viewed from the Z-axis direction, the shapes and positions of the non-through holes 322B, 332B, 342B, and 352B are the same as those of the non-through hole 312B. That is, the non-through holes 322B, 332B, 342B, and 352B overlap with the non-through hole 312B in the Z-axis direction. When viewed from the Z-axis direction, the shapes and positions of the conductors 222B, 232B, 242B, and 252B are the same as those of the conductor 212B. That is, the conductors 222B, 232B, 242B, and 252B overlap with the conductor 212B in the Z-axis direction.

[0098] 25 to 30, a method for manufacturing a multilayer wiring board 2B will be described. First, as shown in FIG. 25, a laminate is prepared, including a dummy core 602 and a pair of prepregs 412 laminated on corresponding main surfaces of the dummy core 602. Each of the pair of prepregs 412 will be used as an insulating layer 132 in a later process. A copper foil 442 is formed on the surface of each prepreg 412 facing the dummy core 602, and a copper foil 432 is formed on the surface of each prepreg 412 opposite the dummy core 602. The copper foil 442 is smaller than the copper foil 432 and the prepreg 412. The dummy core 602 has an insulating layer 612 and a pair of copper foils 622 laminated on both sides of the insulating layer 612. The dummy core 602 may be a copper-clad laminate. An end of the prepreg 412 in a direction perpendicular to the thickness direction is bonded to the copper foil 622 of the dummy core 602.

[0099] Next, a CO2 laser is used to form multiple non-through holes 332A in the prepreg 412. At this time, the multiple non-through holes 332A are formed at intervals from one another in the X-axis direction. Next, multiple conductors 232A are filled into the multiple non-through holes 332A. Specifically, first, smears inside the non-through holes 332A are removed by a desmearing process, and then base plating is applied. Next, the conductors 232A are formed by a filling plating process (copper plating process). At this time, a metal layer 562 is also formed on the copper foil 432 by the copper plating process. Next, the metal layer 562 is thinned by half etching so that the metal layer 562 has a thickness approximately the same as that of the copper foil 432 (for example, 2 μm to 5 μm).

[0100] Next, as shown in FIG. 26, a CO2 laser is used to form multiple non-through holes 332B in the prepreg 412. At this time, the multiple non-through holes 332B are formed at intervals from each other in the X-axis direction. The multiple non-through holes 332B are formed so that the multiple non-through holes 332B do not overlap the multiple non-through holes 332A when viewed from the Z direction. Next, the multiple non-through holes 332B are filled with multiple conductors 232B. Specifically, first, smears inside the non-through holes 332B are removed by a desmearing process, and then base plating is applied. Next, the conductors 232B are formed by a filling plating process (copper plating process). At this time, a metal layer 552 is also formed on the metal layer 562 by the copper plating process.

[0101] Next, the end of the laminate of the dummy core 602 and the pair of prepregs 412 is cut and removed to separate the prepregs 412 from the dummy core 602. Specifically, the portions of the prepregs 412 that are bonded to the dummy core 602 are removed. Next, as shown in FIG. 27, a circuit is formed on the insulating layer 132 by removing portions of the copper foil 432 and the metal layers 552 and 562. This results in a member corresponding to the insulating layer 132 with the conductors 232A and 232B disposed therein.

[0102] 28, insulating layer 122 and insulating layer 142 are laminated in the Z-axis direction on insulating layer 132. These layers are arranged so that insulating layer 122, insulating layer 132, and insulating layer 142 are laminated in this order in the Z-axis direction. Copper foil 422 is formed on the surface of insulating layer 122 opposite to insulating layer 132, and copper foil 452 is formed on the surface of insulating layer 142 opposite to insulating layer 132.

[0103] 29, a CO2 laser is used to form multiple non-through holes 322A in the insulating layer 122, and multiple non-through holes 342A in the insulating layer 142. The multiple non-through holes 322A are formed at intervals in the X-axis direction. The multiple non-through holes 342A are formed at intervals in the X-axis direction. The multiple non-through holes 322A, 342A are formed so that the multiple non-through holes 322A, 342A overlap with the multiple non-through holes 332A when viewed from the Z direction.

[0104] Next, as shown in FIG. 29, the non-through holes 322A are filled with the conductors 222A, respectively. Specifically, first, smears inside the non-through holes 322A are removed by a desmearing process, and then base plating is applied. Next, the conductors 222A are formed by a filling plating process (copper plating process). At this time, a metal layer 542 is also formed on the copper foil 422 by the copper plating process. Also, the non-through holes 342A are filled with the conductors 242A, respectively. Specifically, first, smears inside the non-through holes 342A are removed by a desmearing process, and then base plating is applied. Next, the conductors 242A are formed by a filling plating process (copper plating process). At this time, a metal layer 572 is also formed on the copper foil 452 by the copper plating process. Next, the metal layer 542 is thinned by half etching so that the metal layer 542 has a thickness approximately the same as that of the copper foil 422 (for example, 2 μm to 5 μm). The metal layer 572 is thinned by half etching so that the metal layer 572 has a thickness similar to that of the copper foil 452 (for example, 2 μm or more and 5 μm or less).

[0105] 30, a CO2 laser is used to form a plurality of non-through holes 322B in the insulating layer 122, and a plurality of non-through holes 342B in the insulating layer 142. The plurality of non-through holes 322B are formed so that, when viewed from the Z direction, the plurality of non-through holes 322B do not overlap with the plurality of non-through holes 322A. Furthermore, the plurality of non-through holes 342B are formed so that, when viewed from the Z direction, the plurality of non-through holes 342B do not overlap with the plurality of non-through holes 342A.

[0106] Next, as shown in FIG. 30 , the non-through holes 322B are filled with the conductors 222B, respectively. Specifically, first, smears inside the non-through holes 322B are removed by a desmearing process, and then base plating is applied. Next, the conductors 222B are formed by a filling plating process (copper plating process). At this time, a metal layer 532 is also formed on the metal layer 542 by the copper plating process. Furthermore, the non-through holes 342B are filled with the conductors 242B, respectively. Specifically, first, smears inside the non-through holes 342B are removed by a desmearing process, and then base plating is applied. Next, the conductors 242B are formed by a filling plating process (copper plating process). At this time, a metal layer 582 is also formed on the metal layer 572 by the copper plating process.

[0107] Next, a circuit is formed on insulating layer 122 by removing portions of copper foil 422 and metal layers 532 and 542, and a circuit is formed on insulating layer 142 by removing portions of copper foil 452 and metal layers 572 and 582. Thereafter, similar processes such as laminating insulating layers, forming blind holes, and filling conductors are repeated to obtain multilayer wiring board 2B shown in FIG.

[0108] The structure of a multilayer wiring board 2C manufactured by a manufacturing method according to Comparative Example 3 will be described with reference to FIGS. 31 and 32. FIG. 31 is a cross-sectional view of a multilayer wiring board 2C manufactured by a manufacturing method according to Comparative Example 3. FIG. 32 is a cross-sectional view of the multilayer wiring board 2C taken along line A4-A4 in FIG. 31. The multilayer wiring board 2C includes a laminate 103 having insulating layers 113, 123, 133, 143, and 153 (hereinafter sometimes referred to as "insulating layers 113-153"), and a plurality of conductors 213, 223, 233, 243, and 253 (hereinafter sometimes referred to as "conductors 213-253"). In the laminate 103, insulating layers 113, 123, 133, 143, and 153 are stacked in this order in the Z-axis direction.

[0109] The insulating layers 113 to 153 are made of prepreg. The plurality of conductors 213 to 253 are made of copper. A collection of the plurality of conductors 213 to 253 functions as a thermal via block in the multilayer wiring board 2C. The insulating layer 113 has a plurality of non-through holes 313 formed therein that penetrate the insulating layer 113 in the Z-axis direction. The plurality of conductors 213 are filled in the plurality of non-through holes 313. Similarly, the insulating layers 123, 133, 143, and 153 have a plurality of non-through holes 323, 333, 343, and 353 formed therein that penetrate the corresponding insulating layers in the Z-axis direction. The plurality of conductors 223, 233, 243, and 253 are filled in the corresponding plurality of non-through holes 323, 333, 343, and 353, respectively. That is, in multilayer wiring board 2C, each conductor is located within a corresponding insulating layer (for example, conductor 213 is located within insulating layer 113), and no conductors are located across multiple different insulating layers.

[0110] 32 shows cross sections of the insulating layer 113 along the X-axis and Y-axis directions. When viewed from the Z-axis direction, each of the multiple non-through holes 313 (conductors 213) has a circular shape. The diameter of each of the multiple non-through holes 313 (conductors 213) is 50 μm. The multiple non-through holes 313 (conductors 213) are formed at intervals from one another in the X-axis and Y-axis directions. The intervals between adjacent non-through holes 313 (conductors 213) in each of the X-axis and Y-axis directions are 80 μm.

[0111] When viewed from the Z-axis direction, the shapes and positions of the non-through holes 323, 333, 343, and 353 are the same as the shape and position of the non-through hole 313. That is, the non-through holes 323, 333, 343, and 353 overlap with the non-through hole 313 in the Z-axis direction. When viewed from the Z-axis direction, the shapes and positions of the conductors 223, 233, 243, and 253 are the same as the shape and position of the conductor 213. That is, the conductors 223, 233, 243, and 253 overlap with the conductor 213 in the Z-axis direction.

[0112] 33 to 35, a method for manufacturing a multilayer wiring board 2C will be described. First, as shown in Fig. 33, an insulating layer 133 is formed in which a plurality of conductors 233 are arranged. The process for forming the insulating layer 133 is the same as the process for forming the insulating layer 13 described with reference to Figs. 3 to 6, except that the plurality of non-through holes 333 (conductors 233) are formed at intervals from one another in the X-axis direction and the Y-axis direction, and that the shape of the non-through holes 333 (conductors 233) when viewed from the Z-axis direction is circular.

[0113] 33, insulating layer 123 and insulating layer 143 are laminated in the Z-axis direction on insulating layer 133. These layers are arranged so that insulating layer 123, insulating layer 133, and insulating layer 143 are laminated in this order in the Z-axis direction. Copper foil 423 is formed on the surface of insulating layer 123 opposite to insulating layer 133, and copper foil 453 is formed on the surface of insulating layer 143 opposite to insulating layer 133.

[0114] 34, a CO2 laser is used to form a plurality of non-through holes 323 in the insulating layer 123, and a plurality of non-through holes 343 in the insulating layer 143. Specifically, the plurality of non-through holes 323 are formed at intervals in the X-axis direction and the Y-axis direction, and the plurality of non-through holes 343 are formed at intervals in the X-axis direction and the Y-axis direction. The plurality of non-through holes 323, 343 are formed so that the plurality of non-through holes 323, 343 overlap with the plurality of non-through holes 333 when viewed from the Z direction.

[0115] Next, as shown in FIG. 34 , the non-through holes 323 are filled with the conductors 223, respectively. Specifically, first, smear inside the non-through holes 323 is removed by a desmear process, and then base plating is applied. Next, the conductors 223 are formed by a filling plating process (copper plating process). At this time, a metal layer 523 is also formed on the copper foil 423 by the copper plating process. Furthermore, the non-through holes 343 are filled with the conductors 243, respectively. Specifically, first, smear inside the non-through holes 343 is removed by a desmear process, and then base plating is applied. Next, the conductors 243 are formed by a filling plating process (copper plating process). At this time, a metal layer 543 is also formed on the copper foil 453 by the copper plating process.

[0116] 35, a circuit is formed on insulating layer 123 by removing a portion of copper foil 423 and metal layer 523, and a circuit is formed on insulating layer 143 by removing a portion of copper foil 453 and metal layer 543. Thereafter, similar steps such as laminating insulating layers, forming blind holes, and filling conductors are repeated to obtain multilayer wiring board 2C shown in FIG.

[0117] Returning to FIG. 17, the performance and manufacturing cost of the multilayer wiring boards manufactured by the manufacturing methods of Examples 1 and 2 and Comparative Examples 1 to 3, as well as the results of simulations regarding the number of steps, will be described. Item 1 indicates the thermal resistance of the thermal via block. The thermal conductivity of the conductor (copper) constituting the thermal via block was set to 398 W / mK, and the thermal conductivity of the insulating layer was set to 0.62 W / mK. In addition, the width along the X-axis direction and the length along the Y-axis direction of the heat generating portion located on the first layer (L1 layer) side and the heat dissipation portion located on the sixth layer (L6 layer) side were set to the same as the width along the X-axis direction (500 μm) and length along the Y-axis direction (500 μm) of the thermal via block. It was assumed that the thermal resistance between the thermal via block and the heat generating portion and the thermal resistance between the thermal via block and the heat dissipation portion did not affect the calculated thermal resistance of the thermal via block.

[0118] The manufacturing cost of the thermal via block according to item 2 was calculated by adding up the number of processes (items 3 to 11 in FIG. 17) required to form the thermal via block. The manufacturing cost is shown as an index, with the cost (number of processes) of Comparative Example 1 set to 1.00. When the circuit includes two metal layers (metal layers 51 and 56) formed by a fill plating process, as in the first layer (L1 layer) circuit in Example 2, a half-etching process was performed to reduce the circuit thickness and facilitate high-density circuit formation. Furthermore, non-through holes were formed by direct laser processing without opening the holes (using a conformal mask). However, in the following cases, the metal layer (copper layer) was thick, making direct laser processing difficult, so openings were formed in the holes as a pre-processing step. Specifically, when forming skip-spec holes, a portion of the intermediate layer, which would otherwise be an obstacle, was removed in advance as a pre-processing step. For example, in Example 1, portions of the copper foil 42 and metal layer 52 corresponding to the positions where the non-through holes 31 would be formed were removed in advance. Furthermore, when the process from drilling to filling plating was repeated in the same layer, the interfering layer was removed before the second drilling as a pre-processing step. For example, in the copper foil 41 and the metal layer 51 in Example 2, the portion corresponding to the position where the non-through hole 36 was to be formed was removed beforehand. However, when the interfering layer (the drilled portion) could be removed simultaneously with the circuit formation, the number of circuit formations was not additionally counted.

[0119] The multilayer wiring board manufactured by the manufacturing method of Example 1 can improve heat dissipation by 18% compared to the multilayer wiring board manufactured by Comparative Example 1 with the same manufacturing cost (index 1.00). In other words, the thermal resistance can be improved from 3.02 K / W to 2.47 K / W. Furthermore, the manufacturing method of Example 2 can manufacture a multilayer wiring board with the same heat dissipation (1.51 K / W) as the multilayer wiring board manufactured by the manufacturing method of Comparative Example 2 at a manufacturing cost 29% lower. In other words, the manufacturing cost index can be reduced from 1.75 to 1.25. The manufacturing method of Comparative Example 2 forms thermal via blocks with good heat dissipation (thermal resistance of 1.51), but requires repeated drilling (forming blind holes) and filling plating (filling with conductors) twice for each layer, resulting in a manufacturing cost 75% higher than that of Example 1 and Comparative Example 1. Therefore, it can be seen that the manufacturing methods of Examples 1 and 2 are methods for manufacturing multilayer wiring boards that can improve both heat dissipation and manufacturing efficiency.

[0120] The present invention is not limited to the above-described embodiments and modifications. The materials and shapes of each component are not limited to those described above, and various materials and shapes can be used. For example, the method for manufacturing the multilayer wiring board 1, 1A may further include a step of forming a solder resist on the surface of the multilayer wiring board 1, 1A.

[0121] The length along the Y-axis direction of each of the conductors 21-27 and the non-through holes 31-37 may be equal to or shorter than the length along the X-axis direction. When viewed from the Z-axis direction, each of the non-through holes 31-37 formed in the insulating layer does not have to be defined by the surface of the insulating layer and the surfaces of the conductors filled in the other non-through holes, and may be defined only by the surface of the insulating layer. For example, the non-through hole 35 may be defined only by the surfaces of the insulating layers 14 and 15. In this case, the conductor 25 filled in the non-through hole 35 does not have to be in contact with the conductor 24.

[0122] In each of the plurality of non-through holes 31, 34, 35, the ratio of the depth to the length along the X-axis direction may be 1.2 or less, or 2.0 or more. In each of the plurality of non-through holes 31, 34, 35, the ratio of the depth to the length along the Y-axis direction may be 0.6 or more and 1.2 or less. The multilayer wiring boards 1, 1A may be build-up wiring boards having five or less layers or seven or more layers.

[0123] The shape of each of the conductors 21 to 27 is not limited. For example, when viewed from the Z direction, each of the conductors 21 to 27 may have an elliptical shape with a major axis along the Y-axis direction, or a rectangular shape with unrounded corners. The number of each of the conductors 21 to 27 is not limited, and may be three or more. That is, for example, while the number of the plurality of conductors 24 is two in each of the above embodiments, the number of the plurality of conductors 24 may be three or more.

[0124] The shape of the non-through holes 31 to 37 is not limited. For example, when viewed from the Z direction, each of the non-through holes 31 to 37 may have an elliptical shape with a major axis along the Y-axis direction, or a rectangular shape with unrounded corners. The number of each of the non-through holes 31 to 37 is not limited, and may be three or more. That is, for example, while the number of the non-through holes 34 is two in each of the above embodiments, the number of the non-through holes 34 may be three or more. [Explanation of symbols]

[0125] 1, 1A, 2A, 2B, 2C...Multilayer wiring board 10, 101, 102, 103...Laminate 11, 12, 111, 112, 113, 121, 122, 123, 131, 132, 133, 141, 142, 143, 151, 152, 153...insulating layer 13...Insulating layer (first insulating layer) 14...insulating layer (second insulating layer) 15...Insulating layer (third insulating layer) 21~23, 26, 211, 212A, 212B, 213, 221, 222A, 222B, 223, 231, 232A, 232B, 233, 241, 242A, 242B, 243, 251, 252A, 252B, 253...conductors 24...Conductor (first conductor) 25...Conductor (second conductor) 27...Conductor (third conductor) 31~33, 36, 311, 312A, 312B, 313, 321, 322A, 322B, 323, 331, 332A, 332B, 333, 341, 342A, 342B, 343...Non-through hole 34...Non-through hole (first non-through hole) 35...Non-through hole (second non-through hole) 37...Non-through hole (third non-through hole) 41~46, 62, 421, 422, 423, 432, 442, 451, 452, 453, 622...Copper foil 51~57, 521, 523, 532, 541, 542, 543, 552, 562, 572, 582...metal layer 60, 602...Dummy core 61, 612...insulating layer (dummy core) 410, 412...Prepreg

Claims

1. stacking a second insulating layer on the first insulating layer in a first direction; forming a plurality of first blind holes penetrating the first insulating layer and the second insulating layer in the first direction; filling the plurality of first non-through holes with a plurality of first conductors, respectively; stacking a third insulating layer on the second insulating layer in the first direction; forming a plurality of second blind holes penetrating the second insulating layer and the third insulating layer in the first direction; and filling the second non-through holes with a plurality of second conductors, In the step of forming the plurality of first non-through holes, the plurality of first non-through holes are formed at intervals from one another in a second direction perpendicular to the first direction, In the step of forming the plurality of second non-through holes, the plurality of second non-through holes are formed between the plurality of first non-through holes so that the plurality of second non-through holes do not overlap with the plurality of first non-through holes when viewed from the first direction. A method for manufacturing a multilayer wiring board.

2. In the step of forming the plurality of first non-through holes, the plurality of first non-through holes are formed such that a length of each of the plurality of first non-through holes along a third direction perpendicular to the first direction and the second direction is longer than a length of each of the plurality of first non-through holes along the second direction; In the step of forming the plurality of second non-through holes, the plurality of second non-through holes are formed such that a length of each of the plurality of second non-through holes along the third direction is longer than a length of each of the plurality of second non-through holes along the second direction. The method for manufacturing a multilayer wiring board according to claim 1 .

3. In the step of forming the plurality of first non-through holes, the plurality of first non-through holes are formed such that, for each of the plurality of first non-through holes, a ratio of a depth along the first direction to a length along the second direction is 1.2 or more and 2.0 or less, and a ratio of a depth along the first direction to a length along the third direction is 0.6 or more and 1.2 or less. The method for manufacturing a multilayer wiring board according to claim 2 .

4. In the step of forming the plurality of second non-through holes, the plurality of second non-through holes are formed such that, for each of the plurality of second non-through holes, a ratio of a depth along the first direction to a length along the second direction is 1.2 or more and 2.0 or less, and a ratio of a depth along the first direction to a length along the third direction is 0.6 or more and 1.2 or less. The method for manufacturing a multilayer wiring board according to claim 2 .

5. each of the plurality of first conductors and the plurality of second conductors is copper; The method for manufacturing a multilayer wiring board according to claim 1 or 2.

6. forming a plurality of third blind holes penetrating the third insulating layer in the first direction; and filling the third non-through holes with a plurality of third conductors, respectively; In the step of forming the plurality of third non-through holes, the plurality of third non-through holes are formed between the plurality of second non-through holes so that the plurality of third non-through holes overlap with the plurality of first non-through holes but do not overlap with the plurality of second non-through holes when viewed from the first direction. The method for manufacturing a multilayer wiring board according to claim 1 or 2.

7. a laminate having a first insulating layer, a second insulating layer, and a third insulating layer in this order in a first direction; a plurality of first conductors and a plurality of second conductors disposed within the laminate; the laminated body is formed with a plurality of first non-through holes penetrating the first insulating layer and the second insulating layer in the first direction, and a plurality of second non-through holes penetrating the second insulating layer and the third insulating layer in the first direction, the plurality of first non-through holes are formed at intervals from one another in a second direction perpendicular to the first direction, each of the plurality of second non-through holes is formed between the plurality of first non-through holes so as not to overlap with the plurality of first non-through holes when viewed from the first direction; the plurality of first conductors are respectively filled in the plurality of first non-through holes, The plurality of second conductors are respectively filled in the plurality of second non-through holes. Multilayer wiring board.

8. a length of each of the plurality of first non-through holes along a third direction perpendicular to the first direction and the second direction is longer than a length of each of the first non-through holes along the second direction; In each of the plurality of second non-through holes, a length along the third direction is longer than a length along the second direction. The multilayer wiring board according to claim 7 .

Images