BGA fan-out structure of PCB and manufacturing method thereof

Abstract

The invention discloses a BGA fan-out structure of a PCB and a manufacturing method of the BGA fan-out structure, at least one surface of the PCB is provided with a plurality of BGA bonding pads which are distributed in a square array mode, no wiring is conducted between the BGA bonding pads, the circle of BGA bonding pads arranged on the outermost periphery are peripheral bonding pads, the other BGA bonding pads are inner bonding pads, the center of each inner bonding pad is provided with an in-disc hole with an internal partition, and the in-disc hole is formed in the center of each inner bonding pad. The hole diameter of the in-plate hole is smaller than the outer diameter of the BGA bonding pad, and each inner circuit layer of the PCB is provided with a row of hole rings which are arranged around the in-plate hole in a one-to-one correspondence manner and are communicated with the in-plate hole, and a plurality of fan-out wires which are communicated with the hole rings in a one-to-one correspondence manner. The fan-out wires transversely penetrate through the middle of a gap between every two adjacent in-plate holes which are longitudinally arranged or transversely penetrate through the outer sides of the in-plate holes, and the hole rings in the different inner circuit layers are in one-to-one correspondence with the inner bonding pads in the different columns respectively. According to the invention, the design of fan-out of the BGA bonding pad from the inner layer is realized through the via in the pad and the inner layer wiring, and the problem of difficult fan-out wiring of the high-density bonding pad is solved.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board manufacturing technology, specifically to a BGA fan-out structure for a PCB and its manufacturing method. Background Technology

[0002] Driven by emerging technologies such as 5G communication, artificial intelligence, and the Internet of Things, chip integration is constantly increasing, and the number of pins is increasing significantly. Traditional packaging methods can no longer meet the demands of high-density interconnection. BGA (Ball Grid Array) packaging, by distributing pins in a ball-shaped array on the bottom of the package, effectively improves pin density and packaging efficiency, becoming the mainstream packaging solution for high-end chips. The BGA fan-out design, as a bridge connecting the chip's BGA pads and external circuitry on the PCB, directly impacts signal transmission rate, system stability, and PCB manufacturing costs. Currently, as BGA pin pitch evolves from 1.0mm to 0.8mm, 0.5mm, and even smaller sizes, the problems of wiring congestion and signal interference faced by fan-out designs are becoming increasingly prominent.

[0003] BGA fan-out, as a crucial pre-design step in PCB design, offers significant technical value in three main aspects: First, it ensures routing feasibility. By increasing pad spacing through fan-out, it resolves compatibility issues between high-density BGA pins and conventional PCB routing processes, preventing manufacturing yield drops caused by short circuits or insufficient spacing. Second, it optimizes signal integrity. A well-designed fan-out path reduces conductor length and via count, mitigating signal delay, crosstalk, and reflections. This is particularly important for high-frequency signals (such as 5G RF signals and high-speed serial bus signals), where the quality of fan-out design directly determines signal transmission rate and bit error rate. Third, it enhances reliability. Optimizing pad layout and via design reduces the risk of pad detachment or circuit breakage due to mechanical stress, thermal expansion mismatch, and other factors, extending product lifespan. Especially in high-reliability applications such as automotive electronics and aerospace, the stability of BGA fan-out directly impacts overall system reliability. Furthermore, fan-out design provides a foundation for subsequent power integrity and electromagnetic compatibility (EMC) optimization—by rationally planning power / ground plane partitioning and signal layer distribution, power noise and electromagnetic interference can be further suppressed, improving the system's anti-interference capability. Therefore, BGA fan-out is not only a core challenge in high-density PCB design, but also a key technical support for achieving high-speed signal transmission, stable system operation, and long-term product reliability.

[0004] With the continuous increase in pin density of BGA packages (e.g., the number of pins increases from hundreds to thousands, and the pin pitch decreases from 1.0mm to 0.4mm), the technical bottlenecks faced by fan-out designs are becoming increasingly prominent, mainly focusing on four aspects: wiring space, signal integrity, process compatibility, and cost control, as detailed below: Extremely limited routing space: Limited routing space is the most direct challenge for high-density BGA fan-out. When the BGA pin pitch is ≤0.6mm, the center distance between adjacent pads is only 0.6mm. After deducting the diameter of the pad itself (usually 0.3-0.4mm), the available routing space between pads is less than 0.2mm, which is far from meeting the requirements of conventional PCB routing for "line width + line spacing". If the traditional routing scheme of "BGA pad + inter-pad routing" is adopted, the BGA fan-out conductors compete with the outer pads for routing channels, which seriously restricts the feasibility of high-density BGA fan-out.

[0005] High risk of signal integrity degradation: During high-density BGA fan-out, signal integrity issues manifest in three aspects: First, the impact of blind vias and via rings. To achieve fan-out, designs often require stacking numerous blind vias to guide signals from the top layer (BGA layer) to inner or bottom layers before fanning out. However, blind vias introduce parasitic capacitance, parasitic inductance, and impedance abrupt changes, leading to signal reflection and delay. Especially for high-speed signals with speeds ≥10Gbps, the insertion loss introduced by vias can account for more than 30% of the total loss. Second, mismatch between conductor width, dielectric thickness, and impedance accuracy. In high-density BGA fan-out, to meet routing requirements, conductor widths typically need to be compressed to extremely fine dimensions (e.g., 0.05mm). The ratio of PCB dielectric layer thickness (e.g., 4-6mil) to conductor width is too large, making it difficult to accurately control characteristic impedance (e.g., 50Ω single-ended line or 100Ω differential line). Impedance deviation exceeding ±10% will cause signal reflection and crosstalk. Thirdly, the coupling effect of adjacent signals is aggravated. As the BGA pin spacing decreases, the spacing between adjacent signal lines is close to 1 / 100 of the signal wavelength (e.g., the wavelength of a 10Gbps signal is about 30mm). The capacitive and inductive coupling strength between conductors is significantly increased, causing near-end crosstalk (NEXT) and far-end crosstalk (FEXT) to exceed the limits of IPC-2221 standard [3] (e.g., high-speed signal crosstalk ≤ -40dB), further deteriorating signal quality.

[0006] The conflict between process compatibility and manufacturing cost: To solve the fan-out problem of high-density BGAs, traditional solutions often rely on "layer addition" or "fine-line" processes. Both of these solutions have significant drawbacks: Layer addition requires lamination, drilling, and electroplating for each layer, continuously increasing manufacturing costs; fine-line methods require extremely high precision PCB manufacturing equipment, necessitating the use of M-SAP (modified semi-additive) or SAP (semi-additive) processes. The purchase and maintenance costs of such equipment are far higher than conventional equipment, leading to a surge in single-board manufacturing costs. More importantly, both layer addition and fine-line processes suffer from diminishing marginal returns—when the BGA pin pitch shrinks to below 0.5mm, even increasing the number of layers or further compressing the line width, the wiring space still struggles to meet the requirements. Meanwhile, high-density BGA fan-out places higher demands on process compatibility: for example, in the 3+4+3 HDI board process, blind vias and through-holes are used interchangeably, and the second outermost layer also needs electroplating. Controlling the uniformity of electroplating is difficult, easily leading to insufficient or excessive copper thickness in certain areas, causing signal integrity issues or short-circuit risks. Add-layer methods require expensive film materials (such as ABF) and blind via filling electroplating, and require multiple cycles of lamination, drilling, electroplating, and patterning processes, further increasing manufacturing costs. Therefore, traditional solutions face a dilemma between process compatibility and cost control. More importantly, neither add-layer nor fine-line solutions fundamentally solve the core contradiction of high-density BGA fan-out—the dual constraints of routing space and signal integrity. Simply adapting to requirements through "space expansion" or "line compression" fails to meet the combined demands of "high density, high speed, and high reliability" in scenarios such as 5G communication and high-speed serial buses, leading to a continuous accumulation of scrap rates. Fine-line processes, on the other hand, place higher demands on PCB substrates and etching precision, resulting in decreased manufacturing yields (e.g., when the line width is ≤0.08mm, the yield can drop from 95% to below 80%), thus increasing overall production costs. Furthermore, some traditional processes (such as blind and buried via processes) have "interlayer interconnection limitations," preventing direct connections between arbitrary layers and forcing fan-out paths to detour, further exacerbating routing difficulties. Summary of the Invention

[0007] To address the aforementioned shortcomings of existing technologies, this invention provides a BGA fan-out structure for PCBs and its manufacturing method. By using in-holes and inner layer wiring, and internal partitioning of through-holes, the design of BGA pads fanning out from the inner layer is achieved, solving the problem of difficult high-density pad fan-out wiring.

[0008] Firstly, to solve the above-mentioned technical problems, the present invention provides a BGA fan-out structure for a PCB. At least one surface of the PCB is provided with a plurality of BGA pads arranged in a square array. The outermost ring of BGA pads is the outermost pad, and the other BGA pads are the innermost pads. A hole-in-the-pad is fabricated at the center of each innermost pad using a hole-in-the-pad process, meaning that a copper-free isolation section exists within the hole. The diameter of the hole is smaller than the outer diameter of the BGA pad. In each inner layer of the PCB, a row of vias corresponding to and communicating with the vias is provided, along with a plurality of fan-out conductors corresponding to and communicating with the vias. The fan-out conductors pass laterally through the gap between two adjacent longitudinally arranged vias or laterally from the outside of the vias. The vias in different inner layers correspond one-to-one with different rows of innermost pads.

[0009] Furthermore, the outer diameter of the BGA pad is 250μm, the spacing between two adjacent BGA pads is 50μm, and no traces are routed between the BGA pads; the diameter of the via in the pad is 150μm, the center-to-center distance between two adjacent vias in the pad is 300μm, and the wall spacing between two adjacent vias in the pad is 150μm; the outer diameter of the via ring is 250μm, the inner diameter is 150μm, and the linewidth of the fan-out conductor is 50μm.

[0010] Furthermore, two adjacent fan-out conductors in the same layer pass laterally through the two gaps formed between the three longitudinally arranged adjacent disk holes, and one of the outermost fan-out conductors passes laterally from the outside of the outermost disk hole.

[0011] Furthermore, the number of inner layer circuits on the PCB is an integer multiple of the number of inner pad columns, and the inner pads are connected one-to-one with the hole rings in each inner layer of the PCB in the order of their column arrangement.

[0012] Furthermore, by employing a process of interconnecting arbitrary layers through vias, two separate conductive sections are formed in the vias of each disk.

[0013] Secondly, the present invention also provides a method for manufacturing a BGA fan-out structure, comprising the following steps: S1. A production board is provided, wherein the production board has a plurality of drill holes arranged in a square array, and each inner layer of the production board has a row of hole rings arranged around the drill holes and a plurality of fan-out wires that correspond one-to-one with the hole rings. The production board has two rows of hole rings located in different inner layers at each row of drill holes, and an isolation plate with an outer diameter larger than the drill hole is provided on the outside of the hole rings in each inner layer. Two isolation plates are provided at each drill hole. S2. Drill through holes at each drilling position on the production board, and the two inner isolation discs form an isolation ring. S3. Use an alkaline solution to dissolve and remove the two isolation rings on the hole wall, forming paired pits inside the hole; S4. The production board is subjected to chemical copper plating and DC flash plating in sequence, and then pulse electroplating and DC electroplating are used to form internally isolated through holes. S5. Then, the through holes are filled with resin and cured. The resin protruding from the board surface is ground flat by grinding. Then, copper plating and electroplating are used to form a copper plating layer on the resin surface that is connected to the copper layer of the hole wall. S6. Fabricate outer layer circuitry on the production board, and fabricate a plurality of BGA pads arranged in a square array on at least one surface of the production board. The outer diameter of the BGA pads is larger than the diameter of the via. Among them, the outermost ring of BGA pads is the outermost pad, and the other BGA pads are the innermost pads. The number of innermost pads is the same as the number of drilled holes and they correspond one-to-one, so that the vias form holes in the pads.

[0014] Furthermore, when BGA pads need to be fabricated on both surfaces of the production board, and the number of drill holes is n rows and n columns, the production board has 2n inner layers. The inner layer circuits from the first to the nth layer are set facing away from the upper surface of the production board and towards the upper surface of the production board, while the inner layer circuits from the (n+1)th to the 2nth layer are set away from the lower surface of the production board and towards the upper surface of the production board. This makes the inner layer circuits from the first to the nth layer and the inner layer circuits from the (n+1)th to the 2nth layer symmetrical in structure. A row of hole rings on the two symmetrical inner layer circuit layers corresponds vertically. Thus, an isolation disk is set on the outside of the hole rings of the two symmetrical inner layer circuit layers, and two isolation disks are set at each drill hole position, forming a vertically partitioned structure.

[0015] Furthermore, the hole rings from the first to the nth layer correspond one-to-one with the row number of the drilling positions in the order of the top-down layer number, and the hole rings from the (n+1)th to the 2nth layer correspond one-to-one with the row number of the drilling positions in the order of the bottom-up layer number, so that the fan-out wires from the second to the nth layer all pass through the isolation zone below the fan-out wire of the layer above them, and the fan-out wires from the (n+1)th to the 2n-1th layer pass through the isolation zone above the fan-out wire of the layer below them.

[0016] Furthermore, in step S3, the production plate is immersed in a sodium hydroxide solution at 60 degrees Celsius for 30-120 minutes; and the mass percentage of the solute in the sodium hydroxide solution is 10%.

[0017] Furthermore, in step S4, the current density during DC flash plating is 1.5 ASD, the time is 3-6 min, and the copper layer on the hole wall is thickened by 2-5 micrometers during DC flash plating.

[0018] Furthermore, in step S4, the total time for pulse electroplating is 6 minutes, and the current density of forward pulse electroplating in each cycle is 3 ASD and the time is 10 ms, while the current density of reverse pulse electroplating is 9 ASD and the time is 10 ms. After pulse electroplating, DC electroplating is used to thicken the copper layer on the hole wall.

[0019] Compared with the prior art, the present invention has the following beneficial effects: 1. In this invention, the problem of fan-out conductors being unable to run between pads due to high-density pads is addressed by creating vias in the pads. This prevents traces from running between BGA pads and guides the fan-out design of the inner pads within the BGA pads to the inner layer before exiting. Because the vias are relatively small compared to the pads, and only the inner layer corresponding to each column of inner pads is connected to a via ring (i.e., no via ring is designed at the position of the vias in other columns), the fan-out conductors of that column of inner pads can be led out between two adjacent vias in other columns or outside the vias. This effectively designs the fan-out conductors within the inner layer of the PCB, achieving outward fan-out of the inner pads. It also avoids the problem of existing layer-adding schemes requiring blind via rings in each layer, which can block the fan-out channel. Furthermore, the fan-out conductors of different columns of pads are designed in different inner layers, avoiding mutual interference and ensuring that the fan-out guidance of each layer can fan out in the same direction.

[0020] 2. This invention employs existing through-hole arbitrary layer interconnection technology, which isolates the internal structure of the through-hole within the pad. This ensures that the copper layer on the hole wall within the through-hole only connects to the hole ring connecting to the corresponding layer. No copper layer exists on the hole wall below the hole ring, enabling direct connection between the inner pad and the target inner layer. Unlike traditional layer-addition processes, this eliminates the need for blind via stacking and detours, significantly shortening the signal transmission path, reducing signal loss during transmission, and minimizing signal delay. Furthermore, the through-hole locations traversed by the fan-out conductors in each inner layer are all non-metallic vias, effectively avoiding the "ring-shaped congestion" problem caused by blind via rings. This significantly improves the routing efficiency and overall performance of the circuit board, fundamentally reducing the impact of these adverse factors on signal integrity. This process optimization not only solves the channel blockage problem but also provides greater flexibility and reliability for circuit board design and manufacturing.

[0021] 3. Regarding improving dielectric thickness uniformity, this invention employs a method of creating the in-disk hole after overall lamination. Compared to the layer-by-layer lamination method in existing layer-addition processes, this results in a more uniform PCB dielectric layer thickness. In high-density BGA fan-out, an excessively large ratio of dielectric layer thickness to conductor width can lead to difficulty in accurately controlling characteristic impedance. Uniform dielectric thickness, on the other hand, helps to accurately control characteristic impedance, such as 50Ω single-ended lines or 100Ω differential lines, reducing signal reflection and crosstalk caused by impedance deviations.

[0022] 4. Regarding the issue of uneven copper plating thickness, traditional processes, especially when adding layers or using blind / buried vias, face significant challenges in controlling plating uniformity. This can easily lead to insufficient or excessive copper thickness in certain areas, causing signal integrity issues or short-circuit risks. This application effectively reduces uneven copper plating thickness and ensures signal transmission stability through a process of "isolation pad setting - etching - reverse pulse plating" in the through-hole arbitrary layer interconnection process.

[0023] 5. Regarding line widening, this process provides more flexibility in line design, allowing for appropriate line widening. In high-density BGA fan-out, to meet wiring requirements, the width of fan-out conductors in traditional processes usually needs to be compressed to an extremely thin level. Widening the lines can further reduce resistance during signal transmission, reduce signal loss, and also help to better control characteristic impedance, further improving signal integrity and meeting the needs of high-speed transmission. Especially for high-speed signals with rates ≥10Gbps, it can effectively reduce the proportion of insertion loss introduced by vias in the total loss, improving signal transmission rate and quality.

[0024] 6. Compared with traditional build-up, fine-line, and blind / buried via solutions, the process in this application has significant advantages in cost control: First, the processing technology is simple, using mechanical drilling, through-hole plating, and acid etching, which is much cheaper than the blind via filling plating, laser drilling, pattern plating, copper reduction, grinding, and differential etching used in build-up processes; Second, it simplifies the manufacturing process, as this process does not require multiple pressing and drilling like blind / buried vias, shortening the production process by 40% and reducing the production cycle from 15 days in the traditional solution to 8 days; Third, it improves yield, as the build-up process is accumulated through multiple cycles of layering, drilling, plating, and patterning, while the process in this application only involves this process once, eliminating the accumulation of defect rates.

[0025] 7. The through-hole interconnect process features a large-area surrounding structure between the inner layer and the copper in the hole, unlike the interconnect structure of multilayer boards and blind vias. This structure results in a tighter bond between the copper in the hole and the inner layer copper foil, enhancing the connection strength between the pads and the inner layer and effectively reducing the risk of pad detachment due to mechanical or thermal stress. Simultaneously, the non-metallized through-holes at non-connected locations avoid the local electric field concentration problems that may be caused by blind via rings, reducing the risk of insulation layer breakdown due to electric field stress and further improving the electrical reliability of the circuit board. Furthermore, this process optimizes the electroplating process, resulting in more uniform copper thickness in the holes, avoiding localized overheating or unstable signal transmission caused by uneven copper thickness, thereby improving the reliability of the circuit board under long-term high-temperature operating environments.

[0026] 8. The method described in this application has excellent process compatibility and can be seamlessly integrated with existing PCB manufacturing equipment, substrates, and design software without requiring large-scale equipment upgrades for enterprises. This process supports a wide range of BGA pin pitches (0.3mm-1.27mm). With the improvement of hole diameter and precision in mechanical drilling and UV laser drilling, the BGA pin pitch can be further reduced in the future, making it suitable for various BGA packages from general consumer electronics to high-end industrial equipment. Simultaneously, it supports a "hybrid fan-out" design, meaning that high-density BGAs and ordinary components can be fanned out simultaneously on the same PCB, meeting the design requirements of complex circuit systems.

[0027] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of the invention. Attached Figure Description

[0028] Figure 1 This is a side view of the BGA fan-out structure of each layer in Example 1; Figure 2 This is an overlaid perspective view of the inner BGA fan-out structure in Example 1 on the top plane; Figure 3 This is a schematic diagram of the fan-out structure corresponding to the first column of BGA pads in the second layer; Figure 4 This is a schematic diagram of the fan-out structure corresponding to the second column of BGA pads in the third layer; Figure 5 This is a schematic diagram of the fan-out structure corresponding to the last column of BGA pads in the inner layer; Figure 6 This is a schematic diagram of the fan-out structure when both sides have BGA pads in Examples 2 and 3. Detailed Implementation

[0029] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0031] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0032] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0033] Among them, the existing technical solutions for arbitrary layer interconnection vias are shown in the prior publication number "CN120264633A" and application number "2025115404468".

[0034] Example 1 like Figures 1 to 5 As shown in the figure, this embodiment of the BGA fan-out structure has a plurality of BGA pads arranged in a square array on one surface of the PCB, and no traces are routed between the BGA pads.

[0035] In this embodiment, a seven-layer PCB board with seven rows and seven columns of BGA pads on one surface of the PCB is used as an example. All pads have the same outer diameter. The outermost ring of BGA pads is the outermost pad, and the other BGA pads are the innermost pads. That is, the five rows and five columns of BGA pads in the inner ring are the innermost pads 1. A hole 2 is made at the center of each innermost pad 1 using a hole-in-pad process. The diameter of the hole 2 is smaller than the outer diameter of the innermost pad 1. A column corresponding to the hole is provided in the second to sixth layers of the inner PCB. 2. A hole ring 3 connected to the hole 2 in the disk is set, and a number of fan-out conductors 4 are connected to the hole ring 3 one by one. That is, there are 5 hole rings in each column in each layer, and the hole rings 3 in different inner circuit layers correspond one-to-one with the inner pads 1 in different columns. That is, each column of the inner pads corresponds to the hole ring and fan-out conductor of one layer, so as to realize the purpose of staggered fan-out of the inner pads in each column from different inner layers; and the fan-out conductors 4 pass laterally through the gap between two adjacent holes 2 in the disk arranged vertically or pass laterally from the outside of the hole 2 in the disk.

[0036] Specifically, the outer diameter of the BGA pad is 250μm, and the spacing between two adjacent BGA pads is 50μm; the diameter of the via 2 is 150μm, the center-to-center spacing between two adjacent vias 2 is 300μm, and the minimum wall spacing between two adjacent vias 2 is 150μm; the outer diameter of the via ring is 250μm, and the inner diameter is 150μm, so that the via ring can be adapted to the via.

[0037] Specifically, the linewidth of the fan-out conductor 4 is 50μm, that is, the vertical distance between the two sides of the fan-out conductor 4 and the hole in the disk is 50μm.

[0038] In one embodiment, two adjacent fan-out conductors 4 in the same layer pass laterally through two gaps formed between three adjacent pad holes 2 arranged vertically, and one of the outermost fan-out conductors 2 passes laterally from the outside of the outermost pad hole. For example, in a BGA pad with a seven-row, seven-column distribution, the top or bottom row of BGA pads does not have a pad hole, resulting in no pad holes outside the pad holes in the second and sixth rows. This means that the fan-out conductors connecting the inner pads of the second or sixth row can only pass laterally from the outside of the pad holes in the second or sixth row, rather than from two adjacent pad holes above or below.

[0039] In one embodiment, the inner pads are arranged in columns and connected one-to-one with the vias in each inner layer of the PCB in order of layer number. For example, the first column of inner pads is connected to the vias and fan-out conductors in the second inner layer, the second column of inner pads is connected to the vias and fan-out conductors in the third inner layer, the third column of inner pads is connected to the vias and fan-out conductors in the fourth inner layer, the fourth column of inner pads is connected to the vias and fan-out conductors in the fifth inner layer, and the sixth column of inner pads is connected to the vias and fan-out conductors in the sixth inner layer; of course, the reverse is also possible.

[0040] In one embodiment, to avoid the fan-out conductor from contacting two perforated rings in the same column, the end of the fan-out conductor 4 connected to the perforated ring is provided with a bent section 41. This bent section is connected to the side of a perforated ring and does not pass between two adjacent perforated rings in the same column, forming an avoidance structure design.

[0041] Understandably, in a specific implementation case, since the outer pads are located at the outermost edge, the design of their fan-out lines is not affected by the gap between the inner pads. The outer pads can be directly fanned out from the outer layer of the PCB, that is, fan-out conductors connected to the outer pads are designed on the outer surface of the PCB.

[0042] Understandably, the fan-out design of the outer pads can also be the same as that of the inner pads, guiding the pads to the inner layer through the holes in the pads before leading them out.

[0043] Understandably, BGA pads can also be square in shape.

[0044] Example 2 like Figure 6 As shown in the figure, the BGA fan-out structure shown in this embodiment is basically the same as that in embodiment 1. The difference is that: in this embodiment, both surfaces of the PCB are fabricated with a number of BGA pads arranged in a square array, and the BGA pads on the two surfaces correspond one-to-one.

[0045] In this embodiment, the PCB board has twelve layers. The inner layer design of the second to sixth layers is the same as in Embodiment 1. The inner layer design of the seventh to eleventh layers is symmetrical to that of the second to sixth layers, so that the hole rings and fan-out conductors of the second to sixth layers cooperate with the inner pads on the upper surface to realize the inner layer lead-out of the inner pads on the upper surface. The hole rings and fan-out conductors of the seventh to eleventh layers cooperate with the inner pads on the lower surface to realize the inner layer lead-out of the inner pads on the lower surface.

[0046] In one embodiment, by employing the existing process of interconnecting any layer of through-holes, a copper-free isolation band is formed between the upper and lower hole rings in the same disk, so that the fan-out conductors from the third to the tenth layers all pass through the copper-free isolation band. This can effectively avoid the "ring congestion band" problem caused by blind hole rings, thereby significantly improving the routing efficiency and overall performance of the circuit board, and fundamentally reducing the impact of these adverse factors on signal integrity.

[0047] It is understandable that the number of inner circuit layers on a PCB can be the same as the number of columns of inner pads.

[0048] Example 3 The method for fabricating a BGA fan-out structure shown in this embodiment specifically includes the following steps: S1. A production board is provided, wherein the production board has a plurality of drill holes arranged in a square array, and each inner layer of the production board has a row of hole rings arranged around the drill holes and a plurality of fan-out wires that correspond one-to-one with the hole rings. The production board has two rows of hole rings located in different inner layers at each row of drill holes, and an isolation plate with an outer diameter larger than the drill hole is provided on the outside of the hole rings in each inner layer. Two isolation plates are provided at each drill hole. S2. Drill through holes at each drilling position on the production board, and the two inner isolation discs form an isolation ring. S3. Use an alkaline solution to dissolve and remove the two isolation rings on the hole wall, forming paired pits inside the hole; S4. The production board is subjected to chemical copper plating and DC flash plating in sequence, and then pulse electroplating and DC electroplating are used to form internally isolated through holes. S5. Then, the through holes are filled with resin and cured. The resin protruding from the board surface is ground flat by grinding. Then, copper plating and electroplating are used to form a copper plating layer on the resin surface that is connected to the copper layer of the hole wall. S6. Fabricate outer layer circuitry on the production board, and fabricate a number of BGA pads arranged in a square array on at least one surface of the production board. The outer diameter of the BGA pads is larger than the diameter of the vias. Among them, the outermost ring of BGA pads is the outermost pad, and the other BGA pads are the innermost pads. The number of innermost pads is the same as the number of drill holes and they correspond one-to-one, so that the vias form holes in the pads.

[0049] Specifically, such as Figure 6 As shown, when BGA pads need to be fabricated on both surfaces of the production board, and the number of drill holes is n rows and n columns, the production board has 2n inner layers. The inner layer circuits from the first to the nth layer are set facing away from the upper surface of the production board and towards the upper surface of the production board. The inner layer circuits from the (n+1)th to the 2nth layer are set away from the lower surface of the production board and towards the upper surface of the production board, so that the inner layer circuits from the first to the nth layer and the inner layer circuits from the (n+1)th to the 2nth layer are symmetrical in structure. A row of hole rings on the two symmetrical inner layer circuit layers corresponds vertically. An isolation disk is set on the outside of the hole rings of the two symmetrical inner layer circuit layers. In this way, two isolation disks are set at each drill hole, forming a vertically partitioned structure.

[0050] Specifically, the number of inner pads also has n rows and n columns, and they correspond one-to-one with the center of the drill hole position.

[0051] The process and technology of fabricating isolation pads on the core board before lamination are as shown in the prior publication number "CN120264633A" and application number "2025115404468". The inner layer of the production board adopts a single-sided copper-clad core board, that is, 2n single-sided copper-clad core boards are required for 2n inner layer circuits. After laminating the 2n single-sided copper-clad core boards with the two outer copper foils, the production board is formed. When arranging the boards, the circuit layers on the first core board to the second core board are set away from the BGA on the upper surface (i.e., facing downwards), while the circuit layers on the (n+1)th core board to the 2nth core board are set away from the BGA on the lower surface (i.e., facing upwards). This allows an alkali-soluble photocurable ink with an outer diameter larger than the outer diameter of the drilled hole to be coated on the outer side of the hole rings of the two symmetrical inner layer circuit layers. Then, the alkali-soluble photocurable ink is exposed and cured by UV light to form an isolation pad, thereby separating the upper and lower sections of a single through hole.

[0052] Specifically, in step S3, the production plate is immersed in a sodium hydroxide solution at 60 degrees Celsius for 30-120 minutes; and the mass percentage of the solute in the sodium hydroxide solution is 10%.

[0053] Specifically, in step S4, the current density during DC flash plating is 1.5 ASD, the time is 3-6 min, and the copper layer on the hole wall is thickened by 2-5 micrometers during DC flash plating.

[0054] Specifically, in step S4, the total pulse electroplating time is 6 minutes, and the current density of each cycle of forward pulse electroplating is 3 ASD, with a time of 10 ms; the current density of the reverse pulse electroplating is 9 ASD, with a time of... The outer diameter of the BGA pad is 250μm, and the spacing between two adjacent BGA pads is 50μm; the diameter of the via 2 is 150μm, the center-to-center spacing between two adjacent vias 2 is 300μm, and the minimum wall spacing between two adjacent vias 2 is 150μm; the outer diameter of the via ring is 250μm, and the inner diameter is 150μm, so that the via ring can be adapted to the via in the pad.

[0055] The technical solutions provided by the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the embodiments of the present invention. The descriptions of the embodiments above are only for helping to understand the principles of the embodiments of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the embodiments of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A BGA fan-out structure of a PCB, at least one surface of the PCB is provided with a plurality of BGA pads arranged in a square array, wherein, The BGA pads arranged in the outermost circle are peripheral pads, and the other BGA pads are inner peripheral pads, characterized in that a disc-in-hole is made in the center of each inner peripheral pad by a disc-in-hole process, the aperture of the disc-in-hole is smaller than the outer diameter of the BGA pad, a hole ring corresponding to each disc-in-hole is arranged around the disc-in-hole and communicates with the disc-in-hole in each inner layer circuit layer of the PCB, and a plurality of fan-out wires corresponding to the hole rings communicate with the hole rings; the fan-out wires pass through the gap between longitudinally arranged adjacent disc-in-holes or pass through the outside of the disc-in-hole in a transverse direction, and the hole rings in different inner layer circuit layers correspond to different columns of inner peripheral pads.

2. The BGA fan-out structure of claim 1, wherein, The outer diameter of the BGA pad is 250μm, the spacing between adjacent two BGA pads is 50μm, and no wire is arranged between the BGA pads; the aperture of the disc-in-hole is 150μm, the center spacing between adjacent two disc-in-holes is 300μm, and the wall spacing between adjacent two disc-in-holes is 150μm; the outer diameter of the hole ring is 250μm, and the inner diameter is 150μm; the line width of the fan-out wire is 50μm.

3. The BGA fan-out structure of claim 1 or 2, wherein, The two fan-out wires in the same inner layer pass through the two gaps formed between the three adjacent disc-in-holes arranged in a longitudinal direction, and one of the fan-out wires passes through the outside of the disc-in-hole in a transverse direction.

4. A method for fabricating a BGA fan-out structure, comprising: The method comprises the following steps: S1, providing a production board, a plurality of square array distributed drill sites are arranged on the production board, a hole ring corresponding to each drill site is arranged around the drill site in each inner layer of the production board, and a plurality of fan-out wires corresponding to the hole rings communicate with the hole rings; two hole rings corresponding to each column of drill sites are arranged in different inner layers of the production board, and isolation discs with an outer diameter larger than the drill site are arranged outside the hole rings in each inner layer; two isolation discs are arranged at each drill site; S2, drilling a through hole at each drill site on the production board, and forming an isolation ring by the two isolation discs in the inner layer; S3, removing the two isolation rings on the hole wall by dissolving with an alkaline solution to form a pair of recessed sites in the hole; S4, sequentially performing chemical copper deposition and direct current flash plating on the production board, and then forming an internally isolated via hole by pulse plating and direct current plating; S5, then resin plug hole and solidification are performed on the via hole, the resin protruding from the plate surface is ground flat, and a copper plating layer connected with the copper layer on the hole wall is formed on the resin surface by copper deposition and plating; S6, manufacturing an outer layer circuit on the production board, and manufacturing a plurality of square array distributed BGA pads on at least one surface of the production board, the outer diameter of the BGA pad is larger than the aperture of the through hole; wherein the BGA pads arranged in the outermost circle are peripheral pads, and the other BGA pads are inner peripheral pads, the number of inner peripheral pads is the same as the number of drill sites and corresponds to the drill sites one by one, so that the via hole forms a disc-in-hole.

5. The method of claim 4, wherein, When the BGA pads are needed to be made on both surfaces of the production board, and the number of the drilling positions is n rows and n columns, the inner layers of the production board are 2n layers, wherein the inner layer circuits of the first layer to the n-th layer are arranged to face away from the upper surface of the production board and face the upper surface of the production board, the inner layer circuits of the n+1-th layer to the 2n-th layer are arranged to face away from the lower surface of the production board and face the upper surface of the production board, the inner layer circuits of the first layer to the n-th layer are symmetrically arranged with the inner layer circuits of the n+1-th layer to the 2n-th layer, and one column of holes on the symmetrically arranged inner layer circuit layers correspond to each other, so that one isolation pad is arranged on the outer side of the hole rings of the symmetrically arranged inner layer circuit layers, and two isolation pads are arranged at each drilling position, thereby forming an upper and lower partition type structure.

6. The method of claim 5, wherein, The hole rings of the first layer to the n-th layer correspond to the column number of the drilling positions in the order of the layers from top to bottom, and the hole rings of the n+1-th layer to the 2n-th layer correspond to the column number of the drilling positions in the order of the layers from bottom to top, so that the fan-out conductors of the second layer to the n-th layer pass through the isolation bands below the upper layer fan-out conductors, and the fan-out conductors of the n+1-th layer to the 2n-1-th layer pass through the isolation bands above the lower layer fan-out conductors.

7. The method of claim 4-6, wherein, In step S3, the production board is soaked in a 60-degree Celsius sodium hydroxide solution for 30-120 minutes, and the mass percentage of the solute in the sodium hydroxide solution is 10%.

8. The method of claim 4-6, wherein, In step S4, the current density of the direct current flash plating is 1.5 ASD, and the time is 3-6 minutes, so that the hole wall copper layer is thickened by 2-5 microns.

9. The method of claim 4-6, wherein, In step S4, the total time of the pulse plating is 6 minutes, the current density of the forward pulse plating of each cycle is 3 ASD, the time is 10 ms, the current density of the reverse pulse plating is 9 ASD, the time is 10 ms, and the hole wall copper layer is thickened by direct current plating after the pulse plating.

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