Read-out circuit and magnetic memory device

Abstract

To provide a read-out circuit and a magnetic memory device, in which a pair of electrodes sandwiching an MTJ (magnetic tunnel junction) laminate acts as parasitic capacitance, thereby accumulating charge, when current penetrating a magnetic tunnel junction is made to pass through the MTJ laminate to read bits written in the MTJ laminate.SOLUTION: A read-out circuit 2 for a memory cell MC in which an MTJ laminate is sandwiched between a pair of electrodes includes: a comparator COMP that compares an input voltage corresponding to a resistance state of the MTJ laminate with a reference voltage; and a discharge switch SW2 that discharges the charge charged in a parasitic capacitance CP generated between a pair of electrodes N1 and N2 of the memory cell MC.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a readout circuit and a magnetic memory device. [Background technology]

[0002] There is a demand for improving the signal processing speed in the optoelectronic interface between optical communication networks and electrical communication networks. To address this issue, Patent Document 1 discloses the use of a photonic spin register, and in particular, the use of magnetization reversal due to spin-orbit torque (SOT). Binary bits "1" and "0" are assigned to the magnetization direction written by magnetization reversal and the opposite magnetization direction, and the bit string is stored nonvolatilely.

[0003] In the photonic spin register according to the exemplary example of Patent Document 1, when a photocurrent (write current) generated from a pulsed optical signal flows through a spin Hall element, the magnetization of the ferromagnetic layer directly below the element is reversed. A common ferromagnetic layer is used for a single spin Hall element, and the bit string moves within the ferromagnetic layer due to domain wall motion caused by a shift current.

[0004] In this document, multiple read elements (a stack of a barrier layer, a fixed layer, and a terminal) are provided on a ferromagnetic layer to read the above-mentioned bit string. Paragraph 0034 of the document, in particular, discloses that a read current is generated and detected by applying a predetermined voltage. When the fixed layer and the free layer (the magnetic domains of the ferromagnetic layer directly below the fixed layer) have the same magnetization direction (parallel state), the MTJ (Magnetic Tunnel Junction) stack is in a low resistance state, and the read current is large. When the fixed layer and the free layer have opposite magnetization directions (non-parallel state), the MTJ stack is in a high resistance state, and the read current is small. The MTJ stack described here is composed of a stack of a free layer, a barrier layer, and a fixed layer. International Publication No. WO 2022 / 158545 is incorporated herein by reference in its entirety. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2022 / 158545 Summary of the Invention [Problem to be solved by the invention]

[0006] When a current is passed through a magnetic tunnel junction (MTJ) in the MTJ stack to read bits written in the MTJ stack, the pair of electrodes sandwiching the MTJ stack acts as a parasitic capacitance, causing charge to accumulate. This accumulated charge naturally discharges during periods when bits are not being read, but according to the inventors' investigations, this may have a negative impact on achieving a further leap in speeding up signal processing. [Means for solving the problem]

[0007] A readout circuit according to one embodiment of the present disclosure is a readout circuit for a memory cell in which an MTJ (Magnetic Tunnel Junction) stack is sandwiched between an electrode pair, and includes a comparator that compares an input voltage corresponding to the resistance state of the MTJ stack with a reference voltage, and a discharge switch that discharges electric charge stored in a parasitic capacitance generated between the electrode pair of the memory cell. The memory cell may include an equivalent circuit that is a parallel circuit of a variable resistor corresponding to the MTJ stack and a capacitor corresponding to the electrode pair.

[0008] In some embodiments, the discharge switch is connected in parallel with the memory cell to an input terminal of a comparator related to the input voltage.

[0009] In some embodiments, the readout circuit further includes a current supply switch that supplies a constant current to the memory cell. The discharge switch can be turned on in synchronization with the turning off of the current supply switch. In some embodiments, the readout circuit can further include a branch switch connected in parallel with the current supply switch to the constant current circuit. The branch switch can be connected to ground potential or to another memory cell. The branch switch can be controlled so that constant currents are supplied to the memory cell and the other memory cell in a complementary manner.

[0010] A magnetic memory device according to another aspect of the present disclosure is a magnetic memory device including a first cell array in which a plurality of MTJ stacks are arranged in a predetermined direction, and a circuit unit including a plurality of read circuits, the number of which corresponds to the number of the plurality of MTJ stacks, wherein each of the plurality of read circuits includes the above-described read circuit or a read circuit according to any combination of the above-described read circuit and the above-described features. The circuit unit may further include a reference voltage circuit that supplies two or more different reference voltages to the plurality of read circuits.

[0011] In some embodiments, the first cell array includes a common ferromagnetic layer for the multiple MTJ stacks, the common ferromagnetic layer including each free layer of the multiple MTJ stacks. The first cell array includes first and second electrodes configured to carry a shift current for domain wall motion in the common ferromagnetic layer, and the multiple MTJ stacks can be electrically connected to a ground potential via the second electrode. In some embodiments, each of the multiple MTJ stacks is electrically connected to the ground potential via a common terminal.

[0012] In some embodiments, the first cell array includes a substrate, a spin Hall layer formed on the substrate, a ferromagnetic layer formed on the spin Hall layer, and multiple stacks stacked on the ferromagnetic layer, each stack including a barrier layer, a pinned layer, and a read electrode. The multiple MTJ stacks are configured by stacking the barrier layer and the pinned layer on a layer portion included in the ferromagnetic layer. The read electrode matches one electrode included in an electrode pair, and the spin Hall layer matches the other electrode included in the electrode pair. The first cell array further includes first and second electrodes provided to carry a shift current for domain wall motion in the ferromagnetic layer, and the second electrode can be electrically connected to both the ferromagnetic layer and the spin Hall layer. Each MTJ stack of the multiple memory cells can be connected to ground potential via a common terminal.

[0013] A magnetic memory device according to yet another embodiment of the present disclosure includes a first cell array in which N (N is a natural number of 2 or greater) first MTJ stacks are arranged in a predetermined direction, a second cell array in which M (M is a natural number of 2 or greater) second MTJ stacks are arranged in a predetermined direction, N first read circuits for reading bit strings from the N first MTJ stacks, and M second read circuits for reading bit strings from the M second MTJ stacks. Each of the N first read circuits includes a read circuit according to the above-described read circuit or any combination of the above-described features. Each of the M second read circuits includes a read circuit according to the above-described read circuit or any combination of the above-described features.

[0014] In some embodiments, the magnetic memory device includes at least one constant current circuit common to one first read circuit included in the N first read circuits and one second read circuit included in the M second read circuits, and when N is equal to M, the number of constant current circuits included in the magnetic memory device may be N. [Effects of the Invention]

[0015] According to one aspect of the present disclosure, an increase in the speed and / or reliability of signal readout from a magnetic memory device is facilitated. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a circuit diagram of a magnetic memory device according to an embodiment of the present disclosure. [Figure 2] 2 is a time chart relating to the magnetic memory device shown in FIG. [Figure 3] FIG. 10 is a schematic top view of a magnetic memory device according to an application. [Figure 4] FIG. 4 is a schematic diagram showing a cross-sectional configuration of a device portion of the magnetic memory device shown in FIG. [Figure 5] 4 is a schematic circuit diagram of a read circuit of the magnetic memory device shown in FIG. 3. FIG. [Figure 6] FIG. 10 is a circuit diagram of a magnetic memory device according to a modified example. [Figure 7] FIG. 1 is a circuit diagram of a constant current circuit according to a non-limiting example. [Figure 8] FIG. 10 is a schematic top view of a magnetic memory device according to a further application mode. [Figure 9] 9 is a time chart relating to the magnetic memory device shown in FIG. 8. [Figure 10] 9 is a schematic circuit diagram of a read circuit of the magnetic memory device shown in FIG. 8. FIG. [Figure 11] FIG. 11 is a more detailed circuit diagram of a portion of the readout circuit shown in FIG. [Figure 12] 12 is a time chart relating to a part of the readout circuit shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0017] Non-limiting embodiments and features of the present invention will be described below with reference to the drawings. Those skilled in the art will be able to combine the various embodiments and / or features without the need for excessive explanation, and will also be able to understand the synergistic effects of such combinations. Duplicate descriptions between embodiments will be omitted in principle. The reference drawings are primarily intended to describe the invention, and are simplified for ease of illustration. Each feature is not only effective in the readout circuit disclosed in this specification, but is understood as a universal feature that can also be applied to various other readout circuits not disclosed in this specification.

[0018] 1 and 2. As shown in Fig. 1, the magnetic memory device 1 includes a memory cell MC in which an MTJ (Magnetic Tunnel Junction) laminate is sandwiched between an electrode pair, a read circuit 2 for the memory cell MC, a control unit 3 that supplies a switching signal to the read circuit 2 to control the on / off of a switch included in the read circuit 2, a constant current circuit 5 that supplies a constant current to the read circuit 2, and a reference voltage circuit 6 that supplies a reference voltage to the read circuit 2. The memory cell MC includes an equivalent circuit of an RC parallel circuit, where a node N1 indicates one electrode of the electrode pair, a node N2 indicates the other electrode of the electrode pair, and a variable resistor R MTJ indicates the MTJ stack, and the capacitor C P denotes the parasitic capacitance formed between the electrode pair.

[0019] The magnetic memory device 1 can be used as a buffer memory in an optical / electrical interface between an optical communication network and an electric communication network. For this application, it is more preferable to include a large number of memory cells MC rather than a single memory cell MC. However, some aspects of the present disclosure are not constrained by the number of memory cells MC, and therefore, a form in which the magnetic memory device 1 has a single memory cell MC will first be described. Note that, when optimized for buffer memory application, the magnetic memory device 1 may have a number of memory cells MC that is a power of two excluding 1 (e.g., 2, 4, 8, 16, 32, 64, 128, 256). Note that, exemplarily, the optical communication network upstream of the magnetic memory device 1 is single-channel, and the electric communication network downstream thereof is multi-channel.

[0020] As mentioned above, an MTJ stack is composed of a stack of a free layer, a barrier layer, and a pinned layer. The free layer and the pinned layer are made of ferromagnetic materials, such as ferrimagnetic materials (e.g., GdFeCo) or topological antiferromagnetic materials (e.g., Mn3Sn). The barrier layer is made of an insulating material, such as a non-magnetic material (e.g., MgO). The barrier layer is thin, allowing charge to move between the free layer and the pinned layer via quantum mechanical tunneling. When the free layer has a magnetization direction that is the same as that of the pinned layer (parallel state), the MTJ stack has a lower resistance with respect to the through current flowing through the MTJ. When the free layer has a magnetization direction that is opposite to that of the pinned layer (antiparallel state), the MTJ stack has a higher resistance with respect to the through current flowing through the MTJ. Materials other than those mentioned above can also be used for the pinned layer, free layer, and barrier layer.

[0021] The read circuit 2 includes a current supply switch SW1 that supplies a constant current to the memory cell MC, an input voltage V in and the reference voltage V ref and the parasitic capacitance (capacitor C in the equivalent circuit) that occurs between the electrode pair of the memory cell MC. P The current supply switch SW1 and the discharge switch SW2 typically include a single transistor (bipolar transistor or MOS transistor). The comparator COMP is typically a two-input, one-output logic circuit, and is connected to an input voltage V in The first input terminal receives the reference voltage V ref and an output terminal for outputting a one-bit output signal indicating the comparison result. The resistance state of the MTJ stack is typically one of two states: a low resistance state and a high resistance state. However, configurations in which the MTJ stack has three or more resistance states (specifically, three or more resistance states such as a low resistance state, an intermediate resistance state, and a high resistance state) are also conceivable. In this case, the comparator COMP can compare the input voltage with two or more reference voltages.

[0022] The constant current circuit 5 supplies a constant current I const The constant current circuit 5 can be arbitrarily configured with one or more transistors (for example, bipolar transistors or MOS transistors). The reference voltage circuit 6 generates a reference voltage V ref and supplies it to the second input terminal of the comparator COMP. ref Although the control circuit 3 includes a voltage divider circuit for generating a voltage, other circuits may also be employed. The control unit 3 supplies a switching signal S1 to the current supply switch SW1 for switching it on and off, and supplies a switching signal S2 to the discharge switch SW2 for switching it on and off. The control unit 3 may include, but is not limited to, a digital logic sequence circuit designed for such a function.

[0023] An exemplary connection relationship between circuit elements in the magnetic memory device 1 is as shown in the figure, in which the constant current circuit 5, the current supply switch SW1, and the memory cell MC are connected in series between the power supply potential and the ground potential (note that the order of the current supply switch SW1 and the memory cell MC can be reversed). The constant current circuit 5, the current supply switch SW1, and the discharge switch SW2 are connected in series between the power supply potential and the ground potential. A first input terminal of the comparator COMP is electrically connected to the node N1 of the memory cell MC. In the illustrated example, the first input terminal is connected to the node N1 of the memory cell MC via a node N3. The node N3 is located between the current supply switch SW1 and the discharge switch SW2. The discharge switch SW2 is connected in parallel with the memory cell MC (particularly the MTJ stack) to the first input terminal of the comparator COMP. Control terminals of the current supply switch SW1 and the discharge switch SW2 are each connected to the control unit 3. Note that one or more wirings, such as a bonding wire, a bump, or a pattern wiring layer, may exist between the node N1 and the node N3, but this is not limited thereto.

[0024] The operation of the magnetic memory device 1 will be described with reference to FIG. 2. First, the MTJ stack of the memory cell MC is set to a high resistance state ("H"). The magnetization direction of the free layer of the MTJ stack can be arbitrarily set by an electromagnetic method. At time t1, the control unit 3 supplies an H-level switching signal S1 to the current supply switch SW1, turning the current supply switch SW1 on. A current is supplied from the constant current circuit 5 to the memory cell MC (particularly the MTJ stack) via the current supply switch SW1. This current slowly increases over time according to the time constant of the RC parallel circuit, and a constant current I const The MTJ stack is set to a high resistance state ("H"), and therefore a voltage proportional to this resistance is generated, which is proportional to the input voltage V in is supplied from the memory cell MC to the first input terminal of the comparator COMP.

[0025] Input voltage V in Like the current flowing through the memory cell MC, the input voltage V increases slowly over time and reaches its maximum value slightly after turn-on. in At time t2 during the increase in the input voltage V in is the reference voltage V ref The comparator COMP judges that the voltage exceeds the threshold and outputs a high-level signal S out At time t3, the magnetic memory device 1 is used as a buffer memory, so the output signal S out is stored.

[0026] At time t4, the switching signal S1 changes from H level to L level, turning off the current supply switch SW1. Synchronously with this, the control unit 3 supplies an H level switching signal S2 to the discharge switch SW2, turning on the discharge switch SW2. Note that although it does not matter if the switching timings of the two switches are slightly different, it is better to turn off the current supply switch SW1 before turning on the discharge switch SW2 in order to reduce power consumption.

[0027] When the discharge switch SW2 is turned on, the capacitor C P The charge stored in the discharge switch SW2 is rapidly discharged to ground through the discharge switch SW2. The resistance of the discharge switch SW2 in the short-circuit state is smaller than the resistance of any of the MTJ stacks, and the input voltage V in drops rapidly, and at time t5, the reference voltage V ref The output signal S out The discharge switch SW2 is turned on while the capacitor C P The time is set to be long enough to discharge the charge stored in the transistor, and the transistor is turned off at time t6.

[0028] In FIG. 2, the dashed line D1 indicates the input voltage V in In short, it shows the change in the capacitor C P This indicates that a relatively long time is required for the charge stored in the capacitor to discharge naturally.

[0029] At time t7, the MTJ stack is set to a low resistance state ("L"). At time t8, the control unit 3 supplies an H-level switching signal S1 to the current supply switch SW1, turning the current supply switch SW1 on. A current is supplied from the constant current circuit 5 to the memory cell MC (particularly the MTJ stack) via the current supply switch SW1. The MTJ stack is set to a low resistance state ("L"). Therefore, a voltage proportional to this resistance value is generated, and the input voltage V in is supplied from the memory cell MC to the first input terminal of the comparator COMP as an input voltage V in is the reference voltage V ref Therefore, the comparator COMP outputs a high-level output signal S out At time t10, the output signal S is not output and remains at L level. out is stored.

[0030] At time t11, the switching signal S1 changes from H level to L level, and the current supply switch SW1 is turned off. In synchronization with this, the control unit 3 supplies an H level switching signal S2 to the discharge switch SW2, and the discharge switch SW2 is turned on. When the discharge switch SW2 is turned on, the capacitor C P The charge stored in the input voltage V is rapidly discharged to ground through the discharge switch SW2. in Here too, the dashed line D2 indicates the input voltage V in In short, it shows the change in the capacitor C P This indicates that a relatively long time is required for the charge stored in the capacitor to discharge naturally.

[0031] As can be seen from the above description, in this embodiment, the parasitic capacitance (capacitor C P A discharge switch SW2 is provided to actively discharge the charge stored in the parasitic capacitance of the memory cell MC. By turning on the discharge switch SW2, the charge stored in the parasitic capacitance of the memory cell MC can be rapidly discharged. In addition to or instead of this, the following constant current I const This makes it possible to make the initial state of the memory cell MC before the supply of the voltage more stable. As a result, high-speed reading of signals from the MTJ stack is promoted and / or the reliability of signal reading from the MTJ stack is improved. This can also promote compatibility with high-speed writing techniques for the MTJ stack, as disclosed in Patent Document 1.

[0032] The effect of the resistance value of the MTJ stack (especially larger resistance values) on the time constant of the RC parallel circuit is not small, and the input voltage V in is the constant current I constEven if the supply of R is stopped, it does not immediately become zero. In many cases, it is not easy to reduce the R and C of the RC parallel circuit itself due to the structure of the memory cell MC and / or the MTJ stack. Providing the discharge switch SW2 as described above is a straightforward solution in situations with such constraints. Preferably, the discharge switch SW2 is turned on in synchronization with (typically, simultaneously with or slightly delayed from) the turn-off of the current supply switch SW1, thereby reducing power consumption.

[0033] An application form will be described with reference to Figs. 3 to 5. Fig. 3 is a schematic top view of a magnetic memory device 1' according to the application form. Fig. 4 is a schematic view showing a cross-sectional configuration of a device section of the magnetic memory device 1'. Fig. 5 is a schematic circuit diagram relating to a read circuit of the magnetic memory device 1'. In the form shown in Fig. 3, a number of memory cells MC1 to MC N That is, bits can be simultaneously read from the memory cells MC1 to MC N Even if bit writing to the optical fiber is performed using a single channel (this is of course not limited to this), bit reading from the optical fiber can be performed using multiple channels. This speeds up bit reading from the optical fiber, which is prone to delays compared to bit writing, and helps to reduce delays in the optical / electrical interface between the optical communication network and the electrical communication network.

[0034] As shown in FIG. 3, the magnetic memory device 1′ includes memory cells MC1 to MC N (Alternatively, MTJ stacks E1 to E N ) are arranged in a predetermined direction, and the device section 4 includes a first cell array CA1, and memory cells MC1 to MC N (Alternatively, MTJ stacks E1 to E N A plurality of read circuits RC1 to RC2 are provided for reading bits from the N The circuit section 8 includes:

[0035] 4, the device section 4 includes a substrate 21, a spin Hall layer 22 formed on the substrate 21, a ferromagnetic layer 23 formed on the substrate 21 (here, the spin Hall layer 22), a plurality of stacked sections 24 stacked on the ferromagnetic layer 23, and an insulating layer 28. Each stacked section 24 includes a barrier layer 25, a fixed layer 26, and a read electrode 27. Here, each of the MTJ stacks E1 to E N The MTJ stack is configured by stacking a barrier layer 25 and a fixed layer 26 on a layer portion of a ferromagnetic layer 23. The read electrode 27 matches one of the electrodes in the electrode pair that sandwich the MTJ stack.

[0036] The device section 4 further generates a shift current I shift Typically, these are stacked on a substrate 21 as shown in the figure, and are arranged on both sides of a stack of a spin Hall layer 22 and a ferromagnetic layer 23 (or only the latter if the former is omitted) in the longitudinal direction of the array. The other electrode included in the electrode pair sandwiching the MTJ stack may be, for example, the spin Hall layer 22 or the second electrode EL2, but is not limited to this.

[0037] MTJ stacks E1 to E N have individual free layers (magnetic domains partitioned by domain walls) in a common ferromagnetic layer 23. By passing a shift current between the first electrode EL1 and the second electrode EL2 to move the domain walls in the ferromagnetic layer 23, the magnetic domains also move in the ferromagnetic layer 23, enabling bit updating in the first cell array CA1. In the illustrated example, the shift current I shift flows into the spin Hall layer 22, causing the domain wall in the ferromagnetic layer 23 to move.

[0038] To explain further, the shift current I shift flows in the ferromagnetic layer 23 in addition to the spin Hall layer 22, and the direction of the electron flow (shift current I shiftHowever, the resistivity of the spin Hall layer 22 is significantly lower than that of the ferromagnetic layer 23, and if their thicknesses are appropriately set (for example, the thickness of the spin Hall layer 22 = 4 nm, the thickness of the ferromagnetic layer 23 = 6 nm), a larger shift current I shift flows, and the spin-orbit torque (SOT) becomes dominant over the spin-transfer torque (STT). Therefore, the shift current I shift The magnetic domain wall moves in the direction along the

[0039] Multiple readout circuits RC1 to RC N Each of the plurality of readout circuits RC1 to RC2 includes the readout circuit 2 shown in FIG. 1 (and optionally a constant current circuit 5). N The number of memory cells MC1 to MC N (Alternatively, MTJ stacks E1 to E N ) in the magnetic memory device 1'. In the magnetic memory device 1', the amount of bit data that can be buffered increases by the increase in the number of memory cells MC, and compatibility with the technology disclosed in Patent Document 1 (especially the shift current) is improved. Note that N represents a natural number of 2 or more, and typically represents a power of 2 excluding 1 (for example, 2, 4, 8, 16, 32, 64, 128, 256).

[0040] The magnetic memory device 1′ optionally includes MTJ stacks E1 to E NThe optical waveguide 72 may include a write unit 7 that writes bits to the ferromagnetic layer 23 (see FIG. 3). The write unit 7 includes a substrate 71, an optical waveguide 72 stacked on the substrate 71, a photoelectric converter 73 stacked on the substrate 71 adjacent to the output end of the optical waveguide 72, metal films 74a and 74b arranged on both sides of the photoelectric converter 73, and a spin Hall element 75 stacked on the ferromagnetic layer 23. The substrate 71 is made of, for example, an insulating or semiconductor substrate. The optical waveguide 72 is made of a material transparent to a specific wavelength, such as resin. The photoelectric converter 73 is a dielectric (for example, made of an insulating material or a semiconductor material). The metal films 74a and 74b are made of a metal material such as ARC or Ag. The spin Hall element 75 is made of a heavy metal that exhibits the spin Hall effect, such as Pt or W.

[0041] When the photoelectric converter 73 receives the light propagating through the optical waveguide 72, surface plasmon polaritons (SPPs) are excited at the interfaces between the photoelectric converter 73 and the metal films 74a and 74b, generating a strong magnetic field around the interface. As shown in the figure, a bias voltage is applied from the photoelectric converter 73 to the spin Hall element 75, and a write current I write This write current I write When the shift current I flows through the spin Hall element 75, a spin current is generated in the perpendicular direction (in other words, the direction parallel to the stacking direction of the ferromagnetic layer 23 and the spin Hall element 75) in the spin Hall element 75, and a spin orbit torque (SOT) acts on the magnetization direction of the magnetic domain (the domain to be written) of the ferromagnetic layer 23 directly below the spin Hall element 75, causing a magnetization reversal and writing a bit. shift As a result, the magnetic domain directly below the spin Hall element 75 moves to a position directly below the pinned layer 26 of the MTJ stack E1, and ultimately becomes the free layer. shift By passing N times, N bits are formed in the MTJ stacks E1 to E N The ferromagnetic layer 23 is stored in the shift current I shift The magnetization direction is preset by a magnet or the like on the upstream side of the spin Hall element 75 with respect to the direction in which the write current I write The presence or absence of MTJ stacks E1 to EN The bit value (0 or 1) of the write unit 7 can be controlled. For details of the operation of the write unit 7, see also Patent Document 1.

[0042] 1 and 4, the MTJ stacks E1 to E N is the MTJ stack E N The MTJ stack E1 is positioned away from the second electrode EL2 (a non-limiting example of a "common terminal") in the order of the MTJ stack E1. N The current paths that reach the second electrode EL2 via the MTJ stacks E1 to E3 have different resistances (in the illustrated example, the lengths of the spin Hall layers 22 included in each current path are different). N The input voltage V is input to the comparator COMP from in There is a risk of variation in the results.

[0043] In some cases, the circuit unit 8 includes readout circuits RC1 to RC N Two or more different reference voltages (e.g., different reference voltages V ref_1 ~V ref_N ) (see FIG. 5), thereby avoiding or suppressing the above-mentioned problems. N Each of the readout circuits RC1 to RC2 corresponds to the readout circuit 2 shown in FIG. N Each read circuit RC1 to RC N By setting a reference voltage for each subset of the memory cells MC, the reliability of signal reading from the memory cells MC (i.e., the reliability of the output signal S out The reliability of the readout circuits RC1 to RC2 is improved (in other words, the error rate is reduced). N It is not necessary to set different reference voltages for all of the plurality of readout circuits RC1 to RC N / 2 and setting a first reference voltage for a first subset of the plurality of readout circuits RC (N / 2)+1 ~RC NA second reference voltage different from the first reference voltage can be set for the second subset of the input signals. To set the different reference voltages, a voltage divider circuit having multiple resistors connected in series can be used, but is not limited to this.

[0044] The modified example will be further described with reference to FIG. 6. FIG. 6 is a circuit diagram of a magnetic memory device 1'' according to the modified example. FIG. 7 is a circuit diagram showing a constant current circuit according to a non-limiting example. As shown in FIG. 6, the magnetic memory device 1'' may further include a branch switch SW3 connected in parallel with the current supply switch SW1 for the constant current circuit 5. This allows the constant current I const The branch switch SW3 is connected between the constant current circuit 5 and the ground potential. In the illustrated example, a dummy resistor R Dummy are connected in series. A constant current circuit typically goes through a transient state in which no constant current is generated, followed by a steady state in which a constant current is generated.

[0045] The branch switch SW3 is controlled complementarily to the current supply switch SW1. That is, the branch switch SW3 is turned off during the on period of the current supply switch SW1, and the branch switch SW3 is turned on during the off period of the current supply switch SW1. When the branch switch SW3 is on, the constant current I const is the dummy resistor R Dummy This means that power is consumed in the read circuit even when not reading bits from the MTJ stack.

[0046] FIG. 7 shows only one example of a constant current circuit. The constant current circuit can be constructed from one transistor and should not be limited to the one shown. In the illustrated example, the constant current circuit has a transistor (bipolar transistor or MOS transistor) and a resistor connected between the power supply potential and the current supply switch SW1, and further has an operational amplifier whose output terminal is connected to the control terminal of the transistor via a resistor. A predetermined voltage is input to the non-inverting input terminal of the operational amplifier, and its inverting input terminal is connected to the junction between the output terminal of the transistor and the resistor. The operational amplifier operates to make the input voltage of the non-inverting input terminal equal to the input voltage of the inverting input terminal, resulting in a constant current I const When the current supply switch SW1 is turned off, the constant current I const Even if the current supply switch SW1 is turned on again, the constant current I const does not flow immediately. Therefore, it is advantageous to maintain the constant current circuit in a steady state for fast reading of bits from the MTJ stack.

[0047] Further application modes will be described with reference to FIGS. 8 to 12. FIG. 8 is a schematic top view of a magnetic memory device 1''' according to a further application mode. FIG. 9 is a time chart showing the general operation of the magnetic memory device 1''' shown in FIG. 8. FIG. 10 is a schematic circuit diagram relating to a read circuit of the magnetic memory device 1''' shown in FIG. 8. FIG. 11 is a more detailed circuit diagram of a part of the read circuit shown in FIG. 10. FIG. 12 is a time chart relating to the circuit diagram shown in FIG. 11. Note that the explanations relating to FIGS. 11 and 12 largely overlap with those relating to FIGS. 1 and 2, and therefore detailed explanations thereof will be omitted.

[0048] In the magnetic memory device 1''' according to this application, the device section 4 includes memory cells MC 1_1 ~MC 1_16 (or MTJ stack E 1_1 ~E 1_16 ) are arranged in a predetermined direction, and a first cell array CA1 includes memory cells MC 2_1 ~MC 2_16 (or MTJ stack E2_1 ~E 2_16 ) are arranged in a predetermined direction (i.e., two or more cell arrays), and the circuit unit 8 includes memory cells MC 1_1 ~MC 1_16 and memory cell MC 2_1 ~MC 2_16 A read circuit RC is provided for reading bits from 1_1 ~RC 1_16 ,RC 2_1 ~RC 2_16 and constant current circuits 51-5 16 The circuit section 8 includes a constant current circuit 5' including a readout circuit RC 1_1 ~RC 1_16 a first circuit array A_RC1 including a read circuit RC 2_1 ~RC 2_16 The first cell array CA1 and the second cell array CA2 may include a second circuit array A_RC2 including N. For convenience of explanation, N=16 is used, but of course, this is not limiting. A common write unit 7 is provided for the first cell array CA1 and the second cell array CA2, but two separate units may also be provided. Bit writing to the first cell array CA1 and the second cell array CA2 may also be performed in a time-division manner.

[0049] Readout circuit RC 1_1 ~RC 1_16 ,RC 2_1 ~RC 2_16 Each of the readout circuits RC includes the readout circuit 2 shown in FIG. 1_1 ~RC 1_16 ,RC 2_1 ~RC 2_16 The sum of memory cells MC 1_1 ~MC 1_16 ,MC 2_1 ~MC 2_16 On the other hand, the total number of constant current circuits 51 to 5 16 The number of memory cells is half that (=16). This is the result of sharing a constant current circuit between memory cells belonging to different cell arrays.

[0050] As shown in Fig. 9, a bit write period (W) and a bit read period (R) are set complementary to each other for the first cell array CA1 and the second cell array CA2. A switching control is performed to selectively supply a constant current to the cell array from which a bit is to be read, and as a result, the constant current circuit can be maintained in a steady state without wasting power. For this purpose, as shown in Fig. 10, constant current circuits 51 to 5 16 Branch switch SW that branches the constant current supplied from 3_1 ~SW 3_16 A branch switch SW 3_1 ~SW 3_16 is the readout circuit RC 1_1 ~RC 1_16 The constant current circuits 51 to 5 are controlled to be on and off in a complementary manner with the current supply switches included in the constant current circuits 51 to 5. 16 The constant current flowing from the readout circuit RC 1_1 ~RC 1_16 Instead, the readout circuit RC 2_1 ~RC 2_16 will flow into the memory cell MC 2_1 ~MC 2_16 This allows bit reading from the

[0051] Figure 11 shows the readout circuit RC 1_1 , readout circuit RC 2_1 12 shows an example of the connection of the constant current circuit 51. The readout circuit RC 1_1 When the current supply switch SW1 is turned off, the branch switch SW 3_1 is turned on, and the memory cell MC 2_1 A constant current is supplied to the memory cell MC 1_1 After the bit writing to is completed, the branch switch SW 3_1 is turned off, and at the same time or with a slight delay, the readout circuit RC 1_1 The current supply switch SW1 is turned on, and the memory cell MC 1_1 In the case shown in FIG. 11, the branch switch SW3 is connected to the readout circuit RC 2_1It can also be regarded as a current supply switch for the readout circuit RC 1_1 Current supply switch and readout circuit RC 2_1 The current supply switches are controlled on and off in a complementary manner.

[0052] In this application, a read circuit (for example, RC 1_1 ) and a read circuit (e.g., RC 2_1 ) a common constant current circuit (for example, the constant current circuit 51) is used. Dummy The constant current circuit can be maintained in a steady state without wasting power. [Explanation of symbols]

[0053] 1: Magnetic memory device 2:Readout circuit COMP: Comparator MC: Memory cell N1, N2: Node pair (electrode pair) C P :parasitic capacitance SW2: Discharge switch

Claims

1. A read circuit for a memory cell in which a magnetic tunnel junction (MTJ) stack is sandwiched between an electrode pair, a comparator that compares an input voltage corresponding to the resistance state of the MTJ stack with a reference voltage; The read circuit includes a discharge switch that discharges the charge stored in the parasitic capacitance generated between the electrode pair of the memory cell.

2. 2. The readout circuit of claim 1, wherein the discharge switch is connected in parallel with the memory cell to an input terminal of the comparator related to the input voltage.

3. 3. The read circuit of claim 2, further comprising a current supply switch that supplies a constant current to the memory cell.

4. 4. The readout circuit according to claim 3, wherein the discharge switch is turned on in synchronization with the turning off of the current supply switch.

5. 4. The readout circuit according to claim 3, further comprising a branch switch connected in parallel with said current supply switch to a constant current circuit.

6. The readout circuit of claim 5 , wherein the branch switch is connected to a ground potential or to another memory cell.

7. 7. The readout circuit according to claim 6, wherein said branch switch is controlled so that said constant current is supplied to said memory cell and said another memory cell in a complementary manner.

8. 8. The readout circuit according to claim 1, wherein the memory cell includes an equivalent circuit that is a parallel circuit of a variable resistor corresponding to the MTJ stack and a capacitor corresponding to the electrode pair.

9. a first cell array in which a plurality of MTJ stacks are arranged in a predetermined direction; A magnetic memory device comprising a circuit section including a plurality of read circuits, the number of which corresponds to the number of the plurality of MTJ stacks, and each of the plurality of read circuits including the read circuit according to any one of claims 1 to 7.

10. 10. The magnetic memory device of claim 9, wherein the first cell array includes a common ferromagnetic layer for the plurality of MTJ stacks, the common ferromagnetic layer including each free layer of the plurality of MTJ stacks.

11. 11. The magnetic memory device of claim 10, wherein the first cell array comprises first and second electrodes for passing a shift current for domain wall motion in the common ferromagnetic layer, and the plurality of MTJ stacks are electrically connected to a ground potential via the second electrodes.

12. 10. The magnetic memory device according to claim 9, wherein each of the plurality of MTJ stacks is electrically connected to a ground potential via a common terminal.

13. the first cell array includes a substrate, a spin Hall layer formed on the substrate, a ferromagnetic layer formed on the spin Hall layer, and a plurality of stacked sections stacked on the ferromagnetic layer, each stacked section including a barrier layer, a fixed layer, and a read electrode; 10. The magnetic memory device of claim 9, wherein the plurality of MTJ stacks are configured by stacking the barrier layer and the fixed layer on a layer portion included in the ferromagnetic layer, the read electrode corresponds to one electrode included in the electrode pair, and the spin Hall layer corresponds to the other electrode included in the electrode pair.

14. 14. The magnetic memory device of claim 13, wherein the first cell array further comprises first and second electrodes configured to pass a shift current for domain wall motion in the ferromagnetic layer, the second electrode being electrically connected to both the ferromagnetic layer and the spin Hall layer.

15. 14. The magnetic memory device of claim 13, wherein each MTJ stack of the plurality of memory cells is connected to a ground potential through a common terminal.

16. 10. The magnetic memory device according to claim 9, wherein said circuit section further includes a reference voltage circuit that supplies two or more different reference voltages to said plurality of read circuits.

17. a first cell array in which N (N is a natural number equal to or greater than 2) first MTJ stacks are arranged in a predetermined direction; a second cell array in which M (M is a natural number equal to or greater than 2) second MTJ stacks are arranged in a predetermined direction; N first read circuits for reading bit sequences from the N first MTJ stacks; a magnetic memory device comprising M second read circuits for reading bit sequences from the M second MTJ stacks, 8. A magnetic memory device, wherein each of the N first read circuits includes a read circuit according to claim 1, and each of the M second read circuits includes a read circuit according to claim 1.

18. The magnetic memory device of claim 17, wherein the magnetic memory device includes at least one constant current circuit common to one first read circuit included in the N first read circuits and one second read circuit included in the M second read circuits.

19. 20. The magnetic memory device of claim 18, wherein N is equal to M, 19. The magnetic memory device according to claim 18, wherein the number of the constant current circuits included in the magnetic memory device is N.

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