Semiconductor device

Abstract

To inhibit variation in electrical properties and improve credibility of a semiconductor device using a transistor having an oxide semiconductor.SOLUTION: A semiconductor device comprises: a gate electrode on an insulating surface; an oxide semiconductor film overlapping the gate electrode; a gate insulation film between the gate electrode and the oxide semiconductor film, which contacts the oxide semiconductor film; a protection film which contacts the oxide semiconductor film on a surface opposite to a surface contacting the gate insulation film; and a pair of electrodes contacting the oxide semiconductor film, in which an emission amount of a gas having a mass-to-charge ratio m / z=17 emitted from the gate insulation film or the protection film by a heat treatment is greater than an emission amount of a nitrogen oxide emitted by the heat treatment.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method. The invention relates to the manufacture or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, or any of these devices. In particular, one aspect of the present invention relates to a field effect transistor, a driving method thereof, and a manufacturing method thereof. The present invention relates to a semiconductor device having a transistor.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0003] It is used in many flat panel displays, such as liquid crystal displays and light-emitting displays. The transistors used are made of amorphous silicon and single-crystal silicon formed on a glass substrate. It is made of silicon semiconductor such as silicon or polycrystalline silicon. Transistors using silicon semiconductors are also used in integrated circuits (ICs).

[0004] In recent years, metal oxides that exhibit semiconductor properties have been used in transistors instead of silicon semiconductors. In this specification, metal oxides that exhibit semiconductor properties are referred to as oxides. We will call it a semiconductor.

[0005] For example, a transistor using zinc oxide or an In-Ga-Zn oxide as an oxide semiconductor may be used. A technique for manufacturing a transistor and using the transistor as a switching element for a pixel of a display device. Techniques for this have been disclosed (see Patent Documents 1 and 2).

[0006] Incidentally, it has been pointed out that hydrogen is a carrier source, especially in oxide semiconductors. Therefore, it is necessary to take measures to prevent hydrogen from being mixed in when forming the oxide semiconductor. There is a demand for reducing hydrogen in the oxide semiconductor film and the gate insulating film in contact with the oxide semiconductor. By doing so, fluctuations in the threshold voltage are suppressed (see Patent Document 3). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2009-224479 Summary of the Invention [Problem to be solved by the invention]

[0008] However, nitrogen, like hydrogen, is a carrier supply source. When a large amount of nitrogen is contained in the film in contact with the oxide semiconductor film, the electric conductivity of the transistor having the oxide semiconductor film is improved. Fluctuations in characteristics occur, typically fluctuations in threshold voltage. There is a problem of gender variability.

[0009] In view of the above, one embodiment of the present invention is directed to a semiconductor device including a transistor including an oxide semiconductor. In the semiconductor device, one object is to suppress fluctuations in electrical characteristics and improve reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like. The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment of the present invention to solve all of these problems. The problem is self-evident from the description, drawings, claims, etc. It is possible to extract other issues from documents, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device including a gate electrode on an insulating surface, an oxide semiconductor film overlapping with the gate electrode, and a gate insulating film. a gate insulating film between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film; a protective film in contact with the surface of the oxide semiconductor film opposite to the surface in contact with the gate insulating film; and a pair of electrodes in contact with the oxide semiconductor film, and the gate insulating film or the protective film is The mass-to-charge ratio m / z of nitrogen oxides released by heat treatment was calculated from the amount of nitrogen oxides released by the treatment. This is a semiconductor device having a region with a large amount of gas released (=17).

[0011] Another embodiment of the present invention is a semiconductor device including a gate electrode on an insulating surface and an oxide semiconductor layer overlapping the gate electrode. a gate insulating film between the oxide semiconductor film and the gate electrode and the oxide semiconductor film, the gate insulating film being in contact with the oxide semiconductor film; The insulating film is in contact with the oxide semiconductor film on the surface opposite to the surface in contact with the gate insulating film. A semiconductor device having a transistor including a protective film and a pair of electrodes in contact with an oxide semiconductor film The double logarithmic graph shows the amount of change in the threshold voltage of the transistor with respect to the stress time. In the graph, the intervals of the horizontal and vertical logarithmic scales are equal, and the absolute value of the variation of the threshold voltage is The angle between the power approximation line and the line where the absolute value of the threshold voltage fluctuation is 0V is -3° or more and less than 20°, and the absolute value of the change in threshold voltage when the stress time is 0.1 hours The value is less than 0.3V. The stress time is the time when the transistor is subjected to stresses such as voltage and temperature. This refers to the time to impose a load.

[0012] Another embodiment of the present invention is a semiconductor device including a gate electrode on an insulating surface and an oxide semiconductor layer overlapping the gate electrode. a gate insulating film between the oxide semiconductor film and the gate electrode and the oxide semiconductor film, the gate insulating film being in contact with the oxide semiconductor film; The insulating film is in contact with the oxide semiconductor film on the surface opposite to the surface in contact with the gate insulating film. A semiconductor device having a transistor including a protective film and a pair of electrodes in contact with an oxide semiconductor film The graph shows the amount of change in the threshold voltage of a transistor versus stress time. the exponent of the power approximation line of the fluctuation value of the threshold voltage is not less than -0.1 and not more than 0.3, The variation in threshold voltage when the stress time is 0.1 hours is less than 0.3V.

[0013] The gate insulating film or the protective film has a spin- Density is 1×10 18 spins / cm 3 Less than 1 x 10 17 spins / cm 3 More than 1×10 18 spins / cm 3 Having an area or part that is less than

[0014] In addition, the gate insulating film or protective film has a g value of 2. The first signal is between 0.037 and 2.039, and the second signal is between 2.001 and 2.003. Two signals and a third signal with a g value between 1.964 and 1.966 are observed. It also has a first signal and a second signal, and The split widths of the first and third signals are approximately 5 mT in X-band measurements. .

[0015] Furthermore, signals due to nitrogen oxides are observed in the gate insulating film or protective film. Nitrogen oxides include nitric oxide and nitrogen dioxide.

[0016] A protective film, an oxide semiconductor film, and a gate insulating film are provided between an insulating surface and a gate electrode. Alternatively, a gate electrode and a gate insulating film may be provided between the insulating surface and the oxide semiconductor film. You may do so.

[0017] The pair of electrodes may be provided between the oxide semiconductor film and the protective film. The electrode may be provided between the oxide semiconductor film and the gate insulating film. [Effects of the Invention]

[0018] According to one embodiment of the present invention, fluctuation in electrical characteristics of a transistor including an oxide semiconductor film can be suppressed. Furthermore, the reliability can be improved. According to one embodiment of the present invention, a semiconductor device in which the force is reduced can be provided. It is possible to provide a new semiconductor device. However, it is not necessary for one embodiment of the present invention to have all of these effects. It is not necessary for the invention to have any other effects than those mentioned above. It is obvious that there are other effects than these from the description, drawings, claims, etc. It is possible to extract the results. [Brief explanation of the drawings]

[0019] [Figure 1] 1A to 1C illustrate one embodiment of a transistor. [Figure 2] FIG. 10 is a graph showing absolute values ​​of the amount of change in threshold voltage of a transistor after a BT stress test. [Figure 3] 1A to 1C illustrate one embodiment of a method for manufacturing a transistor. [Figure 4] 1A to 1C illustrate one embodiment of a transistor. [Figure 5] 1A to 1C illustrate one embodiment of a transistor. [Figure 6] 1A to 1C illustrate one embodiment of a transistor. [Figure 7] 1A to 1C illustrate one embodiment of a transistor. [Figure 8] 1A and 1B are diagrams illustrating band structures of transistors. [Figure 9] 1A to 1C illustrate one embodiment of a transistor. [Figure 10] 1A to 1C illustrate one embodiment of a transistor. [Figure 11] A diagram explaining the relationship between the formation energy and transition level, and the electron configuration of defects. [Figure 12] A diagram explaining the change in the Fermi level and the change in the charge state of defects. [Figure 13] Diagram explaining the crystal model of c-SiO2. [Figure 14] A diagram explaining a model in which NO2 is introduced between the lattices of the c-SiO2 model. [Figure 15] A diagram explaining a model in which N2O is introduced between the lattices of a c-SiO2 model. [Figure 16] A diagram explaining a model in which NO is introduced between the lattices of the c-SiO2 model. [Figure 17] A diagram explaining a model in which N is introduced between the lattices of the c-SiO2 model. [Figure 18]FIG. 1 is a diagram illustrating a band diagram. [Figure 19] FIG. 1 is a diagram illustrating a cluster structure model. [Figure 20] FIG. 1 is a diagram illustrating ESR spectra of NO2 and N—Si—N. [Figure 21] 1A and 1B are diagrams illustrating a mechanism of a phenomenon in which the threshold voltage of a transistor is shifted in the positive direction. [Figure 22] FIG. 1 is a diagram illustrating a bulk model. [Figure 23] A diagram explaining the structure of the model. [Figure 24] 1 is a diagram illustrating the relationship between the formation energy and transition level of VOH, and the thermodynamic transition level of VOH. [Figure 25] FIG. 1 is a diagram illustrating the relationship between carrier density and defect density in VOH. [Figure 26] Band structure showing the DOS inside the oxide semiconductor film and near its interface. [Figure 27] 10A to 10C are diagrams illustrating deterioration in a dark state of a transistor including an oxide semiconductor film. [Figure 28] 10A to 10C are diagrams illustrating deterioration in a dark state of a transistor including an oxide semiconductor film. [Figure 29] 10A and 10B are diagrams illustrating deterioration of a transistor including an oxide semiconductor film under light irradiation. [Figure 30] 10A and 10B are diagrams illustrating deterioration of a transistor including an oxide semiconductor film under light irradiation. [Figure 31] 10A and 10B are diagrams illustrating deterioration of a transistor including an oxide semiconductor film under light irradiation. [Figure 32] 1A and 1B are model diagrams illustrating a highly purified intrinsic oxide semiconductor film. [Figure 33] 1A and 1B are diagrams illustrating an InGaZnO4 crystal model and defects. [Figure 34] FIG. 1 is a diagram illustrating the structure and density of states of a model in which C is placed in the interstitial space (6). [Figure 35] FIG. 1 is a diagram illustrating the structure and density of states of a model in which In is replaced with C. [Figure 36]FIG. 1 is a diagram illustrating the structure and density of states of a model in which Ga is substituted with C. [Figure 37] FIG. 1 is a diagram illustrating the structure and density of states of a model in which Zn is substituted with C. [Figure 38] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 39] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a transistor. [Figure 40] 1A and 1B are cross-sectional views illustrating one embodiment of a transistor. [Figure 41] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 42] 1A to 1C illustrate a structure of a display panel according to an embodiment. [Figure 43] 1A to 1C illustrate one embodiment of a display device. [Figure 44] 1A to 1C illustrate one embodiment of a display device. [Figure 45] FIG. 2 is a diagram illustrating a display module. [Figure 46] 1A to 1C illustrate electronic devices according to an embodiment. [Figure 47] FIG. 1 is a diagram illustrating the results of TDS analysis. [Figure 48] FIG. 1 is a diagram illustrating the results of TDS analysis. [Figure 49] FIG. 1 is a diagram illustrating the results of TDS analysis. [Figure 50] FIG. 1 is a diagram illustrating the results of TDS analysis. [Figure 51] FIG. 1 is a diagram illustrating the results of SIMS analysis. [Figure 52] FIG. 1 is a diagram illustrating the results of TDS analysis. [Figure 53] FIG. 1 is a diagram illustrating the results of TDS analysis. [Figure 54] FIG. 1 is a diagram illustrating the results of SIMS analysis. [Figure 55] FIG. 1 is a diagram illustrating the results of SIMS analysis. [Figure 56] FIG. 1 is a diagram illustrating the ESR measurement results. [Figure 57] FIG. 1 is a diagram illustrating the ESR measurement results. [Figure 58] FIG. 10 is a graph showing Vg-Id characteristics of a transistor. [Figure 59] 10A and 10B are graphs showing the amount of change in the threshold voltage and shift value of a transistor after a gate BT stress test and an optical gate BT stress test. [Figure 60] FIG. 10 is a graph showing Vg-Id characteristics of a transistor. [Figure 61] 10A and 10B are graphs showing the amount of change in the threshold voltage and shift value of a transistor after a gate BT stress test and an optical gate BT stress test. [Figure 62] FIG. 10 is a graph showing the amount of change in spin density and threshold voltage. [Figure 63] 1A and 1B are cross-sectional views illustrating one embodiment of a transistor. [Figure 64] FIG. 10 is a graph showing Vg-Id characteristics of a transistor. [Figure 65] FIG. 10 is a graph showing absolute values ​​of the amount of change in threshold voltage of a transistor after a BT stress test. [Figure 66] FIG. 10 is a graph showing the variation in the threshold voltage of a transistor in a repeated ±BT stress test. [Figure 67] FIG. 1 is a diagram illustrating the results of SIMS analysis. [Figure 68] FIG. 1 is a diagram illustrating the ESR measurement results. [Figure 69] FIG. 1 is a diagram illustrating the results of TDS analysis. [Figure 70] Cross-sectional TEM image and local Fourier transform image of an oxide semiconductor. [Figure 71] 1A and 1B are diagrams showing nanobeam electron diffraction patterns of an oxide semiconductor film and an example of a transmission electron diffraction measurement apparatus; [Figure 72] An example of structural analysis using transmission electron diffraction measurements, and a planar TEM image. [Figure 73] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 74] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 75] 10A and 10B illustrate structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 76] Electron diffraction pattern of CAAC-OS. [Figure 77] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 78] Schematic diagram illustrating the film formation model of CAAC-OS and nc-OS. [Figure 79] A diagram explaining InGaZnO4 crystals and pellets. [Figure 80] Schematic diagram illustrating a film formation model of CAAC-OS. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and the embodiments and methods thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the design and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments and examples. In the embodiments and examples described below, the same parts or parts having similar functions For parts, the same symbols or the same hatch patterns are used in common among different drawings, and the repetition The explanation of repetition will be omitted.

[0021] In each figure described in this specification, the size of each component, the thickness of the film, or the area is The figures may be exaggerated for clarity and are not necessarily limited to that scale. stomach.

[0022] In addition, terms such as first, second, and third used in this specification are used interchangeably to avoid confusion of components. It is not intended to limit the number of items. The terms "second" or "third" can be used interchangeably to explain the present invention.

[0023] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it also includes the case where the angle is between -5° and 5°. "Perpendicular" refers to two straight lines that form an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°.

[0024] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0025] The functions of the "source" and "drain" are also different when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "sauce" and "dressing" are used interchangeably. The terms "in" and "in" may be used interchangeably.

[0026] Voltage refers to the potential difference between two points, and potential refers to the electrostatic field at a certain point. This refers to the electrostatic energy (electrical potential energy) of a unit charge in a particle. However, in general, the potential difference between the potential at a certain point and a reference potential (for example, ground potential) This is simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification, unless otherwise specified, the term "potential" may be read as "voltage." , voltage may be read as potential.

[0027] In addition, since the transistor including the oxide semiconductor film is an n-channel transistor, In this specification, when the gate voltage is 0V, it is considered that no drain current flows. A transistor capable of achieving this is defined as a transistor having normally-off characteristics. A transistor that can be considered to have a drain current flowing when the gate voltage is 0V is defined as a transistor having normally-on characteristics.

[0028] Note that the channel length is, for example, the length of the oxide semiconductor film (or or the part of the oxide semiconductor film through which current flows when the transistor is on) and the gate The source (source region or This refers to the distance between the source electrode and the drain electrode. In one transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of a transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as the length of any one of the regions where the channel is formed. The value may be a maximum, minimum or average value.

[0029] The channel width is, for example, the width of the oxide semiconductor film (or the width of the oxide semiconductor film when the transistor is on). The region where the gate electrode overlaps with the gate electrode (the part of the semiconductor film where current flows), or the channel This refers to the length of the portion where the source and drain face each other in the region where they are formed. In one transistor, the channel width does not necessarily have the same value in all regions. That is, the channel width of a transistor may not be fixed to a single value. Therefore, in this specification, the channel width is defined as the width of any one of the regions where the channel is formed. The value may be a maximum, minimum or average value.

[0030] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width (hereinafter referred to as the apparent channel width) may differ from the actual channel width. In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width shown in the figure becomes larger, and the effect becomes non-negligible. For example, in transistors with a fine and three-dimensional structure, oxide semiconductors The ratio of the channel region formed on the side of the oxide semiconductor film to the channel region formed on the top surface of the film is The channel region may be a larger percentage than shown in the top view. The effective channel width where the channel is actually formed is larger than the channel width on the surface. become.

[0031] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order to deposit the oxide semiconductor film, it is necessary to assume that the shape of the oxide semiconductor film is known. When the shape of the nitride semiconductor film is not precisely known, the effective channel width is precisely measured. It is difficult to do so.

[0032] In this specification, in a top view of a transistor, an oxide semiconductor film and a gate electrode are The apparent length is the length of the portion where the source and drain face each other in the overlapping region. The channel width on the In this specification, it is simply referred to as the channel width. In this case, it may refer to the enclosed channel width or apparent channel width. In this specification, when simply referred to as a channel width, it refers to an effective channel width. In addition, there are the channel length, channel width, effective channel width, apparent channel width, The width of the enclosed channel can be determined by acquiring a cross-sectional TEM image and analyzing the image. The value can be determined by

[0033] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0034] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings. The transistor 10 described in this embodiment is a bottom-gate transistor. It is a pedestrian.

[0035] 1. Transistor structure 1A to 1C are a top view and a cross-sectional view of a transistor 10 included in a semiconductor device. 1A is a top view of a transistor 10, and FIG. 1B is a top view of the transistor 10 shown in FIG. FIG. 1(C) is a cross-sectional view taken along the dashed line AB in FIG. 1(A). In FIG. 1(A), for clarity, the substrate 11, the gate insulating film 15, the protective film 21, etc. are not shown. etc. are omitted.

[0036] The transistor 10 shown in FIGS. 1A to 1C has a gate electrode formed on a substrate 11. The electrode 13, the substrate 11, and the gate insulating film 15 formed on the gate electrode 13; The oxide semiconductor film 17 overlaps the gate electrode 13 via the insulating film 15. The gate insulating film 15 and the oxide semiconductor film 1 A protective film 21 is formed on the electrode 7 and the pair of electrodes 19 and 20 .

[0037] The protective film 21 is formed on the surface of the oxide semiconductor film 17 opposite to the surface that is in contact with the gate insulating film 15. That is, the protective film 21 is in contact with the oxide semiconductor film 17 on the opposite side. On the opposite side of the region where the channel is formed (hereinafter referred to as the back channel region), an oxide A function of protecting the back channel region of the oxide semiconductor film 17 by contacting with the semiconductor film 17. It has.

[0038] In this embodiment, a film in contact with the oxide semiconductor film 17, typically a gate insulating film 1 At least one of the insulating film 5 and the protective film 21 is an oxide insulating film, and the oxide insulating film contains nitrogen. It is characterized by containing a large amount of defects and having a small amount of defects.

[0039] A typical example of an oxide insulating film containing nitrogen and having few defects is a silicon oxynitride film. , aluminum oxynitride film, etc. The film refers to a film whose composition contains more oxygen than nitrogen, and is called a silicon nitride oxide film. The aluminum nitride oxide film is a film whose composition contains more nitrogen than oxygen. vinegar.

[0040] The oxide insulating film containing nitrogen and having few defects is a material that can release nitrogen oxides by heat treatment. (NO x , x is 0 or more and 2 or less, preferably 1 or more and 2 or less), the amount of There are areas and parts where the amount of gas emitted with a mass-to-charge ratio of m / z=17 is large. Typical examples of oxides include nitrogen monoxide, nitrogen dioxide, etc., or oxides containing nitrogen and The oxide insulating film with a small amount of defects is a gas with a mass-to-charge ratio of m / z=30 that is released by heat treatment. The amount of gas with a mass-to-charge ratio of m / z = 17 released by heat treatment is larger than the amount of gas released by heat treatment. Alternatively, the oxide insulating film containing nitrogen and having few defects may be formed by heat treatment. The amount of gas with a mass-to-charge ratio of m / z=46 released by the heat treatment was calculated. It has a region or area where the amount of gas released is large with a mass-to-charge ratio of m / z=17, or it contains nitrogen, The oxide insulating film with a small amount of defects has a mass-to-charge ratio of m / z=30, which is released by heat treatment. The mass released by the heat treatment was calculated from the total amount of gas and gas with a mass-to-charge ratio of m / z = 46. There are regions or portions where a large amount of gas with a charge ratio of m / z=17 is released. The amount of gas released by heat treatment is, for example, 60°C or more when the surface temperature of the film is 50°C or more. The amount released is determined by heat treatment at 50°C or less, preferably 50°C to 550°C.

[0041] In addition, the oxide insulating film containing nitrogen and having few defects has a low mass that is released by heat treatment. The amount of gas released with a charge ratio of m / z=30 is below the detection limit, and the mass released by heat treatment The amount of gas released with a charge ratio of m / z=17 is 1×10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 or an oxide insulating film containing nitrogen and having a small amount of defects. The amount of gas with a mass-to-charge ratio of m / z = 46 released by heat treatment was below the detection limit. The amount of gas with a mass-to-charge ratio of m / z = 17 released by heat treatment is 1 × 10 18 pieces / cm 35x10 or more 19 pieces / cm 3 or containing nitrogen. The oxide insulating film with few defects has a mass-to-charge ratio of m / z=3 The amount of gas released by heat treatment is below the detection limit, and the mass-to-charge ratio m / z=4 The amount of gas released by heat treatment is below the detection limit, and the mass-to-charge ratio m / z=1 The amount of gas released from 7 is 1×10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 Area that is less than or equal to and parts.

[0042] A typical example of a gas with a mass-to-charge ratio of m / z=30 is nitric oxide. Ammonia is a typical example of a gas with a mass-to-charge ratio of m / z=17. A typical example of a gas with z=46 is nitrogen dioxide. One example of a measurement method is thermal desorption spectroscopy (TDS). tion Spectroscopy).

[0043] Here, we will explain how to measure the amount of gas released by TDS analysis. Taking molecule x as an example, we will explain how to measure the amount of molecule x released.

[0044] The amount of gas released during TDS analysis is calculated based on the integral value of the spectrum obtained by the analysis. For this reason, the integral value of the spectrum of the insulating film and the ratio to the reference value of the standard sample are used as an example. The reference value of a standard sample is the value of a sample containing a specific atom. It is the ratio of the atomic density of a material to the integral value of the spectrum.

[0045] For example, the TDS analysis results of a silicon wafer containing hydrogen at a predetermined density as a standard sample, From the results of TDS analysis of the insulating film and the insulating film, the amount of released molecules x (N x ) can be calculated using Equation 1. Here, all the spectra detected by the mass-to-charge ratio obtained by TDS analysis are Assume it comes from molecule x.

[0046]

number

[0047] N H2 is the density converted value of the hydrogen molecules released from the standard sample. H2 is the standard This is the integral value of the spectrum when the sample is subjected to TDS analysis. Here, the reference value of the standard sample is N H2 / S H2 Let's say S x is the integral value of the spectrum obtained when the insulating film is analyzed by TDS. α x (x is the molecular species) is a coefficient that affects the spectral intensity in TDS analysis. For details of Formula 1, see Japanese Patent Application Laid-Open No. 6-275697. The amount of molecules x released from the insulating film was measured using a thermal desorption analyzer manufactured by Denshi Kagaku Co., Ltd. The EMD-WA1000S / W was used, and a standard sample of 9.62 × 10 16 atoms / cm 2 The measurement is performed using a silicon wafer containing hydrogen atoms.

[0048] In addition, in the above formula 1, the amount of released nitrogen monoxide, nitrogen dioxide, or ammonia is T The integral value of the spectrum obtained by DS analysis is S x By substituting , nitric oxide, dioxide The amount of nitrogen or ammonia released can be determined.

[0049] In the TDS analysis, the amount of released gas (nitric oxide) with a mass-to-charge ratio of m / z = 30 was The detection limit is 1 x 10 17 pieces / cm 3 , and an even lower detection limit of 5 × 10 16 pieces / cm 3 , An even lower detection limit is 4 × 10 16 pieces / cm 3 , and an even lower detection limit of 1 × 10 16 pieces / cm 3 is.

[0050] In addition, in the TDS analysis, the amount of released gas (nitrogen dioxide) with a mass-to-charge ratio of m / z = 46 was The detection limit is 1 x 10 17 pieces / cm 3 , and an even lower detection limit of 5 × 10 16 pieces / cm 3 , An even lower detection limit is 4 × 10 16 pieces / cm 3 , and an even lower detection limit of 1 × 10 16 pieces / cm 3 is.

[0051] In addition, in the TDS analysis, the amount of gas (ammonia) released with a mass-to-charge ratio of m / z = 17 was The detection limit is 5 x 10 17 pieces / cm 3 , and an even lower detection limit of 1 × 10 17 pieces / cm 3 in be.

[0052] If the sample contains water, the spectrum obtained by TDS analysis will be It splits into fragments with mass-to-charge ratios of 18, 17, and 16. From the intensity ratio of each mass-to-charge ratio, Fragment pattern coefficients can be calculated for mass-to-charge ratios of 18, 17, and 16. The fragment pattern coefficients are 100, 23, and 1, respectively. That is, the mass-to-charge ratio is 1 In the spectrum of 7, the combined intensity of the released ammonia and water is observed. Therefore, the amount of ammonia released is the amount of gas released with a mass-to-charge ratio of m / z = 17 in TDS analysis. The amount of gas emitted with a mass-to-charge ratio of m / z = 18 is multiplied by 0.23 and then subtracted from the In this specification, the mass-to-charge ratio m / z=17 is the mass excluding the amount of released water. This is explained as the release of only the ammonia that was released.

[0053] In addition, the protective film 21 is formed by heating the substrate 100. By using an oxide insulating film that releases a large amount of ammonia due to heat, The protective film 21 is designed to release a gas having a mass-to-charge ratio of m / z=17 at a rate of 1×10 18 pieces / cm 3 End 5×10 19 pieces / cm 3 By using the following oxide insulating film, During the heat treatment in the reaction formula (A-1) and reaction formula (A-2) occur, and nitrogen oxides are As a result, the nitrogen concentration and nitrogen oxide content of the protective film 21 are In addition, the gate insulating film 15 or the protective film 21 and the oxide semiconductor film It is possible to reduce carrier traps at the interface with 17. It is possible to reduce the fluctuation in the threshold voltage of the transistor included in the This can reduce fluctuations in the electrical characteristics of the capacitor.

[0054] [ka]

[0055] [ka]

[0056] In addition, the oxide insulating film containing nitrogen and having few defects has a thickness of 100 In the spectrum obtained by ESR measurement at K or less, the g value is 2.037 or more and 2.039 a first signal having a g value of 2.001 or more and 2.003 or less, a second signal having a g value of 2.001 or more and 2.003 or less, and A third signal with a value between 1.964 and 1.966 is observed. split width of the second signal and the third signal, The rim width is about 5 mT in the X-band ESR measurement. The first signal is above 2.039 and below, and the second signal is above 2.001 and below 2.003. The spin density of the null and the third signal with g values ​​between 1.964 and 1.966 The total is 1 x 10 18 spins / cm 3 less than 1 × 10 17 spin s / cm 3 More than 1×10 18 spins / cm 3 is less than.

[0057] In addition, the g value in the ESR spectrum below 100K is 2.037 or more and 2.039 or less. The first signal has a g value of 2.001 or more and 2.003 or less, and the second signal has a g value of 1 The third signal, between 0.964 and 1.966, is nitrogen oxide (NO x , x is between 0 and 2 Representative examples of nitrogen oxides include: , nitrogen monoxide, nitrogen dioxide, etc. That is, the first a signal with a g value between 2.001 and 2.003, and a second signal with a g value between 1.9 The smaller the sum of the spin densities of the third signals, which is between 64 and 1.966, the higher the oxidation It can be said that the content of nitrogen oxides contained in the insulating film is small.

[0058] At least one of the gate insulating film 15 and the protective film 21 is formed by SIMS (Second-Hand Electron Microscopy). The nitrogen concentration measured by ion mass spectrometry (IMS) is 6× 10 20 atoms / cm 3 As a result, the gate insulating film 15 and Nitrogen oxides are less likely to be generated in at least one of the gate insulating film and the protective film 21. The carrier traps at the interface between the oxide semiconductor film 17 and the protective film 21 or the film 15 are reduced. In addition, it is possible to reduce the variation in the threshold voltage of a transistor included in a semiconductor device. Therefore, it is possible to reduce the fluctuation of the electrical characteristics of the transistor. .

[0059] The gate insulating film 15 or the protective film 21 is an oxide insulating film containing nitrogen and having a small amount of defects. In the transistor 10 having the above structure, a gate voltage is applied to the gate. Before and after the BT stress test, the test time (hereinafter referred to as stress time) The power approximation line L1 representing the absolute value of the amount of change in threshold voltage (|ΔVth|) is shown in FIG. If the test time (stress time) and the amount of change in threshold voltage are plotted on a graph, The plotted values ​​can be approximated by a power law approximation line, which appears on a log-log graph as The exponent of the power approximation line corresponds to the slope of the line on a log-log graph. Figure 2 is a double logarithmic graph, with the horizontal axis representing the logarithm of the stress time and the vertical axis representing the change in threshold voltage. The logarithm of the absolute value of the amount of movement is also shown. When using a display device with this, the maximum operating temperature is 60°C and the maximum driving voltage is 30V. However, stress conditions can be used for any period of time, for example, 100 hours.

[0060] Here, the measurement method of the gate BT stress test will be explained. First, the substrate temperature is The temperature is kept constant at a certain temperature (hereinafter referred to as stress temperature) and the initial characteristics of the transistor are The Vg-Id characteristics are measured.

[0061] Next, while the substrate temperature is maintained at the stress temperature, the source and drain electrodes of the transistor are A pair of electrodes that function as gate electrodes are set to the same potential, and a different potential is applied to the pair of electrodes. The electrode is subjected to a certain time (hereinafter referred to as stress time). The Vg-Id characteristics of the transistor were measured while maintaining the gate BT switch. The difference in threshold voltage and shift value in the electrical characteristics before and after the stress test is obtained as the amount of variation. It is possible.

[0062] The stress test in which a negative voltage is applied to the gate electrode is called the negative gate BT stress test. A stress test in which a positive voltage is applied is called a dark negative stress test. This is called a BT stress test (dark plus stress). The stress test in which a negative voltage is applied is called the photo-negative gate BT stress test (photo-negative The stress test in which a positive voltage is applied is called the optical positive gate BT stress test. (Photoplusstress).

[0063] In Figure 2, the power approximation line L1 is a straight line on a double logarithmic graph, so the horizontal and vertical axes When the intervals between the graduations are equal, the power approximation line L 1 and the line when there is no change in threshold voltage with respect to stress time, i.e., as shown in Figure 2. The angle θ1 between the power function and the dashed line L2, where the exponent of the power function is 0, is within the range of θ2, and the stress |ΔVth| is less than 0.3 V, preferably less than 0.1 V when the time is 0.1 hours. θ2 is the range enclosed by the dashed line, and is typically set when |ΔVth| is 0.1V. The angle is 20° in the positive direction and 3° in the negative direction from the line at That is, the angle is -3° or more and less than 20°, preferably 0° or more and less than 15°. The same interval means, for example, that the stress time on the horizontal axis is 10 times longer than the normal stress time, from 0.01 hours to 0. .1 hour interval and on the vertical axis, between 0.01V and 0.1V where ΔVth is 10 times The positive direction in θ2 is the counterclockwise direction. It is in the direction.

[0064] As in the transistor 10 of this embodiment, the change in threshold voltage with respect to stress time The angle θ1 between the power approximation line L1, which represents the absolute value of the fluctuation (|ΔVth|), and the dashed line L2 is small. The smaller the transistor, the smaller the fluctuation in threshold voltage due to aging, making it a highly reliable transistor. be.

[0065] In addition, in FIG. 2, if the horizontal axis is x and the vertical axis is y, the power approximation line L1 is expressed by the following formula 2: Here, b and C are constants, and b corresponds to the exponent of the power approximation line L1.

[0066]

number

[0067] The exponent b of the power approximation line L1 of the transistor 10 according to this embodiment is −0.1 or more. and 0.3 or less, preferably 0 or more and 0.2 or less, and the stress time is 0.1 hours. The ΔVth is less than 0.3V, preferably less than 0.1V.

[0068] The smaller the exponent b of the power approximation line L1, the smaller the fluctuation of the threshold voltage due to aging. It is a highly reliable transistor. In addition, ΔVth when the stress time is 0.1 hours is The smaller the value, the higher the reliability of the transistor at the initial stage of operation. The index b of L1 is -0.1 or more and 0.3 or less, preferably 0 or more and 0.2 or less, and When the stress time is 0.1 hours, ΔVth is less than 0.3 V, preferably less than 0.1 V. The transistors are highly reliable.

[0069] At least one of the gate insulating film 15 and the protective film 21 in contact with the oxide semiconductor film 17 is As described above, when the content of nitrogen oxide is low, the gate insulating film 15 or the protective film 21 and the oxide It is possible to reduce carrier traps at the interface with the oxide semiconductor film 17. As a result, it is possible to reduce fluctuations in the threshold voltage of the transistor included in the semiconductor device. As a result, fluctuations in the electrical characteristics of the transistor can be reduced.

[0070] Other configuration details of the transistor 10 are described below.

[0071] There is no particular restriction on the material of the substrate 11, but it should be at least strong enough to withstand the subsequent heat treatment. The substrate 11 must have heat resistance. The type of substrate is not limited to a specific one. Examples of the substrate include a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, and the like. , glass substrate, quartz substrate, plastic substrate, metal substrate, stainless steel substrate, Substrate with steel foil, tungsten substrate, tungsten foil substrates, flexible substrates, laminated films, paper containing fibrous materials, or base films Examples of glass substrates include barium borosilicate glass and aluminoborosilicate glass. Glass or soda lime glass, etc. Flexible substrates, laminated films, base films Examples of films include the following: Polyethylene naphthalate (PET), Polyethersulfone (PE Plastics such as acrylic resins are also examples. Examples include polypropylene, polyester, polyvinyl fluoride, Or polyvinyl chloride, etc. Or, for example, polyester, polyamide, poly Examples include polyethylene imide, aramid, epoxy, inorganic vapor deposition film, and paper. By manufacturing a transistor using a substrate, a single crystal substrate, an SOI substrate, or the like, Small size transistors with little variation in characteristics, size, or shape, high current capacity, When a circuit is constructed using such transistors, This allows for lower power consumption of the circuit or higher integration of the circuit.

[0072] In addition, a flexible substrate is used as the substrate 11, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a release layer may be provided between the substrate 11 and the transistor 10. The delamination is performed by separating the semiconductor device from the substrate 11 after completing a part or all of the semiconductor device thereon. In this case, the transistor 10 is mounted on a substrate with poor heat resistance. The above-mentioned release layer can be formed of, for example, a tungsten film. The laminated structure of inorganic film with silicon oxide film, or organic resin film such as polyimide formed on the substrate The structure and the like can be used.

[0073] An example of a substrate on which a transistor is transferred is a substrate on which the above-mentioned transistor is formed. In addition to the substrates that can be used, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, Lum substrate, stone substrate, wood substrate, fabric substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon) , polyurethane, polyester) or regenerated fiber (acetate, cupra, rayon, These substrates include recycled polyester, leather substrates, and rubber substrates. By using this, it is possible to form transistors with good characteristics and low power consumption. This allows for the manufacture of devices that are less likely to break, more heat resistant, lighter in weight, or thinner.

[0074] An underlying insulating film may be provided between the substrate 11 and the gate electrode 13. Silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, gallium oxide hafnium oxide, yttrium oxide, aluminum oxide, aluminum oxynitride, etc. The insulating base film may be made of silicon nitride, gallium oxide, hafnium oxide, or gallium oxide. By using tritium, aluminum oxide, etc., impurities, typically aluminum, are removed from the substrate 11. The diffusion of potassium metal, water, hydrogen, and the like into the oxide semiconductor film 17 can be suppressed.

[0075] The gate electrode 13 is made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or nickel. A metal element selected from the group consisting of nickel, iron, cobalt, and tungsten, or a metal element containing the above-mentioned metal elements. The metal layer can be formed by using an alloy containing the metal elements or an alloy combining the above-mentioned metal elements. In addition, the present invention uses a metal element selected from one or more of manganese and zirconium. The gate electrode 13 may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of aluminum film containing silicon, a single layer structure of copper film containing manganese, Two-layer structure with titanium film stacked on aluminum film, two-layer structure with titanium film stacked on titanium nitride film Layer structure, two-layer structure with tungsten film laminated on titanium nitride film, tantalum nitride film or nitride film Two-layer structure with tungsten film laminated on tungsten oxide film, copper film on copper film containing manganese A two-layer structure in which a titanium film is laminated, and an aluminum film is laminated on top of the titanium film. A three-layer structure in which a titanium film is formed on top of the copper film containing manganese, and a copper film is laminated on top of the copper film. There are three-layer structures, such as a copper film containing manganese on top. One selected from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium Alternatively, an alloy film made by combining a plurality of layers, or a nitride film may be used.

[0076] The gate electrode 13 is made of indium tin oxide or indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of a light-transmitting conductive material and the above metal element may also be used.

[0077] When the protective film 21 is made of an oxide insulating film containing nitrogen and having a small number of defects, the gate The insulating film 15 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn-based metal oxides The oxide semiconductor film 17 may be formed as a stacked layer or a single layer. In order to improve the gate insulating film 15, at least the region in contact with the oxide semiconductor film 17 is preferably formed of an oxide insulating film.

[0078] The gate insulating film 15 is an insulating film having a blocking effect against oxygen, hydrogen, water, etc. By providing the insulating film 16, oxygen can be diffused from the oxide semiconductor film 17 to the outside, and oxygen can be diffused from the outside to the oxide semiconductor film 17. It is possible to prevent hydrogen, water, etc. from entering the membrane 17. Examples of insulating films having such effects include aluminum oxide films, aluminum oxynitride films, and gallium oxide films. gallium oxide film, yttrium oxide film, yttrium oxide nitride film, hafnium oxide film Examples of suitable oxide films include hafnium oxide nitride films and hafnium oxide nitride films.

[0079] The gate insulating film 15 is made of hafnium silicate (HfSiO x ), nitrogen added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminium Laminate (HfAl xO y N z ), hafnium oxide, yttrium oxide, etc. The use of k-materials can reduce gate leakage of transistors.

[0080] The thickness of the gate insulating film 15 is 5 nm or more and 400 nm or less, and more preferably 10 nm or more. It is preferable to set the thickness to 300 nm or less, and more preferably to set the thickness to 50 nm or more and 250 nm or less.

[0081] The oxide semiconductor film 17 is formed of a metal oxide film containing at least In or Zn, Representative examples include In-Ga oxide films, In-Zn oxide films, and In-M-Zn oxide films (where M is It is formed from Al, Ga, Y, Zr, La, Ce, or Nd).

[0082] When the oxide semiconductor film 17 is an In-M-Zn oxide, the sum of In and M is 1 When the atomic ratio of In and M is 0.00 atomic %, the atomic ratio of In is preferably 25 atomic %. ic% or more, M is less than 75 atomic %, and more preferably In is 34 atomic % or more. c% or more and M is less than 66 atomic%.

[0083] The oxide semiconductor film 17 has an energy gap of 2 eV or more, preferably 2.5 eV or more. More preferably, it is 3 eV or more. By using such a material, the off-state current of the transistor 10 can be reduced.

[0084] The thickness of the oxide semiconductor film 17 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 10 0 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0085] The oxide semiconductor film 17 is an In-M-Zn oxide (M is Al, Ga, Y, Zr, La, Ce). In the case of In-Mn-Zn oxide, the sputtering temperature is The atomic ratio of the metal elements in the target preferably satisfies In≧M and Zn≧M. The atomic ratio of the metal elements in such a sputtering target is In:M:Zn=1:1: 1, In:M:Zn=1:1:1.2, and In:M:Zn=3:1:2 are preferred. The atomic ratio of the oxide semiconductor film 17 to be formed is determined by the above sputtering method as an error. This includes a ±40% variation in the atomic ratio of metal elements contained in the target.

[0086] The hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water. Oxygen vacancies are formed in the lattice from which oxygen is desorbed (or in the portion from which oxygen is desorbed). When hydrogen enters the gap, electrons, which act as carriers, are generated. When bonded to oxygen, which bonds to metal atoms, electrons, which act as carriers, may be generated. Therefore, a transistor using an oxide semiconductor containing hydrogen has normally-on characteristics. It is easy to become.

[0087] Therefore, in the oxide semiconductor film 17, oxygen vacancies and hydrogen are reduced as much as possible. Specifically, the oxide semiconductor film 17 is preferably IMS (Secondary Ion Mass Spectrometry) The hydrogen concentration is 2×10 20 atoms / cm 3 Less than or equal to 5 x 10 19 at oms / cm 3 Less than 1 × 10 19 atoms / cm 3 Below 5x, preferably 1018 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Below, More preferably 5 x 10 17 atoms / cm 3 or less, more preferably 1 × 10 16 at oms / cm 3 As a result, the threshold voltage of the transistor 10 becomes positive. The device has electrical characteristics (also called normally-off characteristics).

[0088] In addition, the oxide semiconductor film 17 contains silicon or carbon, which is one of the group 14 elements. If the oxide semiconductor film 17 is exposed to the oxygen vacancies, the oxide semiconductor film 17 becomes n-type. The concentrations of silicon and carbon in the oxide semiconductor film 17 (obtained by secondary ion mass spectrometry) concentration) is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 As a result, the transistor 10 is electrically connected to the transistor 10 so that the threshold voltage is positive. It has a characteristic (also called a normally-off characteristic).

[0089] In addition, in the oxide semiconductor film 17, alkali metals obtained by secondary ion mass spectrometry The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 Alkali metals and alkaline earth metals are When bonded to a carbide semiconductor, carriers may be generated, increasing the off-state current of the transistor. For this reason, the alkali metal or alkaline earth metal in the oxide semiconductor film 17 may It is preferable to reduce the concentration of metalloids. As a result, the threshold voltage of transistor 10 is It has electrical characteristics in which the load is positive (also called normally-off characteristics).

[0090] Furthermore, when nitrogen is contained in the oxide semiconductor film 17, electrons serving as carriers are generated. As a result, the nitride semiconductor containing nitrogen is used. Therefore, the transistor having the oxide semiconductor film tends to be normally on. Therefore, it is preferable that nitrogen is reduced as much as possible. For example, in secondary ion mass spectrometry, The resulting nitrogen concentration is 5 x 10 18 atoms / cm 3 It is preferable to do the following:

[0091] By reducing impurities in the oxide semiconductor film 17, the carrier density of the oxide semiconductor film is reduced. Therefore, the oxide semiconductor film 17 can have a carrier density of 1×10 17 pieces / cm 3 Less than 1 × 10 15 pieces / cm 3 or less, more preferably 1 × 10 13 pieces / cm 3 Less than 1×10, more preferably 11 pieces / cm 3 It is preferable that:

[0092] The oxide semiconductor film 17 is an oxide semiconductor film having a low impurity concentration and a low density of defect states. By using this, a transistor with even better electrical characteristics can be manufactured. Here, the low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or substantially high purity intrinsic. Transistors using conductors have fewer carrier sources, so it is possible to reduce the carrier density. Therefore, when a transistor in which a channel region is formed in the oxide semiconductor film is used, The transistor has electrical characteristics in which the threshold voltage is positive (also called normally-off characteristics). In addition, a transistor using a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film can be easily fabricated. Since the transistor has a low defect level density, the trap level density may also be low. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has an extremely small off-state current. When the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, The off-state current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×10 -13 Therefore, a channel region is formed in the oxide semiconductor film. The transistors that are produced will have little fluctuation in electrical characteristics and will be highly reliable. There is a match.

[0093] The oxide semiconductor film 17 may have a non-single crystal structure, for example. , CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline structure, microcrystalline structure (described below), or Among non-single crystal structures, the amorphous structure has the highest defect level density and CA AC-OS has the lowest defect level density.

[0094] Note that the oxide semiconductor film 17 has an amorphous structure region, a microcrystalline structure region, and a polycrystalline structure region. The film may be a mixed film having two or more of the following: a CAAC-OS region, a single crystal structure region, and a single crystal structure region. The mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAA region, or the like. In the case of a single-layer structure having two or more regions, either a C-OS region or a single-crystal structure region, The mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, and a polycrystalline structure region. The layer structure has two or more types of regions, namely, a CAAC-OS region, a single crystal structure region, and a This may occur.

[0095] The pair of electrodes 19 and 20 are made of aluminum, titanium, chromium, nickel, copper, yttrium, from aluminum, zirconium, molybdenum, iron, cobalt, silver, tantalum, or tungsten The metal or an alloy containing the metal as a main component is used as a single layer structure or a laminated structure. For example, a single layer structure of an aluminum film containing silicon, a single layer structure of a copper film containing manganese, Two-layer structure with aluminum film stacked on tungsten film, and aluminum film stacked on tungsten film a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film; Two-layer structure in which a copper film is laminated on a titanium film, two-layer structure in which a copper film is laminated on a tungsten film, Two-layer structure in which a copper film is laminated on a copper film containing an electron gun, a titanium film or titanium nitride film and its titanium An aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and then Three-layer structure in which a titanium film or titanium nitride film is formed on the surface, a molybdenum film or molybdenum nitride film A film and an aluminum film or a copper film are formed on the molybdenum film or the molybdenum nitride film. A three-layer structure in which a molybdenum film or molybdenum nitride film is formed on top of the laminated film. A copper film is laminated on a copper film containing manganese, and a copper film containing manganese is formed on top of that. In addition, transparent conductive materials containing indium oxide, tin oxide, or zinc oxide are used. Good too.

[0096] In this embodiment, the pair of electrodes 19 and 20 are formed on the oxide semiconductor film 17 and the protective film 21. However, it may be provided between the gate insulating film 15 and the oxide semiconductor film 17 .

[0097] When the gate insulating film 15 is formed of an oxide insulating film containing nitrogen and having few defects: The protective film 21 is made of silicon oxide, silicon oxynitride, Ga—Zn-based metal oxide, or the like. It can be formed using

[0098] In addition, an insulating film having a blocking effect against oxygen, hydrogen, water, etc. is provided as the protective film 21. This allows oxygen to diffuse from the oxide semiconductor film 17 to the outside and oxygen to diffuse from the outside to the oxide semiconductor film 1 It can prevent hydrogen, water, etc. from entering the 7. It has a blocking effect against oxygen, hydrogen, water, etc. Examples of the insulating film include an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, Gallium oxide nitride film, yttrium oxide film, yttrium oxide nitride film, hafnium oxide film , hafnium oxynitride film, silicon nitride film, etc.

[0099] The protective film 21 has a thickness of 50 nm to 1000 nm, preferably 150 nm to 40 It is sufficient to have a region of 0 nm or less.

[0100] 2. Transistor manufacturing method Next, a manufacturing method of the transistor 10 shown in FIG. 1 will be described with reference to FIG. 3, a cross-sectional view in the channel length direction indicated by the dashed line AB in FIG. 1(A) and a cross-sectional view in the channel length direction indicated by the dashed line AB in FIG. A method for fabricating a transistor 10 will be described using a cross-sectional view in the channel width direction indicated by the dashed line CD. do.

[0101] Films constituting the transistor 10 (insulating film, oxide semiconductor film, metal oxide film, conductive film, etc.) The methods include sputtering, chemical vapor deposition (CVD), vacuum evaporation, and pulsed laser deposition ( Alternatively, it can be formed by a coating method or a printing method. The film formation methods include sputtering and plasma enhanced chemical vapor deposition (PECVD). is a typical example, but thermal CVD may also be used. An example of thermal CVD is MOCVD (Metal Oxide Chemical Vapor Deposition). l Organic Chemical Vapor Deposition:Organic Metal Chemical vapor deposition (CVD) and atomic layer deposition (ALD) may also be used.

[0102] In the thermal CVD method, the pressure in the chamber is atmospheric or reduced, and the source gas and oxidant are simultaneously mixed. The reaction is carried out in the chamber near or on the substrate, where it is deposited on the substrate to form a film. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that defects are not generated due to damage.

[0103] In addition, in the ALD method, the pressure inside the chamber is atmospheric or reduced, and the source gas for the reaction is The gases are introduced into the chamber in sequence, and the film is formed by repeating this gas introduction sequence. By switching between the switching valves (also called high-speed valves), two or more types of raw materials can be mixed. The gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the source gases. At the same time as or after the second gas, an inert gas (argon, nitrogen, etc.) is introduced. If an inert gas is introduced at the same time, the inert gas acts as a carrier gas. In addition, an inert gas may be introduced at the same time as the second source gas is introduced. In addition, instead of introducing an inert gas, the first source gas is discharged by vacuum evacuation, and then the second source gas is introduced. The first source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first monoatomic layer. The second monolayer is formed by reacting with the second source gas introduced later. A thin film is formed by laminating it on top.

[0104] This gas introduction sequence is repeated multiple times while controlling it until the desired thickness is achieved. The thickness of the thin film increases depending on the number of times the gas introduction sequence is repeated. Therefore, precise film thickness control is possible, and fine transistors can be fabricated. It is suitable for manufacturing.

[0105] As shown in FIG. 3(A), a gate electrode 13 is formed on a substrate 11.

[0106] The gate electrode 13 is formed by the following methods. First, sputtering, vacuum deposition, A conductive film is formed by pulsed laser deposition (PLD) or thermal CVD, and then a photoresist is applied to the conductive film. A mask is formed by a lithography process. Next, a part of the conductive film is etched using the mask. Etching is performed to form the gate electrode 13. After this, the mask is removed.

[0107] The gate electrode 13 may be formed by electrolytic plating, printing, inkjet printing, or the like instead of the above-mentioned method. It may also be formed by a jet method or the like.

[0108] In addition, a tungsten film can be formed as a conductive film using a film formation device that uses ALD. In this case, WF6 gas and B2H6 gas are introduced repeatedly in sequence to obtain the initial tungsten content. A tungsten film is formed, and then WF6 gas and H2 gas are introduced simultaneously to form a tungsten film. It should be noted that SiH4 gas may be used instead of B2H6 gas.

[0109] Here, a tungsten film having a thickness of 100 nm is formed by sputtering. A mask is formed by a photolithography process, and a tungsten film is formed using the mask. The gate electrode 13 is formed by dry etching.

[0110] Next, a gate insulating film 15 is formed on the substrate 11 and the gate electrode 13. An oxide semiconductor film 17 is formed on the gate electrode 13 in a region overlapping the gate electrode 13 .

[0111] The gate insulating film 15 can be formed by sputtering, CVD, vacuum deposition, pulsed laser deposition, or the like. It is formed by the PLD method, thermal CVD method, etc.

[0112] When a silicon oxide film or a silicon oxynitride film is formed as the gate insulating film 15, As the source gas, it is preferable to use a deposition gas containing silicon and an oxidizing gas. Representative examples of silicon-containing deposition gases include silane, disilane, trisilane, and fluorosilane. Oxidizing gases include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

[0113] When a gallium oxide film is formed as the gate insulating film 15, the MOCVD method is used. It can be formed.

[0114] The gate insulating film 15 is formed by a thermal CVD method such as MOCVD or ALD. To form a hafnium oxide film, a liquid containing a solvent and a hafnium precursor compound (haf Hafnium alkoxide solution, typically tetrakisdimethylamidohafnium (TDMAH Two types of gases are used: the source gas, which is vaporized ozone (O3), as an oxidizing agent. The chemical formula for tetrakisdimethylamidohafnium is Hf[N(CH3)2]4. Other liquid materials include tetrakis(ethylmethylamido)hafnium.

[0115] The gate insulating film 15 is formed by a thermal CVD method such as MOCVD or ALD. When forming an aluminum oxide film, a liquid containing a solvent and an aluminum precursor compound ( The raw material gas is vaporized trimethylaluminum (TMA, etc.) and 2H2O as an oxidizer. The chemical formula for trimethylaluminum is Al(CH3)3. Other liquid materials include tris(dimethylamido)aluminum and triisobutyl Aluminum, Aluminum tris(2,2,6,6-tetramethyl-3,5-heptane) Gionato), etc.

[0116] The gate insulating film 15 is formed by a thermal CVD method such as MOCVD or ALD. When forming a silicon oxide film, hexachlorodisilane is adsorbed onto the surface to be formed. It removes chlorine from the substance and supplies radicals of oxidizing gases (O2, nitrous oxide) for absorption. React with the kimono.

[0117] Here, a silicon oxynitride film is formed as the gate insulating film 15 by the plasma CVD method. Complete.

[0118] A method for forming the oxide semiconductor film 17 will be described below. Tarring method, coating method, pulsed laser deposition method, laser ablation method, thermal CVD method, etc. Next, an oxide semiconductor film is formed on the oxide semiconductor film by a photolithography process. After forming a mask, part of the oxide semiconductor film is etched using the mask. 3B, the gate insulating film 15 is formed on the surface of the gate electrode 13. The oxide semiconductor film 17 is formed so as to separate elements, and then the mask is removed.

[0119] In addition, by using a printing method for the oxide semiconductor film 17, the oxide semiconductor The membrane 17 can be formed directly.

[0120] When an oxide semiconductor film is formed by a sputtering method, a power source for generating plasma is used. The device may be an RF power supply device, an AC power supply device, a DC power supply device, or the like.

[0121] The sputtering gas is a rare gas (typically argon), oxygen gas, or a rare gas and oxygen gas. In the case of a mixture of rare gas and oxygen gas, the rare gas It is preferable to increase the gas ratio of oxygen.

[0122] The target may be appropriately selected depending on the composition of the oxide semiconductor film to be formed. .

[0123] Note that when the oxide semiconductor film is formed by, for example, a sputtering method, The temperature is 150°C or higher and 750°C or lower, preferably 150°C or higher and 450°C or lower, and more preferably The oxide semiconductor film is formed at a temperature of 200°C or higher and 350°C or lower. S film can be formed.

[0124] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0125] By suppressing the inclusion of impurities during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas at a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0126] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition can be reduced. The oxygen ratio in the film forming gas is 30% by volume or more, preferably 100% by volume or more. Expressed as volume %.

[0127] An example of a sputtering target is an In-Ga-Zn metal oxide target. The following is a summary of the above.

[0128] After the oxide semiconductor film is formed, heat treatment is performed to dehydrogenate or The temperature of the heat treatment is typically 150° C. or higher and lower than the substrate distortion point. Preferably, the temperature is 250°C or higher and 450°C or lower, and more preferably, 300°C or higher and 450°C or lower. .

[0129] Heat treatment is carried out using rare gases such as helium, neon, argon, xenon, krypton, or It is carried out in an inert gas atmosphere containing nitrogen, or after heating in an inert gas atmosphere, it is heated in an oxygen atmosphere. It should be noted that the inert atmosphere and oxygen atmosphere do not contain hydrogen, water, etc. The treatment time is preferably from 3 minutes to 24 hours.

[0130] The heat treatment can be carried out using an electric furnace, an RTA device, or the like. Therefore, heat treatment can be performed at a temperature above the strain point of the substrate for a short period of time. The processing time can be reduced.

[0131] The oxide semiconductor film is formed while being heated, and after the oxide semiconductor film is formed, By performing heat treatment, the hydrogen concentration in the oxide semiconductor film is increased to 5×10 19 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than or equal to 5 x 10 1 8 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 The following is preferably is 5 x 10 17 atoms / cm 3 Less than 1 × 10 16 atoms / cm 3 Below It can be below.

[0132] Oxide semiconductor films, such as InGaZnO, are formed using a deposition system that uses ALD. X (X>0) When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form InO Then, Ga(CH3)3 gas and O3 gas are introduced simultaneously to form a GaO layer. Then, Zn(CH3)2 and O3 gases are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. Also, by mixing these gases, the InGaO2 layer and mixed compound layers such as InZnO2 layer, GaInO layer, ZnInO layer, and GaZnO layer. It is also possible to use H2O gas bubbled with an inert gas such as Ar instead of O3 gas. However, it is preferable to use O3 gas that does not contain H. In(CH3) In place of the gas In(C2H5)3, gas Ga(CH3)3 may be used. Alternatively, Ga(C2H5)3 gas may be used. That's fine.

[0133] Here, a 35-nm-thick oxide semiconductor film is formed by a sputtering method. A mask is formed over the oxide semiconductor film, and part of the oxide semiconductor film is selectively etched. Next, after removing the mask, a heat treatment is performed in a mixed gas atmosphere containing nitrogen and oxygen. Then, the oxide semiconductor film 17 is formed.

[0134] The heat treatment is carried out at a temperature higher than 350°C and lower than 650°C, preferably higher than 450°C and lower than 600°C. By carrying out the following, the CAAC conversion rate described below is 70% or more but less than 100%, preferably 80% % or more and less than 100%, preferably 90% or more and less than 100%, more preferably 95% or more and less than 90%. In addition, the oxide semiconductor film can be obtained with a hydrogen content of 8% or less. That is, it is possible to obtain an oxide semiconductor film having a low impurity concentration and a low defect level density. An oxide semiconductor film with a low conductivity can be formed.

[0135] Next, as shown in FIG. 3(C), a pair of electrodes 19 and 20 are formed.

[0136] The method for forming the pair of electrodes 19 and 20 will be described below. First, sputtering and vacuum evaporation are used. A conductive film is formed by deposition, pulsed laser deposition (PLD), thermal CVD, etc. A mask is formed on the conductive film by a photolithography process. The film is etched to form a pair of electrodes 19 and 20. After this, the mask is removed.

[0137] Here, a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a A titanium film having a thickness of 100 nm is then laminated on the titanium film by sputtering. A mask is formed by a photolithography process, and a tungsten film and an aluminum film are formed using the mask. The aluminum film and the titanium film are dry etched to form a pair of electrodes 19 and 20 .

[0138] After the pair of electrodes 19 and 20 are formed, heat treatment may be performed. The heat treatment can be performed under the same conditions as those of the heat treatment performed after the formation of the oxide semiconductor film 17. can.

[0139] After forming the pair of electrodes 19 and 20, a cleaning process is performed to remove etching residues. By carrying out this cleaning process, it is possible to prevent a short circuit between the pair of electrodes 19 and 20. The cleaning process can be carried out using TMAH (Tetramethylammonium hydroxide). Alkaline solutions such as (m Hydroxide) solutions, hydrofluoric acid, oxalic acid, phosphoric acid, etc. This can be done using an acidic solution of 1000 ppm or water.

[0140] Next, a protective film 21 is formed on the oxide semiconductor film 17 and the pair of electrodes 19 and 20. The film 21 can be formed by a sputtering method, a CVD method, a vapor deposition method, or the like.

[0141] When forming an oxide insulating film containing nitrogen and having few defects as the protective film 21, the nitrogen As an example of an oxide insulating film containing silicon and having few defects, a silicon oxynitride film is prepared by CVD. In this case, the source gas is a deposition gas containing silicon. It is preferable to use a gas containing silicon and an oxidizing gas. Examples of oxidizing gases include silane, disilane, trisilane, and fluorinated silane. Examples include dinitrogen chloride and nitrogen dioxide.

[0142] The oxidizing gas is more than 20 times but less than 100 times, preferably 4 times, the deposition gas. The pressure in the processing chamber is set to less than 100 Pa, preferably 50 Pa or less. By using a CVD method that includes nitrogen, an oxide insulating film with few defects can be formed. It is possible.

[0143] Here, the temperature at which the substrate 11 is maintained is 220° C., and the flow rate of silane and The source gas was nitrous oxide at a rate of 2000 sccm, and the pressure in the processing chamber was 20 Pa. The high frequency power supplied to the horizontal plate electrodes was 13.56MHz and 100W (power density 1. 6×10 -2 W / cm 2 ) to form a silicon oxynitride film using the plasma CVD method. do.

[0144] In addition, when an oxide insulating film containing nitrogen and having a small number of defects is formed as the protective film 21, In this case, ammonia is used as a source gas in addition to a silicon-containing deposition gas and an oxidizing gas. As a result, the emission of a gas with a mass-to-charge ratio of m / z=17 (typically ammonia) A film having areas of high outflow can be formed.

[0145] For example, the substrate 11 is maintained at a temperature of 220° C., and the flow rate of silane is 30 sccm, and the flow rate of 4 The raw material gases were nitrous oxide at a flow rate of 1000 sccm and ammonia at a flow rate of 100 sccm. The pressure in the processing chamber was set to 40 Pa, and the high frequency power supplied to the parallel plate electrodes was set to 13.56 MHz. , 150W (power density is 2.4 x 10 -2 W / cm 2 ) plasma CVD method A silicon oxynitride film is formed using the silicon oxynitride film.

[0146] Next, a heat treatment may be performed. The temperature of the heat treatment is typically 150° C. or higher. Less than the strain point, preferably 200°C or more and 450°C or less, more preferably 300°C or more and 450°C or less The heat treatment is performed at a temperature of 0.1° C. or less. The heat treatment is performed to release water, hydrogen, etc. contained in the protective film 21. is possible.

[0147] Here, heat treatment is performed at 350°C for 1 hour in a mixed gas atmosphere containing nitrogen and oxygen. .

[0148] Next, a heat treatment may be performed. The temperature of the heat treatment is typically 150° C. or higher. Less than the strain point, preferably 200°C or more and 450°C or less, more preferably 300°C or more and 450°C or less ℃ or less.

[0149] Through the above steps, a transistor with reduced fluctuation in threshold voltage can be manufactured. Furthermore, a transistor with reduced fluctuation in electrical characteristics can be manufactured.

[0150] <Variation 1> A modification of the transistor 10 in this embodiment will be described with reference to FIG. The transistors explained in the examples have a gate insulating film or a protective film with a stacked structure. explain.

[0151] In a transistor using an oxide semiconductor film, oxygen vacancies in the oxide semiconductor film This leads to poor electrical characteristics of the transistor. The threshold voltage of a transistor using a compound semiconductor film tends to fluctuate in the negative direction. This is because the charge is generated due to the oxygen vacancy contained in the oxide semiconductor. This is because a low resistance occurs.

[0152] Furthermore, if oxygen vacancies are contained in the oxide semiconductor film, deterioration over time and bias temperature stress tests (hereinafter referred to as BT (Bias-Temperature) stress test) The problem of increased fluctuation in the electrical characteristics of transistors, typically the threshold voltage There is.

[0153] Therefore, as part of the protective film, more oxygen than the oxygen required for the stoichiometric composition is contained. By providing an oxide insulating film, the negative shift of the threshold voltage is suppressed, resulting in excellent electrical characteristics. It is also possible to fabricate transistors with excellent properties, such as aging and optical gate BT stress. This makes it possible to fabricate highly reliable transistors with minimal fluctuations in electrical characteristics due to thermal testing. do.

[0154] The transistor 10a shown in FIG. 4A is characterized in that the protective film 21 has a multi-layer structure. Specifically, the protective film 21 contains more oxygen than the oxide insulating film 23, which satisfies the stoichiometric composition. The oxide insulating film 25 containing a large amount of oxygen and the nitride insulating film 27 are included. The oxide insulating film 23 in contact with the gate insulating film 15 of the transistor 10 and the protective film 21 is It is an oxide insulating film containing nitrogen and having few defects that can be used for at least one of the insulating films. It is characterized by the following.

[0155] The oxide insulating film 25 is an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. The oxide insulating film contains more oxygen than the oxygen that satisfies the stoichiometric composition. When heated, some of the oxygen is released. The oxide insulating film containing oxygen is analyzed by TDS (thermal desorption spectroscopy) and the oxygen content is converted to oxygen atoms. The amount of desorption is 1.0×10 18 atoms / cm 3 or more, preferably 3.0 × 10 20 at oms / cm 3 The oxide insulating film is as described above. The surface temperature ranges from 100°C to 700°C or from 100°C to 500°C. preferable.

[0156] The oxide insulating film 25 has a thickness of 30 nm to 500 nm, preferably 50 nm. Silicon oxide, silicon oxynitride, etc., having a thickness of 400 nm or more can be used.

[0157] The oxide insulating film 25 is made of a silicon dioxide film placed in a vacuum-evacuated processing chamber of a plasma CVD apparatus. The substrate is kept at 180°C or higher and 280°C or lower, more preferably 200°C or higher and 240°C or lower. The raw material gas is introduced into the processing chamber to set the pressure in the processing chamber at 100 Pa or more and 250 Pa or less. , more preferably 100 Pa or more and 200 Pa or less, and .17W / cm 2 More than 0.5W / cm 2 or less, more preferably 0.25 W / cm 2 End 0.35W / cm 2 Under the following conditions of high frequency power supply, silicon oxide film or oxide A silicon nitride film is formed.

[0158] As a source gas for the oxide insulating film 25, a deposition gas containing silicon and an oxidizing gas are used. Representative examples of silicon-containing deposition gases include silane, disilane, Examples of oxidizing gases include trisilane, fluorinated silane, etc. Examples of oxidizing gases include oxygen, ozone, and nitrous oxide. , nitrogen dioxide, etc.

[0159] The oxide insulating film 25 is formed under the conditions of high frequency and high power density in a processing chamber under the above pressure. By supplying wave power, the decomposition efficiency of the source gas in the plasma increases, and oxygen radicals increase. As the oxidation of the source gas progresses, the oxygen content in the oxide insulating film 25 becomes stoichiometric. On the other hand, in the film formed at the substrate temperature, the silicon and oxygen Because the bonding strength is weak, some of the oxygen in the film is released by the heat treatment in the subsequent process. , which contains more oxygen than the stoichiometric composition, and some of the oxygen is released by heating. In addition, the oxide insulating film 2 can be formed on the oxide semiconductor film 17. Therefore, in the process of forming the oxide insulating film 25, the oxide insulating film 2 3 serves as a protective film for the oxide semiconductor film 17. As a result, damage to the oxide semiconductor film 17 is prevented. Therefore, the oxide insulating film 25 can be formed using high frequency power with high power density while reducing the In a later heat treatment step, part of the oxygen contained in the oxide insulating film 25 can be converted to oxygen. The amount of oxygen vacancies in the oxide semiconductor film 17 is further reduced. It is possible.

[0160] The nitride insulating film 27 is made of a film having at least a blocking effect against hydrogen and oxygen. Furthermore, it is preferable to use a blocker such as oxygen, hydrogen, water, alkali metal, alkaline earth metal, etc. By providing the nitride insulating film 27, oxygen from the oxide semiconductor film 17 is prevented from The diffusion of hydrogen, water, etc. to the outside and the penetration of hydrogen, water, etc. into the oxide semiconductor film 17 from the outside can be prevented. do.

[0161] The nitride insulating film 27 has a thickness of 50 nm to 300 nm, preferably 100 nm. Silicon nitride, silicon oxynitride, aluminum nitride, and oxynitride Examples include aluminum oxide.

[0162] Instead of the nitride insulating film 27, an oxide film having a blocking effect against oxygen, hydrogen, water, etc. may be used. An oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like may be provided. Examples include aluminum oxide, aluminum oxynitride, gallium oxide, and gallium oxynitride. , yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. be.

[0163] The nitride insulating film 27 can be formed by using a sputtering method, a CVD method, or the like.

[0164] When a silicon nitride film is formed as the nitride insulating film 27 by the plasma CVD method, the silicon The deposition gas containing carbon, nitrogen, and ammonia are used as the source gas. By using a small amount of ammonia compared to nitrogen, ammonia dissociates in the plasma, The active species react with silicon and water contained in the silicon-containing deposition gas. This breaks the silicon bond and the nitrogen triple bond, promoting the bonding of silicon and nitrogen. This results in fewer bonds between silicon and hydrogen, fewer defects, and a dense silicon nitride film. On the other hand, if the amount of ammonia relative to nitrogen in the source gas is large, silicon The decomposition of the deposition gas containing silicon and nitrogen does not proceed, and silicon and hydrogen bonds remain. As a result, the number of defects increases and a rough silicon nitride film is formed. In the raw material gas, the flow rate ratio of nitrogen to ammonia is 5 to 50, preferably 10 It is preferable to set it to 50 or less.

[0165] In the transistor 10b shown in FIG. 4B, the gate insulating film 15 is made of a nitride insulating film 29 and The oxide insulating film 31 containing nitrogen is stacked, and the oxide insulating film 31 is in contact with the oxide semiconductor film 17. The film 31 is characterized by being an oxide insulating film containing nitrogen and having a small amount of defects.

[0166] The nitride insulating film 29 may be a film having a blocking effect against water, hydrogen, etc. Alternatively, it is preferable to use a film with a small amount of defects as the nitride insulating film 29. Representative examples of the nitride insulating film 29 include silicon nitride, silicon nitride oxide, and aluminum nitride. Examples include aluminum and aluminum oxide nitride.

[0167] By using a silicon nitride film as the nitride insulating film 29, the following effects can be obtained. Silicon nitride film has a higher relative dielectric constant than silicon oxide film, and can achieve the same capacitance. Since the thickness required to obtain this is large, the gate insulating film 15 can be physically made thicker. Therefore, the decrease in the dielectric strength voltage of the transistor 10b is suppressed, and the dielectric strength voltage is improved. This makes it possible to suppress electrostatic breakdown of the semiconductor device.

[0168] In a transistor using an oxide semiconductor film, a trap level (interface When a transistor has a high-voltage level, the electrical characteristics of the transistor change, typically the threshold voltage. This causes variations in the electrical characteristics of each transistor. Therefore, by using a silicon nitride film with a small number of defects as the nitride insulating film 29, the threshold This can reduce fluctuations in the voltage and variations in the electrical characteristics of the transistors.

[0169] The nitride insulating film 29 may be formed in a laminated structure. For example, a first silicon nitride film As a result, a silicon nitride film having a small amount of defects is formed, and hydrogen molecules are released onto the first silicon nitride film. By providing a second silicon nitride film with a low amount of ammonia molecules and a low amount of ammonia molecules released, As a result, the gate insulating film 15 has a small number of defects and is resistant to the release of hydrogen molecules and ammonia molecules. As a result, the gate insulating film 15 can be formed with a small amount of outflow. This can prevent the hydrogen and nitrogen from transferring to the oxide semiconductor film 17.

[0170] Such a nitride insulating film 29 is formed by stacking silicon nitride films using a two-stage forming method. First, a mixed gas of silane, nitrogen, and ammonia is mixed with a raw material gas. A first silicon nitride film with a small amount of defects was formed by plasma CVD using the silicon nitride film as a source. By using the flow rate ratio of the source gases as in the nitride insulating film 27 described above, hydrogen molecules A silicon nitride film with a low emission rate and ammonia molecule emission rate is used as the second silicon nitride film. It can be formed.

[0171] <Variation 2> A modification of the transistor 10 described in this embodiment will be described with reference to FIG. The transistor 10 shown in the embodiment is a channel-etched transistor. The transistor 10c described as an example is a channel protection type transistor.

[0172] The transistor 10c shown in FIG. 5A includes a gate electrode 13 provided over a substrate 11; A gate insulating film 15 is formed on the substrate 11 and the gate electrode 13, and a gate insulating film 15 is formed on the gate electrode 13. The oxide semiconductor film 17 overlapping the gate electrode 13, the gate insulating film 15 and the oxide semiconductor film 17 overlapping the gate electrode 13, and the gate insulating film 15 and the oxide semiconductor film 17 overlapping the gate electrode 13 are formed. The insulating film 33 on the oxide semiconductor film 17 and the insulating film 33 are in contact with the oxide semiconductor film 17 at the openings. It has a pair of electrodes 19 and 20.

[0173] Note that the transistor 10d illustrated in FIG. 5B has an insulating film formed over the oxide semiconductor film 17. an insulating film 35 and a pair of electrodes having ends formed in the insulating film 35 and in contact with the oxide semiconductor film 17; 19, 20.

[0174] In the transistors 10c and 10d, when the pair of electrodes 19 and 20 are formed, an oxide semiconductor film A part of 17, typically the back channel region, is covered with insulating films 33 and 35. By etching to form the pair of electrodes 19 and 20, the back channel of the oxide semiconductor film 17 is formed. Furthermore, the insulating films 33 and 35 are formed by using a method in which the insulating films 33 and 35 have nitrogen and a low defect amount. By using a low oxide insulating film, fluctuations in electrical characteristics are suppressed, resulting in a transistor with improved reliability. A transistor can be fabricated.

[0175] <Variation 3> A modification of the transistor 10 described in this embodiment will be described with reference to FIG. The transistor 10 shown in the embodiment is a transistor having one gate electrode. The transistor 10e described in this modification has two gate electrodes sandwiching an oxide semiconductor film. Has.

[0176] 6A to 6C are top views and cross-sectional views of a transistor 10e included in a semiconductor device. 6A is a top view of the transistor 10e, and FIG. 6B is a side view of the transistor 10e. 6(A) is a cross-sectional view taken along the dashed line AB of FIG. 6(B), and FIG. 6(C) is a cross-sectional view taken along the dashed line CD of FIG. 6A, for clarity, the substrate 11, the gate insulating film 15, and the protective film 16 are not shown. The protective film 21 and the like are omitted.

[0177] The transistor 10e shown in FIGS. 6B and 6C is a channel-etched transistor. a gate electrode 13 provided on a substrate 11; and a gate insulating film 15 formed on the gate electrode 13, which overlaps the gate insulating film 15. The semiconductor device includes an oxide semiconductor film 17 and a pair of electrodes 19 and 20 in contact with the oxide semiconductor film 17 . Further, an oxide semiconductor film is formed on the gate insulating film 15, the oxide semiconductor film 17, and the pair of electrodes 19 and 20. A protective film 21 made up of an insulating film 23, an oxide insulating film 25, and a nitride insulating film 27, and a protective The gate electrode 37 is formed on the gate insulating film 15. The gate electrode 13 is connected to the protective film 21 through openings 42 and 43 formed in the protective film 21. Here, the gate insulating film 15 is formed by laminating a nitride insulating film 29 and an oxide insulating film 31. The protective film 21 is made of an oxide insulating film 23, an oxide insulating film 25, and a nitride film. A material insulating film 27 is laminated thereon.

[0178] The gate insulating film 15 and the protective film 21 have a plurality of openings. As shown in FIG. 1, openings 42 and 43 sandwiching the oxide semiconductor film 17 in the channel width direction are formed. That is, the oxide semiconductor film 17 has openings 42 and 43 on the outer side of the side surface thereof. 2 and 43, the gate electrode 13 and the gate electrode 37 are connected. In the direction of the gate electrode 13 and the gate electrode 37, the gate insulating film 15 and the protective film 21 are The oxide semiconductor film 17 is surrounded by the protective film 21 in the channel width direction. The side surface of the oxide semiconductor film 17 and the gate electrode 37 provided in the openings 42 and 43 are located. do.

[0179] As shown in FIG. 6C, the side surface of the oxide semiconductor film 17 in the channel width direction and the gate electrode 37 are opposed to each other, and thus, in the channel width direction, 13 and the gate electrode 37 are connected to the oxide semiconductor film 1 through the gate insulating film 15 and the protective film 21. 7, the carriers in the oxide semiconductor film 17 are transported to the gate insulating film 15 and the protective film 16. The flow occurs not only at the interface between the oxide semiconductor film 21 and the oxide semiconductor film 17 but also inside the oxide semiconductor film 17. As a result, the amount of carrier movement in the transistor 10e increases. The on-current of the transistor 10 increases and the field effect mobility also increases. The electric field of the oxide semiconductor film 17 influences the side surface of the oxide semiconductor film 17 or the end portion including the side surface and its vicinity. Therefore, the occurrence of a parasitic channel at the side or end of the oxide semiconductor film 17 can be suppressed. can be done.

[0180] <Variation 4> Modifications of the transistor 10 in this embodiment will be described with reference to FIGS. 7 and 8. The transistor 10 described in this embodiment has a single oxide semiconductor film. The transistors 10f and 10g described as examples have multilayer films.

[0181] 7A to 7C are top views and cross-sectional views of a transistor 10f included in a semiconductor device. 7A is a top view of the transistor 10f, and FIG. 7B is a side view of the transistor 10f. 7(A) is a cross-sectional view taken along the dashed line AB of FIG. 7(B), and FIG. 7(C) is a cross-sectional view taken along the dashed line CD of FIG. 7A, for clarity, the substrate 11, the gate insulating film 15, and the protective film 16 are not shown. The protective film 21 and the like are omitted.

[0182] The transistor 10f shown in FIG. 7A has a gate electrode 13 via a gate insulating film 15. The multilayer film 45 overlaps the gate electrode 19, and a pair of electrodes 19, 20 contact the multilayer film 45. A protective film 21 is formed on the gate insulating film 15, the multilayer film 45, and the pair of electrodes 19 and 20. do.

[0183] In the transistor 10f described in this embodiment, the multilayer film 45 includes the oxide semiconductor film 17 and an oxide semiconductor film 46. That is, the multilayer film 45 has a two-layer structure. A part of the conductive film 17 functions as a channel region. A protective film 21 is formed.

[0184] The oxide semiconductor film 46 is composed of one or more elements that constitute the oxide semiconductor film 17. Therefore, at the interface between the oxide semiconductor film 17 and the oxide semiconductor film 46, Therefore, the movement of carriers is not hindered at the interface. This results in a high field effect mobility of the transistor.

[0185] The oxide semiconductor film 46 is formed of a metal oxide containing at least In or Zn. Generally, In-Ga oxide film, In-Zn oxide film, In-M-Zn oxide film (M is A) l, Ga, Y, Zr, La, Ce, or Nd) and is thicker than the oxide semiconductor film 17 The energy of the bottom of the conduction band is close to the vacuum level. The difference between the energy at the bottom of the conduction band of the oxide semiconductor film 17 and the energy at the bottom of the conduction band of the oxide semiconductor film 17 is 0. 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 e V or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. The difference between the electron affinity of the oxide semiconductor film 46 and the electron affinity of the oxide semiconductor film 17 is 0.05 eV or more. , 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 e V or less, 0.5 eV or less, or 0.4 eV or less.

[0186] The oxide semiconductor film 46 contains In, which increases carrier mobility (electron mobility). Therefore, it is preferable.

[0187] The oxide semiconductor film 46 may be formed by using Al, Ga, Y, Zr, La, Ce, or Nd in a layer other than In. By having a higher atomic ratio, the following effects may be obtained: (1) An oxide semiconductor film (2) To increase the energy gap of the oxide semiconductor film 46. (3) The diffusion of impurities from the outside is reduced. (4) Compared with the oxide semiconductor film 17, (5) Al, Ga, Y, Zr, La, Ce, or Nd has high insulating properties. Since it is a metal element with a strong bonding force with oxygen, oxygen deficiency is unlikely to occur.

[0188] When the oxide semiconductor film 46 is an In-M-Zn oxide, the sum of In and M is 100a When the atomic percentage is 50 atomic %, the atomic ratio of In to M is preferably 50 atomic %. %, M is more than 50 atomic %, and more preferably In is 25 atomic % %, and M is greater than 75 atomic%.

[0189] The oxide semiconductor film 17 and the oxide semiconductor film 46 are made of In-M-Zn oxide (M is In the case of Al, Ga, Y, Zr, La, Ce, or Nd), the oxide semiconductor film 17 In addition, M (Al, Ga, Y, Zr, La, Ce, or Nd) contained in the oxide semiconductor film 46 ) is larger than the above atoms contained in the oxide semiconductor film 17. The atomic ratio is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more higher.

[0190] The oxide semiconductor film 17 and the oxide semiconductor film 46 are made of In-M-Zn oxide (M is A). In the case of In:M, the oxide semiconductor film 46 is Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor film 17 is In:M:Zn=x2: When y2:z2 is the atomic ratio, y1 / x1 is greater than y2 / x2, and preferably, y1 / x1 is 1.5 times or more than y2 / x2. More preferably, y1 / x1 is y 2 / x2, and more preferably, y1 / x1 is at least three times larger than y2 / x2. In this case, when y2 is equal to or larger than x2 in the oxide semiconductor film, the oxide semiconductor This is preferable because it can impart stable electrical characteristics to a transistor using a conductor film.

[0191] The oxide semiconductor film 17 is an In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, In the case of Ce or Nd), the target used to form the oxide semiconductor film 17 In this case, if the atomic ratio of the metal elements is In:M:Zn=x1:y1:z1, then 、 x1 / y1 is , 1 / 3 or more and 6 or less, further 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less It is more preferable that z1 / y1 is 1 or more and 6 or less. This facilitates the formation of a CAAC-OS film as the oxide semiconductor film 17. Typical examples of atomic ratios of metal elements are In:M:Zn=1:1:1, In:M:Zn =1:1:1.2, In:M:Zn=3:1:2, etc.

[0192] The oxide semiconductor film 46 is an In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, In the case of Ce or Nd), the target used to form the oxide semiconductor film 46 In this case, if the atomic ratio of the metal elements is In:M:Zn=x2:y2:z2, then 、 x2 / y2< x1 / y1, and z2 / y2 is 1 / 3 or more and 6 or less, and further 1 or more and 6 or less. When z2 / y2 is greater than or equal to 1 and less than or equal to 6, the oxide semiconductor film 46 can be formed. The CAAC-OS film is easily formed when the atomic ratio of the target metal elements is For example, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn= 1:3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:3, In:M:Z n=1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:4:6, In:M :Zn=1:5:5, In:M:Zn=1:5:6, etc.

[0193] The atomic ratios of the oxide semiconductor film 17 and the oxide semiconductor film 46 are each calculated using an error. The above atomic ratios may vary by plus or minus 40%.

[0194] The thickness of the oxide semiconductor film 46 is 3 nm to 100 nm, preferably 3 nm to 50 nm. nm or less.

[0195] In addition, the oxide semiconductor film 46 may have a non-single crystal structure, for example, similar to the oxide semiconductor film 17. The non-single crystal structure is, for example, CAAC-OS (C Axis Alignment) which will be described later. d-Crystalline Oxide Semiconductor), polycrystalline structure , a microcrystalline structure, as described below, or an amorphous structure.

[0196] The oxide semiconductor film 46 may have, for example, an amorphous structure. For example, the atomic arrangement is disordered and does not have crystalline components. Alternatively, the oxide semiconductor has an amorphous structure. The conductor film has, for example, a completely amorphous structure and does not have any crystalline portions.

[0197] Note that in the oxide semiconductor film 17 and the oxide semiconductor film 46, the amorphous region and the microcrystalline region are Two or more of the following: a crystal structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region The mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, and two or more of the following: a polycrystalline structure region, a CAAC-OS region, and a single-crystalline structure region In some cases, the mixed film has a single layer structure having an amorphous structure region, a microstructure region, etc. The region may be a crystalline structure region, a polycrystalline structure region, a CAAC-OS region, or a single-crystalline structure region. Alternatively, the layer structure may have a laminated structure of two or more regions.

[0198] Here, an oxide semiconductor film 46 is provided between the oxide semiconductor film 17 and the protective film 21. Therefore, the oxide semiconductor film 46 and the protective film 21 are separated by impurities and defects. Even if carrier traps are formed, the region where the carrier traps are formed and the oxide semiconductor There is a gap between the oxide semiconductor film 17 and the conductive film 17. As a result, the electrons flowing through the oxide semiconductor film 17 are It is difficult to be captured by rear traps, and it is possible to increase the on-current of the transistor. At the same time, the field effect mobility can be increased. When the electrons are released, they act as fixed negative charges. This results in a transistor threshold voltage However, the oxide semiconductor film 17 and the carrier trap are formed. The gap between the regions reduces the capture of electrons in the carrier traps. This makes it possible to reduce the variation in threshold voltage.

[0199] In addition, the oxide semiconductor film 46 can block impurities from the outside. It is possible to reduce the amount of impurities that move from the oxide semiconductor film 17 to the oxide semiconductor film 17. The oxide semiconductor film 46 is less likely to form oxygen vacancies. It is possible to reduce the impurity concentration and oxygen vacancy amount.

[0200] The oxide semiconductor film 17 and the oxide semiconductor film 46 are not simply stacked. Continuous junction (here, a structure in which the energy at the bottom of the conduction band changes continuously between each film) In other words, the interfacial trap centers and recombination centers of each film are formed. The stacked structure is designed so that there are no impurities that would create defect levels. When impurities are present between the oxide semiconductor film 17 and the oxide semiconductor film 46, the energy The band continuity is lost, and carriers are trapped or recombined at the interface and disappear. It ends up like this.

[0201] To form continuous junctions, a multi-chamber deposition system equipped with a load lock chamber is required. Each film is laminated in succession using a sputtering device without being exposed to the atmosphere. Each chamber in the sputtering device is required for the oxide semiconductor film. In order to remove impurities such as water as much as possible, an adsorption type vacuum pump such as a cryopump is used. High vacuum pumping (5×10 -7 Pa~1×10 -4 It is preferable to Alternatively, a turbomolecular pump and a cold trap can be combined to separate the chamber from the exhaust system. It is preferable to prevent the backflow of gases, especially gases containing carbon or hydrogen, into the bar. stomach.

[0202] In place of the multilayer film 45, a multilayer film such as a transistor 10g shown in FIG. 7(D) may be used. 48.

[0203] The multilayer film 48 includes an oxide semiconductor film 47, an oxide semiconductor film 17, and an oxide semiconductor film 46. That is, the multilayer film 48 has a three-layer structure. It functions as a channel region.

[0204] In addition, the gate insulating film 15 and the oxide semiconductor film 47 are in contact with each other. An oxide semiconductor film 47 is provided between the oxide semiconductor film 17 and the oxide semiconductor film 47 .

[0205] In addition, the oxide semiconductor film 46 and the protective film 21 are in contact with each other. An oxide semiconductor film 46 is provided between the film 21 and the oxide semiconductor film 46 .

[0206] The oxide semiconductor film 47 can be formed by using the same material and method as the oxide semiconductor film 46, as appropriate. This can be done.

[0207] The oxide semiconductor film 47 is preferably thinner than the oxide semiconductor film 17. The thickness of the body film 47 is set to 1 nm or more and 5 nm or less, preferably 1 nm or more and 3 nm or less. Therefore, it is possible to reduce the amount of variation in the threshold voltage of the transistor.

[0208] The transistor described in this embodiment has an oxide semiconductor film between the oxide semiconductor film 17 and the protective film 21. Therefore, the oxide semiconductor film 46 is provided between the oxide semiconductor film 46 and the protective film 21. Even if carrier traps are formed by impurities and defects, the carrier traps There is a gap between the region where the oxide semiconductor film 17 is formed and the oxide semiconductor film 17. Electrons flowing through the film 17 are less likely to be captured by carrier traps, increasing the on-current of the transistor. It is possible to increase the carrier mobility and also to increase the field effect mobility. When an electron is captured in the trap, it behaves as a fixed negative charge. However, the oxide semiconductor film 17 and the capacitor Because of the gap between the region where the rear trap is formed and the carrier trap, the charge in the carrier trap It is possible to reduce trapping of electrons, and thus to reduce the variation in threshold voltage.

[0209] In addition, the oxide semiconductor film 46 can block impurities from the outside. It is possible to reduce the amount of impurities that move from the oxide semiconductor film 17 to the oxide semiconductor film 17. The oxide semiconductor film 46 is less likely to form oxygen vacancies. It is possible to reduce the impurity concentration and oxygen vacancy amount.

[0210] In addition, an oxide semiconductor film 47 is provided between the gate insulating film 15 and the oxide semiconductor film 17. An oxide semiconductor film 46 is provided between the oxide semiconductor film 17 and the protective film 21. Therefore, silicon and carbon in the vicinity of the interface between the oxide semiconductor film 47 and the oxide semiconductor film 17 are the concentration of silicon or carbon in the oxide semiconductor film 17, or the concentration of the oxide semiconductor film 4 Therefore, the concentration of silicon and carbon in the vicinity of the interface between the oxide semiconductor film 17 and the oxide semiconductor film 6 can be reduced. Cut.

[0211] The transistor 10g having such a structure includes a multilayer film 48 including an oxide semiconductor film 17. Since there are very few defects in the This typically allows for an increase in on-current and an improvement in field effect mobility. The thresholds in the gate BT stress test and the optical gate BT stress test, which are examples of the stress test, are The voltage fluctuation is small and the reliability is high.

[0212] Note that the transistor 10f shown in FIG. 7B is provided with a gate electrode 37. 10h can be produced (see Figure 7(E)). Alternatively, the transformer shown in Figure 7(D) can be used. A transistor 10i can be fabricated by providing a gate electrode 37 on the transistor 10g. See Figure 7(F).

[0213] <Transistor band structure> Next, the multilayer film 45 provided in the transistor 10f shown in FIG. 7(A) and the multilayer film 45 provided in the transistor 10f shown in FIG. 7(D) are The band structure of the multilayer film 48 provided in the transistor 10g shown in FIG. explain.

[0214] Here, for example, the oxide semiconductor film 17 has an energy gap of 3.15 eV. The oxide semiconductor film 46 is made of an In-Ga-Zn oxide having an energy gap of 3 The energy gap is measured by spectroscopic ellipsometry using In-Ga-Zn oxide, which has a value of 0.5 eV. It can be measured using a meter (HORIBA JOBIN YVON UT-300).

[0215] Energy difference between the vacuum level and the top of the valence band of the oxide semiconductor film 17 and the oxide semiconductor film 46 (also called ionization potential) are 8 eV and 8.2 eV, respectively. The energy difference between the vacuum level and the top of the valence band is measured by ultraviolet photoelectron spectroscopy (UPS). Ultraviolet Photoelectron Spectroscopy (ULV) Measurement can be performed using AC-PHI VersaProbe.

[0216] Therefore, the vacuum level and the energy at the bottom of the conduction band of the oxide semiconductor film 17 and the oxide semiconductor film 46 are The energy difference (also called electron affinity) is 4.85 eV and 4.7 eV, respectively.

[0217] FIG. 8A is a schematic diagram showing a part of the band structure of the multilayer film 45 included in the transistor 10f. In this example, the gate insulating film 15 and the protective film 21 are silicon oxide films, and the multilayer The case where the film 45 and the silicon oxide film are provided in contact with each other will be described. EcI1 indicates the energy of the bottom of the conduction band of the silicon oxide film, and EcS1 indicates the energy of the bottom of the conduction band of the oxide semiconductor film. 17, and EcS2 is the energy of the bottom of the conduction band of the oxide semiconductor film 46. EcI2 indicates the energy at the bottom of the conduction band of the silicon oxide film. cI1 corresponds to the gate insulating film 15 shown in FIG. 7(B), and EcI2 corresponds to the protection film 15 shown in FIG. It corresponds to the protective film 21 .

[0218] As shown in FIG. 8A, in the oxide semiconductor film 17 and the oxide semiconductor film 46, The energy at the lower band edge changes smoothly without any barrier. In other words, it changes continuously. This can also be said to be because the multilayer film 45 contains elements common to the oxide semiconductor film 17, Oxygen moves between the oxide semiconductor film 17 and the oxide semiconductor film 46, forming a mixed layer. This can be said to be because

[0219] As shown in FIG. 8A, the oxide semiconductor film 17 of the multilayer film 45 serves as a well, and the multilayer film 4 In the transistor using the semiconductor device 5, a channel region is formed in the oxide semiconductor film 17. In addition, since the energy of the conduction band minimum changes continuously in the multilayer film 45, It can also be said that the oxide semiconductor film 17 and the oxide semiconductor film 46 are continuously joined together.

[0220] As shown in FIG. 8A, the oxide semiconductor film 46 and the protective film 21 are adjacent to each other. Although trap levels due to impurities or defects may be formed, the oxide semiconductor film 46 is By blocking the oxide semiconductor film 17, the oxide semiconductor film 17 can be separated from the trap levels. However, when the energy difference between EcS1 and EcS2 is small, the electrons in the oxide semiconductor film 17 The electron may exceed the energy difference and reach the trap level. As a result, negative fixed charges are generated on the surface of the oxide insulating film, and the threshold voltage of the transistor It shifts in the positive direction. Therefore, the energy difference between EcS1 and EcS2 is If the capacitance is set to 0.1 eV or more, preferably 0.15 eV or more, the threshold voltage of the transistor can be reduced. This is preferable because the fluctuation is reduced and the electrical characteristics are stable.

[0221] FIG. 8B is a schematic diagram showing a part of the band structure of the multilayer film 45 of the transistor 10f. 8(A) and is a modified example of the band structure shown in FIG. When the protective film 21 is a silicon oxide film and the multilayer film 45 is provided in contact with the silicon oxide film, The EcI1 shown in FIG. 8B is the energy of the bottom of the conduction band of the silicon oxide film. EcS1 represents the energy of the bottom of the conduction band of the oxide semiconductor film 17, and EcI2 represents the energy of the bottom of the conduction band of the oxide semiconductor film 17. The energy of the bottom of the conduction band of the silicon oxide film is shown in FIG. EcI2 corresponds to the gate insulating film 15, and EcI3 corresponds to the protective film 21 shown in FIG. 7(B).

[0222] In the transistor shown in FIG. 7B, the multilayer film 45 On the other hand, the oxide semiconductor film 46 may be etched. The upper surface of the oxide semiconductor film 17 is in contact with the oxide semiconductor film 17 during the formation of the oxide semiconductor film 46. 46 mixed layers may form.

[0223] For example, the oxide semiconductor film 17 is an In- Ga-Zn oxide, or In-Ga-Z with an atomic ratio of In:Ga:Zn=3:1:2 n oxide as a sputtering target, and The semiconductor film 46 is an In-Ga-Zn oxide having an atomic ratio of In:Ga:Zn=1:3:2. , In-Ga-Zn oxide with In:Ga:Zn=1:3:4 [atomic ratio], or In: In-Ga-Zn oxide with a Ga:Zn=1:3:6 atomic ratio was used as a sputtering target. In the case of an oxide semiconductor film formed using a PET bottle, the oxide semiconductor film is thicker than the oxide semiconductor film 17. Since the conductor film 46 contains a large amount of Ga, the upper surface of the oxide semiconductor film 17 is covered with GaO x Layers In this case, a mixed layer containing more Ga than the oxide semiconductor film 17 can be formed.

[0224] Therefore, even when the oxide semiconductor film 46 is etched, the Ec The energy at the bottom of the conduction band on the I2 side becomes higher, resulting in the band structure shown in Figure 8(B). There are cases where this happens.

[0225] When the band structure shown in FIG. 8B is obtained, when observing the cross section of the channel region, The multilayer film 45 may appear to be composed of only the oxide semiconductor film 17. In reality, a mixture containing more Ga than the oxide semiconductor film 17 is formed on the oxide semiconductor film 17. Since a mixed layer is formed, the mixed layer can be regarded as the 1.5th layer. The mixed layer was analyzed by, for example, EDX analysis to measure the elements contained in the multilayer film 45. In this case, it can be confirmed by analyzing the composition above the oxide semiconductor film 17. For example, The composition above the oxide semiconductor film 17 has a higher Ga content than the composition in the oxide semiconductor film 17. This can be confirmed by the fact that the configuration is high in

[0226] FIG. 8C is a schematic diagram showing a part of the band structure of the multilayer film 48 of the transistor 10g. Here, the gate insulating film 15 and the protective film 21 are silicon oxide films, and the multilayer film 48 is The case where a silicon oxide film is provided in contact with the silicon dioxide film will be described. indicates the energy of the bottom of the conduction band of the silicon oxide film, and EcS1 indicates the conduction band EcS2 is the energy of the conduction band minimum of the oxide semiconductor film 46. EcS3 represents the energy of the bottom of the conduction band of the oxide semiconductor film 47, and EcI2 represents the energy of the oxide semiconductor film 47. EcI1 represents the energy of the bottom of the conduction band of the silicon dioxide film. EcI2 corresponds to the protective film 21 shown in FIG. 7(D).

[0227] As shown in FIG. 8C, the oxide semiconductor film 47, the oxide semiconductor film 17, and the oxide semiconductor film 18 are In the film 46, the energy of the conduction band minimum changes smoothly without any barrier. This means that the multilayer film 48 changes continuously from the oxide semiconductor film 1 7, and the oxide semiconductor film 17 and the oxide semiconductor film 47 are formed between the oxide semiconductor film 17 and the oxide semiconductor film 47. Oxygen moves between the compound semiconductor film 17 and the oxide semiconductor film 46, forming a mixed layer. It can be said that this is done in order to achieve this.

[0228] As shown in FIG. 8C, the oxide semiconductor film 17 of the multilayer film 48 becomes a well, and the multilayer film 4 In the transistor using the oxide semiconductor film 17, a channel region is formed in the oxide semiconductor film 17. In addition, since the energy of the conduction band minimum changes continuously in the multilayer film 48, The oxide semiconductor film 47, the oxide semiconductor film 17, and the oxide semiconductor film 46 are continuously joined together. It can also be said that...

[0229] The vicinity of the interface between the oxide semiconductor film 17 and the protective film 21, and the oxide semiconductor film 17 and Trap levels due to impurities or defects may be formed near the interface of the gate insulating film 15. However, as shown in FIG. 8C, the oxide semiconductor film 46 and the oxide semiconductor film 47 are provided. By doing so, the oxide semiconductor film 17 and the region where the trap levels are formed are separated from each other. However, the energy difference between EcS1 and EcS2 and the energy difference between EcS1 and EcS3 When the energy difference is small, electrons in the oxide semiconductor film 17 exceed the energy difference and are trapped. When electrons are captured in the trap level, they are released onto the surface of the oxide insulating film. A negative fixed charge is generated, and the threshold voltage of the transistor shifts in the positive direction. Therefore, the energy difference between EcS1 and EcS2 and the energy difference between EcS1 and EcS3 are If the difference is 0.1 eV or more, preferably 0.15 eV or more, the threshold voltage of the transistor is This is preferable because it reduces fluctuations in the voltage and provides stable electrical characteristics.

[0230] In place of the oxide semiconductor film 46, an In-M oxide (wherein M is Al, Ga, Y, Zr A metal oxide film formed of a metal such as La, Ce, or Nd can be used. In order to prevent the metal oxide film from functioning as a part of the channel region, the metal oxide film The metal oxide film should be made of a material with sufficiently low conductivity. The energy difference between the vacuum level and the bottom of the conduction band is smaller than that of the oxide semiconductor film 17. The difference between the energy at the bottom of the conduction band and the energy at the bottom of the conduction band of the oxide semiconductor film 17 (band offset) The material used should have a threshold voltage that depends on the magnitude of the drain voltage. In order to suppress the occurrence of a voltage difference, the energy of the conduction band minimum of the metal oxide film is A material whose conduction band energy is closer to the vacuum level by 0.2 eV or more than the minimum energy of the conduction band of the oxide semiconductor film 17 It is preferable to use a material having a potential close to the vacuum level of 0.5 eV or more.

[0231] In addition, by increasing the atomic ratio of element M to In, the energy gap of the metal oxide film can be increased. For example, the metal oxide film can be In-M oxide (M is Al, Ga, Y, Zr, La, Ce, or Nd) When a material is used, a band offset of the conduction band is formed between the material and the oxide semiconductor film 17, and a gold To prevent the formation of a channel in the metal oxide film, the metal oxide film should be In:M = x:y [atomic number ratio], y / (x+y) is 0.75 or more and 1 or less, preferably It is preferable that the ratio is 0.78 or more and 1 or less, and more preferably 0.80 or more and 1 or less. In the metal oxide film, elements other than the main components indium, M, and oxygen are mixed in as impurities. In this case, the proportion of impurities is preferably 0.1% or less.

[0232] In addition, when a metal oxide film is formed by sputtering, the ratio of element M to In is By increasing the atomic ratio, it is possible to reduce the number of particles during film formation. In order to reduce the number of tickles, if In:M=x:y [atomic ratio], then y / (x+ y) is preferably set to 0.90 or more, for example, 0.93. However, when the metal oxide film is formed by sputtering, When forming by the ring method, if the atomic ratio of M to In is too high, It has high insulating properties, making it difficult to form a film using DC discharge, and it becomes necessary to apply RF discharge. Therefore, in order to perform film formation using DC discharge that can be applied to large area substrates, the following equation must be satisfied: y / (x+ y) is set to 0.96 or less, preferably 0.95 or less, for example, 0.93. By applying a film formation method suitable for the plate, productivity of the semiconductor device can be improved.

[0233] It is preferable that the metal oxide film does not contain a spinel type crystal structure. When a spinel-type crystal structure is contained in the metal oxide film, the spinel-type crystal structure and other regions are The constituent elements of the pair of electrodes 19 and 20 diffuse into the oxide semiconductor film 17 between the electrodes 19 and 20 and the oxide semiconductor film 17. For example, when an In-M oxide is used as the metal oxide film, By making the composition free of divalent metal atoms (e.g., zinc), a spinel-type crystal can be obtained. This is preferable because it is possible to form a metal oxide film that does not contain a crystal structure.

[0234] The thickness of the metal oxide film is determined by the diffusion of the constituent elements of the pair of electrodes 19 and 20 into the oxide semiconductor film 17. The thickness of the protective film 21 to the oxide semiconductor film 17 is equal to or greater than the thickness that can prevent the oxide semiconductor film 17 from being damaged. For example, the thickness of the metal oxide film is 10 nm or more. In this case, the constituent elements of the pair of electrodes 19 and 20 are prevented from diffusing into the oxide semiconductor film 17. Furthermore, when the thickness of the metal oxide film is 100 nm or less, the protective film 21 Oxygen can be effectively supplied to the oxide semiconductor film 17.

[0235] <Variation 5> A modification of the transistor described in this embodiment will be described with reference to FIGS. The transistor 10j shown in the example has an oxide semiconductor film 17a formed using a multi-tone mask. and a pair of electrodes 19a and 20a.

[0236] By using a multi-tone mask, it is possible to form resist masks with multiple thicknesses. After the oxide semiconductor film 17a is formed using the resist mask, oxygen plasma By exposing the resist mask to the light, a part of the resist mask is removed, forming a pair of electrodes. Therefore, the oxide semiconductor film 17a and the pair of electrodes 19 This allows reducing the number of photolithography steps in the manufacturing process of 20a and 20a.

[0237] Note that by using a multi-tone mask, part of the oxide semiconductor film 17a is formed in a uniform shape in plan view. The pair of electrodes 19a and 20a are exposed to the outside.

[0238] Note that the structures and methods shown in this embodiment may be used in conjunction with structures and methods shown in other embodiments and examples. and methods can be used in appropriate combination.

[0239] <Variation 6> A modification of the transistor described in this embodiment will be described with reference to FIG. The transistor 10k shown in FIG.

[0240] The organic insulating film 38 may be made of, for example, polyimide, acrylic, polyamide, epoxy, or the like. An organic resin film can be used. The organic insulating film 38 has a thickness of 500 nm to 10 μm. Preferably, it is below.

[0241] The organic insulating film 38 may be provided on the entire surface of the protective film 21. The oxide semiconductor film 17 is separated for each transistor and is set to overlap with the oxide semiconductor film 17 of each transistor. If the organic insulating film 38 is formed separately, water from the outside may penetrate the organic insulating film. This is preferable because it does not diffuse through the film 38 into the semiconductor device.

[0242] Since the organic insulating film 38 is thick, ie, 500 nm or more, a negative voltage is applied to the gate electrode 13. The electric field generated by the application of the electric field does not affect the surface of the organic insulating film 38, and the organic insulating film The surface of 38 is hard to be positively charged. In addition, positively charged particles in the air are easily attracted to the organic insulator. Even if the organic insulating film 38 is adsorbed on the surface thereof, the organic insulating film 38 has a thickness of 500 nm or more, so that the organic insulating film 38 is not adsorbed on the surface thereof. The electric field of the positively charged particles adsorbed on the surface of the organic insulating film 38 is generated between the oxide semiconductor film 17 and the protective film 2 As a result, the interface between the oxide semiconductor film 17 and the protective film 21 is hardly affected. Therefore, a positive bias is not applied to the transistor, and the threshold voltage of the transistor does not change. There is little movement.

[0243] Note that the structures and methods shown in this embodiment may be used in conjunction with structures and methods shown in other embodiments and examples. and methods can be used in appropriate combination.

[0244] (Embodiment 2) In this embodiment, an oxide semiconductor film included in a transistor and a The defects contained in the contacting oxide insulating film and the degradation of transistor characteristics will be explained.

[0245] <1. NO x > First, we investigated the nitrogen oxide (NO ) contained in the oxide insulating film in contact with the oxide semiconductor film. x (x=0 or more and 2 or less, preferably 1 or more and 2 or less) will be described.

[0246] <1-1. NO in oxide insulating film x About the transition level First, we will explain using the transition level of point defects in solids. The transition level is the gap This section explains the charge state of impurities or defects (hereinafter referred to as defects D) that form levels in The transition level is calculated from the defect formation energy. This is a concept similar to the acceptor level.

[0247] The relationship between the formation energy of the charge state of defect D and the transition level is explained. The formation energy varies depending on the charge state and also depends on the Fermi energy. The state where one is released is D + and the state in which one electron is captured is represented as D - and the electron transfer The state without 0 This indicates:

[0248] Defect D + , Defect D 0 , Defect D - The relationship between the formation energy and the transition level is shown in Fig. 11. In addition, in Fig. 11(B), the defect D has an orbital with one electron occupied in the neutral state. In this case, defect D + , Defect D 0 , Defect D - The electron configuration of each is shown below.

[0249] In Figure 11(A), the dotted line indicates defect D + The solid line indicates the formation energy of the defect D 0 Formation energy of Energy, dashed lines indicate defects - The transition levels represent the formation energies of the different charge states of the defect D. This represents the position of the Fermi level where the formation energies of the defect D are equal. + and Defect D 0 The shape of The position of the Fermi level where the combined energy is equal (i.e., the intersection of the dotted line and the solid line) is defined as ε( + / 0) and defect D 0 and Defect D - The Fermi level at which the formation energy of The position (i.e., the position of the intersection of the solid line and the dashed line) is represented as ε(0 / -).

[0250] Next, we consider the transition of the energetically stable charge state of the defect when the Fermi level is changed. A conceptual diagram is shown in Figure 12. In Figure 12, the dashed two-dot line represents the Fermi level. In the left figure, the band diagram when (1), (2), and (3) are the Fermi levels is as follows: This is shown in the right figure of Figure 12.

[0251] By knowing the transition levels of a solid, when the Fermi level is used as a parameter, It is important to qualitatively understand the charge state of defects at the Fermi level that is energetically stable. This can be done.

[0252] Next, silicon oxynitride (SiO ) is a typical example of an oxide insulating film in contact with an oxide semiconductor film. N) was used to study the defect levels in silicon oxynitride and the ESR signals resulting from these defect levels. Specifically, NO2 in silicon oxide (SiO2), For the model with NO, NO, and N atoms, By examining the transition levels of the molecules, NO2, N2O, NO, and N atoms can be seen to affect the transistor's electrical conductivity. We verified whether it could become a child trap.

[0253] For the calculation, SiO2 (c-SiO2) with a low-temperature quartz (α-quartz) crystal structure was used as a model. A crystal model of defect-free c-SiO2 is shown in Figure 13.

[0254] First, for a 72-atom model in which the unit cell of c-SiO2 is doubled in all axial directions, The structural optimization calculations were carried out for the constants and each atomic coordinate. AVASP(The Vienna Ab initio simulation pa The effect of the inner shell electrons was measured using the Projector Augmentation The calculations were performed using the d-Wave (PAW) method, and the functional was the Heyd-Scuseria-Er The calculation conditions were as follows: The matters are shown below.

[0255] [Table 1]

[0256] The band gap of the optimized c-SiO2 model is close to the experimental value of 9.0 eV. 0.97eV.

[0257] Next, in the c-SiO2 model, NO2 and N are placed in the spaces (interstitial spaces) within the crystal structure. 2) For each model with O, NO, or N atoms introduced, a structural optimization calculation was performed. Here, for each model, if the entire model has a +1 valence (charge: +1), When the entire model is electrically neutral (0 valence) (charge: neutral), and when the entire model is -1 valence, Optimization calculations were performed for each of the three cases. The charges imposed on the whole molecule are NO2, N2O, NO, and N atoms in the electronic ground state, respectively. We confirmed that it localizes to defects containing nuclei.

[0258] First, we performed optimization calculations for a model in which NO2 was introduced between the lattices of the c-SiO2 model. The structure after the treatment and the structural parameters of the NO2 molecule are shown in Figure 14. As a reference example, the structural parameters of the NO2 molecule in the gas phase are also given.

[0259] Generally, molecules that are not electrically neutral are often called molecular ions, but here we will use the crystalline structure Since we are discussing molecules introduced into the interior of a molecule, unlike the gas phase state, we cannot quantify the valence of the molecule. Therefore, for convenience, molecules that are not electrically neutral are also referred to as molecules. We will do so.

[0260] From Figure 14, when an NO2 molecule is introduced, if the charge of the model is +1, the NO2 molecule The ONO bond angle tends to decrease as the charge of the model increases from neutral to -1. This structural change of the NO2 molecule is similar to that observed when the charge number of an isolated molecule in the gas phase is changed. Since this is almost the same as the change in bond angle, most of the assumed charge is carried by the NO2 molecule. It is also inferred that NO2 molecules in SiO2 exist in a state close to isolated molecules. .

[0261] Next, we performed optimization calculations on a model in which N2O was introduced between the lattices of the c-SiO2 model. The structure after this and the structural parameters of the N2O molecule are shown in Figure 15. As a reference example, the structural parameters of the N2O molecule in the gas phase are also given.

[0262] From Figure 15, the structure of the NO molecule is almost the same when the charge of the model is +1 and when it is neutral. On the other hand, when the charge of the model is -1, the N2O molecule is bent. The structure is curved, and the distance between NO molecules is longer than in the other two conditions. Child's Pi * This is thought to be because an electron has entered the LUMO level, which is an orbital.

[0263] Next, we performed optimization calculations for a model in which NO was introduced between the lattices of the c-SiO2 model. The structure after this reaction and the structural parameters of the NO molecule are shown in Figure 16.

[0264] From Figure 16, when the charge of the model is +1, the distance between NOs is short, and conversely, when the charge of the model is -1 The distance between NO molecules is longer when the charge of the NO molecule in the gas phase is +1. When the value is 0 or -1, the bond order of the NO bond is 3.0, 2.5, and 2.0, respectively. This is presumably because the charge is the largest when it is +1. It is presumed that NO molecules in iO2 exist stably in a state close to that of isolated molecules.

[0265] Finally, we performed optimization calculations on a model in which N atoms were introduced between the lattices of the c-SiO2 model. The structure after this is shown in FIG.

[0266] From Figure 17, in any charge state, N atoms exist more frequently in the interstitial space than as isolated atoms. It was found that bonding with atoms in SiO2 is more energetically stable.

[0267] Subsequently, the transition levels were calculated for each model.

[0268] Here, in a model with a defect D in the structure, the states of charge q and charge q' are The transition level ε(q / q′) can be calculated by the following equation 3.

[0269]

number

[0270] where E tot (D q ) is the total energy of the model with a defect D of charge q, E tot ( bulk) is the total energy of the defect-free model, n i is the number of atoms i contributing to the defect, μ i is the chemical potential of atom i, ε VBM is the energy at the top of the valence band in a defect-free model. Energy, ΔVq is the correction term for the electrostatic potential, E f is the Fermi energy .

[0271] The band diagram showing the transition levels obtained from the above formula is shown in FIG. The oxide semiconductor film is made of metal oxide with an atomic ratio of In:Ga:Zn=1:1:1. The oxide semiconductor film (hereinafter referred to as IGZO(111)) formed on the substrate was used. In addition to the band diagrams of the above four models, the band diagram of IGZO(111) is also shown. The unit of the values ​​in Figure 18 is eV.

[0272] In Figure 18, the value of each transition level is based on the top of the valence band of SiO2 (0.0 eV). Here, the literature value was used as the electron affinity of SiO2, but When SiO2 and IGZO(111) are joined, the positional relationship of each band is actually S It may be affected by the electron affinity of iO2.

[0273] The transition level where the charge of the model transitions between +1 and 0 is denoted as (+ / 0). The transition level where the charge of the model transitions between 0 and -1 is denoted as (0 / -). .

[0274] In Figure 18, in the model where NO2 molecules are introduced into SiO2, IGZO(111) There are two transition levels, (+ / 0) and (0 / -), at positions corresponding to the band gap of These results suggest that the presence of Si may be involved in the trapping and detrapping of electrons. In the model where NO molecules are introduced into O2 and the model where N atoms are introduced, both IGZO There is a (+ / 0) transition level at a position corresponding to the (111) band gap. On the other hand, the transition levels of the models with N2O molecules introduced into SiO2 are all the same as those of IGZO(11 1) exists outside the band gap and acts as a neutral molecule regardless of the position of the Fermi level. It is assumed that the molecule exists stably.

[0275] From the above results, it is clear that the electron transport that causes the positive shift in the threshold voltage of the transistor Nitrogen-containing interstitial molecules involved in trapping and detrapping are band gap-dependent on IGZO(111). It is a molecule with a transition level located closer to the conduction band in the gap. 11) The molecule with a transition level closer to the conduction band within the band gap is the NO2 molecule. It is strongly suggested that it is likely to be the NO molecule, or both.

[0276] <1-2. Verification of ESR signal> Based on the above calculation results of the transition level, the ESR signal of the NO2 molecule is calculated as follows. In addition, a similar study was conducted on a model in which N atoms were substituted for O atoms in SiO2. I gave testimony.

[0277] Here, the N atom has 7 electrons and the O atom has 8 electrons, so the NO2 molecule has Therefore, the neutral NO2 molecule has a lone electron, so it is not possible to measure it with ESR. In addition, when N atoms are substituted for O atoms in SiO2, the surroundings of the N atoms There are only two Si atoms, and N has a dangling bond, so ES It can be measured by R. 14 Since N has a nuclear spin of 1, 14 N The peak of the ESR signal involved splits into three. The splitting width is the hyperfine coupling constant.

[0278] Therefore, the origin of the ESR signal splitting into three in the oxide insulating film is NO2 It is unclear whether this is due to the molecules or to the N atoms that replaced the O atoms in SiO2. It should be noted that if the SiO2 crystal structure is used as a model, the amount of calculation required will be enormous. Therefore, we use two types of cluster structure models as shown in Figure 19. After performing structural optimization for the , the g value and hyperfine coupling constant were calculated. is a model of a neutral NO2 molecule, and Figure 19(B) shows a model of a NO2 molecule with Si-N-Si bonds. In the model shown in FIG. 19(B), the dangling bond of the Si atom is replaced by H A cluster model terminated by atoms was used.

[0279] Geometry optimization of models and calculation of g values ​​and hyperfine coupling constants of geometry-optimized models ADF (Amsterdam Density Functional software) In addition, the structural optimization of the model and the g value and Both the calculation of the hyperfine coupling constants and the functional "GGA:BP" are used, and the basis functions are "QZ 4P” and “None” was used as the Core Type. When calculating the constants, the "Spin-Orbit" effect is taken into account, and the ESR / EP The calculation method for R was selected as "g & A-Tensor (full SO)". The calculation conditions are as follows:

[0280] [Table 2]

[0281] As a result of the structure optimization, first, for the NO2 molecule shown in Figure 19(A), the NO bond length is 0 1205 nm, and the ONO bond angle is 134.1°. The bond length was 0.1197 nm and the bond angle was 134.3°, which are close to the experimental values. For the Si-N-Si cluster model shown in Figure 19(B), the Si-N bond length is 0. The Si-N-Si bond angle was 138.3°, which was calculated by first-principles calculations. The structure after the structural optimization calculation was performed by substituting N atoms for O atoms in the SiO2 crystal. The Si-N bond length was 0.170 nm and the Si-N-Si bond angle was 139.0°. Ta.

[0282] The calculated g values ​​and hyperfine coupling constants are shown below.

[0283] [Table 3]

[0284] As mentioned above, the hyperfine coupling constant A corresponds to the split width of the peak of the ESR signal. From Table 3, the average value of the hyperfine coupling constant A of the NO2 molecule is approximately 5 mT. For the Si-N-Si cluster model, only the hyperfine coupling constant A_x is positive. The value is about 3 mT. The ESR spectra of 2 and Si-N-Si are shown in Figure 20(A) and Figure 20(B), respectively. vinegar.

[0285] From this result, it was found that the X-band ESR measurement had three signals and an excess of about 5 mT. The ESR spectrum with a fine structure constant and a g value of about 2 is the NO2 fraction in the SiO2 crystal. It is highly likely that this is due to the child. The g value is approximately 2.

[0286] <1-3. Consideration of the degradation mechanism of transistors> Based on the above results, we conducted a positive gate BT stress test (+GBT). The mechanism of the phenomenon of a positive shift in the threshold voltage of a transistor when We will consider the following.

[0287] The mechanism will be considered using Figure 21. Figure 21 shows the gate (GE), gate insulating film ( A structure in which a GI film, an oxide semiconductor film (OS), and a silicon oxynitride film (SiON) are stacked in this order. Here, the silicon oxynitride film on the back channel side of the oxide semiconductor film (OS) is A case where nitrogen oxide is contained in the SiON film will be described.

[0288] First, when a transistor is subjected to a positive gate BT stress test (+GBT), the oxide semiconductor The electron density of the conductive film OS is large on the gate insulating film GI side and the silicon oxynitride film SiON side. The silicon oxynitride film SiON side of the oxide semiconductor film OS is The electron density is smaller than that of the other side. The NO molecules are deposited at the interface between the gate insulating film GI and the oxide semiconductor film OS, and at the interface between the oxide semiconductor film OS and the gate insulating film GI. When the silicon dioxide diffuses into the interface between the OS and the silicon oxide nitride film (SiON), the positive gate BT stress test (+GBT) induced electrons on the gate insulating film GI side and back channel side. As a result, the trapped electrons are transported between the gate insulating film GI and the oxide semiconductor film OS and the vicinity of the interface between the oxide semiconductor film OS and the silicon oxynitride film SiON. Therefore, the threshold voltage of the transistor shifts in the positive direction.

[0289] That is, in the silicon oxynitride film in contact with the oxide semiconductor film, the nitrogen oxide contained The lower the concentration of is, the more the fluctuation of the threshold voltage of the transistor can be suppressed. The silicon oxynitride film in contact with the oxide semiconductor film is a protective film in contact with the back channel side. and gate insulating films. By providing the insulating film in contact with the oxide semiconductor film, a highly reliable transistor can be realized. It is possible.

[0290] <2.V O H> Next, oxygen vacancies V, which are one of the vacancies contained in the oxide semiconductor film, O H atom located in (Hereinafter, V O This section explains about H.

[0291] <2-1. Energy and stability of H forms> First, we calculated the energy difference and stability of the forms of H present in the oxide semiconductor film. Here, the oxide semiconductor film is InGaZnO4 (hereinafter referred to as IGZ O(111).

[0292] The structure used in the calculation is a hexagonal unit cell of IGZO(111) divided into two layers along the a-axis and b-axis. The basis was a doubled 84-atom bulk model.

[0293] In the bulk model, one O atom bonded to three In atoms and one Zn atom is assigned to H A model in which atoms are replaced with atoms is prepared (see FIG. 22(A)). In FIG. 22(A), The ab plane of the InO layer viewed from the c axis is shown in Figure 22(B). The region where one O atom bonded to each Zn atom is removed is called an oxygen vacancy V. O As shown in Figure 22( 22(A) and 22(B) are shown by dashed lines. O The H atom located in the V O It is written as H.

[0294] In addition, in the bulk model, one O atom is bonded to three In atoms and one Zn atom. Remove the oxygen vacancies (V O ) is formed. O In the vicinity, one Ga atom is A model was prepared in which an H atom is bonded to an O atom bonded to an atom and two Zn atoms (Figure 22 In addition, in FIG. 22(C), the ab plane of the InO layer is viewed from the c axis. is shown in FIG. 22(D). In FIG. 22(C) and FIG. 22(D), oxygen vacancies V O with dashed lines In addition, oxygen deficiency V O and oxygen deficiency V O In the vicinity, one Ga atom is A model with an H atom bonded to an O atom bonded to a V atom and two Zn atoms is shown. O +H and Write.

[0295] For the above two models, optimization calculations were performed with the lattice constants fixed, and the total energy was calculated as The smaller the total energy value, the more stable the structure.

[0296] The calculations were performed using the first-principles calculation software VASP (The Vienna Ab ini The calculation conditions are shown in Table 4.

[0297] [Table 4]

[0298] The electronic state pseudopotential is PAW (Projector Augmented Wave). The potential generated by the GGA / PBE (General ized-Gradient-Approximation / Perdew-Burke -Ernzerhof) was used.

[0299] The calculated total energies of the two models are shown in Table 5.

[0300] [Table 5]

[0301] From Table 5, V O H is better than V O The total energy is 0.78 eV smaller than +H. V O H is better than V O +H. Therefore, oxygen deficiency (V O ) to Hhara When the atoms approach, the H atoms form oxygen vacancies (V) rather than bonding with O atoms. O ) easily absorbed It is thought that this is the case.

[0302] <2-2. V O Thermodynamic state of H> Next, oxygen vacancies (V O ) with an H atom incorporated in O electrons with respect to the thermodynamic state of H The results of evaluation using state calculation will be explained.

[0303] Defect V in IGZO(111) OFor H, (V O H) + , (V O H) - , ( V O H) 0 The formation energies of each were calculated. O H) + releases one electron (V O H) - indicates a state in which one electron has been captured, and (V O H) 0 is the electron Indicates no movement.

[0304] The calculation was performed using the first-principles calculation software VASP. The calculation conditions are shown in Table 6. The structure of the model used in the calculation is shown in Figure 23. The formation energy was evaluated using Equation 4. The calculation was performed assuming the reaction shown in the figure. The resulting potential is given by the Heyd-Scuseria-Ernzerhof functional. (HSE) DFT hybrid functional (HSE06) was used. Also, the formation of oxygen vacancies In the energy calculation, the dilute limit of the oxygen vacancy concentration is assumed, and the conduction band of the electron and hole, the valence electron The energy was calculated by correcting for excess broadening in the valence band. The valence band shift due to the defect structure is calculated using the average electrostatic potential. This was corrected.

[0305] [Table 6]

[0306]

number

[0307] The formation energies obtained in this calculation are shown in Figure 24(A).

[0308] In Figure 24(A), (V O H) + , (V O H) - , (V O H) 0 The respective formation energies The horizontal axis is the Fermi level, and the vertical axis is the formation energy. The dotted line indicates the O H) + The solid line indicates the formation energy of (V O H) 0 The dashed line indicates the formation energy of (V O H) - The formation energy of V is also shown. O The charge of H is (V O H) + From (V O H) 0 Through (V O H) - The transition level between these two is denoted as ε(+ / -).

[0309] In Figure 24(B), V O The thermodynamic transition levels of H are shown. The energy gap of 4 was 2.739 eV. The valence band energy was 0 e V, the transition level (ε(+ / -)) is 2.62 eV, which is located just below the conduction band. From this, if the Fermi level exists within the energy gap, V O Charge of H The state is always +1, and V O H is thought to be a donor. That is, oxygen vacancy (V O ) and the incorporation of H atoms into the IGZO(111) surface makes it n-type. .

[0310] Next, the carrier (electron) density and defect (VO H) The results of evaluating the relationship between density are shown in Figure 25. vinegar.

[0311] From Figure 25, the defect (V O H) It was found that the carrier density increases as the density increases. Light.

[0312] From the above, V in IGZO(111) O H was found to be a potential donor. Ta, V O It was found that as the density of H increased, IGZO(111) became n-type.

[0313] <3. Model explaining the DOS in oxide semiconductor films and the relationship between elements that cause the DOS > The DOS (De When the density of States is present, a transistor having an oxide semiconductor film The DOS inside the oxide semiconductor film and in the vicinity of the interface is (O), oxygen deficiency (V O ), hydrogen (H), and nitrogen oxides (NO x ) position and bonding relationship The following is an outline of the model.

[0314] In order to provide a transistor with stable electrical characteristics, it is necessary to It is important to reduce the DOS near the interface (high purity intrinsic). To reduce this, it is necessary to reduce oxygen vacancies, hydrogen, and nitrogen oxides. The DOS in the oxide semiconductor film and in the vicinity of the interface, and the oxygen vacancies, hydrogen, and nitrogen oxides The relationship is explained using a model.

[0315] FIG. 26 shows a band structure showing the DOS inside an oxide semiconductor film and in the vicinity of the interface therewith. Hereinafter, the oxide semiconductor film will be described as an oxide semiconductor film containing indium, gallium, and zinc ( The case where IGZO(111) is used will be explained.

[0316] First, in general, there are shallow level DOS (shallow level DOS) In this specification, there are two types of DOS: deep level DOS and deep level DOS. The shallow level DOS is the energy at the bottom of the conduction band. This refers to the DOS between the energy (Ec) and the midgap. Therefore, for example, the shallow level DOS is the conduction band It is located near the lower energy limit. The ep level DOS is the energy of the upper valence band (Ev) and the mid-gap. Therefore, for example, the deep level DOS (deep level el DOS) is located closer to the midgap than the energy of the top of the valence band.

[0317] Shallow level DOS in oxide semiconductor films There are two types of DOS. The first type is shallow level DOS. Near the surface of the oxide semiconductor film (at or near the interface with the insulating film (insulator)) The second shallow DOS (surface shallow DOS) (shallow level DOS) is the DOS inside the oxide semiconductor film (bulk On the other hand, deep level DOS (deep level D The OS includes DOS inside the oxide semiconductor film (bulk deep DOS).

[0318] These DOS may act as follows: First, on the surface of the oxide semiconductor film. The nearby surface shallow DOS is located shallower than the bottom of the conduction band. Therefore, in the surface shallow DOS, charge is easily captured and lost. On the other hand, the bulk shallow DOS inside the oxide semiconductor film can occur due to the oxidation. Compared with the surface shallow DOS near the surface of the semiconductor film, the conduction band Therefore, in the bulk shallow DOS, the charge dissipation Losses are unlikely to occur.

[0319] The elements that cause DOS in an oxide semiconductor film will be described below.

[0320] For example, when a silicon oxide film is formed on an oxide semiconductor film, the silicon oxide film is The indium contained in the semiconductor film penetrates and replaces the silicon, resulting in a shallow D Sometimes an OS (shallow level DOS) is created.

[0321] Furthermore, for example, at the interface between the oxide semiconductor film and the silicon oxide film, The bond between the indium and oxygen contained in the silicon is broken, and a bond between the oxygen and silicon is formed. , the bond energy between silicon and oxygen is higher than the bond energy between indium and oxygen This is due to the fact that silicon (tetravalent) has a higher valence than indium (trivalent). In addition, oxygen contained in the oxide semiconductor film is taken away by silicon, and the oxide semiconductor film is converted into indium and The bonded oxygen sites become oxygen vacant. This phenomenon occurs not only on the surface but also throughout the oxidation The same occurs when silicon penetrates into the semiconductor film. A deep level DOS is formed.

[0322] In addition to silicon, other factors can also break the bond between indium and oxygen. For example, in an oxide semiconductor film containing indium, gallium, and zinc, The bond between indium and oxygen is weaker and more easily broken than the bonds between gallium and zinc and oxygen. Therefore, for example, damage caused by plasma or sputter particles can However, the bond between indium and oxygen can be broken, resulting in oxygen vacancies. This forms a deep level DOS.

[0323] These deep level DOS can trap holes. This creates a hole trap (hole capture center). The oxygen vacancies form a bulk deep DOS inside the semiconductor film. This forms p-DOS, which becomes a factor that causes instability in the oxide semiconductor film.

[0324] In addition, the deep level DOS due to these oxygen vacancies is As will be explained below, a bulk shallow DOS is formed inside the oxide semiconductor film. This will be one of the factors that will lead to this success.

[0325] The oxygen vacancies in the oxide semiconductor film become metastable by capturing hydrogen. It is a deep level DOS that can capture holes. When oxygen vacancies capture hydrogen, a bulk shallow DOS is formed, resulting in a metastable state. This is the state shown in this embodiment. <V O As mentioned in the section Thermodynamic states of H, oxygen vacancies are When the electrons are captured, they become neutral or positively charged. k shallow DOS V O H releases an electron and becomes neutral or positive Because it becomes charged, it affects the characteristics of the transistor.

[0326] In order to prevent oxygen vacancies from adversely affecting the characteristics of transistors, Therefore, it is important to reduce the density of oxygen vacancies. By supplying oxygen, that is, by filling the oxygen vacancies with excess oxygen, the oxygen vacancies in the oxide semiconductor film can be reduced. The density can be reduced. In other words, oxygen vacancies become stable when excess oxygen enters. For example, an insulating film provided inside the oxide semiconductor film or near the interface of the oxide semiconductor film may be formed. When excess oxygen is contained in the film, the excess oxygen fills oxygen vacancies in the oxide semiconductor film. As a result, oxygen vacancies in the oxide semiconductor film can be effectively eliminated or reduced.

[0327] Thus, oxygen vacancies can be transformed into metastable or stable states by either hydrogen or oxygen. This is the state.

[0328] In addition, the NO in the oxide insulating film described in this embodiment x Regarding the transition level of Like, NO x The NO or NO2 captures electrons contained in the oxide semiconductor film. NO x The NO or NO2 is released from the surface sha Since it is one of the low DOS, it is formed in the insulating film near the interface of the oxide semiconductor film. NOx The presence of these elements affects the characteristics of the transistor.

[0329] Furthermore, NO x In order to prevent this from adversely affecting the transistor characteristics, NO contained in the insulating film formed near the interface of the oxide semiconductor film x Reducing the content of becomes important.

[0330] <3-1. Hysteresis degradation model in dark state of transistors having oxide semiconductor films Dell> Next, the mechanism of deterioration of a transistor including an oxide semiconductor film will be described. A transistor having a compound semiconductor film exhibits a photo-induced change when irradiated with light and when not irradiated with light. When light is irradiated, the oxide semiconductor It is possible that the DOS deep inside the membrane (bulk deep DOS) has a large effect. When light is not irradiated, the oxide semiconductor film is irradiated with the insulating film. The DOS at a shallow position (at or near the interface with the w DOS) may be involved.

[0331] First, a transistor including an oxide semiconductor film is not irradiated with light (dark In the dark state, the oxide semiconductor film is The DOS at a shallow position (at or near the interface with the The mechanism of transistor degradation is discussed based on the relationship between charge capture and release due to DOS. Here, the insulating film provided near the interface of the oxide semiconductor film The film will be described using a gate insulating film.

[0332] For a transistor including an oxide semiconductor film, the gate bias Threshold voltage (Vth) when repeatedly performing temperature stress tests The change in the value is shown in Figure 27. From Figure 27, it is possible to perform a positive gate BT stress test (+GBT). This causes the threshold voltage to shift in the positive direction. Next, the negative gate BT stress test When (-GBT) is performed, the threshold voltage changes in the negative direction and returns to the initial value (Initial The threshold voltage is about the same as that of the positive gate BT stress test. When the negative gate BT stress test is repeated alternately, the threshold voltage changes up and down. (hysteresis occurs). In other words, when no light is irradiated, the negative gate When the BT stress test and the positive gate BT stress test are repeatedly performed, the threshold voltage shifts repeatedly in the positive and negative directions, but overall, it remains within a certain range. It was found that the changes were limited to

[0333] The threshold voltage of the transistor in the gate BT stress test under such a dark condition The change is due to the surface shallow DOS near the surface of the oxide semiconductor film. FIG. 28 shows a band structure including an oxide semiconductor film and a band structure corresponding to the oxide semiconductor film. The corresponding flowchart is shown.

[0334] Before the application of gate BT stress (gate voltage (Vg) is 0), the oxide semiconductor film The surface shallow DOS is located at a higher energy level than the Fermi level (Ef). Since the potential is high and no electrons are captured, the material is electrically neutral (step S101 in FIG. 28). The threshold voltage measured in step S101 is the value before the application of gate BT stress. This is the initial value.

[0335] Next, a positive gate BT stress test (dark state) is performed. By this, the conduction band is bent, and the surface sh allow the DOS to be lower than the Fermi level. Electrons are trapped in the surface shallow DOS near the surface of the membrane, and the membrane becomes negatively charged. (Step S102 in FIG. 28).

[0336] Next, the stress is stopped and the gate voltage is set to 0. By setting the gate voltage to 0, the oxide The surface shallow DOS near the surface of the semiconductor film is higher than the Fermi level. However, the surface shal It takes a long time for the electrons trapped in the low DOS to be released. The surface shallow DOS near the surface of the semiconductor film remains negatively charged. At this time, a gate electrode is formed in the channel forming region of the transistor (Step S103 in FIG. 28). In addition to the negative voltage, a negative voltage is continuously applied. To turn on the capacitor, a gate voltage higher than the initial value must be applied, and the threshold voltage The pressure changes in the positive direction. In other words, it may be easier for the device to become normally off.

[0337] Next, a negative gate BT stress test (dark state) was performed, and a negative gate voltage was applied. Applying a negative gate voltage bends the conduction band, forming an oxide semiconductor. The surface shallow DOS near the surface of the membrane becomes even higher energy. Therefore, the surface shallow DOS near the surface of the oxide semiconductor film The captured electrons are released, and the device becomes electrically neutral (step S104 in FIG. 28).

[0338] Next, the stress is stopped and the gate voltage is set to 0. At this time, the surface of the oxide semiconductor film The surface of shallow DOS has already emitted electrons, so Therefore, the threshold voltage changes in the positive direction, As a result, it returns to the initial value before the application of gate BT stress. Repeated gate BT stress tests and positive gate BT stress tests The voltage value changes repeatedly between positive and negative. In the surface shallow DOS near the surface of the film, the positive gate BT The electrons captured during the stress test are released during the negative gate BT stress test. Overall, it was found that the threshold voltage varied within a certain range.

[0339] As described above, the threshold voltage of the transistor in the gate BT stress test under dark conditions The change in voltage is related to the surface shallow DOS near the surface of the oxide semiconductor film. Understanding can explain.

[0340] 3-2. Degradation Model of Transistors Having Oxide Semiconductor Films in Bright States Next, we will explain the degradation mechanism when light is irradiated (bright state). In the bright state, the DOS at a deep position inside the oxide semiconductor film (bulk deep DOS) The mechanism of transistor degradation can be explained based on the relationship between the capture and release of charges by the This can be done.

[0341] Gate BT stress test was performed on a transistor having an oxide semiconductor film under a bright state. The change in threshold voltage (Vth) when this process is repeated is shown in FIG. The threshold voltage (Vth) changes from the initial value (Initial) in the negative direction.

[0342] In Figure 29, first, the initial value of the threshold voltage is set without applying gate BT stress. The results measured in the dark state were plotted. Next, without applying gate BT stress, The threshold voltage was measured in the bright state. As a result, compared with the threshold voltage in the dark state, It was found that the threshold voltage in the bright state shifted significantly in the negative direction. By irradiating light, electrons and holes are generated, and the generated electrons are conductive. One of the reasons is that the gate BT stress is not applied. Even in this case, the threshold voltage of a transistor including an oxide semiconductor film is increased by light irradiation. The pressure shifts to the negative direction, making it easier for the oxide to become normally on. The larger the energy gap of the semiconductor film, or the smaller the DOS in the gap. Therefore, in such a case, the electrons excited by only light irradiation are The change in threshold voltage becomes smaller.

[0343] Next, a negative gate BT stress test (-GBT) was performed while the light was still irradiated. When the SiO2 concentration was increased, the threshold voltage shifted further in the negative direction.

[0344] After that, a positive gate BT stress test (+GBT) was performed while the light was still irradiated. When the ion concentration was increased, the threshold voltage shifted in the positive direction.

[0345] Furthermore, under the condition of light irradiation, a negative gate BT stress test and a positive gate BT stress test were performed. By repeatedly performing the BT stress test, the threshold voltage changes in both the positive and negative directions. While repeatedly changing in a positive direction, the overall trend is gradually changing in a negative direction. I found out.

[0346] The gate BT stress test (positive gate BT and negative gate BT) in the bright state shown above The mechanism by which the threshold voltage of a transistor changes during repeated BT tests This will be explained using the band structures shown in Figures 30 and 31. , bulk deep DOS inside the oxide semiconductor film, and non-bridging oxygen in the gate insulating film. The following explanation will be given using the hole trapping centers (NBOHC1 and NBOHC2). The hole trapping center (NBOHC1) is more oxidized than the non-bridging oxygen hole trapping center (NBOHC2). Non-bridging oxygen hole centers (NBOHCs) located near the interface with the semiconductor film (surface side) is.

[0347] Before applying gate BT stress and irradiating light (gate voltage (Vg) is 0), The bulk deep DOS inside the semiconductor film is located at an energy level higher than the Fermi level (Ef). is low and no holes are trapped, so the semiconductor is electrically neutral (step S111 in FIG. 30). At this time, the threshold voltage measured in the dark state is set as the initial value in the dark state.

[0348] Next, when the oxide semiconductor film is irradiated with light without applying gate BT stress, electrons and positive Holes are generated (step S112 in FIG. 30). The generated electrons are excited into the conduction band, Change the threshold voltage in the negative direction (electrons are omitted in the following steps.) In addition, the generation of holes lowers the quasi-Fermi level (Efp) of holes. The Fermi level (Efp) decreases, and the bulk deep D Holes are trapped in the OS (step S113 in FIG. 30). When light is irradiated without adding any electric field, the threshold voltage shifts in the negative direction compared to when it is in the dark. This may lead to a tendency for the device to become normally on.

[0349] Next, when a negative gate BT stress test is performed with light still irradiated, the electric field gradient The holes trapped in the bulk deep DOS inside the oxide semiconductor film are transferred to the gate The electrons are injected into the non-bridging oxygen hole trap (NBOHC1) in the insulating film (step 30 in Figure 30). S114) Furthermore, the electric field causes the non-bridging oxygen hole trapping centers further inside the gate insulating film. Some of the holes also move to (NBOHC2) (Step S115 in FIG. 31). The non-bridging oxygen hole trap (NBOH) is converted from a non-bridging oxygen hole trap (NBOHC1) to a non-bridging oxygen hole trap (NBOH) in the film. The longer the electric field is applied, the more holes move to C2). The holes in the bridging oxygen hole traps (NBOHC1 and NBOHC2) are positive fixed charges and This changes the threshold voltage in the negative direction, making it easier to become normally on. become.

[0350] For ease of understanding, the light irradiation and negative gate BT stress test are used here. Although the above is shown in separate steps, it should not be construed as being limited to this. For example, Steps S112 to S115 may be considered to be steps occurring in parallel. No.

[0351] Next, a positive gate BT stress test is performed with the light still irradiated. By applying a voltage to the oxide semiconductor film, the electrons are captured in the bulk deep DOS inside the oxide semiconductor film. The trapped holes and the holes of the non-bridging oxygen hole trapping center (NBOHC1) in the gate insulating film As a result, the threshold voltage changes in the positive direction. However, the non-bridging oxygen hole trapping center (NBOHC2) in the gate insulating film Since the location is deep inside the velum, the positive gate BT stress test was performed under bright conditions. Even if the non-bridging oxygen in the gate insulating film is To release the hole from the hole capture center (NBOHC2), the non-bridged acid on the surface side must first be broken down. The electron hole trapping center (NBOHC1) must be transferred to the non-bridged acid in the gate insulating film. Hole transfer from an oxygen hole trap (NBOHC2) to a non-bridging oxygen hole trap (NBOHC1) The movement of the electrons occurs little by little depending on the time the electric field is applied. The amount of change in direction is also small, and it does not return to the initial value.

[0352] In addition, the non-bridging oxygen hole trapping center (NBOHC1) in the gate insulating film and the oxide semiconductor film Hole exchange also occurs between the bulk deep DOS and the internal bulk DOS. In the bulk deep DOS inside the semiconductor film, many holes are already trapped. Therefore, the charge amount of the oxide semiconductor film and the gate insulating film as a whole hardly decreases. There is a possibility that this is the case.

[0353] Next, when the negative gate BT stress test is performed again with the light still irradiated, An electric field gradient occurs, and the holes trapped in the bulk deep DOS inside the oxide semiconductor film , are injected into non-bridging oxygen hole centers (NBOHC1) in the gate insulating film. This allows holes to be trapped in the non-bridging oxygen hole centers (NBOHC2) further inside the gate insulating film. A part of the non-bridging oxygen in the gate insulating film is implanted (Step S117 in FIG. 31). The hole trapping center (NBOHC2) is formed by the hole that entered in step S115 and remains there without being released. Therefore, if more holes are injected, the positive charge will behave as a fixed charge. The number of holes increases further. The threshold voltage is further shifted in the negative direction, resulting in a more normally-on state. It becomes easier to convert.

[0354] Next, when a positive gate BT stress test is performed while the light is still irradiated, the positive gate By applying a voltage to the bulk deep DOS inside the oxide semiconductor film, Trapped holes and holes in non-bridging oxygen hole centers (NBOHC1) in the gate insulating film As a result, the threshold voltage changes in the positive direction. However, the holes in the non-bridging oxygen hole traps (NBOHC2) in the gate insulating film are Therefore, the amount of change in the threshold voltage in the positive direction is small, and the initial value It never goes back to normal.

[0355] As described above, in the bright state, the negative gate BT stress test and the positive gate BT By repeatedly performing stress tests, the threshold voltage changes in both positive and negative directions. As the number of positive and negative changes increases, the overall number of negative changes will gradually increase. It is possible.

[0356] As described above, the threshold voltage of the transistor in the gate BT stress test under bright conditions The change in pressure affects the bulk deep DOS inside the oxide semiconductor film and the gate insulating film. Explained by understanding non-bridging oxygen hole traps (NBOHC1 and NBOHC2) It is possible.

[0357] <3-3. Process model for dehydration, dehydrogenation, and oxygen addition of oxide semiconductor films > In order to provide a transistor with stable electrical characteristics, it is necessary to It is important to reduce the DOS near the interface (high purity intrinsic). We will explain the process model for making oxide semiconductor films highly intrinsic. Dehydration and dehydrogenation of semiconductor films are explained, and then oxygen vacancies (V O ) is filled with oxygen This section explains how oxygenation can be achieved by using

[0358] Before describing the process model for achieving high-purity intrinsic oxide semiconductor film, Explain where the loss is likely to occur. Oxide containing indium, gallium, and zinc In semiconductor films, the bond between indium and oxygen is larger than that between gallium and oxygen and zinc and oxygen. The bond with oxygen is the easiest to break. Therefore, in the following, the bond between indium and oxygen breaks, A model for forming oxygen vacancies will be explained.

[0359] When the bond between indium and oxygen breaks, the oxygen is released and the oxygen that was bonded to indium The oxygen vacancies are caused by the DOS (deep Since the oxygen vacancies in the oxide semiconductor film are unstable, Stabilization is achieved by capturing oxygen or hydrogen. Therefore, hydrogen is present near the oxygen vacancy. The oxygen vacancies trap hydrogen, forming V O H. V O H is the shallow position of the oxide semiconductor film. This creates a shallow level DOS.

[0360] Next, the V of the oxide semiconductor film O When oxygen approaches H, it reacts with V O Remove hydrogen from H In this case, hydrogen is released in the state of a hydroxyl group (OH) (see FIGS. 32(A) and 32(B)). The oxygen moves in the oxide semiconductor film by heat treatment or the like and approaches the oxide semiconductor film.

[0361] Furthermore, the released hydroxyl groups are transferred to the V O As you approach H, V O H to hydrogen The hydrogen atoms are then desorbed into water molecules (HO) and the hydrogen atoms are released (Fig. 32(C) and Fig. 32 As described above, one oxygen atom releases two hydrogen atoms from the oxide semiconductor film. This is called dehydration and dehydrogenation of the oxide semiconductor film. Therefore, the DOS at a shallow position in the oxide semiconductor film is reduced. This results in the formation of a deep level DOS.

[0362] Next, when oxygen approaches an oxygen vacancy in the oxide semiconductor film, the oxygen is captured by the oxygen vacancy. As a result, the oxygen vacancies disappear (see Figures 32(E) and 32(F)). This is called oxygenation of the oxide semiconductor film. p level DOS) can be reduced.

[0363] When the oxide semiconductor film is dehydrated, dehydrogenated, and oxygenated in the above manner, , the shallow level DOS and the deep level DOS of the oxide semiconductor film. This can reduce the DOS (deep level DOS) at the oxide This is called high-purity intrinsic semiconductors.

[0364] Note that the structures and methods shown in this embodiment may be used in conjunction with structures and methods shown in other embodiments and examples. and methods can be used in appropriate combination.

[0365] (Embodiment 3) In this embodiment, an oxide semiconductor film included in a transistor and a Here, we will explain the degradation of transistor characteristics. 1) and carbon as one of the impurities.

[0366] 1. The effect of carbon in IGZO We performed calculations of the electronic state for a model in which C is introduced into IGZO(111).

[0367] For the calculation, the IGZO(111) crystal model (number of atoms: 112) shown in Figure 33(A) was used. Used.

[0368] Here, as a model in which C is mixed into IGZO(111), the results shown in Figure 33(A) and Table 7 are used. In this model, C atoms are placed in the interstitial spaces (1) to (6), and one In atom is replaced by C. A model with one Ga atom replaced with C, a model with one Zn atom replaced with C, and a model with one A model in which O was replaced by C was considered.

[0369] [Table 7]

[0370] <1-1. Model with C atoms placed between lattices> For the models with C placed between the lattices shown in (1) to (6), the total energy after structural optimization is The stable configuration was investigated by comparing the energy. The calculation conditions are shown in Table 8. The band gap tends to be underestimated because the GGA is applied to the numbers.

[0371] [Table 8]

[0372] The results of the structural optimization calculations for the models with C placed between the lattices shown in (1) to (6) are shown in Table 9. show.

[0373] [Table 9]

[0374] The initial position of C was chosen as an interstitial site, but after structural optimization, (1) and (3) , (4) The model in which C is placed between the lattices is shown in Figure 33(C), (CO) O defect The structure was changed to "(CO) O " is the structure shown in Figure 33(B) O shown in Figure 33(C) This means that the carbon atom has been replaced with CO. (CO) O In the defect structure, C bonds with O. C bonds to atoms M1 and M2. O bonds to atoms M3 and M4. In addition, the models (5) and (6) in which C is placed between the lattices are the atoms in IGZO(111). When comparing the energies, the (CO) bond is stronger than the interstitial bond. O Defect structure The results showed that the structure bonded to atoms in IGZO(111) was more stable.

[0375] Next, the model with the lowest energy and the most stable in the calculation (model with C placed in (6)) The structure of the FET is shown in Figure 34(A), and the density of states is shown in Figure 34(B). ) on the horizontal axis, the Fermi level E f is set to 0 eV, and the upper half is up-spin. The lower half shows the down-spin density of states.

[0376] In the structure shown in Figure 34(A), C is bonded to one In and two O. In the model where Si, which is a homologue of C, is placed between the lattices, Si is bonded only to O. Referring to the results, the difference in the bonding state between Si and C is the ionic radius and electronegativity. In addition, in Fig. 34(B), the Elmi level E f When the density of states is integrated between Fermi level E f is located two electrons closer to the vacuum level than the bottom of the conduction band, By placing C at the surface, two electrons are released from the C, and the IGZO(111) becomes n-type. It is possible.

[0377] <1-2. Model in which metal elements are replaced with C> Next, the optimal structure and density of states of a model in which one In atom is replaced by C are shown in Figure 35. In FIG. 35(B), the Fermi level E f is set to 0 eV.

[0378] In the structure shown in Figure 35(A), C is bonded to three Os, forming a triangle with Os as vertices. The shape of the density of states shown in Figure 35(B) is the same as that of the defect-free case. Although it is almost the same, the Fermi level E f is located one electron closer to the vacuum level than the bottom of the conduction band Therefore, by substituting In for C, one electron is released from C, and the IGZO(111) This is thought to be due to the substitution of trivalent In with tetravalent C. .

[0379] Next, the optimal structure and density of states of a model in which one Ga atom is replaced by C are shown in Figure 36. In FIG. 36(B), the Fermi level E f is set to 0 eV.

[0380] In the structure shown in Figure 36(A), C is bonded to four Os, forming a tetrahedron with Os as vertices. The outline of the density of states shown in FIG. 36(B) is similar to that in the case without defects. It is almost the same, but the Fermi level E f is located one electron closer to the vacuum level than the bottom of the conduction band Therefore, by substituting Ga with C, one electron is released from C, and the IGZO(111) This is thought to be due to the substitution of trivalent Ga with tetravalent C. .

[0381] Next, the optimal structure and density of states of a model in which one Zn atom is replaced by C are shown in Figure 37. In FIG. 37(B), the Fermi level E f is set to 0 eV.

[0382] In the structure shown in Figure 37(A), C is bonded to three Os, forming a triangular plane with Os as vertices. The shape of the density of states shown in FIG. 37(B) is almost the same as that in the case without defects. The same, but the Fermi level E fis located two electrons away from the bottom of the conduction band toward the vacuum level. By substituting Zn for C, two electrons are released from C, and IGZO(111) becomes n This is thought to be due to the substitution of divalent Zn with tetravalent C.

[0383] <1-3. Model where O is replaced by C> Next, we examined whether C replaces O. When one O is replaced by C, the O site becomes Considering the combination of metals, there are four locations, so we created a substitution model for each. As a result, O bonded to two Ga atoms and one Zn atom was placed on C. The converted model was energetically stable.

[0384] IGZO(111) formed in an oxygen atmosphere contains sufficient O. To compare the energy required for C to substitute for O in IGZO(111), We consider models (1) and (2) in Table 10. Note that the following two models are mutually After matching the number of atoms to the total energy, the total energy was calculated.

[0385] [Table 10]

[0386] To investigate the stable configuration of C, we assumed IGZO(111) containing a large amount of oxygen. The total energy was calculated using a model that matches the model. The calculation results are shown in Table 11.

[0387] [Table 11]

[0388] In addition, model (1) in Table 10 assumes that C exists as CO2 in IGZO(111). In addition, model (2) in Table 10 is a model in which O in IGZO(111) is replaced with C. It is a converted model.

[0389] As a result of the calculation, the (1) model was found to be approximately 10.8 eV lower and more stable. It is thought that model (1) is more likely to occur than model (2). In other words, if C is replaced with O, It is difficult to replace, and the substitution of O for C is considered unstable.

[0390] As shown in Table 11, the substitution of C with Ga in IGZO(111) is more efficient than that of Ga. It is thought that because the valence is low, substitution with O is unlikely to occur. And "IGZO:C 原子 " indicates that atoms in InGaZnO4 are replaced with C. means.

[0391] From the above results, it is possible that C is located between lattices or that C is located between metal atoms (In, Ga, Zn) It was found that when IGZO(111) was substituted with , it became n-type. C in 11) is thought to be stable, especially when substituted with Ga.

[0392] Note that the structures and methods shown in this embodiment may be used in conjunction with structures and methods shown in other embodiments and examples. and methods can be used in appropriate combination.

[0393] (Fourth embodiment) In this embodiment mode, a semiconductor device having a structure different from that in Embodiment Mode 1 and a manufacturing method thereof will be described. The transistor 50 described in this embodiment is the same as that described in Embodiment 1. The transistor 10 differs from the transistor 10 in that it is a transistor with a top gate structure.

[0394] 1. Transistor structure 38A to 38C show top views and cross-sectional views of the transistor 50. 38(A) is a top view of the transistor 50, and FIG. 38(B) is a diagram showing the structure of the transistor 50 shown in FIG. 38(A) along the dashed line. FIG. 38(C) is a cross-sectional view between the dashed line CD in FIG. 38(A). In FIG. 38(A), for clarity, the substrate 51, the protective film 53, and the gate insulating film 5 9, insulating film 63, etc. are omitted.

[0395] The transistor 50 illustrated in FIG. 38 includes an oxide semiconductor film 55 formed over a protective film 53 and A pair of electrodes 57 and 58 in contact with the oxide semiconductor film 55; A gate insulating film 59 contacting the electrodes 57 and 58 and an oxide semiconductor film 5 5. Also, a protective film 53, a pair of electrodes 57, 58, a gate electrode 61 overlapping with the ... An insulating film 63 may be formed on the gate insulating film 59 and the gate electrode 61 .

[0396] In this embodiment, a film in contact with the oxide semiconductor film 55, typically, the protective film 53 and At least one of the gate insulating films 59 is an oxide insulating film containing nitrogen, and the oxide The oxide insulating film is characterized by having a small amount of defects.

[0397] A typical example of an oxide insulating film containing nitrogen and having few defects is a silicon oxynitride film. , aluminum oxynitride film, etc. The term "silicon nitride oxide film" refers to a film whose composition contains more oxygen than nitrogen. Aluminum nitride oxide refers to a film whose composition contains more nitrogen than oxygen.

[0398] The oxide insulating film containing nitrogen and having few defects is a material that can release nitrogen oxides by heat treatment. (NO x , x is 0 or more and 2 or less, preferably 1 or more and 2 or less), the amount of There are areas and parts where the amount of gas emitted with a mass-to-charge ratio of m / z=17 is large. Typical examples of oxides include nitrogen monoxide, nitrogen dioxide, etc., or oxides containing nitrogen and The oxide insulating film with a small amount of defects is a gas with a mass-to-charge ratio of m / z=30 that is released by heat treatment. The amount of gas with a mass-to-charge ratio of m / z = 17 released by heat treatment is larger than the amount of gas released by heat treatment. Alternatively, the oxide insulating film containing nitrogen and having few defects may be formed by heat treatment. The amount of gas with a mass-to-charge ratio of m / z=46 released by the heat treatment was calculated. It has a region or area where the amount of gas released is large with a mass-to-charge ratio of m / z=17, or it contains nitrogen, The oxide insulating film with a small amount of defects has a mass-to-charge ratio of m / z=30, which is released by heat treatment. The mass released by the heat treatment was calculated from the total amount of gas and gas with a mass-to-charge ratio of m / z = 46. There are regions and areas where a large amount of gas with a charge ratio of m / z=17 is released.

[0399] In addition, the oxide insulating film containing nitrogen and having few defects has a low mass that is released by heat treatment. The amount of gas released with a charge ratio of m / z=30 is below the detection limit, and the mass released by heat treatment The amount of gas released with a charge ratio of m / z=17 is 1×10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 or an oxide insulating film containing nitrogen and having a small amount of defects. The amount of gas with a mass-to-charge ratio of m / z = 46 released by heat treatment was below the detection limit. The amount of gas with a mass-to-charge ratio of m / z = 17 released by heat treatment is 1 × 10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 or containing nitrogen. The oxide insulating film with few defects has a mass-to-charge ratio of m / z=3 The amount of gas released by heat treatment is below the detection limit, and the mass-to-charge ratio m / z=4 The amount of gas released by heat treatment is below the detection limit, and the mass-to-charge ratio m / z=1 The amount of gas released from 7 is 1×10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 Area that is less than or equal to and parts.

[0400] A typical example of a gas with a mass-to-charge ratio of m / z=30 is nitric oxide. Ammonia is a typical example of a gas with a mass-to-charge ratio of m / z=17. A typical example of a gas with z=46 is nitrogen dioxide.

[0401] The oxide insulating film containing nitrogen and having few defects is 100K or less after heat treatment. In the spectrum obtained by ESR measurement, the g value is 2.037 or more and 2.039 or less. The first signal, the second signal with a g value between 2.001 and 2.003, and the g value between 1. A third signal with a g value of 2.037 or more is observed. The first signal is less than or equal to 2.039, and the second signal is between 2.001 and 2.003. The sum of the spin densities of the third signal and the g-values ​​of the third signal with a g-value between 1.964 and 1.966 The total is 1 x 10 18 spins / cm 3 less than 1 × 1017 spins / cm 3 More than 1×10 18 spins / cm 3 is less than.

[0402] In addition, the g value in the ESR spectrum below 100K is 2.037 or more and 2.039 or less. The first signal has a g value of 2.001 or more and 2.003 or less, and the second signal has a g value of 1 The third signal, between 0.964 and 1.966, is nitrogen oxide (NO x , x is between 0 and 2 Representative examples of nitrogen oxides include: , nitric oxide, nitrogen dioxide, etc.

[0403] At least one of the protective film 53 and the gate insulating film 59 in contact with the oxide semiconductor film 55 is As described above, when the content of nitrogen oxides is low, the protective film 53 and the gate insulating film 59 are oxidized. As a result, it is possible to reduce carrier traps at the interface with the compound semiconductor film 55. As a result, it is possible to reduce fluctuations in the threshold voltage of the transistor included in the semiconductor device. This reduces fluctuations in the electrical characteristics of the transistor.

[0404] At least one of the protective film 53 and the gate insulating film 59 is nitrogen-containing as measured by SIMS. The element concentration is 6×10 20 atoms / cm 3 As a result, the protective film Nitrogen oxides are less likely to be generated in at least one of the gate insulating film 53 and the gate insulating film 59. , carriers at the interface between the protective film 53 or the gate insulating film 59 and the oxide semiconductor film 55 It is possible to reduce traps. It is possible to reduce the fluctuation of the low voltage, and the fluctuation of the electrical characteristics of the transistor. It is possible.

[0405] Other configuration details of transistor 50 are described below.

[0406] As the substrate 51, any of the substrates listed as the substrate 11 in the first embodiment can be used as appropriate.

[0407] When the gate insulating film 59 is formed of an oxide insulating film containing nitrogen and having few defects: The protective film 53 is made of an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. Oxides containing more oxygen than the stoichiometric composition can be formed. The insulating film can diffuse oxygen into the oxide semiconductor film by heat treatment. Typical examples include silicon oxide films, silicon oxynitride films, silicon nitride oxide films, and gas oxide films. hafnium oxide film, yttrium oxide film, aluminum oxide film, aluminum oxynitride film Examples include aluminum films.

[0408] The protective film 53 has a thickness of 50 nm or more, preferably 200 nm or more and 3000 nm or less, The thickness of the protective film 53 is set to 300 nm or more and 1000 nm or less. It is possible to increase the amount of released oxygen molecules and also to prevent the protective film 53 and the oxide film formed later from being damaged. It is possible to reduce the interface state at the interface with the compound semiconductor film.

[0409] Here, "a portion of the oxygen is released by heating" means that the amount of oxygen released is converted to oxygen atoms by TDS analysis. The amount of oxygen released is 1.0 × 10 18 atoms / cm 3 or more, preferably 3.0 x 1 0 20 atoms / cm 3In addition, the membrane quality during the TDS analysis The surface temperature is in the range of 100°C to 700°C or 100°C to 500°C. is preferred.

[0410] The oxide semiconductor film 55 is formed in a manner similar to that of the oxide semiconductor film 17 described in Embodiment 1. can be done.

[0411] The pair of electrodes 57 and 58 are formed in the same manner as the pair of electrodes 19 and 20 shown in the first embodiment. It is possible.

[0412] In this embodiment, the pair of electrodes 57 and 58 are formed on the oxide semiconductor film 55 and the gate insulating film 56. However, the insulating film 54 may be provided between the protective film 53 and the oxide semiconductor film 55 .

[0413] When the protective film 53 is made of an oxide insulating film containing nitrogen and having few defects, The insulating film 59 may be, for example, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, or a nitride film. silicon oxide film, aluminum oxide film, hafnium oxide film, gallium oxide film or Ga-Z An n-based metal oxide film or the like may be used, and the oxide semiconductor film may be formed as a stacked layer or a single layer. In order to improve the interface characteristics with 55, at least an oxide semiconductor is used in the gate insulating film 59. The region in contact with the film 55 is preferably formed of an oxide insulating film.

[0414] The gate insulating film 59 is an insulating film having a blocking effect against oxygen, hydrogen, water, etc. By providing the insulating film 54, oxygen can be diffused from the oxide semiconductor film 55 to the outside, and oxygen can be diffused from the outside to the oxide semiconductor film 55. It is possible to prevent the intrusion of hydrogen, water, etc. into the membrane 55. Examples of insulating films having such effects include aluminum oxide films, aluminum oxynitride films, and gallium oxide films. gallium oxide film, yttrium oxide film, yttrium oxide nitride film, hafnium oxide film Examples of suitable oxide films include hafnium oxide nitride films and hafnium oxide nitride films.

[0415] The gate insulating film 59 is made of hafnium silicate (HfSiO x ), nitrogen added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminium Laminate (HfAl x O y N z ), hafnium oxide, yttrium oxide, etc. The use of k-materials can reduce gate leakage of transistors.

[0416] The gate insulating film 59 has a thickness of, for example, 5 nm to 400 nm, more preferably 10 nm. The thickness is set to 300 nm or more, more preferably 15 nm or more and 100 nm or less.

[0417] The gate electrode 61 can be formed in the same manner as the gate electrode 13 shown in the first embodiment. .

[0418] The insulating film 63 has a thickness of 30 nm to 500 nm, preferably 100 nm to 400 nm. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, oxide Aluminum, aluminum oxide nitride, aluminum nitride oxide, aluminum nitride, etc. It may be provided as a laminated layer or a single layer.

[0419] The insulating film 63 contains more oxygen than the stoichiometric composition, as in the protective film 53. The insulating film is made of an oxynitride insulating film containing a large amount of oxygen and an insulating film having blocking properties against oxygen, hydrogen, water, etc. As an insulating film having a blocking effect against oxygen, hydrogen, water, etc., are aluminum oxide films, aluminum oxynitride films, gallium oxide films, and gallium oxynitride films. film, yttrium oxide film, yttrium oxynitride film, hafnium oxide film, hafnium oxynitride film As a result, the gate insulating film 59 or Oxygen is supplied to the oxide semiconductor film 55 through the protective film 53 and / or the gate electrode 54. The interface state between the oxide insulating film 59 and / or the protective film 53 and the oxide semiconductor film 55 can be reduced. In addition, the amount of oxygen vacancies in the oxide semiconductor film 55 can be reduced.

[0420] 2. Transistor manufacturing method Next, a manufacturing method of the transistor in FIG. 38 will be described with reference to FIG. 39 is a cross-sectional view in the channel length direction indicated by the dashed line AB in FIG. 38(A); A method for manufacturing a transistor 50 will be described with reference to a cross-sectional view in the channel width direction indicated by the dashed-dotted line CD. explain.

[0421] As shown in FIG. 39(A), a protective film 53 is formed on a substrate 51. Next, An oxide semiconductor film 55 is formed on the insulating film 51 .

[0422] The protective film 53 is formed by a sputtering method, a CVD method, or the like.

[0423] When an oxide insulating film containing nitrogen and having few defects is formed as the protective film 53, the nitrogen As an example of an oxide insulating film containing silicon and having few defects, a silicon oxynitride film is prepared by CVD. In this case, the source gas is a deposition gas containing silicon. It is preferable to use a gas containing silicon and an oxidizing gas. Examples of oxidizing gases include silane, disilane, trisilane, and fluorinated silane. Examples include dinitrogen chloride and nitrogen dioxide.

[0424] In addition, when an oxide insulating film from which part of oxygen is released by heating is formed as the protective film 53, In this case, the oxide insulating film is formed under conditions where the amount of oxygen in the film-forming gas is high, and part of the oxygen is released by heating. It is preferable to form the film by a sputtering method using oxygen or oxygen and rare gas. Typically, the oxygen concentration in the deposition gas is 6% or more. It is preferable to set it to 00% or less.

[0425] In addition, when an oxide insulating film from which part of oxygen is released by heating is formed as the protective film 53, In this case, an oxide insulating film is formed by the CVD method as an oxide insulating film from which part of the oxygen is released by heating. After forming the oxide insulating film, oxygen is introduced into the oxide insulating film, thereby increasing the amount of oxygen released by heating. Oxygen can be introduced into the oxide insulating film by ion implantation, In this embodiment, an oxide film is formed under the protective film 53. Since no semiconductor film is provided, even if oxygen is introduced into the protective film 53, the introduction of oxygen into the oxide semiconductor film is not Therefore, the oxide semiconductor film is not damaged and the oxide semiconductor film is in contact with the oxide semiconductor film. Oxygen can be introduced into the protective film 53 .

[0426] In addition, when an oxide insulating film is formed as the protective film 53 by a CVD method, hydrogen from the source gas In addition, water may be mixed into the oxide insulating film. After the formation of the compound, it is preferable to perform a heat treatment for dehydrogenation or dehydration.

[0427] The oxide semiconductor film 55 can be formed by a method similar to that of the oxide semiconductor film 17 described in Embodiment 1. It can be used as appropriate.

[0428] In addition, in order to improve the orientation of the crystal parts in the CAAC-OS film, It is preferable to improve the flatness of the surface of the protective film 53, which is a base insulating film. The average surface roughness (Ra) of the protective film 53 is 1 nm or less, 0.3 nm or less, or 0.1 nm or less can.

[0429] As a planarization process for improving the flatness of the surface of the protective film 53, chemical mechanical polishing (CPM) is used. Mechanical Polishing (CMP) processing, dry etching In the vacuum treatment, an inert gas, such as argon gas, is introduced into a vacuum chamber, and the surface to be treated is heated to a cathode. This is a plasma treatment (known as reverse sputtering) that flattens the surface by applying an electric field with a ) or more of the above may be applied.

[0430] Next, as shown in FIG. 39(B), a pair of electrodes 57 and 58 are formed. , 58 may be formed by the same method as that for forming the pair of electrodes 19, 20 shown in the first embodiment. Alternatively, the pair of electrodes 57 and 58 may be formed by a printing method or an ink-jet method. It is possible.

[0431] Next, as shown in FIG. 39(C), a gate insulating film 59 and a gate electrode 61 are formed. An insulating film is formed by a sputtering method, a CVD method, a vapor deposition method, or the like, and a sputtering A conductive film is formed by a photolithography method, a CVD method, a vapor deposition method, etc. Next, a photolithography method is applied to the conductive film. Next, a mask is formed by a etching process. Then, the insulating film and a part of the conductive film are etched using the mask. Then, the gate insulating film 59 and the gate electrode 61 are formed. After that, the mask is removed. do.

[0432] The film that becomes the gate insulating film 59 is formed by a sputtering method, a CVD method, a vapor deposition method, or the like. The film that becomes the electrode 61 is formed by sputtering, CVD, vapor deposition, or the like.

[0433] The film to be the gate insulating film 59 is an oxide insulating film containing nitrogen and having a small amount of defects. When forming the film, the same conditions as those for the protective film 53 can be used appropriately.

[0434] Next, as shown in FIG. 39(D), the substrate 51, the pair of electrodes 57 and 58, and the gate insulating film 5 9 and the gate electrode 61. The insulating film 63 is formed by a sputtering method. The layer can be formed by appropriately using a CVD method, a printing method, a coating method, or the like.

[0435] Next, heat treatment may be performed in the same manner as in Embodiment 1. The temperature of the heat treatment is typically The temperature is preferably 150°C or higher and lower than the substrate strain point, more preferably 250°C or higher and 450°C or lower, and even more preferably The temperature is usually between 300°C and 450°C.

[0436] Through the above steps, a transistor with reduced fluctuation in threshold voltage can be manufactured. Furthermore, a transistor with reduced fluctuation in electrical characteristics can be manufactured.

[0437] Note that the structures and methods shown in this embodiment may be used in conjunction with structures and methods shown in other embodiments and examples. and methods can be used in appropriate combination.

[0438] <Variation 1> A modification of the transistor 50 shown in the fourth embodiment will be described with reference to FIG. The transistor described in the modified example has a gate insulating film or a protective film having a stacked structure. I will explain.

[0439] The transistor 50a shown in FIG. 40A is characterized in that the protective film 53 has a multi-layer structure. Specifically, the protective film 53 is formed by stacking an oxide insulating film 65 and an oxide insulating film 67. The oxide insulating film 65 contains more oxygen than the oxygen required for the stoichiometric composition. The oxide insulating film 67 in contact with the oxide semiconductor film 55 is the protective film 5 of the transistor 50. 3 and / or the gate insulating film 59, It is a small amount of oxide insulating film.

[0440] The oxide insulating film 65 containing more oxygen than the oxygen satisfying the stoichiometric composition is 50 nm or more. Preferably, the thickness is 200 nm or more and 3000 nm or less, more preferably 300 nm or more and 1000 nm or less. The oxide insulating film 65 containing more oxygen than the oxygen that satisfies the stoichiometric composition is By increasing the thickness, the oxide insulating film 65 containing more oxygen than the oxygen that satisfies the stoichiometric composition can be obtained. The amount of oxygen molecules released from the oxide insulating film 67 and the oxide semiconductor can be increased. It is possible to reduce the interface state at the interface of the body film 55.

[0441] As a method for forming the oxide insulating film 65 containing more oxygen than the oxygen that satisfies the stoichiometric composition, For this purpose, an oxide insulating film from which part of the oxygen is released by heating as described for the protective film 53 is appropriately used. It is possible.

[0442] The oxide insulating film 67 is formed between the protective film 53 and the gate insulating film included in the transistor 50. 59, and use the method for forming an oxide insulating film containing nitrogen and having few defects. can be done.

[0443] Note that the oxide insulating film 65 and the oxide insulating film 66 each contain more oxygen than the oxygen that satisfies the stoichiometric composition. An oxide insulating film 67 is formed, an oxide semiconductor film 55 is formed on the oxide insulating film 67, and then heating By the heat treatment, more oxygen than the oxygen required for the stoichiometric composition may be produced. Part of the oxygen contained in the oxide insulating film 65 containing oxygen is oxidized by the oxide insulating film 67 and the oxide semiconductor As a result, the oxide insulating film 67 and the oxide semiconductor film 55 can be diffused in the vicinity of the interface. It is possible to reduce the interface state near the interface of the conductor film 55, and the change in the threshold voltage This can reduce movement.

[0444] The temperature of the heat treatment is typically 150° C. or higher and lower than the substrate distortion point, preferably 250° C. or higher. The temperature is preferably 300°C or higher and 450°C or lower, and more preferably 300°C or higher and 450°C or lower.

[0445] Heat treatment is carried out using rare gases such as helium, neon, argon, xenon, krypton, or It is carried out in an inert gas atmosphere containing nitrogen, or after heating in an inert gas atmosphere, it is heated in an oxygen atmosphere. It should be noted that the inert atmosphere and oxygen atmosphere do not contain hydrogen, water, etc. The treatment time is preferably from 3 minutes to 24 hours.

[0446] In a transistor 50b shown in FIG. 40B, the gate insulating film 59 is formed of an oxide insulating film 69 and a and a nitride insulating film 71 are laminated in this order, and the oxide insulating film 71 is in contact with the oxide semiconductor film 55. The reference numeral 69 is characterized by being an oxide insulating film containing nitrogen and having a small amount of defects.

[0447] The nitride insulating film 71 is the same as the nitride insulating film 29 shown in the first modification of the first embodiment. As a result, the gate insulating film 59 can be physically thickened. Therefore, the decrease in the dielectric strength voltage of the transistor 50b can be suppressed, and the dielectric strength voltage can be improved. As a result, electrostatic breakdown of the semiconductor device can be suppressed.

[0448] <Variation 2> A modification of the transistor 50 shown in Embodiment 4 will be described with reference to FIG. The transistor described in the modification has an oxide semiconductor film between a pair of electrodes and a gate insulating film. An example of this will be explained.

[0449] 41A to 41C show transistors included in a semiconductor device of one embodiment of the present invention. 41(A) is a top view and FIG. 41(B) is a cross-sectional view of 50c. 41(A) shows a cross-sectional schematic view taken along the dashed line AB in FIG. 41(C). A schematic cross-sectional view taken along dashed line CD is shown.

[0450] The transistor 50c shown in FIG. 41(B) and FIG. 41(C) is formed on a protective film 53. an oxide semiconductor film 73 formed on the oxide semiconductor film 73; an oxide semiconductor film 55 formed on the oxide semiconductor film 73; a pair of electrodes 57 and 58 in contact with the oxide semiconductor film 55 and the oxide semiconductor film 73; an oxide semiconductor film 75 in contact with the dielectric film 55 and the pair of electrodes 57 and 58; The gate insulating film 59 is formed on the oxide semiconductor film 55 and overlaps the oxide semiconductor film 55 via the gate insulating film 59. The gate electrode 61 is made of a protective film 53, a pair of electrodes 57 and 58, and an oxide semiconductor. An insulating film 63 may be formed on the body film 75, the gate insulating film 59, and the gate electrode 61. .

[0451] In the transistor 50c, the protective film 53 has a convex portion, and a layer The oxide semiconductor film 73 and the oxide semiconductor film 55 are formed by the above-described steps.

[0452] As shown in FIG. 41B, the oxide semiconductor film 75 is formed on the upper surface of the oxide semiconductor film 55 and The pair of electrodes 57 and 58 are in contact with each other on the top and side surfaces thereof, and as shown in FIG. 41(C), a protective film The side surfaces of the protrusions of the oxide semiconductor film 53, the side surfaces of the oxide semiconductor film 73, and the side surfaces and top surface of the oxide semiconductor film 55 are Treat them kindly.

[0453] As shown in FIG. 41C, the gate voltage Vg is 0.01 V in the channel width direction of the transistor 50c. The electrode 61 is connected to the upper surface of the oxide semiconductor film 55 via the oxide semiconductor film 75 and the gate insulating film 59. and facing the side.

[0454] The gate electrode 61 electrically surrounds the oxide semiconductor film 55. With this structure, The on-state current of the transistor 50c can be increased. This is called the Surrounded Channel (S-Channel) structure. In the channel structure, current flows through the entire oxide semiconductor film 55 (bulk). Since the current flows inside the semiconductor film 55, it is less susceptible to the influence of interface scattering, and therefore a high on-state current can be obtained. Note that when the oxide semiconductor film 55 is made thicker, the on-state current can be improved. It is possible.

[0455] Furthermore, when the channel length and the channel width of a transistor are reduced, a resist mask is used. When a pair of electrodes and an oxide semiconductor film are formed while the substrate is being recessed, The edges of the film may be rounded (curved). The oxide semiconductor film 75 and the gate insulating film 59 formed on the conductor film 55 are provided to have improved coverage. In addition, the electric field concentration that may occur at the ends of the pair of electrodes 57 and 58 can be reduced. This makes it possible to suppress the deterioration of the transistor.

[0456] Furthermore, by miniaturizing transistors, the degree of integration can be increased, resulting in higher density. For example, the channel length of the transistor is set to 100 nm or less, preferably 40 nm or less, and Preferably, the thickness is 30 nm or less, more preferably 20 nm or less, and the thickness of the transistor channel is The channel width is 100 nm or less, preferably 40 nm or less, more preferably 30 nm or less, The channel width of the transistor according to one embodiment of the present invention is preferably 20 nm or less. Even with the above-mentioned reduction, the on-current can be increased by having an S-channel structure It is possible.

[0457] The oxide semiconductor film 73 is made of the same material as the oxide semiconductor film 46 described in the fourth modification of the first embodiment. 39A, the oxide semiconductor film 55 can be formed by Before forming the oxide semiconductor film 73, a film to be the oxide semiconductor film 73 is formed. The oxide semiconductor film 73 and the oxide semiconductor film 55 are processed. A compound semiconductor film 55 can be formed.

[0458] The oxide semiconductor film 75 is formed using the material of the oxide semiconductor film 47 described in Modification 4 of Embodiment 1. In addition, in FIG. 39(C), a film that will become a gate insulating film 59 is formed. Before this, a film that will become the oxide semiconductor film 75 is formed. After forming the film that will become the gate electrode 61, they are processed simultaneously to form an oxide semiconductor. A dielectric film 75, a gate insulating film 59, and a gate electrode 61 can be formed.

[0459] In addition, the oxide semiconductor film 73 has the effect of suppressing the generation of interface states in the oxide semiconductor film 55. For example, the oxide semiconductor film 55 may have a thickness that is smaller than that of the oxide semiconductor film 7. 3, more than 1 time, preferably 2 times or more, more preferably 4 times or more; More preferably, the thickness of the region is six times or more. However, this is not the case when it is not necessary to increase the current. It may have a region whose thickness is equal to or greater than the thickness of the conductive film 55 .

[0460] In addition, like the oxide semiconductor film 73, the oxide semiconductor film 75 also has a structure in which the oxide semiconductor film 55 It is sufficient to have a region with a thickness that does not lose the effect of suppressing the generation of levels. It is sufficient that the oxide semiconductor film 73 has a region whose thickness is equal to or less than that of the oxide semiconductor film 73. If the oxide semiconductor film 75 is thick, the electric field generated by the gate electrode 61 may not easily reach the oxide semiconductor film 55. Therefore, it is preferable to form the oxide semiconductor film 75 thinly. It is sufficient that the thickness of the oxide semiconductor film 7 is thinner than that of the oxide semiconductor film 55. The thickness of 5 is determined according to the voltage at which the transistor is driven, taking into consideration the withstand voltage of the gate insulating film 59. It may be set appropriately.

[0461] To increase the integration density of semiconductor devices, miniaturization of transistors is essential. It is known that the electrical characteristics of transistors deteriorate as the channel width decreases. Shrinking reduces the on-current.

[0462] However, in the transistor of one embodiment of the present invention, as described above, An oxide semiconductor film 75 is formed so as to cover a region where a channel of the transistor 55 is to be formed. The channel region and the gate insulating film 59 are not in contact with each other. The scattering of carriers occurring at the interface between the gate insulating film 55 and the gate insulating film 59 can be suppressed, This allows the on-state current of the transistor to be increased.

[0463] In addition, when the oxide semiconductor film is intrinsic or substantially intrinsic, the oxide semiconductor film There is a concern that the reduction in the number of carriers will result in a decrease in field effect mobility. In one embodiment of the transistor, a gate electric field is applied to the oxide semiconductor film 55 in a direction perpendicular to the gate electrode. In addition, a gate electric field is applied from the side. A gate electric field is applied to the oxide semiconductor film, and current flows through the bulk of the oxide semiconductor film. Therefore, by achieving high purity intrinsic material, the fluctuation of electrical characteristics can be suppressed, and the electric field of the transistor can be reduced. It is possible to improve the effective mobility.

[0464] In the transistor of one embodiment of the present invention, the oxide semiconductor film 55 is formed on the oxide semiconductor film 73. By forming the oxide semiconductor film 55 in a sintered state, it is possible to prevent the formation of an interface state. By providing it between the membranes 73 and 75, it is possible to eliminate the influence of impurities from above and below. Therefore, the oxide semiconductor film 55 has the oxide semiconductor film 73 and the oxide semiconductor The structure is surrounded by the film 75 (and electrically surrounded by the gate electrode 61). In addition to the improvement in the on-state current of the transistor, the threshold voltage can be stabilized. Therefore, the current flowing between the source and drain when the gate electrode voltage is 0V is This reduces the power consumption. Since the voltage is stabilized, the long-term reliability of the semiconductor device can be improved.

[0465] Note that the structures and methods shown in this embodiment may be used in conjunction with structures and methods shown in other embodiments and examples. and methods can be used in appropriate combination.

[0466] (Embodiment 5) In this embodiment, a transistor included in the semiconductor device described in the above embodiment is In this section, one embodiment applicable to an oxide semiconductor film will be described.

[0467] The oxide semiconductor film is an oxide semiconductor having a single crystal structure (hereinafter referred to as a single-crystal oxide semiconductor). , a polycrystalline oxide semiconductor (hereinafter referred to as a polycrystalline oxide semiconductor), a microcrystalline oxide semiconductor oxide semiconductors (hereinafter referred to as microcrystalline oxide semiconductors) and amorphous oxide semiconductors (hereinafter referred to as amorphous oxide semiconductors) The oxide semiconductor film may be formed of one or more of the following: Alternatively, the oxide semiconductor film may be an amorphous oxide semiconductor film. The insulating film may be made of an oxide semiconductor having a conductor and crystal grains.

[0468] Oxide semiconductors are divided into, for example, non-single-crystal oxide semiconductors and single-crystal oxide semiconductors. Alternatively, oxide semiconductors can be divided into crystalline oxide semiconductors and amorphous oxide semiconductors, for example. can be done.

[0469] Note that as a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Alignment d Crystalline Oxide Semiconductor), polycrystalline oxide There are various types of oxide semiconductors, such as amorphous oxide semiconductors, microcrystalline oxide semiconductors, and amorphous oxide semiconductors. Conductors include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors. semiconductors, etc.

[0470] CAAC-OS, microcrystalline oxide semiconductors, and amorphous oxide semiconductors are described below. do.

[0471] First, let me explain about CAAC-OS.

[0472] CAAC-OS is an oxide having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0473] CAAC-OS was analyzed using a transmission electron microscope (TEM). When observed under a crystalline microscope, clear boundaries between the crystals, i.e., crystal boundaries, are clearly visible. It is not possible to confirm the grain boundary. It can be said that AC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0474] For example, as shown in FIG. 73(A), the CAAC-OS A high-resolution TEM image of the cross section is observed. Here, spherical aberration correction (Spherical A) The TEM image is observed using the sphere (aberration corrector) function. High-resolution TEM images using the surface aberration correction function are hereafter referred to as Cs-corrected high-resolution TEM images. The Cs-corrected high-resolution TEM image can be obtained using, for example, an atomic analyzer manufactured by JEOL Ltd. This can be done using a high-resolution analytical electron microscope such as the JEM-ARM200F.

[0475] An enlarged Cs-corrected high-resolution TEM image of area (1) in Figure 73(A) is shown in Figure 73(B). From Figure 73(B), it can be seen that metal atoms are arranged in layers in the crystalline part. Each layer of metal atoms is formed on the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). The shape reflects the unevenness of the surface, and is aligned parallel to the surface on which the CAAC-OS is formed or the top surface. .

[0476] In Figure 73(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines. The size of each pellet is about 1 nm to 3 nm, and the size of the pellets is It can be seen that the size of the gap caused by the tilt is about 0.8 nm. The nanocrystals can also be called nanocrystals (nc).

[0477] Here, from the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 is The layout of 5100 is shown diagrammatically as a structure of stacked bricks or blocks. (See Figure 73(D)). The tilt between the pellets observed in Figure 73(C) The area where this occurs corresponds to the area 5161 shown in FIG.

[0478] Also, for example, as shown in FIG. 74(A), the CAAC- Observe the Cs-corrected high-resolution TEM image of the OS plane. The Cs-corrected high-resolution TEM images of area (2) and area (3) are shown in Figure 74(B), respectively. As shown in Figure 74(C) and Figure 74(D), Figure 74(B), Figure 74(C) and Figure 74(D) ) In the crystal part, metal atoms are arranged in a triangular, quadrangular or hexagonal shape. However, there is no regularity in the arrangement of metal atoms between different crystal parts. I can't.

[0479] Figure 70(A) is a high-resolution TEM image of the cross section of CAAC-OS. ) is a high-resolution TEM image of the cross section of Figure 70(A) which is further enlarged to facilitate understanding. The atomic arrangement is highlighted for clarity.

[0480] Figure 70(C) shows the area surrounded by a circle (diameter approximately 4 mm) between AO-A' in Figure 70(A). From Figure 70(C), it is clear that the c-axis orientation is In addition, the c-axis orientation is different between A-O and O-A', so different graphs are formed. The c-axis angles between the A and A crystals are 14.3° and 16. 6°, 26.4°, and so on. Between these, the angle of the c-axis gradually changes to -18.3°, -17.6°, and -15.9°. It is clear that things are changing.

[0481] When electron diffraction is performed on CAAC-OS, spots (bright spots) indicating orientation are observed. For example, electrons with a thickness of 1 nm to 30 nm are measured on the top surface of the CAAC-OS. When electron diffraction using a line (also called nanobeam electron diffraction) is performed, spots are observed. (See Figure 71(A)).

[0482] The high-resolution TEM images of the cross section and the plane reveal the crystalline part of CAAC-OS. It can be seen that the film has orientation.

[0483] Most of the crystals in CAAC-OS are cubic with sides less than 100 nm. Therefore, the crystal part included in the CAAC-OS has a side length of 10 nm. This also includes cases where the size fits within a cube of less than 5 nm or less than 3 nm. The multiple crystal parts in CAAC-OS are connected to form a single large crystal region. For example, in a high-resolution TEM image of a plane, 2 That's it, 5 μm 2 More than or equal to 1000 μm 2 Crystal regions with more than this size may be observed.

[0484] For example, X-ray diffraction (XRD) was performed on CAAC-OS with InGaZnO4 crystals. Using an X-Ray Diffraction (X-Ray Diffraction) device, the out-of-plane method When analyzed, a peak appears at a diffraction angle (2θ) of approximately 31°, as shown in Figure 75(A). This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the CAAC-OS crystal has a c-axis orientation, and the c-axis is approximately perpendicular to the surface on which the CAAC-OS is formed or the upper surface. It can be seen that it is facing the right direction.

[0485] In addition, the out-of-plane method of CAAC-OS with InGaZnO4 crystals In the structural analysis, in addition to the peak at 2θ around 31°, there is also a peak at 2θ around 36°. The peak at 2θ around 36° is due to the c-axis orientation in some CAAC-OS. This indicates that the CAAC-OS contains crystals that do not have the same structure. It is preferable that the peak is exhibited at 2θ of around 36° and that the peak is not exhibited at 2θ of around 36°.

[0486] On the other hand, in-pl X-rays are incident on the CAAC-OS from a direction approximately perpendicular to the c-axis. When the ane method is used, a peak appears at 2θ around 56°. It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was fixed at approximately 100°, and the analysis was performed while rotating the sample around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears as shown in Figure 75(B). However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ is In the case of scanning, as shown in Figure 75(C), the crystal planes that belong to the (110) plane are Six peaks are observed. Therefore, from the structural analysis using XRD, CAAC-OS It can be seen that the orientation of the a-axis and b-axis is irregular.

[0487] Next, the CAAC-OS (In-Ga-Zn oxide) was subjected to a TEM image from a direction parallel to the sample surface. The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident (selected area transmission electron diffraction) This is also called a folding pattern.) is shown in Figure 76(A). From Figure 76(A), for example, InGaZ Therefore, the electron diffraction pattern is confirmed to be due to the (009) plane of the nO4 crystal. Therefore, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the film is formed. On the other hand, for the same sample, the direction perpendicular to the sample surface The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident from a certain direction is shown in Figure 76( As shown in Figure 76(B), a ring-shaped diffraction pattern is observed. Electron diffraction also revealed that the a-axis and b-axis of the pellets contained in CAAC-OS have orientation. It can be seen that the first ring in Figure 76(B) is made of InGaZnO4 crystals. This is thought to be due to the (010) and (100) planes of the crystal. The second ring in the figure is thought to be due to the (110) plane.

[0488] In this way, the c-axis of each pellet (nanocrystal) is approximately perpendicular to the surface on which it is formed or the upper surface. Since the CAAC-OS is facing in a different direction, It can also be called an oxide semiconductor having nanocrystals.

[0489] From the above, it is considered that the a-axis and b-axis orientations are inconsistent between different crystal regions in CAAC-OS. Although it is regular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. Therefore, the orientation of the crystals is consistent with the high-resolution TEM image of the cross section mentioned above. Each layer of metal atoms arranged in layers is parallel to the ab plane of the crystal.

[0490] The crystalline part is formed when the CAAC-OS film is formed or when a crystallization process such as heat treatment is performed. As mentioned above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS is formed or The orientation is parallel to the normal vector of the upper surface. When the crystal is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS is formed or It may not be parallel to the normal vector of the top surface.

[0491] Furthermore, the distribution of c-axis oriented crystal parts in the CAAC-OS does not need to be uniform. For example, the crystalline part of the CAAC-OS is formed by crystal growth from the vicinity of the top surface of the CAAC-OS. When the crystal is formed, the area near the top surface has a larger proportion of c-axis oriented crystals than the area near the surface on which the crystal is formed. In addition, the CAAC-OS containing impurities may have a high The crystallized area may be altered, forming areas with different proportions of c-axis oriented crystals. be.

[0492] CAAC-OS is an oxide semiconductor with a low concentration of impurities. These are elements other than the main components of oxide semiconductors, such as silicon and transition metal elements. Any element that has a stronger bond with oxygen than the metal elements that make up an oxide semiconductor is By depriving the body of oxygen, the atomic arrangement of oxide semiconductors is disrupted, causing a decrease in crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have atomic radii (or atomic Since the molecular radius is large, when the oxide semiconductor is included, it disrupts the atomic arrangement of the oxide semiconductor. Impurities contained in an oxide semiconductor are carrier to carrier, which causes a decrease in crystallinity. It can be a source of rap and career.

[0493] In addition, the CAAC-OS is an oxide semiconductor with a low density of defect states. Oxygen vacancies in conductors can act as carrier traps or trap hydrogen, increasing the carrier density. It can be a source of rear emissions.

[0494] In addition, transistors using CAAC-OS exhibit improved electrical characteristics when irradiated with visible light or ultraviolet light. The fluctuation is small.

[0495] Furthermore, a semiconductor device including a transistor using the CAAC-OS is not easily damaged even when bent. For this reason, a transistor using a CAAC-OS is used in a flexible semiconductor device. It is preferable that

[0496] Next, a microcrystalline oxide semiconductor will be described.

[0497] Microcrystalline oxide semiconductors have regions where crystals can be confirmed in high-resolution TEM images. The microcrystalline oxide semiconductor has a crystal structure including a region where a crystal part is not clearly visible and a region where a crystal part is not clearly visible. The crystal part contained is between 1 nm and 100 nm, or between 1 nm and 10 nm in size. In particular, fine crystals of 1 nm to 10 nm or 1 nm to 3 nm are often The oxide semiconductor with nanocrystalline structure is called nc-OS (nanocrystalline silicon). The nc-OS is called e Oxide Semiconductor. In high-resolution TEM images, it may not be possible to clearly identify the grain boundaries. It is possible that the origin of the pellets is the same as that of the pellets in CAAC-OS. The crystalline part of nc-OS is sometimes called a pellet.

[0498] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, an XRD device using X-rays with a diameter larger than the crystal part is used for nc-OS. When structural analysis was performed using the out-of-plane method, peaks indicating crystal planes were observed. In addition, for nc-OS, the probe diameter (e.g., 50 When electron diffraction (also called selected area electron diffraction) is performed using an electron beam of 100 nm or more, a halo is On the other hand, the size of the crystalline part is smaller than that of nc-OS. Nanobeam electron diffraction, which uses an electron beam with a probe diameter close to or smaller than the crystal part, Furthermore, when nanobeam electron diffraction is performed on the nc-OS, a circular pattern is observed. In some cases, a bright area (ring-shaped) may be observed. When performing electron diffraction, multiple spots may be observed within a ring-shaped region. (See Figure 71(B)).

[0499] In this way, the crystal orientation of each pellet (nanocrystal) is irregular. , nc-OS has NANC (Non-Aligned nanocrystals) The oxide semiconductor may also be called an oxide semiconductor.

[0500] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. However, the density of defect states in nc-OS is lower than that in amorphous oxide semiconductors. In S, there is no regularity in the crystal orientation between different crystal parts. The defect level density is higher than that of AC-OS.

[0501] The oxide semiconductor may be, for example, an amorphous oxide semiconductor, a microcrystalline oxide semiconductor, or a CAAC. The film may be a laminated film having two or more of the -OS.

[0502] When an oxide semiconductor film has multiple structures, the structure can be resolved by using nanobeam electron diffraction. analysis may be possible.

[0503] FIG. 71(C) shows an electron gun chamber 310, an optical system 312 below the electron gun chamber 310, and an optical system 313. 12, a sample chamber 314, an optical system 316, and a viewfinder 316. An observation room 320, a camera 318 installed in the observation room 320, and a film below the observation room 320. The transmission electron diffraction measurement apparatus shown has a chamber 322. The camera 318 is located inside the observation chamber 320. The film chamber 322 does not necessarily have to be provided.

[0504] FIG. 71(D) shows the internal structure of the transmission electron diffraction measurement device shown in FIG. 71(C). Inside the transmission electron diffraction measurement device, electrons emitted from an electron gun installed in the electron gun chamber 310 The electrons are irradiated onto a substance 328 placed in a sample chamber 314 via an optical system 312. The electrons passing through 28 are projected onto a fluorescent screen 33 installed inside an observation chamber 320 via an optical system 316. On the fluorescent screen 332, a pattern appears according to the intensity of the incident electrons. A transmission electron diffraction pattern can be measured.

[0505] The camera 318 is set facing the fluorescent screen 332 and captures the pattern that appears on the fluorescent screen 332. The center of the lens of the camera 318 and the center of the fluorescent screen 332 can be photographed. The angle between the line passing through the center and the upper surface of the fluorescent screen 332 is, for example, 15° or more and 80° or less. , 30° to 75° or 45° to 70°. The smaller the angle, the The transmission electron diffraction pattern taken by MERA318 is highly distorted. If this angle is known, it is possible to correct distortions in the obtained transmission electron diffraction pattern. There are cases where the camera 318 may be installed in the film chamber 322. For example, The camera 318 is installed in the film chamber 322 so as to face the incident direction of the electrons 324. In this case, a transmission electron diffraction pattern with little distortion is captured from the rear surface of the fluorescent screen 332. It is possible.

[0506] In the sample chamber 314, a holder for fixing a substance 328 as a sample is installed. The holder is constructed to be transparent to electrons passing through the material 328. For example, the holder may have a function to move the substance 328 in the X-axis, Y-axis, Z-axis, etc. The movement function can be, for example, 1 nm to 10 nm, 5 nm to 50 nm, or 10 nm or more. Ranges such as 100nm or less, 50nm to 500nm, and 100nm to 1μm. These ranges are optimal ranges depending on the structure of the substance 328. Just set it as follows.

[0507] Next, the transmission electron diffraction pattern of the substance is measured using the above-mentioned transmission electron diffraction measurement device. This article explains how to do this.

[0508] For example, as shown in FIG. 71(D), the irradiation position of the electron 324, which is a nanobeam, in the material By changing the position (scanning), we can observe how the structure of a material changes. In this case, if the substance 328 is a CAAC-OS film, as shown in FIG. If the material 328 is an nc-OS film, the diffraction pattern shown in Figure 71 ( A diffraction pattern similar to that shown in B) is observed.

[0509] By the way, even if the material 328 is a CAAC-OS film, it may be partially an nc-OS film. Therefore, the quality of the CAAC-OS film can be evaluated. is the ratio of the area where the diffraction pattern of the CAAC-OS film is observed in a certain range (CA It can be expressed as follows: For example, a high-quality CAAC-OS film can be If so, the CAAC conversion rate is 50% or more, preferably 80% or more, and more preferably 90% or more. % or more, and more preferably 95% or more. The area where CAAC is observed is referred to as the non-CAAC rate.

[0510] As an example, immediately after film formation (denoted as as-sputtered), or in an atmosphere containing oxygen The top surface of each sample with the CAAC-OS film after the heat treatment at 450°C in air was scanned. Transmission electron diffraction patterns were acquired while scanning at a speed of 5 nm / s for 60 seconds. The diffraction pattern was observed while scanning, and the observed diffraction pattern was captured as a still image every 0.5 seconds. The CAAC rate was calculated by converting the electron beam into the probe diameter of 1n. The nano-beam electron beam of 1000 nm was used. The same measurements were carried out on six samples. The AC conversion rate was calculated using the average value of six samples.

[0511] The CAAC conversion rate for each sample is shown in Figure 72(A). The AAC conversion rate was 75.7% (non-CAAC conversion rate was 24.3%). The CAAC content of the treated CAAC-OS membrane was 85.3% (non-CAAC content was 14.7%). It can be seen that the CAAC conversion rate is higher after heat treatment at 450°C than immediately after film formation. That is, the non-CAAC rate is reduced by heat treatment at a high temperature (for example, 400°C or higher). It can be seen that the CAAC conversion rate increases (the CAAC conversion rate increases). It can be seen that a CAAC-OS film with a high CAAC content can be obtained even with the SiO2 solution.

[0512] Here, most of the diffraction patterns different from those of the CAAC-OS film are similar to those of the nc-OS film. The amorphous oxide semiconductor film was not observed in the measurement area. Therefore, the heat treatment did not produce a region with a structure similar to that of the nc-OS film. However, it is suggested that the structure of the adjacent region influences the rearrangement and formation of CAAC. .

[0513] Figure 72(B) and Figure 72(C) show the CAAC- High-resolution TEM images of the planar surface of the OS film. Compare Figure 72(B) with Figure 72(C). This shows that the CAAC-OS film after the 450°C heat treatment has a more uniform film quality. That is, the quality of the CAAC-OS film is improved by heat treatment at high temperatures. I understand.

[0514] This measurement method makes it possible to analyze the structure of oxide semiconductor films with multiple structures. This may be the case.

[0515] Next, the amorphous oxide semiconductor will be described.

[0516] Amorphous oxide semiconductors are oxides in which the atomic arrangement within the film is irregular and does not have crystalline parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0517] In amorphous oxide semiconductors, no crystalline parts can be observed in high-resolution TEM images.

[0518] When structural analysis is performed on amorphous oxide semiconductors using an XRD device, out-of-p In the analysis by the Lane method, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductor, a halo pattern is observed. When nanobeam electron diffraction is performed on the specimen, no spots are observed, but a halo pattern is observed. will be done.

[0519] There are various views on amorphous structures. For example, A structure that does not have this property is called a completely amorphous structure. The distance between the nearest neighboring atoms or the second nearest neighboring atoms is also called the structure. A structure that has order at the interface but does not have long-range order is sometimes called an amorphous structure. Therefore, according to the strictest definition, an oxide semiconductor that has even a slight degree of order in its atomic arrangement is called a non-metallic oxide semiconductor. Furthermore, it cannot be called an crystalline oxide semiconductor. Therefore, since the semiconductor has crystalline parts, it cannot be called an amorphous oxide semiconductor. For example, CAAC-OS and nc-OS are used as amorphous oxide semiconductors or completely amorphous It cannot be called an oxide semiconductor.

[0520] Note that oxide semiconductors have a structure that exhibits physical properties between those of nc-OS and amorphous oxide semiconductors. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor. Body(a-like OS:amorphous-like Oxide Semicon ductor).

[0521] In a-like OS, voids (also called voids) are observed in high-resolution TEM images. In addition, crystals can be clearly seen in high-resolution TEM images. and regions where no crystalline portions can be identified.

[0522] The following describes how the influence of electron irradiation varies depending on the structure of the oxide semiconductor.

[0523] a-like OS, nc-OS, and CAAC-OS were prepared. It is n-Ga-Zn oxide.

[0524] First, high-resolution cross-sectional TEM images of each sample are acquired. It can be seen that all the materials have crystalline parts.

[0525] Furthermore, the size of the crystal part of each sample is measured. Figure 77 shows the crystal part of each sample (22 locations). This is an example of investigating the change in the average size of the a-like OS. Sample B has an nc-OS, and sample C has a CAAC-OS. It can be seen that the crystalline portion of the like OS grows in size according to the cumulative amount of electron irradiation. Specifically, as shown in FIG. 77 (1), the initial stage of TEM observation was 1.2n The crystal, which was about m in size, grew to a cumulative irradiation dose of 4.2 × 10 8 e - / nm 2 In 2 On the other hand, the nc-OS and CAAC -OS: The cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 Until It can be seen that within this range, no change in the size of the crystals is observed regardless of the cumulative electron irradiation dose. Specifically, as shown in (2) in Figure 77, regardless of the course of TEM observation, the crystal The size of the part is about 1.4 nm. Regardless of the TEM observation process, the size of the crystals was found to be about 2.1 nm. do.

[0526] Thus, a-like OS can be formed by irradiating it with a small amount of electrons, the same level as observed by TEM. On the other hand, in the case of high-quality nc-OS and In the case of CAAC-OS, crystallization due to minute electron irradiation, such as that observed by TEM, is hardly observed. I know it's hardly visible.

[0527] The size of the crystalline parts of a-like OS and nc-OS was measured using a high-resolution TE For example, InGaZnO4 crystals have a layered structure, and There are two Ga-Zn-O layers between the InGaZnO layers. The unit cell of the InGaZnO4 crystal is It has three In-O layers and six Ga-Zn-O layers, totaling nine layers layered in the c-axis direction. Therefore, the spacing between adjacent layers is determined by the (009) plane grid. This is approximately the same as the interplanar spacing (also called the d value), and crystal structure analysis has revealed that the value is 0.29 nm. Therefore, we focused on the lattice fringes in high-resolution TEM images and investigated the spacing of the lattice fringes. In the area where the thickness is 0.28 nm or more and 0.30 nm or less, each lattice fringe is InGa It corresponds to the ab plane of the ZnO4 crystal.

[0528] Furthermore, the density of oxide semiconductors may differ depending on the structure. If the composition of the crystal is known, the density can be determined by comparing it with the density of a single crystal of the same composition. For example, the density of a single crystal can be estimated by The density of ke OS is 78.6% or more and less than 92.3%. In contrast, the density of nc-OS and CAAC-OS was 92.3% or more and less than 100%. Note that an oxide semiconductor having a density of less than 78% of the density of a single crystal can be formed by film formation. This in itself is difficult.

[0529] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atom In oxide semiconductors that satisfy the [atomic ratio], single crystal InGaZnO4 with a rhombohedral crystal structure The density of 3 Therefore, for example, In:Ga:Zn=1:1:1 In oxide semiconductors that satisfy the atomic ratio, the density of a-like OS is 5.0 g / cm m 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1:1[ In oxide semiconductors that satisfy the atomic ratio, the density of the nc-OS and the density of the CAAC-OS are The strength is 5.9g / cm 3 More than 6.3g / cm 3 It will be less than.

[0530] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions may be used in any proportion. By combining single crystals with the desired composition, the density corresponding to the single crystal of the desired composition can be calculated. The density of a single crystal of a desired composition varies depending on the ratio of the single crystals of different compositions combined. However, the density should be calculated using as few types of single crystals as possible. It is preferable to calculate it by combining the above.

[0531] The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or a microcrystalline oxide semiconductor. The layer may be a laminated film having two or more of a compound semiconductor and a CAAC-OS.

[0532] Oxide semiconductors with low impurity concentrations and low defect state densities (few oxygen vacancies) Therefore, such oxide semiconductors can be used as high-purity intrinsic or CAAC-OS and nc-OS are called high-purity intrinsic oxide semiconductors. The impurity concentration is lower than that of amorphous oxide semiconductors and amorphous oxide semiconductors, and the density of defect states is lower. That is, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor is likely to be obtained. Therefore, transistors using CAAC-OS or nc-OS have a negative threshold voltage. In addition, the electrical characteristics are rarely such that A highly pure or substantially intrinsic oxide semiconductor has few carrier traps. Transistors using AC-OS or nc-OS have small fluctuations in their electrical characteristics and are highly reliable. The charge trapped in the carrier traps in the oxide semiconductor is However, it takes a long time to release the charge, and it may behave as if it were a fixed charge. Therefore, a transistor using an oxide semiconductor with a high impurity concentration and a high density of defect states The electrical characteristics may become unstable.

[0533] <Film formation model> An example of a film formation model for CAAC-OS and nc-OS will be described below.

[0534] FIG. 78(A) shows the formation of a CAAC-OS film by sputtering. Schematic diagram of the inside of the membrane chamber.

[0535] The target 5130 is glued to a backing plate. A plurality of magnets are arranged at positions facing the target 5130 through the magnets. The magnetic field is generated by a number of magnets. The arrangement and configuration of the magnets are as described above. Please refer to the description of the film deposition chamber mentioned above. The ring method is called a magnetron sputtering method.

[0536] The target 5130 has a polycrystalline structure, and each grain contains a cleavage plane.

[0537] As an example, the cleavage surface of target 5130 having In-Ga-Zn oxide is described. FIG. 79(A) shows the crystal structure of InGaZnO4 contained in the target 5130. In addition, in FIG. 79(A), the c-axis is directed upward, and the InGaZn This is the structure of an O4 crystal.

[0538] As shown in Figure 79(A), in two adjacent Ga-Zn-O layers, It can be seen that the oxygen atoms are arranged close to each other. By doing so, two adjacent Ga-Zn-O layers repel each other. The aZnO4 crystal has a cleavage plane between two adjacent Ga-Zn-O layers.

[0539] The substrate 5120 is disposed so as to face the target 5130, and the distance therebetween is d( The target-substrate distance (also called the TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the film deposition chamber is 0.02m or more and 0.5m or less. oxygen, argon, or a gas mixture containing 5% or more by volume of oxygen) and The pressure is controlled to 1 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a voltage above a certain level to the target 5130, a discharge begins and plasma is generated. It is confirmed that a high density plasma region is generated near the target 5130 by the magnetic field. In the high density plasma region, the deposition gas is ionized, and ions 5101 The ions 5101 are, for example, positive ions of oxygen (O + ) and argon cations ( Ar + ) etc.

[0540] The ions 5101 are accelerated toward the target 5130 by the electric field, and eventually At this time, flat or pellet-shaped sputter particles are ejected from the cleavage plane. The pellets 5100a and 5100b are separated and knocked out. The pellet 5100a and the pellet 5100b are formed by the impact of the collision of the ion 5101. distortion may occur.

[0541] The pellet 5100a is a flat plate or pellet having a triangular, for example, equilateral triangular, plane. The pellet 5100b is a sputtered particle having a hexagonal shape, for example, a regular hexagonal plane. The pellets 5100a and 5100b are sputtered particles in the form of plates or pellets. Sputter particles in the form of flat or pellets, such as pellets 5100b, are collectively called pellets. The pellet 5100 is called 5100 (see Figure 73(D)). The planar shape of the pellet 5100 is triangular, hexagonal, and The shape is not limited to a polygon, but may be a shape made up of multiple triangles. , two triangles (e.g., equilateral triangles) may join to form a quadrilateral (e.g., a rhombus). be.

[0542] The thickness of the pellet 5100 is determined depending on the type of deposition gas, etc. The reason for this will be explained later. It is preferable that the thickness of the pellet 5100 is uniform. Thin pellets are preferable to thick cubes. The thickness of the PET 5100 is 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. For example, the pellet 5100 has a width of 1 nm or more and 3 nm or less, preferably The pellet 5100 is the one shown in FIG. ) corresponds to the initial nucleus described in (1). For example, the target 5 having In-Ga-Zn oxide When ions 5101 are collided with the Ga-Zn-O A pellet 5100 having three layers, a Ga-Zn-O layer, an In-O layer, and a Ga-Zn-O layer, pops out. FIG. 79(C) shows the structure of the pellet 5100 when observed from a direction parallel to the c-axis. Therefore, the pellet 5100 consists of two Ga-Zn-O layers (pans) and an In It can also be called a nano-sized sandwich structure having a -O layer (layer).

[0543] The pellet 5100 receives a charge as it passes through the plasma, causing the sides to become negative or The pellet 5100 has oxygen atoms on the side, and the oxygen atoms In this way, the sides can be charged with the same polarity, The loads repel each other, allowing the flat shape to be maintained. When S is an In-Ga-Zn oxide, the oxygen atoms bonded to the indium atoms are negatively charged. Or, the compound bonded to an indium atom, a gallium atom, or a zinc atom may The oxygen atoms may become negatively charged. Also, as the pellet 5100 passes through the plasma, When this happens, the atoms bond with indium, gallium, zinc, and oxygen, etc., and grow. This corresponds to the difference in size between (2) and (1) in Figure 77 above. Here, when the substrate 5120 is at room temperature, the pellet 5100 does not grow any further. As a result, it becomes nc-OS (see Figure 78(B)). Since the temperature at which film formation is possible is around room temperature, Therefore, even if the substrate 5120 has a large area, the nc-OS film can be formed. In order to grow 5100 in plasma, the film formation power in the sputtering method must be increased. It is effective to increase the film formation power to stabilize the structure of the pellet 5100. It is possible.

[0544] As shown in Figures 78(A) and 78(B), for example, the pellet 5100 is a plasma It flies like a kite through the air and flutters up to the top of the board 5120. Since the pellet 100 is electrically charged, it will be attracted to an area where other pellets 5100 are already deposited. Here, on the upper surface of the substrate 5120, a repulsive force is generated in a direction parallel to the upper surface of the substrate 5120. A horizontal magnetic field (also called a horizontal magnetic field) is generated between the substrate 5120 and the target 5120. Since a potential difference is applied between the substrate 5120 and the target 5130, Therefore, the pellet 5100 is on the upper surface of the substrate 5120. , and is subjected to a force (Lorentz force) due to the action of a magnetic field and an electric current. This can be understood using Gu's left-hand rule.

[0545] The pellet 5100 has a larger mass than an atom. In order to move the surface, it is important to apply some kind of force from the outside. One of these forces is It may be a force generated by the action of a magnetic field and an electric current. In order to increase the force, the upper surface of the substrate 5120 is The magnetic field is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and more preferably Alternatively, it is preferable to provide an area where the resistance is 50 G or more. A magnetic field oriented parallel to the top surface of the plate 5120 is 1. 5 times or more, preferably 2 times or more, more preferably 3 times or more, and even more preferably 5 times or more. It is advisable to set up an area where

[0546] At this time, the magnet and / or the substrate 5120 may move relatively or rotate. By rotating the substrate 5120, the direction of the horizontal magnetic field on the upper surface of the substrate 5120 continues to change. Therefore, on the upper surface of the substrate 5120, the pellet 5100 is subjected to forces in various directions, It can move in various directions.

[0547] Also, when the substrate 5120 is heated as shown in FIG. 78(A), the pellet 510 0 and the substrate 5120, the resistance due to friction etc. is small. The pellet 5100 glides over the top surface of the substrate 5120. The transfer occurs with the flat surface facing the substrate 5120. When the particles reach the side of the pellet 5100, the sides are joined together. The oxygen atom on the side of 00 is released. The released oxygen atom causes the Since oxygen vacancies may be filled, a CAAC-OS with a low density of defect states is obtained. The temperature of the upper surface of the plate 5120 is, for example, 100°C or higher and lower than 500°C, or 150°C or higher and 450°C. or 170° C. or higher and lower than 400° C. That is, when the substrate 5120 has a large area, CAAC-OS films can be formed even in such cases.

[0548] Furthermore, when the pellet 5100 is heated on the substrate 5120, the atoms are rearranged, The structural distortion caused by the collision of the ions 5101 is relaxed. Pellet 5100 becomes almost single crystal. Even if the 5100 is heated after bonding, the pellet 5100 itself hardly expands or contracts. Therefore, the gaps between the pellets 5100 widen, and the grain boundaries and other No defects or crevasses will form.

[0549] In addition, the CAAC-OS is not made of a single-crystal oxide semiconductor. The aggregates of pellets 5100 (nanocrystals) resemble bricks or blocks stacked on top of each other. In addition, there are no grain boundaries between them. Even if deformation such as shrinkage occurs in CAAC-OS due to subsequent heating or bending, local stress It is therefore possible to provide a flexible semi-conductor. The structure is suitable for semiconductor devices. nc-OS does not contain pellet 5100 (nanocrystal). The arrangement is like an orderly stack.

[0550] When the target is sputtered with ions, not only pellets but also zinc oxide etc. fly out. Since zinc oxide is lighter than the pellets, it may reach the top surface of the substrate 5120 first. And it reaches 0.1nm to 10nm, 0.2nm to 5nm, or 0. A zinc oxide layer 5102 having a thickness of 5 nm or more and 2 nm or less is formed. A cross-sectional schematic diagram is shown in FIG.

[0551] As shown in FIG. 80(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are deposited. The pellets 5105c are arranged so that their sides are in contact with each other. After being deposited on pellet 5105b, the pellet 510 slides on pellet 5105b. In another aspect of FIG. 05a, a plurality of particles 51 ejected from the target along with zinc oxide. The substrate 5120 is heated and crystallized to form a region 5105a1. The particles 5103 may include oxygen, zinc, indium, and gallium, among others.

[0552] Then, as shown in FIG. 80(B), the region 5105a1 is assimilated with the pellet 5105a. The pellet 5105c has a side surface that is the same as that of the pellet 5105a. It is arranged so as to be in contact with another side surface of 105b.

[0553] Next, as shown in FIG. 80(C), a pellet 5105d is further added to the pellet 5105a2. After being deposited on pellet 5105a2 and pellet 5105b, It slides on the other side of the pellet 5105c. The pellet 5105e slides on the zinc oxide layer 5102.

[0554] As shown in FIG. 80(D), the pellet 5105d has a side surface similar to that of the pellet 51. The pellet 5105e is placed so that its side faces the pellet 5105a2. Also, the other side of the pellet 5105d is placed in contact with the other side of the pellet 5105c. At the surface, a plurality of particles 5103 that have been ejected from the target together with zinc oxide are deposited on the substrate 51. The film is crystallized by heating at 20 to form a region 5105d1.

[0555] As described above, the piled pellets are arranged so that they come into contact with each other, and the pellets are Crystal growth occurs, forming a CAAC-OS on the substrate 5120. CAAC-OS has larger pellets than nc-OS. This corresponds to the difference in size between (3) and (2) in Figure 77.

[0556] In addition, the gaps between the 5100 pellets are extremely small, making it appear as if they were one large pellet. Large pellets may form. Large pellets have a single crystal structure. The pellet size, as viewed from the top, is 10 nm to 200 nm, 15 nm to 100 nm m or less, or 20 nm to 50 nm. If the channel formation area of ​​the pellet is smaller than that of the large pellet, the single crystal is used as the channel formation area. In addition, the pellets can be enlarged to allow for the formation of a region with a crystalline structure. The transistor has a channel forming region, a source region, and a drain region each having a single crystal structure. In some cases, a region can be used.

[0557] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. By doing so, it may be possible to improve the frequency characteristics of the transistor.

[0558] Based on the above model, it is assumed that the pellet 5100 is deposited on the substrate 5120. Therefore, unlike epitaxial growth, if the surface on which the film is to be formed does not have a crystalline structure, It can be seen that CAAC-OS film formation is possible even in the case of a substrate 5120. Even if the structure of the top surface (surface to be formed) is amorphous (e.g., amorphous silicon oxide), It is possible to form an AC-OS film.

[0559] In addition, even if the upper surface of the substrate 5120 on which the formation is performed is uneven, the CAAC-OS It can be seen that the pellets 5100 are arranged along the shape of the substrate 5120. If the surface is atomically flat, the pellet 5100 will be placed on a flat surface that is parallel to the ab plane. Since the layers are aligned toward each other, a layer with uniform thickness, flatness, and high crystallinity is formed. By stacking these layers n times (n is a natural number), CAAC-OS can be obtained. Cut.

[0560] On the other hand, even if the upper surface of the substrate 5120 has irregularities, the CAAC-OS can be easily formed by the pellet 51 The structure is made up of n layers (n is a natural number) of layers in which 00 are arranged along the unevenness. Because the surface of the CAAC-OS is uneven, gaps tend to form between the pellets. However, intermolecular forces act between the pellets 5100, so even if there are irregularities, the pellets Therefore, even if there are irregularities, high crystallinity can be achieved. The CAAC-OS may have the following characteristics:

[0561] Therefore, CAAC-OS does not require laser crystallization and can be grown on large-area glass substrates. Even if the thickness is small, a uniform film can be formed.

[0562] Since the CAAC-OS film is formed using this model, the sputtered particles are distributed evenly across the film thickness. It is preferable that the sputtered particles are in the form of thick dices. In this case, the surface facing the substrate 5120 is not uniform, and the thickness and crystal orientation cannot be made uniform. There is.

[0563] The film formation model shown above allows for highly crystalline films to be formed even on a surface with an amorphous structure. Therefore, a CAAC-OS having the desired properties can be obtained.

[0564] Note that the structures and methods shown in this embodiment may be used in conjunction with structures and methods shown in other embodiments and examples. and methods can be used in appropriate combination.

[0565] (Sixth embodiment) In this embodiment, a structural example of a display panel according to one embodiment of the present invention will be described.

[0566] <Configuration example> FIG. 42A is a top view of a display panel of one embodiment of the present invention, and FIG. 42B is a top view of a display panel of one embodiment of the present invention. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display panel according to one embodiment of the present invention. 42C is a circuit diagram illustrating a display panel according to one embodiment of the present invention. A circuit for explaining a pixel circuit that can be used when an organic EL element is applied to a pixel. Figure.

[0567] The transistors disposed in the pixel portion can be formed according to the above-described embodiment modes. In addition, since the transistor can be easily made into an n-channel type, the n-channel transistor in the driver circuit can be easily made into an n-channel type. A part of the driver circuit can be configured with a panel-type transistor, and the transistors in the pixel section can be In this way, the transistor shown in the above embodiment mode is formed in the pixel portion and the driver circuit. By using the capacitor, a highly reliable display device can be provided.

[0568] An example of a block diagram of an active matrix display device is shown in Figure 42(A). On this substrate 900, a pixel portion 901, a first scanning line driving circuit 902, a second scanning line driving circuit 903, and a The pixel portion 901 has a signal line driver circuit 903 and a signal line driver circuit 904. A plurality of scanning lines are arranged extending from a first scanning line driving circuit 902 and a second scanning line driving circuit 904. The scanning lines are arranged extending from the second scanning line driving circuit 903. In the area, pixels each having a display element are arranged in a matrix. The substrate 900 of the device is a flexible printed circuit (FPC) or the like. It is connected to a timing control circuit (also called a controller or control IC) via a connection. do.

[0569] In FIG. 42A, a first scanning line driver circuit 902, a second scanning line driver circuit 903, a signal The line driver circuit 904 is formed on the same substrate 900 as the pixel portion 901. The number of components such as drive circuits to be provided is reduced, which contributes to cost reduction. 900 If a drive circuit is provided externally, the wiring must be extended, and the number of connections between the wiring increases. When a driver circuit is provided on the same substrate 900, the number of connections between the wirings can be reduced. This can improve reliability or yield.

[0570] <LCD panel> An example of the circuit configuration of a pixel is shown in Figure 42(B). Here, a VA type liquid crystal display panel 1 shows a pixel circuit that can be applied to the pixel of FIG.

[0571] This pixel circuit can be applied to a configuration in which one pixel has a plurality of pixel electrodes. The pixel electrodes are connected to different transistors, and each transistor can be driven by a different gate signal. This allows the individual pixel voltages of the multi-domain designed pixels to be The signals applied to the poles can be controlled independently.

[0572] The gate wiring 912 of the transistor 916 and the gate wiring 913 of the transistor 917 are separated so that different gate signals can be applied. The source or drain electrode 914, which functions as a 17. Transistors 916 and 917 are used in common in the above embodiment. The transistors described in the following embodiments can be used as appropriate. A display panel can be provided.

[0573] A first pixel electrode electrically connected to the transistor 916 and a second pixel electrode electrically connected to the transistor 917 The shape of the second pixel electrode that is electrically connected to the first pixel electrode and the second pixel electrode will be described. The first pixel electrode has a V-shaped shape and is separated by a slit. The second pixel electrode is formed so as to surround the outside of the first pixel electrode.

[0574] The gate electrode of the transistor 916 is connected to the gate wiring 912, and the gate electrode of the transistor 917 is connected to the gate wiring 912. The gate electrode of the gate electrode 912 is connected to the gate wiring 913. 3, different gate signals are applied to transistors 916 and 917. By varying the voltage, the orientation of the liquid crystal can be controlled.

[0575] Also, a capacitance wiring 910, a gate insulating film functioning as a dielectric, and a first pixel electrode or A storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode.

[0576] The multi-domain structure has a first liquid crystal element 918 and a second liquid crystal element 919 in one pixel. The first liquid crystal element 918 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer therebetween. The second liquid crystal element 919 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer therebetween.

[0577] Note that the pixel circuit shown in FIG. 42(B) is not limited to this. For example, The pixel shown may be newly equipped with a switch, a resistor, a capacitor, a transistor, a sensor, or a logic circuit. etc. may be added.

[0578] <Organic EL panel> Another example of the circuit configuration of a pixel is shown in FIG. 42(C). 1 shows the pixel structure of the display panel.

[0579] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are emitted from one of the pair of electrodes. and holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The electrons and holes recombine to form an excited state in the light-emitting organic compound, When the excited state returns to the ground state, light is emitted. The optical element is called a current-excited light-emitting element.

[0580] FIG. 42(C) is a diagram showing an example of an applicable pixel circuit. An example in which a transistor is used in a pixel is shown. The pixel circuit is driven by digital time gray scale. can be applied.

[0581] Regarding the configuration of applicable pixel circuits and pixel operation when digital time gray scale driving is applied, and explain.

[0582] The pixel 920 includes a switching transistor 921, a driving transistor 922, and a light emitting element. The switching transistor 921 has a gate element 924 and a capacitor element 923. The gate electrode is connected to the scanning line 926, and the first electrode (one of the source electrode and the drain electrode) is The second electrode (the other of the source electrode and the drain electrode) is connected to the signal line 925. The driving transistor 922 is connected to the gate electrode of the driving transistor 922. The first electrode is connected to a power supply line 927 via a capacitor element 923, and the second electrode is connected to the power supply line 927. The second electrode is connected to the first electrode (pixel electrode) of the light emitting element 924. The second electrode of 4 corresponds to the common electrode 928. The common electrode 928 is formed on the same substrate. It is electrically connected to the common potential line.

[0583] The switching transistor 921 and the driving transistor 922 are the same as those in the above embodiment. This allows for the development of highly reliable organic EL devices. A display panel can be provided.

[0584] The potential of the second electrode (common electrode 928) of the light-emitting element 924 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 927, for example, GN The low power supply potential can be set to D, 0 V, or the like. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the light emitting element 92 By applying a voltage to the light emitting element 924, a current flows through the light emitting element 924, causing it to emit light. The forward voltage of 24 refers to the voltage required to achieve the desired brightness, and is at least Includes threshold voltage.

[0585] The capacitor 923 is substituted for the gate capacitance of the driving transistor 922. The gate capacitance of the driving transistor 922 can be omitted. A capacitance may be formed between the

[0586] Next, a description will be given of the signal input to the driving transistor 922. Voltage input voltage driving In this method, the driving transistor 922 is in two states: fully on and fully off. A video signal that becomes a pixel value is input to the driving transistor 922. In order to operate the motor 922 in the linear region, a voltage higher than the voltage of the power supply line 927 is applied to the drive A signal line 925 is applied to the gate electrode of the transistor 922. A voltage equal to or greater than the threshold voltage Vth of the input transistor 922 is applied.

[0587] When analog gradation driving is performed, the gate electrode of the driving transistor 922 is connected to the light emitting element 92 4 plus the threshold voltage Vth of the driving transistor 922. A video signal is input so that the driving transistor 922 operates in the saturation region. The driving transistor 922 is operated in the saturation region. In order to do this, the potential of the power supply line 927 is set higher than the gate potential of the driving transistor 922. By converting the video signal into an analog signal, a current corresponding to the video signal is supplied to the light emitting element 924. It is possible to perform analog gradation driving.

[0588] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. 2(C) in the pixel circuit, a switch, a resistor, a capacitor, a sensor, a transistor or a logic A logic circuit or the like may be added.

[0589] When the transistors exemplified in the above embodiments are applied to the circuit illustrated in FIG. The source electrode (first electrode) is on the low potential side, and the drain electrode (second electrode) is on the high potential side. Furthermore, the first gate electrode (and the third gate electrode) are electrically connected by a control circuit or the like. The potential of the second gate electrode is controlled by a wiring (not shown) connected to the source electrode. It is only necessary to configure the device so that a potential lower than the applied potential can be input.

[0590] For example, in this specification, a display element, a display device which is a device having a display element, a light-emitting device, A light-emitting device, which is a device having an element and a light-emitting element, can be used in various forms or in various Examples of a display element, a display device, a light-emitting element, or a light-emitting device include is an EL (electroluminescence) element (EL element including organic and inorganic materials, organic EL EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc. etc.), transistors (transistors that emit light according to the current), electron-emitting elements, liquid crystal elements, Electronic ink, electrophoretic element, grating light valve (GLV), plasma display ray (PDP), MEMS (Micro-Electro-Mechanical Systems) based display Display element, Digital Micromirror Device (DMD), DMS (Digital Micromirror Scatter), MIRASOL (registered trademark), IMOD (Interference Module shutter-type MEMS display element, optical interference-type MEMS display element, Electrowetting elements, piezoelectric ceramic displays, carbon nanotubes, Displays whose contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic effects, such as An example of a display device using an EL element is an EL display. An example of a display device using electron-emitting elements is a field emission device. Flat panel display (FED) or SED type flat panel display (SED: Surface-c Induction Electron-emitter Display An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display). Transflective LCD displays, reflective LCD displays, direct-view LCD displays, projection LCD displays A type of display device that uses electronic ink or electrophoretic elements. An example is electronic paper.

[0591] For example, an example in which a liquid crystal element is provided in the transistor shown in FIG. 1B is shown in FIG. The liquid crystal element includes a pixel electrode 80, a liquid crystal layer 83, and a common electrode 82. The common electrode 82 is , are provided on a substrate 81. As another example, a light emitting element may be provided in the transistor shown in FIG. An example in which an insulating film 84 is provided on the electrodes 19 and 20 is shown in FIG. The pixel electrode 80 is provided on the insulating film 84. The light emitting element has a pixel electrode 80, a light emitting layer 86, and a common electrode 82. In this way, various display elements can be combined with transistors of various structures to create display devices. The device can be configured.

[0592] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done.

[0593] (Embodiment 7) In this embodiment, a display module to which the semiconductor device of one embodiment of the present invention is applied will be described. In addition, structural examples of electronic devices to which the semiconductor device of one embodiment of the present invention is applied will be described. Reveal.

[0594] The display module 8000 shown in FIG. 45 includes an upper cover 8001 and a lower cover 8002. Between them, touch panel 8004 connected to FPC8003 and A display panel 8006, a backlight unit 8007, a frame 8009, a printed circuit board The backlight unit 8007, the battery 8011, and the The telly 8011, the touch panel 8004, etc. may not be provided.

[0595] The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0596] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel The shape and dimensions can be changed as needed to fit the size of the 8006.

[0597] The touch panel 8004 is a resistive or capacitive touch panel. The display panel 8006 can be used by overlapping it with the opposing substrate (sealing substrate). It is also possible to provide a touch panel function to the display panel. It is also possible to provide an optical sensor in each pixel of the 8006 to create an optical touch panel. Alternatively, a touch sensor electrode may be provided in each pixel of the display panel 8006, and a capacitive touch sensor may be used. It is also possible to use it as a touch panel.

[0598] The backlight unit 8007 includes a light source 8008. It may be provided at the end of the light source unit 8007 and may be configured to use a light diffusion plate.

[0599] The frame 8009 has a function of protecting the display panel 8006 and also a function of preventing the movement of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the The frame 8009 may also function as a heat sink.

[0600] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. 1 can be omitted if commercial power is used.

[0601] The display module 8000 also includes components such as a polarizing plate, a retardation plate, and a prism sheet. Additional ones may be provided.

[0602] FIG. 46 is an external view of an electronic device including a semiconductor device of one embodiment of the present invention.

[0603] Examples of electronic devices include television sets (televisions or television receivers) (also called "computer monitors"), cameras such as digital cameras and digital video cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), Examples include large game machines such as small game machines, mobile information terminals, sound reproduction devices, and pachinko machines. can be.

[0604] FIG. 46(A) shows a portable information terminal, which includes a main body 1001, a housing 1002, a display unit 1003, and a display unit 1004. The display unit 1003a, 1003b, etc. The display unit 1003b is a touch panel. By touching the keyboard button 1004 displayed on the display unit 1003b, Of course, the display unit 1003a can be configured as a touch panel. The transistor described in the above embodiment may be used as a switching element in a liquid crystal panel. By fabricating a display panel or an organic light-emitting panel and applying it to the display parts 1003a and 1003b, This makes it possible to provide a highly reliable portable information terminal.

[0605] The portable information terminal shown in FIG. 46(A) displays various information (still images, moving images, text images, etc.) Functions that display calendars, dates, or times on the display, functions that display Functions for manipulating or editing displayed information, processing by various software (programs) In addition, external connection terminals can be provided on the back and sides of the housing. It may also be configured to include a connector (such as an earphone jack or USB terminal), a recording medium insertion section, etc.

[0606] The portable information terminal shown in FIG. 46(A) is configured to be capable of transmitting and receiving information wirelessly. You can also purchase and download desired book data from an electronic book server wirelessly. It is also possible to configure it so that it is downloaded.

[0607] FIG. 46(B) shows a portable music player, and the main body 1021 has a display unit 1023 and earphones. a fixing part 1022 for attaching to a speaker, an operation button 1024, an external memory slot, The transistor shown in the above embodiment is a switching transistor. By manufacturing a liquid crystal panel or an organic light-emitting panel as an element and applying it to the display unit 1023, This makes it a more reliable portable music player.

[0608] Furthermore, the portable music player shown in Figure 46(B) is equipped with an antenna, microphone function, and wireless function. If you carry it and connect it to your mobile phone, you can enjoy wireless hands-free driving while driving a car. Conversations in Lee are also possible.

[0609] FIG. 46(C) shows a mobile phone, which is composed of two housings, a housing 1030 and a housing 1031. The housing 1031 is provided with a display panel 1032, a speaker 1033, a microphone, and the like. a phone 1034, a pointing device 1036, a camera lens 1037, an external connection terminal The housing 1030 also includes a solar cell for charging the mobile phone. The device is equipped with a cell 1040, an external memory slot 1041, and the like. 031. The transistor described in the above embodiment is built in the display panel 10 32, a highly reliable mobile phone can be obtained.

[0610] The display panel 1032 is also equipped with a touch panel, and the image displayed on the display panel 1032 is shown in FIG. The multiple operation keys 1035 are shown by dotted lines. A boost circuit is also implemented to boost the input voltage to the voltage required for each circuit.

[0611] The display direction of the display panel 1032 changes appropriately depending on the usage mode. The camera lens 1037 is located on the same surface as the lens 1032, so video calls are possible. The speaker 1033 and the microphone 1034 are not limited to voice calls, but also to video calls. Furthermore, the housing 1030 and the housing 1031 can be slid apart. As shown in Figure 46(C), it can be folded from the unfolded state to the overlapped state, making it easy to carry. Suitable miniaturization is possible.

[0612] The external connection terminal 1038 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. By inserting a recording medium into the external memory slot 1041, it is possible to store and transfer a larger amount of data. Cut.

[0613] In addition to the above functions, it also has infrared communication functions, TV reception functions, etc. Good too.

[0614] FIG. 46(D) shows an example of a television device. The television device 1050 is A display unit 1053 is built into the housing 1051. The display unit 1053 displays an image. In addition, the CPU is built into the stand 1055 that supports the housing 1051. The transistor described in the above embodiment is incorporated in the display portion 1053 and the CPU. By applying this, the television device 1050 can be made highly reliable.

[0615] The television device 1050 can be operated using an operation switch provided on the housing 1051 or a separate remote control. This can be done by a remote controller. A display unit for displaying information output from the machine may be provided.

[0616] The television device 1050 is configured to include a receiver, a modem, and the like. It is possible to receive general television broadcasts, and also to receive wired or wireless signals via a modem. By connecting to a communication network, it can be one-way (sender to receiver) or two-way It is also possible to communicate information in both directions (between a sender and a receiver, or between receivers). .

[0617] The television device 1050 also includes an external connection terminal 1054 and a storage medium playback / recording unit 1055. 052, and an external memory slot. The external connection terminal 1054 is for connecting a USB cable or the like. It can be connected to any type of cable, enabling data communication with a personal computer, etc. In the storage medium playback / recording unit 1052, a disk-shaped recording medium is inserted and It is possible to read the stored data and write it to the recording medium. Images and videos stored in the external memory 1056 inserted in the reslot It is also possible to display it on the display unit 1053.

[0618] In addition, when the off-leak current of the transistor described in the above embodiment is extremely small, By applying this transistor to the external memory 1056 or the CPU, power consumption can be reduced sufficiently. This can result in a highly reliable television device 1050 with reduced power consumption.

[0619] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done. [Example]

[0620] This example can be applied to a transistor included in a semiconductor device according to one embodiment of the present invention. The results of evaluating the oxide insulating film will be described below. The amount of nitrous oxide, nitrogen dioxide, ammonia, water, and nitrogen released was evaluated using TDS. The results will be explained below.

[0621] <Sample preparation method> In this example, a test oxide insulating film that can be used for a transistor according to one embodiment of the present invention was prepared. Sample A1, and comparative samples A2 and A3 were prepared.

[0622] <Sample A1> The sample A1 is a film formed by at least one of the gate insulating film 15 and the protective film 21 ( The plasma CVD method was applied under the conditions applicable to the formation of a silicon wafer. An oxide insulating film was formed.

[0623] The oxide insulating film was formed by holding the silicon wafer at 220°C and using a flow rate of 50 sccm. Silane and nitrous oxide at a flow rate of 2000 sccm were used as raw material gases, and the pressure in the processing chamber was ...

Claims

[Claim 1] A transistor is included. the transistor includes a first gate electrode, a gate insulating film, a first oxide semiconductor film, a source electrode, and a drain electrode; the first gate electrode is provided on an insulating surface; the gate insulating film is provided on the first gate electrode; the first oxide semiconductor film is provided on the gate insulating film; a pair of electrodes functioning as the source electrode and the drain electrode are provided in contact with an upper surface of the first oxide semiconductor film; a protective film is provided in contact with an upper surface of the first oxide semiconductor film, an upper surface of the source electrode, and an upper surface of the drain electrode; one of the gate insulating film and the protective film is a silicon oxynitride film; In a graph where the horizontal axis (x) represents the logarithm of the stress time and the vertical axis (y) represents the logarithm of the absolute value of the amount of variation in threshold voltage of the transistor when the stress time is 0.1 hour, the temperature is 60° C., +30 V is applied to the first gate electrode, and 0 V is applied to the pair of electrodes, the exponent of the power approximation line of the variation in threshold voltage is between −0.1 and 0.3, and the variation in threshold voltage is less than 0.3 V. The power approximation line is expressed by the following mathematical formula (1): where b and C are constants, and b is the exponent of the power approximation line. (Equation 1) y=Cx ｂ (1)

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