Memory device

Abstract

To provide a memory device with a large storage capacity.SOLUTION: A NAND-type memory device connects a plurality of memory cells, each including a write transistor, a read transistor, and a capacitor, wherein an oxide semiconductor is used for the semiconductor layer of the write transistor. The read transistor includes a back gate. The information stored in the memory cell is read by applying a voltage for reading to the back gate.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] One aspect of the present invention relates to a storage device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an article, a method, or a manufacturing method. , process, machine, manufacture, or composition of matter (This is related to the above.)

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. It refers to semiconductor elements such as transistors and diodes, as well as semiconductor devices. The circuit is a semiconductor device. Also, the circuit is applicable to display devices, light-emitting devices, lighting devices, electro-optical devices, imaging devices, etc. Devices, storage devices, communication devices, and electronic equipment may contain semiconductor elements and semiconductor circuits. Therefore, the present invention is applicable to display devices, light-emitting devices, lighting devices, electro-optical devices, imaging devices, storage devices, and communication devices. Devices and electronic devices may also be called semiconductor devices. [Background technology]

[0004] Recently, transistors using oxide semiconductors or metal oxides in the channel formation region (Oxi de Semiconductor transistor, hereinafter referred to as "OS transistor" or " OS-FETs, also known as "OS-FETs," have been attracting attention (Patent Document 1).

[0005] OS transistors have an off-state current (when the transistor is in the off state, The current that flows is very small. Nonvolatile memories that utilize this feature are described in Patent Documents 2 and and Patent Document 3. Nonvolatile memories using OS transistors are There is no limit to the number of times it can be rewritten, and it consumes little power when rewriting data. In addition, Patent Document 3 discloses an example in which a memory cell of a nonvolatile memory is configured using only OS transistors. has been disclosed.

[0006] In this specification, nonvolatile memory using OS transistors is referred to as NOSRAM (registered trademark). NOSRAM is a trademark of Nonvolatile Oxide Semiconductor. It is an abbreviation for "Gain Cell RAM" and is a type of gain cell (2T type, 3T type). Refers to RAM with memory cells. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 [Patent Document 3] Japanese Patent Application Laid-Open No. 2016-115387 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a highly reliable storage device. An object of one embodiment of the present invention is to provide a storage device with a large storage capacity. An object of one embodiment of the present invention is to provide a memory device that occupies a small area. An object of one embodiment of the present invention is to provide a memory device with low manufacturing costs. An object of one embodiment of the present invention is to provide a highly reliable semiconductor device. An object of one embodiment of the present invention is to provide a semiconductor device that can be manufactured at low cost. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

[0009] The description of these problems does not preclude the existence of other problems. The embodiment does not necessarily solve all of these problems. Problems other than these may be solved by the description. The above is self-evident from the description, drawings, claims, etc. From the above descriptions, it is possible to extract other issues. [Means for solving the problem]

[0010] One aspect of the present invention is a memory device including a write transistor and a read transistor. A NAND type memory device in which multiple memory cells are connected, and the semiconductor of the write transistor By using an oxide semiconductor for the dielectric layer, a storage capacitor is not required or can be made smaller. The read transistor has a back gate. By applying a voltage, the information stored in the memory cell can be read.

[0011] One aspect of the present invention is a memory cell array including n memory cells (n is an integer of 3 or more), n first wirings, and n The second wiring and the third wiring are provided, and the i-th (i is an integer equal to or greater than 2 and less than n) memory cell is , a first transistor [i], a second transistor [i], and a capacitance [i], The first memory cell has a first transistor [i-1], a second transistor [i-1], and , capacitance [i-1], and the i+1th memory cell has a first transistor [i+1] a second transistor [i+1] and a capacitance [i+1], and the first transistor [i The gate of the first transistor [i] is electrically connected to the i-th first wiring, and the source of the first transistor [i] is is electrically connected to the drain of the first transistor [i-1], and the drain of the first transistor [i The drain of the first transistor [i+1] is electrically connected to the source of the second transistor [i+2]. The gate of the first transistor [i] is electrically connected to the drain of the second transistor [i]. The source of the transistor [i] is electrically connected to the drain of the second transistor [i-1]. The drain of the second transistor [i] is connected to the source of the second transistor [i+1]. The back gate of the second transistor [i] is electrically connected to the i-th second wiring. The back gate of the second transistor [i-1] is connected to the (i-1)-th second wiring. The back gate of the second transistor [i+1] is electrically connected to the (i+1)th second wiring. and a capacitance [i] is provided between the gate of the second transistor [i] and the third wiring. A capacitance [i-1] is provided between the gate of the second transistor [i-1] and the third wiring, and the second A memory device having a capacitance [i+1] between the gate of transistor [i+1] and the third wiring. be.

[0012] The first transistor [i] preferably contains an oxide semiconductor in the semiconductor layer. The transistor [i] preferably contains an oxide semiconductor in the semiconductor layer. It is preferable that the metal contains at least one of sodium and zinc. [Effects of the Invention]

[0013] According to one embodiment of the present invention, a highly reliable memory device can be provided. According to one embodiment of the present invention, a storage device with a large storage capacity can be provided. According to one embodiment of the present invention, a memory device with a small area can be provided. According to the present invention, it is possible to provide a memory device with low manufacturing costs. In this manner, a highly reliable semiconductor device can be provided. Therefore, a semiconductor device with low manufacturing cost can be provided. As a result, a novel semiconductor device can be provided.

[0014] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This becomes clear from the description, drawings, claims, etc. From any description, it is possible to extract effects other than these. [Brief explanation of the drawings]

[0015] [Figure 1] Fig. 1A is a circuit diagram showing an example of the configuration of a memory device, Figs. 1B to 1D are circuit diagrams showing an example of the configuration of a memory cell, and Fig. 1E is a circuit diagram showing an example of the configuration of a transistor. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of the storage device. [Figure 3] FIG. 3 is a circuit diagram showing an example of the configuration of a storage device. [Figure 4] FIG. 4 is a circuit diagram showing an example of the configuration of a storage device. [Figure 5] FIG. 5 is a circuit diagram showing an example of the configuration of a storage device. [Figure 6] Figure 6A is a timing chart illustrating a write operation, and Figure 6B is a timing chart illustrating a read operation. [Figure 7]7A and 7B are circuit diagrams illustrating a write operation. [Figure 8] 8A and 8B are circuit diagrams illustrating a write operation. [Figure 9] FIG. 9 is a circuit diagram illustrating the write operation. [Figure 10] 10A and 10B are circuit diagrams illustrating a read operation. [Figure 11] 11A and 11B are circuit diagrams illustrating a read operation. [Figure 12] FIG. 12 is a circuit diagram showing an example of the configuration of a storage device. [Figure 13] FIG. 13 is a circuit diagram showing an example of the configuration of a storage device. [Figure 14] FIG. 14 is a timing chart illustrating the write operation. [Figure 15] 15A and 15B are circuit diagrams illustrating a write operation. [Figure 16] FIG. 16 is a circuit diagram illustrating the write operation. [Figure 17] FIG. 17 is a circuit diagram showing an example of the configuration of a storage device. [Figure 18] FIG. 18 is a circuit diagram showing an example of the configuration of a storage device. [Figure 19] FIG. 19 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 20] 20A, 20B, and 20C are perspective views illustrating configuration examples of semiconductor devices. [Figure 21] FIG. 21 is a diagram illustrating a configuration example of a semiconductor device. [Figure 22] FIG. 22 is a diagram illustrating a configuration example of a semiconductor device. [Figure 23] 23A to 23C are diagrams showing examples of the configuration of a transistor. [Figure 24] 24A to 24C are diagrams showing examples of the configuration of a transistor. [Figure 25] 25A to 25C are diagrams showing examples of the configuration of a transistor. [Figure 26] Figure 26A is a diagram explaining the classification of IGZO crystal structures, Figure 26B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 26C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. [Figure 27] 27A and 27B are schematic and perspective views of a semiconductor device. [Figure 28] 28A to 28E are diagrams illustrating an example of a storage device. [Figure 29] 29A to 29G are diagrams illustrating an example of an electronic device. [Figure 30] Figure 30A is an optical microscope photograph of the memory device, and Figure 30B is a cross-sectional TEM photograph of the memory device. [Figure 31] FIG. 31 is a circuit diagram of the memory device. [Figure 32] Fig. 32A is a timing chart illustrating a write operation, and Fig. 32B is a timing chart illustrating a read operation. [Figure 33] Fig. 33A shows the temperature dependence of the off-current of a CAAC-IGZOFET, and Fig. 33B shows the measurement results of the retention time of information written in a memory device. [Figure 34] Fig. 34A is a timing chart of signals supplied to the wiring WG5 and the wiring WSL, and Fig. 34B is a diagram showing the verification results of the rewrite endurance. [Figure 35] 35A and 35B are timing charts for verifying the write disturbance resistance. [Figure 36] 36A is a diagram showing the verification results of write disturbance resistance, and FIG. 36B is a Shmoo plot of the gate potential and pulse width of the write transistor. [Figure 37] FIG. 37 is a diagram showing various storage devices by hierarchical level. [Figure 38] FIG. 38 is a two-dimensional structural diagram of the memory device used in the device simulation. [Figure 39]FIG. 39 shows the calculation results for the write and read operations. DETAILED DESCRIPTION OF THE INVENTION

[0016] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. Therefore, the present invention is based on the following embodiments. It should be noted that the following description of the invention is not intended to be limiting. In this case, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. The explanation will be omitted here.

[0017] In addition, the position, size, range, etc. of each component shown in the drawings are for the purpose of facilitating understanding of the invention. Therefore, the actual location, size, range, etc. may not be shown. The invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings. In the actual manufacturing process, resist masks, etc., may be unintentionally damaged by etching or other processes. However, this may not be reflected in the diagram to make it easier to understand.

[0018] In addition, in top views (also called "plan views") and perspective views, etc., Therefore, descriptions of some components may be omitted.

[0019] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "line" is formed as a single unit.

[0020] In this specification, a "terminal" in an electric circuit refers to an input or output of a current, It refers to the part where pressure is input or output, or where a signal is received or transmitted. In some cases, a part of the wiring or electrode functions as a terminal.

[0021] In this specification, the terms "above" and "below" refer to the positional relationship of components directly above or below each other. For example, "electrode on insulating layer A" is not limited to being below and in direct contact with the insulating layer A. If the expression is "B", electrode B does not need to be formed directly on insulating layer A, The inclusion of other components between the edge layer A and the electrode B is not excluded.

[0022] The source and drain functions may also be different when using transistors with different polarities or when using circuits When the direction of the current changes during circuit operation, they are interchanged depending on the operating conditions. Therefore, it is difficult to determine which is the source and which is the drain. In this specification, the terms source and drain may be used interchangeably. Therefore, in order to make the description of one embodiment of the present invention easier to understand, the following will be described in this specification and the like. In this case, either the source or the drain is called the "source" and the other is called the " It may be called a "drain."

[0023] In this specification, "electrically connected" refers to a direct connection and a connection made by some means. This includes cases where the device is connected via "something that has an electrical effect." "Something that has an electrical effect" means something that allows the transmission and reception of electrical signals between connected objects. Therefore, even if it is expressed as "electrically connecting," In real circuits, there may be no physical connections, just wires running along the circuit. .

[0024] In this specification, "parallel" means that two lines are at an angle of -10° to 10°. This refers to the state in which the object is arranged at an angle between -5° and 5°. Also, "perpendicular" and "orthogonal" mean, for example, that two straight lines are at an angle of 80° or more and 100° or less. This refers to a state in which the object is arranged at an angle between 85° and 95°.

[0025] In this specification and elsewhere, terms such as "identical," "same," and "equal" are used to refer to counting values ​​and measurement values. When we say "even" or "uniform," we mean plus or minus 20 unless otherwise specified. This includes a margin of error of %.

[0026] Voltage is the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be used interchangeably. In this specification and the like, unless otherwise specified, voltage and potential can be interchangeable. It shall be.

[0027] Even when written as "semiconductor," if the conductivity is sufficiently low, it may be written as "insulator." Therefore, it is possible to use "semiconductor" instead of "insulator." In this case, the boundary between "semiconductor" and "insulator" is vague, and it is difficult to make a strict distinction between the two. Therefore, the terms "semiconductor" and "insulator" used in this specification can be interpreted interchangeably. This may be possible.

[0028] Also, even if a material is written as a "semiconductor," if the material has a sufficiently high conductivity, it may be written as a "conductor." Therefore, it is possible to use "semiconductor" instead of "conductor." In this case, the boundary between "semiconductor" and "conductor" is vague, and it is difficult to make a strict distinction between the two. Therefore, the terms "semiconductor" and "conductor" in this specification can be interpreted interchangeably. This may be possible.

[0029] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. It does not indicate any order or ranking such as the order of processes or stacking. In addition, even if a term is not accompanied by an ordinal number in this specification, etc., it is possible to avoid confusion of the constituent elements. In order to avoid this, ordinal numbers may be used in the claims. Even if a term has an ordinal number in In addition, even if a term is accompanied by an ordinal number in this specification, Ordinal numbers may be omitted in patent claims, etc.

[0030] In this specification, the "on state" of a transistor means that the source and This refers to a state in which the drain is considered to be electrically short-circuited (also called a "conducting state"). The "off state" of a transistor means that the source and drain of the transistor are electrically isolated. This refers to a state in which the conduction state can be considered to be non-conductive (also called a "non-conductive state").

[0031] In this specification, the term "on-state current" refers to the current flowing between the source and the transistor when the transistor is in the on state. The term "off-state current" may refer to the current that flows between the drain and the transistor. It can also refer to the current that flows between the source and drain when the device is in an open state.

[0032] In addition, in this specification and the like, a high power supply potential VDD (hereinafter simply referred to as "VDD", "H potential", or or "H") is the low power supply potential VSS (hereinafter simply referred to as "VSS", "L potential", or VSS refers to the power supply potential that is higher than VDD. It also refers to the power supply potential, which is the lowest potential. For example, VDD can be used as the ground potential. In the case of a potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0033] In addition, unless otherwise specified, the transistors shown in this specification and the like are enhancement transistors. The transistor is a normally-off n-channel field effect transistor. The threshold voltage (also called "Vth") is greater than 0V. Except in the case where "H potential is supplied to the gate of a transistor" means "to Unless otherwise specified, the term "transistor" is sometimes used interchangeably with "transistor on." "To supply an L potential to the gate of a transistor" is equivalent to "to turn off the transistor." There are cases where...

[0034] In this specification, the term "gate" refers to a gate electrode and a part or all of a gate wiring. The gate wiring is a wiring that connects the gate electrode of at least one transistor and another This refers to wiring that electrically connects electrodes or other wiring.

[0035] In this specification, the source includes a source region, a source electrode, and a source wiring. The source region is a semiconductor layer with a resistivity below a certain value. The source electrode is the conductive layer connected to the source region. The source wiring is a wiring that connects the source electrode of at least one transistor with another electrode or wiring. This refers to the wiring that electrically connects the

[0036] In this specification, the term "drain" refers to a drain region, a drain electrode, and a drain electrode. The drain region is a part or all of the wiring. The drain electrode is the conductive layer connected to the drain region. The drain wiring is a wiring that is connected to the drain electrode of at least one transistor. This refers to wiring that electrically connects electrodes or other wiring.

[0037] In addition, in drawings, etc., the potentials of the wiring and electrodes are shown in order to make them easier to understand. "H" indicating high potential or "L" indicating low potential may be added next to the electrode. In addition, wiring and electrodes where a potential change occurs are marked with "H" or "L" in a circle. When a transistor is in an off state, the transistor is An "x" symbol may be added.

[0038] Generally, a "capacitance" has a structure in which two electrodes face each other through an insulator (dielectric). In this specification and the like, the term "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, a "capacitance element" refers to a capacitor having two electrodes facing each other with an insulator interposed therebetween. a structure in which two wires face each other through an insulator; This includes cases where two wires are arranged with an insulator between them.

[0039] In addition, in this specification and the like, when the same reference numeral is used for a plurality of elements, it is not necessary to particularly distinguish between them. If necessary, use identifiers such as "_1", "_2", "[n]", "[m,n]", etc. For example, the second wiring GL is called wiring GL[2]. It may be stated.

[0040] (Embodiment 1) FIG. 1A shows a circuit diagram of a memory device 100 according to one embodiment of the present invention. A configuration including a plurality of memory cells 110 is provided between the transistor 131 and the transistor 132. do.

[0041] In this embodiment, the first memory cell 110 is designated as memory cell 110[1], and The th (n is an integer equal to or greater than 3) memory cell 110 is denoted as memory cell 110[n]. The i-th (i is an integer equal to or greater than 2 and less than n) memory cell 110 is denoted as memory cell 110[i]. Note that the common matters among the memory cells 110[1] to 110[n] will be explained. In this case, it may be simply referred to as "memory cell 110."

[0042] The memory cell 110 includes a transistor 111, a transistor 112, and a capacitor 113. In this embodiment, the transistor 111 included in the i-th memory cell 110 , transistor 112, and capacitor 113 are connected to transistor 111[i], transistor 112[i], and capacitance 113[i].

[0043] <Storage device configuration example> An example of the circuit configuration of the memory device 100 shown in FIG. 1A will be described in detail. The gate of the transistor 111[1] included in the terminal 121[1] is electrically connected to the terminal 121[1]. The source or drain of the transistor 111[1] is electrically connected to the terminal 137. The other end is electrically connected to one electrode of the capacitor 113[1]. The other electrode of [1] is electrically connected to terminal 123[1].

[0044] The gate of transistor 112[1] is connected to the source or drain of transistor 111[1]. One of the source or drain of the transistor 112[1] is electrically connected to the other of the two terminals. The source of the transistor 112[1] is electrically connected to the transistor 131. The other of the two is electrically connected to the source or drain of the transistor 112[2]. The back gate of the transistor 112[1] is electrically connected to the terminal 122[1]. are connected to the network.

[0045] The other of the source or drain of the transistor 111[1] and one of the capacitors 113[1] The node where the electrode and the gate of the transistor 112[1] are electrically connected is called node ND[1]. That's what they say.

[0046] In addition, one of the source and drain of the transistor 131 is electrically connected to the terminal 138. The other end is electrically connected to either the source or the drain of the transistor 112[1]. The gate of the transistor 131 is electrically connected to a terminal 133.

[0047] The gate of the transistor 111[2] included in the memory cell 110[2] is connected to the terminal 121[ 2]. Either the source or the drain of the transistor 111[2] is , electrically connected to the node ND[1], and the other is electrically connected to one electrode of the capacitor 113[2]. The other electrode of the capacitor 113[2] is electrically connected to the terminal 123[2]. do.

[0048] The gate of transistor 112[2] is connected to the source or drain of transistor 111[2]. One of the source or drain of the transistor 112[2] is electrically connected to the other of the two terminals. One of the terminals is electrically connected to the other of the source or drain of the transistor 112[1]. The other of the source and drain of transistor 112[2] is connected to transistor 112[3] The transistor 11 is electrically connected to either the source or the drain of the transistor 11 (not shown). The back gate of MOSFET 2[2] is electrically connected to terminal 122[2].

[0049] The other of the source or drain of the transistor 111[2] and one of the capacitors 113[2] The node where the electrode and the gate of the transistor 112[2] are electrically connected is called node ND[2]. That's what they say.

[0050] The gate of transistor 111[i] included in memory cell 110[i] is connected to terminal 121[i]. One of the source and drain of transistor 111[i] is electrically connected to , the other is electrically connected to the node ND[i-1] (not shown), The other electrode of the capacitor 113[i] is electrically connected to the terminal 123[i]. and electrically connected to each other.

[0051] The gate of transistor 112[i] is connected to the source or drain of transistor 111[i]. One of the source or drain of the transistor 112[i] is electrically connected to the other of the two terminals. The other of the source and drain of the transistor 112[i-1] is electrically connected to the other of the source and drain of the transistor 112[i-1]. The other of the source or drain of the transistor 112[i] is connected to the transistor 112[ i+1] (not shown). The back gate of the starter 112[i] is electrically connected to the terminal 122[i].

[0052] The other of the source or drain of the transistor 111[i] and one of the capacitors 113[i] The node where the electrode and the gate of the transistor 112[i] are electrically connected is called node ND[i]. That's what they say.

[0053] The gate of the transistor 111[n] included in the memory cell 110[n] is connected to the terminal 121[ One of the source and drain of the transistor 111[n] is electrically connected to , the other is electrically connected to the node ND[n-1] (not shown), The other electrode of the capacitor 113[n] is electrically connected to the terminal 123[n]. and electrically connected to each other.

[0054] The gate of transistor 112[n] is connected to the source or drain of transistor 111[n]. One of the source or drain of the transistor 112[n] is electrically connected to the other of the two terminals. The other of the source and drain of the transistor 112[n-1] (not shown) is connected to the power supply. The other of the source and drain of the transistor 112[n] is electrically connected to the transistor The back gate of the transistor 112[n] is electrically connected to the terminal 122[n] is electrically connected to the

[0055] The other of the source or drain of the transistor 111[n] and one of the capacitors 113[n] The node where the electrode and the gate of the transistor 112[n] are electrically connected is called a node ND[n]. That's what they say.

[0056] In addition, one of the source and drain of the transistor 132 is connected to the transistor 112[n] The source or drain of the transistor 132 is electrically connected to the other of the source or drain of the transistor 132. The other of the drains is electrically connected to a terminal 139. The gate of the transistor 132 is The terminal 134 is electrically connected to the terminal 134.

[0057] The memory device 100 shown in FIG. 1A has n transistors between the transistors 131 and 132. The memory cell 110 includes transistors 111[1] to 111[n]. The source of one transistor and the drain of the other transistor are shared between adjacent transistors. The transistors 112[1] to 112[2] are connected in series while being used (electrically connected). The transistor 112[n] shares the source and drain with the adjacent transistors (electrically The two circuits are connected in series.

[0058] More specifically, the source of transistor 111[i] is connected to the source of transistor 111[i-1]. The drain of transistor 111[i] is electrically connected to the drain of transistor 111 The source of transistor 112[i] is electrically connected to the source of transistor 112[i+1]. is electrically connected to the drain of the transistor 112[i-1], and the drain of the transistor 112[i ] is electrically connected to the source of transistor 112[i+1].

[0059] In this specification and the like, the gate of a transistor may be referred to as a first terminal, a source, or a drain. The other of the source or drain is the third terminal, and the back gate is the fourth terminal. For example, the second terminal of transistor 111[i] is the third terminal of transistor 111[i-1] is electrically connected to the third terminal of transistor 111[i]. the second terminal of transistor 111[i+1], and the third terminal of transistor 111[i]. It can be said that the first terminal of transistor 112[i] is electrically connected to the first terminal of transistor 112[i].

[0060] In this way, the transistor included in one memory cell 110 is The structure in which a plurality of memory cells 110 are connected in series with the transistors included in 10 is called a "series memory cell." These may be called "strings," "cell strings," or "memory cell strings." For example, one storage device 100 having a string structure may be referred to as "one string," or It may simply be called a "string." It may also be referred to as a "memory cell string" unit.

[0061] [Memory Cell] The memory cell 110 has a function of holding the potential (charge) written to the node ND. Specifically, a voltage that turns on the transistor 111 is applied to the gate of the transistor 111. Node N D is supplied to the node N through the source and drain of the transistor 111. Then, a charge is supplied to the gate of transistor 111 to set D to a predetermined voltage. A voltage is supplied to turn off the transistor 111. By doing so, the charge written to the node ND can be maintained.

[0062] The semiconductor layers of the transistor 111 and the transistor 112 are made of a single crystal semiconductor, a polycrystalline semiconductor, or the like. The semiconductor, the microcrystalline semiconductor, the amorphous semiconductor, etc. can be used alone or in combination. As the semiconductor material, for example, silicon or germanium can be used. In addition, silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, nitride The semiconductor layer of the transistor 131 and the transistor The semiconductor layer of the transistor 132 can also be made of a similar semiconductor material.

[0063] Note that the semiconductor layers used in the transistor may be stacked. Semiconductors having different crystal states may be used for each of the layers, or different semiconductor materials may be used for each of the layers. It's fine.

[0064] In particular, the transistor 111 is preferably an OS transistor. Since the band gap is 2 eV or more, the off-state current is significantly small. When an OS transistor is used for this purpose, the charge written to the node ND can be retained for a long period of time. When an OS transistor is used for the transistor 111, the memory cell 110 can be It can be called "S memory."

[0065] OS memory can be written for more than one year, or even more than ten years, even if the power supply is cut off. Therefore, the OS memory can be considered non-volatile memory. It is also possible.

[0066] In addition, since the amount of charge written into the OS memory is unlikely to change over a long period of time, the OS memory is binary ( It is possible to store not only 1 bit but also multi-value (multi-bit) information.

[0067] In addition, since OS memory writes charge to the node via the OS transistor, It does not require the high voltage required for conventional flash memory, and also enables high-speed write operations. In addition, the erase operation before rewriting data in flash memory is performed in the same way as the OS memory. In addition, charge injection and extraction into the floating gate or charge trapping layer is not required. Since there is no data being written to or removed from the OS memory, data can be written to and read from the OS memory virtually unlimited times. The OS memory is less susceptible to deterioration and has a high Reliability is gained.

[0068] In addition, the OS memory is magnetoresistive memory (MRAM) or resistive random access memory (ReRAM) ) does not involve structural changes at the atomic level. Therefore, OS memory is a magnetoresistive memory. It has better rewrite endurance than memory and resistive change memory.

[0069] Furthermore, the off-state current of OS transistors hardly increases even in high-temperature environments. The off-state current hardly increases even in ambient temperatures above 200°C and below. The on-state current is unlikely to decrease even in high-temperature environments. In addition, the OS transistor has a stable insulation between the source and drain. By using OS transistors as transistors in a semiconductor device, This makes it possible to realize a semiconductor device that operates stably even in a high-temperature environment and has good reliability.

[0070] 1B and 1C, the transistor 11 included in the memory cell 110 A transistor having a back gate may be used in the transistor 11. In FIG. 1C shows an example in which the back gate of transistor 1 is electrically connected to terminal 124. 1 shows an example in which the gate and back gate of the transistor 111 are electrically connected.

[0071] As shown in FIG. 1D, a transistor with a small off-state current is used as the transistor 111. By doing so, the capacitor 113 can be omitted.

[0072] Also, as shown in FIG. 1E, transistor 131 and / or transistor 132 may be connected to a buffer. A transistor having a gate may also be used. An example in which the back gate is electrically connected is shown.

[0073] Alternatively, the gate of the transistor 111 may be electrically connected to the wiring WL. The gate of the transistor 111 may be electrically connected to the wiring WL via a terminal 121. Alternatively, the back gate of the transistor 112 may be electrically connected to the wiring CL. The back gate of the transistor 112 is electrically connected to the wiring CL via the terminal 122. Alternatively, the other terminal of the capacitor 113 may be electrically connected to the wiring GL. The other terminal of the capacitor 113 may be electrically connected to the wiring GL via a terminal 123 .

[0074] In FIG. 2, the gate of the transistor 111[1] is electrically connected to the wiring WL[1]. The gate of the transistor 111[2] is electrically connected to the wiring WL[2], and the transistor 111 The gate of transistor 111[i] is electrically connected to wiring WL[i], and the gate of transistor 111[n] is is electrically connected to the wiring WL[n].

[0075] In addition, in FIG. 2, the back gate of the transistor 112[1] is electrically connected to the wiring CL[1]. The back gate of the transistor 112[2] is electrically connected to the wiring CL[2]. The back gate of the transistor 112[i] is electrically connected to the wiring CL[i]. 11 shows an example in which the back gate of the star 112[n] is electrically connected to the wiring CL[n].

[0076] Also, in FIG. 2, the capacitance 113[1], capacitance 113[2], capacitance 113[i], and capacitance 113[n] is electrically connected to the wiring GL. It is preferable that a fixed potential is supplied to the line GL. For example, VSS or GN It is preferable to supply a fixed potential such as VSS or G. It may be a potential other than ND, for example, VDD.

[0077] Alternatively, the gate of the transistor 131 may be electrically connected to the wiring RSL. The gate of the transistor 131 may be electrically connected to the wiring RSL via a terminal 133. In addition, one of the source and the drain of the transistor 131 is electrically connected to the wiring RBL. Alternatively, one of the source and drain of the transistor 131 may be connected to the terminal 138. The wiring RBL may be electrically connected to the wiring RBL via a wiring RBL.

[0078] Alternatively, the gate of the transistor 132 may be electrically connected to the wiring SSL. The gate of the transistor 132 may be electrically connected to the wiring SSL via a terminal 134. The other of the source and the drain of the transistor 132 is electrically connected to the wiring SL. Alternatively, the other of the source and drain of the transistor 132 may be connected to the terminal 139. The wiring SL may be electrically connected to the wiring SL via a wiring SL.

[0079] Furthermore, by using a plurality of storage devices 100, the storage capacity of a semiconductor device including the storage devices 100 can be increased. In other words, by increasing the number of strings, the memory capacity of the semiconductor device can be increased. As an example, two storage devices 100 (two The circuit diagram of the first memory device is shown in Figure 3 and Figure 4. The first storage device 100 is designated as storage device 100[1], and the second storage device 100 is designated as storage device 100[2]. are.

[0080] In this case, for example, as shown in FIG. 3, the wiring RBL, the wiring SSL, the wiring SL, the wiring WL, and and the wiring CL can be used as a common wiring between multiple storage devices 100. This allows for miniaturization of a semiconductor device having a plurality of memory devices 100. In this way, the wiring RSL may be used as a common wiring, and the wiring RBL may be provided for each storage device 100. By providing a wiring RBL for each storage device 100, Therefore, the information stored in the memory device 100 can be read out simultaneously. This can increase the speed at which information can be read out in a mobile device.

[0081] In most cases, one string is provided extending in one direction. The wiring that controls the reading or writing (for example, the wiring WL and the wiring CL) is In many cases, it extends in a direction perpendicular to the extension direction.

[0082] <Variation 1> FIG. 5 shows a storage device 100A, which is a modification of the storage device 100. The difference from the device 100 is that either the source or the drain of the transistor 111[1] is connected to The point is electrically connected to the other of the source and drain of the transistor 131. In the storage device 100A, the wiring WBL shown in FIGS. 2 to 4 can be omitted. This allows the area occupied by the storage device 100 to be reduced.

[0083] <Example of storage device operation> An example of the operation of the storage device 100 will be described with reference to the drawings. The following description will be given taking as an example the storage device 100 shown in FIG. 2, which includes a recell 110.

[0084] [Write operation] In this embodiment, the memory cell 110[1], the memory cell 110[2], and the memory cell When writing an H potential to the memory cell 110[4] and an L potential to the memory cell 110[3], An example of the operation will be described. FIG. 6A is a timing chart illustrating the write operation. 7B, 8A, 8B, and 9 are circuit diagrams for explaining the write operation.

[0085] As an initial state, an L potential is written to the memory cells 110[1] to 110[4]. In addition, the wiring WL[1] to the wiring WL[4], the wiring CL[1] to the wiring CL[3], The L potential is supplied to the wiring CL[4], wiring RSL, wiring RBL, wiring SSL, and wiring SL. The potential of the wiring GL is set to GND.

[0086] [Period T1] In the period T1, an H potential is applied to the wirings WL[1] to WL[4] and the wiring WBL. Then, the potentials of the nodes ND[1] to ND[4] become H potentials. Therefore, the transistors 112[1] to 112[4] are turned on. becomes.

[0087] [Period T2] During the period T2, the L potential is applied to the wiring WL[4] (see FIG. 7B). The transistor 111[4] is turned off, and the charge written to the node ND[4] is retained. Here, a charge equivalent to the H potential is held. Also, transistor 111[4] After turning off the node ND[1], an L potential is supplied to the wiring WBL. The potential of the node ND[3] becomes the L potential. The resistor 112[3] is turned off.

[0088] [Period T3] In the period T3, the L potential is supplied to the wiring WL[3] (see FIG. 8A). The transistor 111[3] is turned off, and the charge written to the node ND[3] is retained. Here, a charge equivalent to the L potential is held. Also, transistor 111[3] After turning off the node ND[1], an H potential is supplied to the wiring WBL. The potential of the node ND[2] and the transistor 112[1] becomes the H potential. The transistor 112[2] is turned on.

[0089] [Period T4] In the period T4, the L potential is supplied to the wiring WL[2] (see FIG. 8B). The transistor 111[2] is turned off, and the charge written to the node ND[2] is retained. Here, a charge equivalent to the H potential is held.

[0090] [Period T5] In the period T5, the L potential is supplied to the wiring WL[1] (see FIG. 9). The resistor 111[1] is turned off, and the charge written to the node ND[1] is retained. Here, a charge equivalent to the H potential is held. In this way, the memory cell 110 Information can be written to the memory cells [1] to 110[4].

[0091] As described above, the storage device 100 according to one aspect of the present invention is implemented in a flash memory. There is no need to erase the data before rewriting it. The same can be done as in the operation.

[0092] When writing data to the memory cell 110 close to the wiring WBL, The operation of writing information to the memory cells 110 farther away from the memory cell 110 in question is omitted. For example, when writing information to memory cell 110[1], The operation of writing information to the memory cells 110[2] to 110[4] can be omitted. When writing information to the memory cell 110[2], the memory cells 110[3] and In addition, the operation of writing information to the memory cell 110[4] can be omitted. Information that is frequently rewritten is stored in the memory cell 110 close to the wiring WBL. This reduces the time required to write (rewrite) information. This can increase the read (rewrite) speed.

[0093] [Read operation] In this embodiment, the data stored in the memory cells 110[1] to 110[4] An example of the read operation of the information stored in the memory cell 110[2] is as follows: It is assumed that the memory cell 110[2] is held at H potential. 10A, 10B, 11A, and 11B are timing charts illustrating the read operation. 11B is a circuit diagram for explaining a read operation.

[0094] [Period T6] In the period T6, an H potential is supplied to the wirings CL[1] to CL[4] and the wiring RSL. Transistors 112[1] to 112[4] and transistor 13 1 is turned on. Also, the wiring RBL is precharged to an H potential (see FIG. 10A). Specifically, after supplying an H potential to the wiring RBL, the wiring RBL is brought into a floating state. do.

[0095] [Period T7] In the period T7, the L potential is supplied to the wiring CL[2] (see FIG. 10B). Since the H potential is maintained in [2], the transistor 112[2] remains on. be.

[0096] [Period T8] In a period T8, an H potential is supplied to the wiring SSL to turn on the transistor 132. (See FIG. 11A.) Transistors 112[1] to 112[4] are all ON. Since the line RBL is in the ON state, the line RBL and the line SL are electrically connected, and the potential of the line RBL is the L potential. It changes to rank.

[0097] If the potential of the node ND[2] is the L potential, the L potential is supplied to the wiring CL[2]. In this case, transistor 112[2] is turned off. Even if the potential of the wiring RBL changes to the H potential, the potential of the wiring RBL remains at the H potential. In this way, the information stored in the memory cell 110 can be known.

[0098] That is, in the period T8, the potential of the wiring CL corresponding to the memory cell 110 to be read is By setting the potential at L, the information stored in the memory cell 110 can be read. Cut.

[0099] [Period T9] During the period T9, the wirings CL[1] to CL[4], the wiring RSL, and the wiring SSL (See FIG. 11B.) Then, the transistor 131 and the transistor Starter 132 is turned off.

[0100] In this way, the storage device 100 shown in this embodiment functions as a NAND type storage device. It works.

[0101] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0102] (Embodiment 2) In this embodiment, other configurations and operation examples of the storage device 100 shown in the above embodiment will be described. We will explain about this.

[0103] <Storage device configuration example> Figure 12 shows a circuit diagram of the memory device 100B, and Figure 13 shows a circuit diagram of the memory device 100C. The storage device 100B and the storage device 100C are the same as the storage device 100 shown in the above embodiment. In order to reduce the repetition of the explanation, in this embodiment, the storage devices 100B and The differences between the storage device 100 and the storage device 100C will be mainly described.

[0104] The memory device 100B and the memory device 100C are memory devices 100 with the addition of a transistor 116. It has a configuration that

[0105] In the memory device 100B shown in FIG. 12, the source or drain of the transistor 111[1] One of the terminals is electrically connected to the wiring WBL1. One of the drains is electrically connected to the node ND[n], and the other is electrically connected to the wiring WBL2. The gate of the transistor 116 is electrically connected to a terminal 136.

[0106] The storage device 100C shown in FIG. 13 is a modified example of the storage device 100B. Then, either the source or drain of transistor 111[1] is connected to transistor 131 In the memory device 100C, the transistor The other of the source or drain of transistor 116 is connected to the source or drain of transistor 132. It is electrically connected to one of the drains.

[0107] As with the storage device 100, the transistors included in the storage device 100B and the storage device 100C The gate of the transistor 111 may be electrically connected to the wiring WL. The gate may be electrically connected to the wiring WL via the terminal 121. The back gate of the transistor 112 may be electrically connected to the wiring CL. The back gate of the transistor 2 may be electrically connected to the wiring CL via the terminal 122. The gate of the transistor 116 may be electrically connected to a wiring WSL, which will be described later. The gate of the transistor 116 may be electrically connected to the wiring WSL via a terminal 136. .

[0108] The transistor 116 can be the same as the transistor 111 . It is preferable to use an OS transistor as the transistor 116. The transistor 116 may be a transistor having a back gate.

[0109] <Example of storage device operation> An example of the operation of the storage device 100B will be described with reference to FIGS. 14, 15A, 15B, and 16. Here, a memory device 100B including four memory cells 110 will be described as an example. In addition, in the memory device 100B, the gate of the transistor 111[1] is connected to the wiring WL[1]. The gate of the transistor 111[2] is electrically connected to the wiring WL[2]. The gate of the transistor 111[3] is electrically connected to the wiring WL[3]. The gate of the transistor 111[4] is electrically connected to the wiring WL[4], and the transistor 11 It is assumed that the gate of 6 is electrically connected to the wiring WSL.

[0110] In addition, in the memory device 100B, the back gate of the transistor 112[1] is connected to the wiring CL[ The back gate of the transistor 112[2] is electrically connected to the wiring CL[2]. The back gate of the transistor 112[3] is electrically connected to the wiring CL[3]. , and the back gate of the transistor 112[4] is electrically connected to the wiring CL[4]. It is assumed that this is the case.

[0111] In the memory device 100B, the gate of the transistor 131 is electrically connected to the wiring RSL. One of the source and the drain of the transistor 131 is electrically connected to the wiring RBL. The gate of the transistor 132 is electrically connected to the wiring SSL. The other of the source and the drain of the transistor 132 is electrically connected to the wiring SL. It is assumed that

[0112] [Write operation] In this embodiment, an H potential is written to the memory cells 110[1] to 110[3]. An example of the operation when writing an L potential into the memory cell 110[4] will be described. 15A, 15B, and 16 are timing charts illustrating a write operation. FIG. 10 is a circuit diagram for explaining a write operation.

[0113] As an initial state, an L potential is written to the memory cells 110[1] to 110[4]. In addition, the wiring WL[1] to the wiring WL[4], the wiring CL[1] to the wiring CL[3], Wiring CL[4], wiring RSL, wiring RBL, wiring SSL, wiring SL, wiring WSL, wiring W It is assumed that the L potential is supplied to BL1 and the wiring WBL2.

[0114] [Period T11] In the period T11, the wiring WL[1], the wiring WL[2], the wiring WL[4], the wiring WSL, An H potential is applied to the wiring WBL1 and the wiring WBL2 (see FIG. 15A). 3] is left at the L potential. Then, transistor 111[1], transistor 111[ 2], transistor 111[4], and transistor 116 are turned on, and the node The potentials of the nodes ND[1] to ND[4] become H potentials. 1] to transistor 112[4] are turned on.

[0115] [Period T12] In the period T12, the L potential is supplied to the wiring WL[2] and the wiring WL[4] (FIG. 15 (See B.) Then, transistor 111[2] and transistor 111[4] are turned off. The charge written to the nodes ND[2] and ND[3] is retained. In this embodiment, a charge equivalent to an H potential is held. Then, the potential of the node ND[4] becomes the L potential. 12[4] becomes OFF state.

[0116] [Period T13] In a period T13, the L potential is supplied to the wiring WL[1] and the wiring WSL (see FIG. 16). Then, the transistor 111[1] and the transistor 116 are turned off. The charges written to the nodes ND[1] and ND[4] are retained. In this state, a charge equivalent to an H potential is held at node ND[1], and an L potential is held at node ND[4]. A charge corresponding to the potential is retained.

[0117] In the storage device 100B, information can be written from both the wiring WBL1 and the wiring WBL2. Therefore, the time required for the write operation can be made shorter than that of the storage device 100. .

[0118] The storage device 100C can operate in the same manner as the storage device 100B. In 100C, during a write operation, the wiring RBL functions as the wiring WBL1, and the wiring SL functions as the wiring WBL2. In the memory device 100C, the transistor 13 functions as the line WBL2 during a write operation. 1 and the transistor 132 are turned on. At this time, at least one of the plurality of wirings CL By supplying an L potential to the wiring RBL and the wiring SL, a short circuit between the wiring RBL and the wiring SL can be prevented.

[0119] In the storage device 100B and the storage device 100C, n is preferably an even number. The transistor 111 that is turned off during the interval T11 is the (n / 2+1)th transistor 111 is.

[0120] [Read operation] The read operation of the storage devices 100B and 100C is performed in the same manner as the storage device 100. Therefore, the description will be omitted in this embodiment.

[0121] <Modification> A modification of the storage device 100B is shown in FIG. 17 as storage device 100D. A modified example is shown in FIG. 18 as storage device 100E. E is memory device 100B and memory device 100C except for transistor 116. The transistor 111[k] and the transistor 111[k+1] are electrically isolated from each other. .

[0122] In the storage device 100D and the storage device 100E, n is preferably an even number. In this case, k can be set to n / 2.

[0123] In the memory cell 110[k+1], the source or drain of the transistor 111[k+1] One of the drains is electrically connected to the gate of transistor 112[k+1], and the other is It is electrically connected to either the source or the drain of the transistor 111[k+2] (not shown). will be done.

[0124] In addition, in the memory cell 110[n], the source or drain of the transistor 111[n] One of the inputs is electrically connected to the gate of the transistor 112[n], and the other is connected to the wiring WBL 2. Also, one of the source or drain of the transistor 111[n] is electrically connected to the The other side is connected to the source or drain of the transistor 111[n-1] (not shown). electrically connected.

[0125] In the memory cells 110[k+1] to 110[n], the transistor 111 The node where one of the source or drain of the transistor 112 is electrically connected to the gate of the transistor 112. acts as node ND.

[0126] The write operation of the memory device 100D and the memory device 100E is turned off during the period T11. The transistor 111 (for example, the transistor 111 in the above description of the write operation) 3].) except that it does not have the same operation as storage device 100B and storage device 100C. The read operation can be performed in the same manner as in the memory device 100B and the memory device 100C. can.

[0127] In the memory device 100D and the memory device 100E, the memory cells 110[1] to The write operation of the memory cell 110[k] and the write operation of the memory cells 110[k+1] to 110[k+1] The write operation of 0[n] can be performed separately. Therefore, the power consumption required for the write operation is Power consumption can be reduced.

[0128] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0129] (Embodiment 3) In this embodiment, a configuration example of a semiconductor device 200 including a memory device 100 will be described.

[0130] FIG. 19 is a block diagram illustrating a configuration example of a semiconductor device 200 according to one embodiment of the present invention. The semiconductor device 200 shown in FIG. 19 includes a driver circuit 210 and a memory array 220. The memory array 220 includes one or more memory devices 100. In FIG. An example in which multiple storage devices 100 (multiple strings) are arranged in a matrix. This shows:

[0131] The drive circuit 210 includes a PSW 241 (power switch), a PSW 242, and a peripheral circuit 2 The peripheral circuit 215 includes a peripheral circuit 211, a control circuit 212 (Cont control circuit), and a voltage generating circuit 228.

[0132] In the semiconductor device 200, each circuit, each signal, and each voltage may be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. For example, a power supply circuit A circuit or a boost circuit may be provided. Signals BW, CE, GW, CLK, WAKE, ADDR , WDA, PON1, PON2 are input signals from the outside, and signal RDA is output to the outside. The signal CLK is a clock signal.

[0133] The signals BW, CE, and GW are control signals. The signal CE is a chip enable signal. signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. The signal ADDR is the address signal. The signal WDA is the write enable signal. The signal PON1 and PON2 are write data signals, and the signal RDA is a read data signal. are signals for power gating control. Alternatively, the signal may be generated by the control circuit 212.

[0134] The control circuit 212 is a logic circuit having a function of controlling the overall operation of the semiconductor device 200. For example, the control circuit may be a logic circuit that converts the signals CE, GW, and BW into logic signals. The operation mode (for example, write operation, read operation) of the semiconductor device 200 is determined by calculation. Alternatively, the control circuit 212 may set the peripherals to perform this mode of operation. Generates a control signal for circuit 211.

[0135] The voltage generating circuit 228 has a function of generating a negative voltage. For example, when a high-level signal is given to WAKE, When this signal is input, the signal CLK is input to the voltage generating circuit 228, and the voltage generating circuit 228 generates a negative voltage. Complete.

[0136] The peripheral circuit 211 is used to write and read data to and from the storage device 100. The peripheral circuit 211 includes a row decoder 221, a column decoder 222, and a Column Decoder 222, Row Driver 223 er), a column driver 224, an input circuit 225 t Cir.), an output circuit 226 (Output Cir.), a sense amplifier 227 (S It has a Sense Amplifier.

[0137] The row decoder 221 and the column decoder 222 have the function of decoding the signal ADDR. The row decoder 221 is a circuit for specifying the row to be accessed, and the column decoder 222 is a circuit for specifying a column to be accessed. The column driver 224 has a function of selecting the wiring WL designated by the column driver 224. A function for writing data to the storage device 100, a function for reading data from the storage device 100, and a function for storing the read data. It has functions such as holding.

[0138] The input circuit 225 has a function of holding the signal WDA. The output data of the input circuit 225 is output to the column driver 224. The data (Din) that the column driver 224 reads from the memory device 100 is written to the The data (Dout) is output to the output circuit 226. The output circuit 226 stores the Dout. The output circuit 226 outputs Dout to the outside of the semiconductor device 200. The data output from the output circuit 226 is the signal RDA.

[0139] The PSW 241 has a function of controlling the supply of VDD to the peripheral circuit 215. has the function of controlling the supply of VHM to the row driver 223. The high power supply voltage of 200 is VDD, and the low power supply voltage is GND (ground potential). HM is a high power supply voltage used to set the word line to a high level, and is higher than VDD. The signal PON1 controls the on / off of the PSW 241, and the signal PON2 controls the 19, in the peripheral circuit 215, VDD Although the number of power domains to which the power is supplied is set to 1, it is also possible to have multiple power domains. A power switch may be provided for each power domain.

[0140] The drive circuit 210 and the memory array 220 may be provided on the same plane. As shown in the figure, the drive circuit 210 and the memory array 220 may be provided overlapping each other. By overlapping the memory array 220, the signal propagation distance can be shortened. As shown in FIG. 20B, a plurality of memory arrays 220 are stacked on the driving circuit 210. That's fine.

[0141] As shown in FIG. 20C, the memory array 220 is disposed above and below the drive circuit 210. In FIG. 20C, one memory layer may be provided above and one memory layer below the driving circuit 210. In this example, a plurality of memory arrays 220 are provided. By placing them in a sandwiched position, the signal propagation distance can be further shortened. The memory array 220 is stacked on the upper layer of the drive circuit 210, and the memory array 220 is stacked on the lower layer of the drive circuit 210. The number of layers of the memory array 220 may be one or more. The number of stacked memory arrays 220 and the memory arrays stacked below the drive circuit 210 Preferably, the 220 numbers are equal.

[0142] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0143] (Fourth embodiment) In this embodiment, the memory device 100 and the semiconductor device 200 described in the above embodiment are The structure of an applicable transistor will be described. As an example, A structure in which transistors are stacked will be described. This increases the degree of freedom in device design. By providing the layers, the integration degree of the semiconductor device can be increased.

[0144] A part of the cross-sectional structure of the semiconductor device is shown in FIG. 21. The semiconductor device shown in FIG. 550, a transistor 500, and a capacitor 600. 23A is a cross-sectional view of the transistor 500 in the channel length direction, and FIG. 23B is a cross-sectional view of the transistor 500 in the channel width direction. 23C is a cross-sectional view of transistor 550 in the channel width direction. For example, the transistor 500 corresponds to the transistor 111 shown in the above embodiment. The transistor 550 corresponds to the transistor 112. The capacitance 600 corresponds to the capacitance 113. Correct.

[0145] The transistor 500 is an OS transistor. Therefore, the data voltage written to the storage node via the transistor 500 is In other words, the lift of the storage node (node ​​ND) The frequency of refresh operations is reduced, or the refresh operation is not required, so that the semiconductor device The power consumption can be reduced.

[0146] In FIG. 21, transistor 500 is provided above transistor 550, and capacitor 600 is It is provided above the transistor 550 and the transistor 500 .

[0147] The transistor 550 is disposed on a substrate 311 and includes a conductor 316, an insulator 315, and a substrate 316. 11, a semiconductor region 313 serving as a source region or a drain region, It has a resistive region 314a and a low resistive region 314b.

[0148] As shown in FIG. 23C, transistor 550 is formed by connecting the upper surface and channel of semiconductor region 313. The side surfaces in the width direction are covered with the conductor 316 via the insulator 315. By making the resistor 550 a fin type, the effective channel width is increased, This can improve the on-characteristics of the transistor 550. In addition, the contribution of the electric field of the gate electrode can be increased, which can improve the off-state characteristics of the transistor 550. .

[0149] The transistor 550 may be a p-channel transistor or an n-channel transistor. Either a transistor or a gate driver may be used.

[0150] The region where the channel of the semiconductor region 313 is formed, the region nearby, the source region, or the drain region In the low resistance region 314a and the low resistance region 314b, which are the drain region, silicon is It preferably contains a semiconductor such as a silicon-based semiconductor, and preferably contains single crystal silicon. Or Ge (germanium), SiGe (silicon germanium), GaAs (gas arsenide) It may be formed of a material having gallium aluminum arsenide (GaAlAs), etc. By applying stress to the crystal lattice and changing the lattice spacing, we can control the effective mass of silicon. Alternatively, GaAs and GaAlAs may be used to form a transistor. The transistor 550 may be a HEMT.

[0151] The low resistance region 314a and the low resistance region 314b are semiconductor regions applied to the semiconductor region 313. In addition to the body material, elements that impart n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. The element imparting electrical conductivity is included.

[0152] The conductor 316 that functions as the gate electrode is made of an element that gives n-type conductivity, such as arsenic or phosphorus. Semiconductor materials such as silicon that contain elements that impart p-type conductivity, such as silicon or boron A conductive material such as a metal material, an alloy material, or a metal oxide material can be used.

[0153] In addition, since the work function is determined by the conductor material, by selecting the conductor material, Specifically, the threshold voltage of the transistor can be adjusted by using titanium nitride as the conductor. It is preferable to use materials such as tantalum nitride or tantalum nitride. To achieve this, metal materials such as tungsten and aluminum are used as layers for the conductor. is preferable, and tungsten is particularly preferable in terms of heat resistance.

[0154] The transistor 550 is formed on a silicon on insulator (SOI) substrate or the like. It may be formed using

[0155] In addition, SOI substrates are made by implanting oxygen ions into mirror-polished wafers and then heating them at high temperatures. This allows an oxide layer to form at a certain depth from the surface, and also eliminates defects that have occurred in the surface layer. SIMOX (Separation by Implanted Oxide) xygen) substrate and the growth of microvoids formed by hydrogen ion implantation through heat treatment. Smart Cut method and ELTRAN method (registered trademark: Epit The SOI substrate was fabricated using a method such as axial layer transfer. A transistor formed using a single crystal substrate may have a single crystal semiconductor in a channel formation region. It has a conductor.

[0156] Note that the transistor 550 shown in FIG. 21 is an example, and the circuit configuration is not limited to this. For example, a semiconductor device may be used as an OS transistor. A unipolar circuit consisting of only n-channel transistors (such as n-channel transistors) 22, the configuration of the transistor 550 is The transistor 500 may have a similar configuration to that of the transistor 500. The details of the transistor 500 will be described later. Describe.

[0157] Over the transistor 550, an insulator 320, an insulator 322, an insulator 324, and an insulator The bodies 326 are stacked one on top of the other.

[0158] The insulators 320, 322, 324, and 326 may be, for example, oxide. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxide Aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0159] In this specification, silicon oxynitride refers to a material containing more oxygen than nitrogen as its composition. Silicon nitride oxide refers to silicon that has a high content of nitrogen rather than oxygen. Thus, in this specification, "oxynitride" refers to a material having a high silicon content. "Oxynitride" refers to a material that has a higher oxygen content than nitrogen in its composition. This refers to a material that contains more nitrogen than oxygen.

[0160] The insulator 322 smooths out the steps caused by the transistor 550 and other components provided below it. For example, the top surface of the insulator 322 may have a function as a planarizing film. To improve flatness, the surface is flattened by a planarization process such as chemical mechanical polishing (CMP). It's fine.

[0161] The insulator 324 is also provided with a substrate 311 or a transistor 550 or the like. A film having a barrier property that prevents hydrogen and impurities from diffusing is used in the area where the capacitor 500 is provided. It is preferable that

[0162] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, a semiconductor having an oxide semiconductor such as the transistor 500 can be used. When hydrogen diffuses into the element, the characteristics of the semiconductor element may be deteriorated. A film that suppresses hydrogen diffusion is used between the transistor 500 and the transistor 550. Specifically, the film that suppresses hydrogen diffusion is a film that has a small amount of hydrogen desorption. The membrane.

[0163] The amount of desorbed hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of hydrogen desorption from the insulator 324 can be measured by TDS analysis when the surface temperature of the film is 5 In the range of 0 to 500°C, the amount of desorption converted to hydrogen atoms is Converted to 10 x 10 15 atoms / cm 2 Less than or equal to 5 x 10 15 at oms / cm 2 The following is fine.

[0164] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, The dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. The relative dielectric constant of the insulating material 26 is preferably 0.7 times or less than the relative dielectric constant of the insulating material 324, and more preferably 0.6 times or less. It is more preferable to use a material with a low dielectric constant as the interlayer film to reduce the parasitic capacitance that occurs between wiring. It is possible.

[0165] In addition, the insulators 320, 322, 324, and 326 have a capacitance of 600 Alternatively, the conductor 328 and the conductor 330 connected to the transistor 500 are embedded. The conductors 328 and 330 function as plugs or wiring. In addition, the conductor having the function of a plug or wiring can be used to integrate multiple components. In addition, in this specification and the like, the same reference numerals may be used to refer to wiring and devices connected to the wiring. In other words, when a part of the conductor functions as a wiring, , and a portion of the conductor may also function as a plug.

[0166] The materials for each plug and wiring (conductor 328, conductor 330, etc.) include metal materials, alloys, and the like. Conductive materials such as gold, metal nitride, or metal oxide materials are used as single or multilayered layers. High-melting materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, can be used. It is preferable to use a point material, and it is preferable to use tungsten. It is preferable to form the wiring layer from a low-resistance conductive material such as aluminum or copper. This can reduce the wiring resistance.

[0167] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring that connects to the transistor 550. The conductor 356 is made of the same material as the conductors 328 and 330. It can be established.

[0168] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator. In addition, the conductor 356 has a barrier property against hydrogen. It is preferable that the insulating material 350 contains a conductor. In particular, the insulating material 350 has a barrier property against hydrogen. In the opening, a conductor having a barrier property against hydrogen is formed. The transistor 550 and the transistor 500 may be separated by a barrier layer. This can suppress the diffusion of hydrogen from the resistor 550 to the transistor 500.

[0169] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from the transistor 550 can be suppressed while maintaining the conductivity of the transistor 550. In this case, the tantalum nitride layer having a barrier property against hydrogen has a barrier property against hydrogen. It is preferable that the insulating material 350 is in contact with the insulating material 350.

[0170] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. An insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductive material 328 and the conductive material 330 can be formed using the same materials.

[0171] For example, the insulator 360 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator. The conductor 366 has a barrier property against hydrogen. It is preferable that the insulating material 360 contains a conductor. In particular, the insulating material 360 has a barrier property against hydrogen. In the opening, a conductor having a barrier property against hydrogen is formed. The transistor 550 and the transistor 500 may be separated by a barrier layer. This can suppress the diffusion of hydrogen from the resistor 550 to the transistor 500.

[0172] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. An insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed on the insulators 370, 372, and 374. The conductor 376 functions as a plug or wiring. The conductive material 328 and the conductive material 330 can be formed using the same materials.

[0173] For example, the insulator 370 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator. In addition, the conductor 376 has a barrier property against hydrogen. It is preferable that the insulating material 370 contains a conductor. In particular, the insulating material 370 has a barrier property against hydrogen. In the opening, a conductor having a barrier property against hydrogen is formed. The transistor 550 and the transistor 500 may be separated by a barrier layer. This can suppress the diffusion of hydrogen from the resistor 550 to the transistor 500.

[0174] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in FIG. An insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. A conductor 386 is formed on the insulators 380, 382, ​​and 384. The conductor 386 functions as a plug or wiring. The conductive material 328 and the conductive material 330 can be formed using the same materials.

[0175] For example, the insulator 380 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator. The conductor 386 has a barrier property against hydrogen. It is preferable that the insulating material 380 has a barrier property against hydrogen. In the opening, a conductor having a barrier property against hydrogen is formed. The transistor 550 and the transistor 500 may be separated by a barrier layer. This can suppress the diffusion of hydrogen from the resistor 550 to the transistor 500.

[0176] In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, and the conductor 376 The wiring layer including the conductor 386 has been described above. The semiconductor device is not limited to this. Alternatively, the number of wiring layers may be three or less, or five or more wiring layers similar to the wiring layer including the conductor 356 may be provided. Good too.

[0177] On the insulator 384, an insulator 510, an insulator 512, an insulator 514, and an insulator 516 are formed. , and are stacked in this order. It is preferable that either of the insulating layers 516 is made of a material that has a barrier property against oxygen or hydrogen. stomach.

[0178] For example, the insulator 510 and the insulator 514 may include, for example, the substrate 311 or the transistor. The region where the transistor 500 is provided is filled with hydrogen and impurities. Therefore, it is preferable to use a film having a barrier property against the insulator 324. Materials can be used.

[0179] As an example of a film with barrier properties against hydrogen, silicon nitride formed by CVD is used. Here, a semiconductor element including an oxide semiconductor such as the transistor 500 can be The diffusion of hydrogen may deteriorate the characteristics of the semiconductor device. A film that suppresses hydrogen diffusion is used between the transistor 500 and the transistor 550. is preferred.

[0180] In addition, as a film having a barrier property against hydrogen, for example, an insulator 510 and an insulator 5 14 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable.

[0181] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. Therefore, it has a high blocking effect that prevents impurities such as acid and moisture from passing through the membrane. Aluminum oxide is resistant to hydrogen, moisture, etc. during and after the transistor manufacturing process. It is possible to prevent impurities from being mixed into the transistor 500. This can suppress the release of oxygen from the oxide that makes up the transistor. Suitable for use as a protective film against 500.

[0182] For example, the insulators 512 and 516 may be made of the same material as the insulator 320. In addition, by using materials with a relatively low dielectric constant for these insulators, , the parasitic capacitance occurring between the wirings can be reduced. The body 516 may be a silicon oxide film, a silicon oxynitride film, or the like.

[0183] In addition, the insulators 510, 512, 514, and 516 are provided with conductors 5 18, and conductors (for example, conductor 503) that constitute the transistor 500 are embedded. The conductor 518 is connected to the capacitor 600 or the transistor 550. The conductor 518 functions as a plug or wiring. It may be provided using the same material as the body 330 .

[0184] In particular, the insulator 510 and the conductor 518 in the area in contact with the insulator 514 are free of oxygen, hydrogen, It is preferable that the conductive material has a barrier property against water. The transistor 550 and the transistor 500 have a barrier property against oxygen, hydrogen, and water. The layer separating the transistor 550 from the transistor 500 can separate the hydrogen Diffusion can be suppressed.

[0185] Above the insulator 516 is the transistor 500 .

[0186] As shown in FIGS. 23A and 23B, transistor 500 includes an insulator 514 and an insulator The conductor 503 is disposed so as to be embedded in the insulator 516, and the insulator 516 and the conductor 5 an insulator 520 disposed on the insulating layer 520; and an insulator 522 disposed on the insulating layer 520. An insulator 524 is disposed on the insulator 522, and an oxide 5 is disposed on the insulator 524. 30a, oxide 530b disposed on oxide 530a, and oxide 530b disposed on oxide 530b. Conductor 542a and conductor 542b are spaced apart from each other, and conductor 542a and conductor The conductive material 542a is disposed on the conductive material 542b, and an opening is formed between the conductive material 542a and the conductive material 542b so as to overlap the conductive material 542a. an insulator 580 disposed on the bottom and side of the opening; an insulator 545 disposed on the bottom and side of the opening; and a conductor 560 disposed on the forming surface.

[0187] As shown in FIGS. 23A and 23B, the oxide 530a, the oxide 530b, the conductor 542a, and an insulator 544 is disposed between the conductor 542b and the insulator 580. 23A and 23B, the conductor 560 is preferably 5, and a conductor 560a provided inside the conductor 560a. 23A and 23B, the conductor 560b is preferably formed on the substrate 500. As shown, insulator 574 is disposed over insulator 580, conductor 560, and insulator 545. It is preferable that the

[0188] In this specification and the like, the oxide 530a and the oxide 530b are collectively referred to as oxides. Sometimes it's 530.

[0189] In the transistor 500, the region where the channel is formed and the vicinity thereof are oxidized. 5 shows a structure in which two layers of a metal 530a and an oxide 530b are stacked. For example, a single layer of oxide 530b or a stack of three or more layers may be used. A configuration may be provided.

[0190] In addition, although the conductor 560 in the transistor 500 has a two-layer structure, The invention is not limited to this. For example, the conductor 560 may have a single layer structure. However, it may have a laminated structure of three or more layers. The transistor 500 is an example, and the configuration is not limited to this, and may vary depending on the circuit configuration, driving method, etc. An appropriate transistor can be used accordingly.

[0191] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and The conductor 542b functions as a source electrode and a drain electrode, respectively. As shown, the conductor 560 is inserted through the opening in the insulator 580 and the conductors 542a and 542b. The conductor 560, the conductor 542a, and the conductor 542b are formed so as to be embedded in the sandwiched region. The placement of the conductive material 542b is selected to be self-aligned with the opening of the insulator 580. In the transistor 500, the gate electrode is connected between the source electrode and the drain electrode. Therefore, the conductor 560 can be positioned with a margin for alignment. Since the transistor 500 can be formed without any trouble, the area occupied by the transistor 500 can be reduced. This allows for miniaturization and high integration of semiconductor devices.

[0192] Furthermore, a conductor 560 is formed in a self-aligned manner in the region between the conductors 542a and 542b. Therefore, the conductor 560 has an overlapping area with the conductor 542a or the conductor 542b. This prevents the formation of a gap between the conductor 560 and the conductors 542a and 542b. Therefore, the parasitic capacitance of the transistor 500 can be reduced. It is possible to improve the speed and have high frequency characteristics.

[0193] The conductor 560 may function as a first gate (also called a top gate) electrode. The conductor 503 may function as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the conductor 503 is linked to the potential applied to the conductor 560. The threshold voltage of the transistor 500 can be controlled by changing it independently. In particular, applying a negative potential to the conductor 503 It is possible to increase the threshold voltage and reduce the off-current. Applying a negative potential to the conductor 503 increases the potential applied to the conductor 560 compared to not applying a negative potential. The drain current when the potential is 0V can be reduced.

[0194] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, The electric field generated by the conductor 503 is connected to the electric field generated by the conductor 503, and the chalcogenide formed in the oxide 530 The chel forming area can be covered.

[0195] In this specification, a pair of gate electrodes (a first gate electrode and a second gate electrode) The structure of a transistor in which the channel formation region is electrically surrounded by the electric field of This is called a surrounded channel (S-channel) configuration. The disclosed S-channel configuration is different from the Fin type and planar type configurations. By adopting a -channel structure, the resistance to short channel effects is increased. This makes it possible to provide a transistor in which the short channel effect is less likely to occur.

[0196] The conductor 503 has the same structure as the conductor 518, and the insulators 514 and 5 Conductor 503a is formed in contact with the inner wall of opening 16, and conductor 503b is formed further inside. In the transistor 500, the conductor 503a and the conductor 503b are Although a stacked structure is shown, the present invention is not limited to this. The electric conductor 503 may be provided as a single layer or as a laminated structure of three or more layers.

[0197] Here, the conductor 503a prevents the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use a conductive material that has the function of suppressing the impurities (i.e., the impurities are less likely to permeate). Alternatively, the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is suppressed. It is preferable to use a conductive material that has the above-mentioned function (i.e., that is difficult for oxygen to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of the above impurities or oxygen. The function is to suppress the diffusion of any one or all of the above oxygen.

[0198] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b This can prevent the conductivity from decreasing due to oxidation.

[0199] When the conductor 503 also functions as a wiring, the conductor 503b is made of tungsten, copper, Alternatively, it is preferable to use a highly conductive material containing aluminum as a main component. In this embodiment, the conductor 503 is illustrated as a stack of conductors 503a and 503b. However, the conductor 503 may have a single layer structure.

[0200] The insulators 520, 522, and 524 function as a second gate insulating film. It has.

[0201] Here, the insulator 524 in contact with the oxide 530 has more oxygen than the stoichiometric composition. It is preferable to use an insulator containing oxygen. The oxygen is released from the film by heating. In this specification and elsewhere, the oxygen released by heating may be referred to as "excess oxygen." That is, a region containing excess oxygen (also called an "excess oxygen region") is formed in the insulator 524. It is preferable that the insulator containing such excess oxygen is in contact with the oxide 530. By providing the oxide 530, oxygen vacancies (V O :oxygen vacancy and This can reduce the oxidation (also referred to as oxidation) and improve the reliability of the transistor 500. When hydrogen enters the oxygen vacancy in the substance 530, the defect (hereinafter referred to as V O It may be called H. ) can act as a donor, generating electrons as carriers. The oxygen atom may bond with the metal atom to generate electrons, which act as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen has a normally-on characteristic. In addition, hydrogen in oxide semiconductors tends to move due to stresses such as heat and electric fields. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor will decrease. In one embodiment of the present invention, V in the oxide 530 O Reduce H as much as possible, It is preferable to make it highly pure or substantially highly pure. O H is enough To obtain an oxide semiconductor with reduced impurities, it is necessary to remove impurities such as moisture and hydrogen from the oxide semiconductor. (also called "dehydration" or "dehydrogenation treatment") and supplying oxygen to the oxide semiconductor. It is important to compensate for the oxygen deficiency by adding oxygen (also called "oxygenation treatment"). O H, etc. To use an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor This allows stable electrical properties to be imparted.

[0202] As an insulator having an excess oxygen region, specifically, an oxide film in which some oxygen is released by heating is used. It is preferable to use a material that releases oxygen when heated. In the normal desorption spectroscopy (DDS) analysis, The calculated amount of oxygen released is 1.0 x 10 18 atoms / cm 3 More than 1.0x, preferably 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis was 100°C or higher and 700°C or lower, or 10 The temperature is preferably in the range of 0°C or higher and 400°C or lower.

[0203] In addition, the insulator having the excess oxygen region is brought into contact with the oxide 530 and then subjected to heat treatment. One or more of the following may be performed: microwave processing, RF processing, or the like. By this, water or hydrogen in the oxide 530 can be removed. In 30, a reaction occurs in which the VoH bond is broken, in other words, "V O H→Vo+H This reaction occurs, and some of the hydrogen generated is dehydrogenated. The oxide 530 or the insulator adjacent to the oxide 530 is removed by combining with the element to form H2O. In addition, some of the hydrogen may be gettered to the conductor 542.

[0204] The microwave treatment may be carried out using, for example, an apparatus having a power source for generating high-density plasma, Alternatively, it is preferable to use an apparatus having a power source for applying RF to the substrate side. By using a gas containing oxygen and high density plasma, high density oxygen radicals are generated. By applying RF to the substrate side, the oxide generated by the high-density plasma can be The atomic radicals can be efficiently introduced into the oxide 530 or into the insulator in the vicinity of the oxide 530. The microwave treatment can be carried out at a pressure of 133 Pa or more, preferably 200 Pa or more. The pressure may be a or more, more preferably 400 Pa or more. The gas introduced into the device is, for example, oxygen and argon, and the oxygen flow ratio (O2 / The gas is preferably heated at a concentration of (O2 + Ar) of 50% or less, preferably 10% or more and 30% or less.

[0205] In addition, during the manufacturing process of the transistor 500, when the surface of the oxide 530 is exposed, The heat treatment is preferably performed at a temperature of 100° C. or higher and 450° C. or lower. More preferably, the temperature is 350° C. or higher and 400° C. or lower. or an inert gas atmosphere, or an oxidizing gas of 10 ppm or more, 1% or more, or 1 For example, it is preferable to carry out the heat treatment in an oxygen atmosphere. By this, oxygen is supplied to the oxide 530, and oxygen vacancies (V O ) can be reduced. The heat treatment may be carried out under reduced pressure or in an atmosphere of nitrogen gas or inert gas. After heat treatment in an oxidizing gas atmosphere, 10ppm of oxidizing gas was added to compensate for the oxygen that was removed. The oxidation may be carried out in an atmosphere containing 1% or more, 1% or more, or 10% or more. After heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more, The heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0206] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are filled. In other words, it promotes the reaction "Vo + O → null" Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530. This allows the hydrogen to be removed as H2O (dehydration). The hydrogen remaining in 530 recombines with the oxygen vacancy and V O By suppressing the formation of H This can be done.

[0207] Also, if the insulator 524 has an excess oxygen region, the insulator 522 may be oxygen-resistant (e.g., It has the function of suppressing the diffusion of oxygen (element atoms, oxygen molecules, etc.) (the oxygen mentioned above is less likely to permeate) is preferred.

[0208] The insulator 522 has a function of suppressing the diffusion of oxygen and impurities, and the oxide 530 is effective. The oxygen does not diffuse to the insulator 520 side, which is preferable. This can prevent the insulator 524 and the oxide 530 from reacting with oxygen.

[0209] The insulator 522 may be, for example, aluminum oxide, hafnium oxide, aluminum and hafnium oxide. oxides containing ammonium (hafnium aluminate), tantalum oxide, zirconium oxide, titanium Lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (B Insulators containing so-called high-k materials such as a,Sr)TiO3 (BST) are deposited as single layers or As transistors become smaller and more highly integrated, Thinning the gate insulating film can cause problems such as leakage current. By using high-k materials as insulators that function as a transistor, the physical thickness can be maintained. This makes it possible to reduce the gate potential during start operation.

[0210] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the oxygen is difficult to penetrate) ) Insulators containing oxides of one or both of aluminum and hafnium, which are insulating materials It is recommended to use an insulator containing oxides of either or both aluminum and hafnium. , aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium It is preferable to use such a material as the insulator 5. When the insulator 522 is formed, the insulator 522 prevents oxygen from being released from the oxide 530 and prevents the transistor from being formed. It functions as a layer that suppresses the intrusion of impurities such as hydrogen from the periphery of 500 into the oxide 530. .

[0211] Alternatively, for example, aluminum oxide, bismuth oxide, or germanium oxide may be added to these insulators. Niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Alternatively, zirconium oxide may be added to these insulators, or these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

[0212] The insulator 520 is preferably thermally stable. For example, silicon oxide and Silicon oxide nitride and silicon oxynitride are suitable because they are thermally stable. By combining the insulator with silicon oxide or silicon oxynitride, thermally stable and It is possible to obtain the insulator 520 or the insulator 526 having a laminated structure with a high relative dielectric constant.

[0213] 23A and 23B, the second transistor 500 has a three-layer laminated structure. As the gate insulating film, an insulator 520, an insulator 522, and an insulator 524 are illustrated. However, the second gate insulating film may have a single layer, two layers, or a laminated structure of four or more layers. In this case, the laminated structure is not limited to the same material, but may be a laminated structure made of different materials. That's fine too.

[0214] The transistor 500 has an oxide 530 including a channel formation region, which functions as an oxide semiconductor. For example, the oxide 530 is an In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , neodymium, hafnium, tantalum, tungsten, magnesium, etc. It is preferable to use a metal oxide such as one or more metal oxides.

[0215] The metal oxide that functions as an oxide semiconductor may be formed by a sputtering method. Alternatively, the ALD (Atomic Layer Deposition) method may be used. The metal oxide functioning as an oxide semiconductor will be described in detail in another embodiment. do.

[0216] In addition, the metal oxide that functions as a channel formation region in the oxide 530 is a band gap metal oxide. It is preferable to use a material with a gap of 2 eV or more, preferably 2.5 eV or more. By using metal oxides with a wide band gap, the off-state current of transistors can be reduced. It is possible.

[0217] The oxide 530 has the oxide 530a under the oxide 530b, so that the oxide 530 is thicker than the oxide 530a. This can suppress the diffusion of impurities from the underlying structure into the oxide 530b. Cut.

[0218] The oxide 530 has a laminated structure of a plurality of oxide layers each having a different atomic ratio of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the constituent elements are preferably The atomic ratio of element M in the oxide 530b is It is preferable that the atomic ratio of the metal oxide used for the oxide 530a is larger than that of the element M. In the oxide 530b, the atomic ratio of the element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element M. In the metal oxide used, the atomic ratio of In to the element M is It is preferable that the atomic ratio of In to the element M in the metal oxide is larger than that of In.

[0219] In addition, the energy of the conduction band minimum of the oxide 530a is smaller than that of the oxide 530b. In other words, the electron affinity of the oxide 530a is preferably higher than the energy. , preferably smaller than the electron affinity of oxide 530b.

[0220] Here, at the junction between the oxide 530a and the oxide 530b, the energy of the conduction band minimum is In other words, the junction of oxide 530a and oxide 530b The energy level of the conduction band minimum in this region is said to change continuously or to form a continuous junction. To achieve this, the oxide 530a and the oxide 530b must be at the interface between them. This can reduce the defect level density of the mixed layer formed by the above process.

[0221] Specifically, the oxide 530a and the oxide 530b have a common element other than oxygen (main component). By using a mixed layer with a low defect level density, for example, an oxide When 530b is an In-Ga-Zn oxide, the oxide 530a is an In-Ga-Zn oxide. It is preferable to use gallium oxide, Ga-Zn oxide, gallium oxide, etc.

[0222] At this time, the main path of the carriers is the oxide 530b. This reduces the defect state density at the interface between the oxide 530a and the oxide 530b. Therefore, the influence of interface scattering on carrier conduction is reduced, and the The transistor 500 can obtain a high on-state current.

[0223] On the oxide 530b, a conductor 542a is formed, which functions as a source electrode and a drain electrode. The conductor 542a and the conductor 542b are provided as follows: , aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum , tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconia Sodium, beryllium, indium, ruthenium, iridium, strontium, lanthanum or an alloy containing the above metal elements, or It is preferable to use a combination of alloys, for example, tantalum nitride, titanium nitride, tantalum titanium and aluminum nitrides, tantalum and aluminum nitrides, Ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum It is preferable to use oxides containing nickel. , nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide Ruthenium, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel Oxides containing oxygen are conductive materials that are resistant to oxidation or that maintain conductivity even after absorbing oxygen. Furthermore, metal nitride films such as tantalum nitride are preferable because they can be easily etched by hydrogen or oxygen. It is preferable because it has a barrier property against elements.

[0224] In addition, although the conductor 542a and the conductor 542b are shown as having a single layer configuration in FIG. Alternatively, a laminated structure of two or more layers may be used. For example, a tantalum nitride film and a tungsten film may be laminated. Alternatively, a titanium film and an aluminum film may be stacked. Two-layer structure with an aluminum film laminated on a copper-magnesium-aluminum alloy film, and a copper film on a copper-magnesium-aluminum alloy film Two-layer structure with a copper film on a titanium film, two-layer structure with a copper film on a tungsten film A two-layer structure may also be used.

[0225] Also, a titanium film or titanium nitride film and an aluminum film overlaid on the titanium film or titanium nitride film are used. A titanium film or a copper film is laminated, and a titanium film or a titanium nitride film is further formed on the aluminum film or a copper film. Three-layer structure: a molybdenum film or molybdenum nitride film and a molybdenum film or molybdenum nitride film. An aluminum film or copper film is laminated on top of the molybdenum film, and then a molybdenum film or The molybdenum nitride film may be formed as a three-layer structure. A transparent conductive material containing zinc oxide may also be used.

[0226] As shown in FIG. 23A, the oxide 530 and the conductor 542a (conductor 542b) At the interface and its vicinity, a region 543a and a region 543b are formed as low resistance regions. In this case, the region 543a functions as either a source region or a drain region. The region 543b functions as the other of the source region and the drain region. A channel forming region is formed in the region sandwiched between region 543a and region 543b.

[0227] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, The oxygen concentration in the region 543a (region 543b) may decrease. The metal contained in the conductor 542a (conductor 542b) and the oxide 530 are mixed in the region 543b. In such a case, a metal compound layer containing the metal compound may be formed in the region 543a (region The carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region. do.

[0228] The insulator 544 is provided to cover the conductor 542a and the conductor 542b. The insulator 544 prevents oxidation of the oxide 542a and the conductor 542b. 530 and may be provided to be in contact with the insulator 524.

[0229] Insulator 544 includes hafnium, aluminum, gallium, yttrium, and zirconium. Aluminum, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, or a metal oxide containing one or more selected from magnesium, etc. The insulator 544 may be made of silicon nitride oxide, silicon nitride, or the like. can also be used.

[0230] In particular, the insulator 544 may be an oxide of aluminum or hafnium, or both. Insulators containing aluminum oxide, hafnium oxide, aluminum, and hafnium It is preferable to use oxides containing hafnium (hafnium aluminate). Hafnium aluminate has higher heat resistance than hafnium oxide. This is preferable because it is difficult to crystallize during the heat treatment. 542b is a material that is oxidation-resistant, or the conductivity does not decrease significantly even when it absorbs oxygen. In the case of a material, the insulator 544 is not an essential component. , can be designed appropriately.

[0231] By providing the insulator 544, impurities such as water and hydrogen contained in the insulator 580 are converted into acids. In addition, the excess oxygen in the insulator 580 can prevent the diffusion of oxygen into the oxide 530b. Therefore, oxidation of the conductor 542 can be suppressed.

[0232] The insulator 545 functions as a first gate insulating film. Similar to 524, it is made using an insulator that contains excess oxygen and releases oxygen when heated. It is preferable to form

[0233] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, and nitride silicon dioxide, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, carbon, and Silicon oxide doped with nitrogen and silicon oxide having vacancies can be used. Silicon oxide and silicon oxynitride are preferred because they are stable to heat.

[0234] By providing an insulator containing excess oxygen as the insulator 545, the oxide In addition, oxygen can be effectively supplied to the channel forming region of the insulator 530b. As in 24, the concentration of impurities such as water or hydrogen in the insulator 545 is reduced. It is preferable that the thickness of the insulator 545 is 1 nm or more and 20 nm or less. The microwave treatment described above may be performed before and / or after the formation of the insulator 545. stomach.

[0235] In addition, in order to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530, A metal oxide may be provided between the body 545 and the conductor 560. The metal oxide may be an insulator. It is preferable to suppress the diffusion of oxygen from 545 to the conductor 560. The metal oxide prevents excess oxygen from diffusing from the insulator 545 to the conductor 560. In other words, it is possible to suppress a decrease in the amount of excess oxygen supplied to the oxide 530. This can prevent the conductor 560 from being oxidized by excess oxygen. Any material that can be used for the insulator 544 may be used.

[0236] Note that the insulator 545 may have a stacked structure similar to the second gate insulating film. As the miniaturization and high integration of devices progresses, the gate insulating film becomes thinner, which reduces leakage current and other problems. Therefore, the insulator that functions as the gate insulating film is made of high-k material. By using a laminated structure of a material that is thermally stable and a material that is thermally stable, the thickness of the material is maintained while the It is possible to reduce the gate potential during transistor operation. It may have a laminated structure.

[0237] The conductor 560 functioning as the first gate electrode has a two-layer structure in FIGS. 23A and 23B. However, it may have a single layer structure or a laminated structure of three or more layers.

[0238] The conductor 560a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule ( Conductive material with the function of suppressing the diffusion of impurities such as N2O, NO, NO2, etc., copper atoms, etc. It is preferable to use a material containing at least oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the function of suppressing the diffusion of the conductor 56. Oa has the function of suppressing oxygen diffusion, so the oxygen contained in the insulator 545 This can prevent the conductor 560b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing this include tantalum, tantalum nitride, and ruthenium. It is preferable to use ruthenium or ruthenium oxide as the conductor 560a. In this case, an oxide semiconductor that can be used for the oxide 530 can be used. By forming a film of conductor 560b by sputtering, the electrical resistance value of conductor 560a is reduced. This is called an OC (Oxide Conductor) electrode. This can be done.

[0239] The conductor 560b is a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 560b also functions as a wiring, It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. The conductor 560b can be made of a conductive material containing silicon as a main component. For example, a laminated structure of titanium or titanium nitride and the above conductive material may be used. good.

[0240] The insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544. Preferably, the insulator 580 has an excess oxygen region. For example, the insulator 58 0, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine silicon oxide doped with carbon, silicon oxide doped with carbon, and acid doped with nitrogen. It is particularly preferable that the insulating layer 100 has a silicon oxide, a silicon oxide having pores, or a resin. Silicon oxide and silicon oxynitride are preferred because they are thermally stable. Silicon oxide and silicon oxide with vacancies easily form excess oxygen regions in later processes. This is preferable because it is possible to

[0241] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580, oxygen in the insulator 580 is efficiently supplied to the oxide 530. It should be noted that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced. It is preferable.

[0242] The opening in the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b. As a result, the conductor 560 is inserted through the opening in the insulator 580 and the conductor 542a and the conductor 542b. It is formed so as to be embedded in the region sandwiched between 542b.

[0243] In miniaturizing semiconductor devices, it is required to shorten the gate length. Therefore, the thickness of the conductor 560 must be increased. As a result, the conductor 560 can have a shape with a high aspect ratio. In order to embed the conductor 560 in the opening of the insulator 580, the conductor 560 is formed to have an aspect ratio Even if the shape is high, the conductor 560 can be formed without collapsing during the process. do.

[0244] The insulator 574 is connected to the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. The insulator 574 is preferably provided in contact with the , insulator 545, and insulator 580. From this excess oxygen region, oxygen can be supplied into the oxide 530 .

[0245] For example, the insulator 574 may be hafnium, aluminum, gallium, yttrium, or di zinc, tungsten, titanium, tantalum, nickel, germanium, or magnesium Metal oxides containing one or more metals selected from the group consisting of sodium, do.

[0246] In particular, aluminum oxide has a high barrier property and is a thin film of 0.5 nm to 3.0 nm. Therefore, the diffusion of hydrogen and nitrogen can be suppressed even if the sputtering method is used. The aluminum oxide film formed by this method is both an oxygen source and a barrier to impurities such as hydrogen. It can also function as a membrane.

[0247] In addition, it is preferable to provide an insulator 581 that functions as an interlayer film over the insulator 574. The insulator 581, like the insulator 524, has a low impurity concentration such as water or hydrogen. It is preferably reduced.

[0248] Also, openings formed in the insulators 581, 574, 580, and 544 Conductor 540a and conductor 540b are placed in the mouth. The conductors 540a and 540b are provided opposite each other with the conductor 560 in between. b has the same configuration as conductor 546 and conductor 548 described later.

[0249] An insulator 582 is provided on the insulator 581. The insulator 582 is resistant to oxygen and hydrogen. Therefore, the insulator 582 is preferably made of an insulating material having a barrier property. The insulator 582 may be made of a material similar to that of the insulator 514. For example, the insulator 582 may be made of aluminum oxide. It is preferable to use metal oxides such as tantalum oxide, hafnium oxide, and the like.

[0250] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. Therefore, it has a high blocking effect that prevents impurities such as acid and moisture from passing through the membrane. Aluminum oxide is resistant to hydrogen, moisture, etc. during and after the transistor manufacturing process. It is possible to prevent impurities from being mixed into the transistor 500. This can suppress the release of oxygen from the oxide that makes up the transistor. Suitable for use as a protective film against 500.

[0251] In addition, an insulator 586 is provided on the insulator 582. The insulator 586 is 20 can be used. In addition, these insulators have a relatively low dielectric constant. By applying the material, it is possible to reduce the parasitic capacitance that occurs between wiring. For example, The body 586 can be a silicon oxide film, a silicon oxynitride film, or the like.

[0252] Also, the insulator 520, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator The body 574, the insulator 581, the insulator 582, and the insulator 586 are provided with the conductor 546 and and a conductor 548 and the like are embedded therein.

[0253] The conductor 546 and the conductor 548 are connected to the capacitor 600, the transistor 500, or the transistor The conductor 546 and the resistor 550 function as plugs or wirings. The conductor 548 may be formed using the same material as the conductor 328 and the conductor 330. can be done.

[0254] After the transistor 500 is formed, an opening is formed to surround the transistor 500. An insulator having high barrier properties against hydrogen or water may be formed so as to cover the opening. By encasing the transistor 500 in the insulator with high barrier properties, moisture and It is possible to prevent the intrusion of hydrogen and oxygen. Alternatively, the transistor may be wrapped in an insulator that has a high barrier property against hydrogen or water. When forming an opening to surround the transistor 500, for example, the insulator 522 or the insulator 5 14, and the burr 522 or 514 is in contact with the insulator 522 or 514. If a highly insulating material is formed, it can be used as part of the manufacturing process of the transistor 500. In addition, examples of insulators with high barrier properties against hydrogen or water include: A material similar to that of the insulator 522 or the insulator 514 may be used.

[0255] Next, a capacitor 600 is provided above the transistor 500. The capacitor 600 has the following characteristics: It has a conductor 610, a conductor 620, and an insulator 630.

[0256] Moreover, a conductor 612 may be provided on the conductor 546 and the conductor 548. 12 has a function as a plug or wiring that connects to the transistor 500. The conductive body 610 functions as an electrode of the capacitor 600. The body 610 can be formed simultaneously.

[0257] The conductor 612 and the conductor 610 may be made of molybdenum, titanium, tantalum, or tungsten. a metal film containing an element selected from aluminum, copper, chromium, neodymium, and scandium; Or a metal nitride film containing the above-mentioned elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, etc.) Indium tin oxide (ITO) or tungsten nitride (Tungsten nitride) can be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide, Conductive materials such as indium zinc oxide and indium tin oxide with added silicon oxide are used You can also do this.

[0258] In this embodiment, the conductor 612 and the conductor 610 are shown as having a single-layer structure. For example, a conductive material having a barrier property and a conductive material having a barrier property may be laminated. Conductors with barrier properties are placed between the highly conductive conductors and those with high conductivity. A highly adhesive conductor may be formed.

[0259] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. The conductor 620 is made of a conductive material such as a metal material, an alloy material, or a metal oxide material. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, are used. It is preferable to use tungsten, and it is particularly preferable to use tungsten. When forming the layer simultaneously with other components, low-resistance metal materials such as Cu (copper) and Al (aluminum) are used. It is best to use a

[0260] An insulator 640 is provided on the conductor 620 and the insulator 630. The insulator 640 can be formed using a material similar to that of the insulator 320. It may also function as a planarizing film that covers the underlying unevenness.

[0261] By using this structure, a semiconductor device including a transistor having an oxide semiconductor This allows for miniaturization or high integration.

[0262] Examples of a substrate that can be used for a semiconductor device of one embodiment of the present invention include a glass substrate and a quartz substrate. , sapphire substrate, ceramic substrate, metal substrate (e.g., stainless steel substrate, Substrate with steel foil, tungsten substrate, tungsten foil semiconductor substrates (e.g., single crystal semiconductor substrates, polycrystalline semiconductor substrates, or compound semiconductor substrates), SOI (Silicon on Insulator) substrate In addition, a material having heat resistance capable of withstanding the processing temperature of this embodiment can be used. A plastic substrate may also be used. An example of a glass substrate is barium borosilicate glass. Glass, aluminosilicate glass, or aluminoborosilicate glass, or soda lime Glass, etc. Alternatively, crystallized glass, etc. can be used.

[0263] Alternatively, the substrate may be a flexible substrate, a laminated film, a paper containing a fibrous material, or A flexible substrate, a laminated film, a base film, etc. can be used. Examples of such materials include polyethylene terephthalate. (PET), polyethylene naphthalate (PEN), polyethersulfone (PES) , and plastics such as polytetrafluoroethylene (PTFE). An example is a synthetic resin such as acrylic. Another example is polypropylene. Examples include polyethylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Examples include polyamide, polyimide, aramid resin, epoxy resin, inorganic vapor deposition film, In particular, semiconductor substrates, single crystal substrates, or SOI substrates are used. By manufacturing transistors, there is little variation in characteristics, size, or shape. This allows the manufacture of transistors with high current capability and small size. When a circuit is constructed using transistors, it is possible to reduce the power consumption of the circuit or to increase the integration density of the circuit. This can be achieved.

[0264] In addition, a flexible substrate is used as the substrate, and transistors, resistors, and Alternatively, a substrate and a transistor, a resistor, and / or a capacitor may be formed. Alternatively, a release layer may be provided between the capacitors and the like. Or, after the whole process is completed, it can be separated from the substrate and used for transferring to another substrate. In this case, transistors, resistors, and / or capacitors are mounted on substrates with poor heat resistance or flexible substrates. The above-mentioned peeling layer may be formed of, for example, a tungsten film and a silicon oxide film. A laminated structure of an inorganic film and a substrate, or a structure in which an organic resin film such as polyimide is formed on a substrate Alternatively, a silicon film containing hydrogen or the like can be used.

[0265] In other words, even if a semiconductor device is formed on a certain substrate and then transferred to another substrate, An example of a substrate onto which a semiconductor device is transferred is a substrate on which the above-described transistor is formed. In addition to the substrates that can be used, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, Film substrate, stone substrate, wood substrate, fabric substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon) Polyurethane, polyester) or regenerated fiber (acetate, cupra, rayon , recycled polyester), leather substrates, or rubber substrates. By using the plate, it is possible to manufacture flexible semiconductor devices and to manufacture semiconductor devices that are not easily broken. It is possible to provide heat resistance, reduce weight, or reduce thickness.

[0266] By providing a semiconductor device over a flexible substrate, an increase in weight can be suppressed and the semiconductor device is less likely to be damaged. Therefore, a semiconductor device with a high resistance can be provided.

[0267] <Transistor variation 1> The transistor 500A shown in FIGS. 24A, 24B, and 24C is the same as that shown in FIGS. 24A is a modified example of the transistor 500A having the configuration shown in FIG. 24A is a top view, FIG. 24B is a cross-sectional view of the transistor 500A in the channel length direction, and FIG. 24A is a cross-sectional view of the transistor 500A in the channel width direction. In order to clarify the figures, some elements are omitted. 24C are structures including a transistor 550 or the like included in a semiconductor device of one embodiment of the present invention. It can also be applied to other transistors.

[0268] The transistor 500A having the configuration shown in FIGS. 24A, 24B, and 24C has an insulator 55 2. The insulator 513 and the insulator 404 are included in the configuration shown in FIGS. 23A and 23B. The transistor 500 is different from the transistor 500. In addition, an insulator 552 is provided in contact with the side surface of the conductor 540a. 23A and 23B, the insulator 552 is provided in contact with the side surface of the conductor 540b. 2. Furthermore, the transistor 500 does not have the insulator 520. 3A and 23B.

[0269] The transistor 500A having the configuration shown in FIGS. 24A, 24B, and 24C has an insulator 51 An insulator 513 is provided on the insulator 574. A body 404 is provided.

[0270] In the transistor 500A having the configuration shown in FIGS. 24A, 24B, and 24C, the insulator 5 14, insulator 516, insulator 522, insulator 524, insulator 544, insulator 580, and The insulating layer 574 is patterned, and the insulating layer 404 covers the insulating layer 574. That is, the insulator 404 is formed on the top surface of the insulator 574, the side surface of the insulator 574, and the insulator 580. the side of the insulator 544, the side of the insulator 524, the side of the insulator 522, and the insulator 516 The side surface of the insulating material 514 and the top surface of the insulating material 513 are in contact with each other. The object 530 etc. are isolated from the outside by the insulator 404 and the insulator 513 .

[0271] The insulator 513 and the insulator 404 are formed of at least hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). It is preferable that the insulator 513 has a high function of suppressing the diffusion of water molecules. The insulator 404 is made of a material having a high hydrogen barrier property, such as silicon nitride or oxynitride. It is preferable to use silicon dioxide, which prevents hydrogen and the like from diffusing into the oxide 530. Therefore, the deterioration of the characteristics of the transistor 500A can be suppressed. The reliability of the semiconductor device according to one embodiment of the present invention can be improved.

[0272] Insulator 552 includes insulator 581, insulator 404, insulator 574, insulator 580, and insulator 574. The insulator 552 is provided in contact with the insulator 544. The insulator 552 has a function of suppressing the diffusion of hydrogen or water molecules. For example, the insulator 552 is preferably made of a material with high hydrogen barrier properties. Insulators such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. In particular, silicon nitride is a material with high hydrogen barrier properties, so the insulator 552 It is preferable to use a material with high hydrogen barrier properties as the insulator 552. As a result, impurities such as water or hydrogen are transported from the insulator 580 to the conductor 540a and the conductor 540b. 0b, the diffusion into the oxide 530 can be suppressed. and suppressing absorption of oxygen contained in the conductive material 540a and the conductive material 540b. As described above, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0273] <Transistor variation 2> A configuration example of the transistor 500B will be described with reference to FIGS. 25A, 25B, and 25C. FIG. 25A is a top view of transistor 500B. FIG. 25B shows the transistor 500B shown in FIG. 25A with a dashed line. 25C is a cross-sectional view of the L1-L2 region shown in FIG. 25A is a cross-sectional view of the part. Note that in the top view of FIG. 25A, the markings of some elements are omitted for clarity. The information is omitted.

[0274] Transistor 500B is a modification of transistor 500, and Therefore, to avoid repetition, we will mainly focus on transistors. The differences between transistor 500B and transistor 500 will be described.

[0275] The conductor 560 functioning as the first gate electrode is made up of the conductor 560a and the conductor 560b. The conductor 560a has a conductor 560b on the surface of the conductor 560a. The conductor 560a is composed of hydrogen atoms, hydrogen molecules, water molecules, copper atoms, and the like. It is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as electrons. has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that can

[0276] Since the conductor 560a has the function of suppressing the diffusion of oxygen, the material selection of the conductor 560b is easy. In other words, the presence of the conductor 560a allows the conductor 560b to This suppresses oxidation of the material, thereby preventing a decrease in electrical conductivity.

[0277] In addition, the insulator 544 is formed so as to cover the upper and side surfaces of the conductor 560 and the side surface of the insulator 545. It is preferable to provide the insulator 544. The insulator 544 is preferably formed of a material that can absorb impurities such as water or hydrogen, and acids. It is advisable to use an insulating material that has the function of suppressing the diffusion of elements. For example, aluminum oxide Alternatively, hafnium oxide or the like is preferably used. Sium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, Metal oxides such as lanthanum, neodymium oxide or tantalum oxide, silicon oxide nitride or Silicon nitride or the like can be used.

[0278] By providing the insulator 544, oxidation of the conductor 560 can be suppressed. By having the insulator 544, impurities such as water and hydrogen contained in the insulator 580 can be prevented from This can prevent the light from diffusing to the star 500B.

[0279] Transistor 500B has a conductor 560 connected to a portion of conductor 542a and a portion of conductor 542b. Therefore, the parasitic capacitance is likely to be larger than that of the transistor 500. However, the operating frequency tends to be lower than that of the insulator 580. Since there is no need to provide an opening in the substrate and fill in the conductor 560 or the insulator 545, Higher productivity compared to Transistor 500.

[0280] The configurations, structures, methods, etc. shown in this embodiment may be used in conjunction with the configurations shown in other embodiments and examples. The composition, structure, method, etc. can be used in appropriate combination.

[0281] (Embodiment 5) In this embodiment, the crystal structure of an oxide semiconductor will be described in detail.

[0282] [Classification of crystal structures] First, classification of crystal structures in oxide semiconductors will be described with reference to FIG. 26A. FIG. 26A shows an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn). FIG. 1 is a diagram illustrating the classification of crystal structures of metals (oxides).

[0283] As shown in FIG. 26A, oxide semiconductors are broadly divided into "amorphous" and ", "Crystalline" and "Crystal" Also, "Amorphous" includes completely amorp Also, "Crystalline" includes CAAC (c-ax is-aligned crystalline), nc(nanocrystalli ne), and cloud-aligned composite (CAC). The classification of "Crystalline" includes single crystal, pol Crystalline and completely amorphous materials are excluded. "Crystal" includes single crystal and poly crystal. Contains stal.

[0284] The structures within the bold frame in Figure 26A are classified into "Amorphous" and "Cry It is an intermediate state between "crystal" and "new crystal" This structure belongs to the line phase. It is completely different from the stable "Amorphous" and "Crystal" This can be rephrased as a structure.

[0285] The crystal structure of the film or substrate can be determined by X-ray diffraction (XRD). It can be evaluated using the "Crystalline" spectrum. CAAC-IGZO films classified as The XRD spectrum obtained by the GIXD measurement is shown in Figure 26B. This is also called the Seemann-Bohlin method. The XRD spectrum obtained by the method shown in FIG. 26B is simply referred to as the XRD spectrum. The composition of the AAC-IGZO film is approximately In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in FIG. 26B is 500 nm.

[0286] As shown in Figure 26B, the XRD spectrum of the CAAC-IGZO film shows clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows the following peaks: A peak indicating the c-axis orientation is detected near 2θ=31°. The peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0287] The crystal structure of the film or substrate was also analyzed by nanobeam electron diffraction (NBED). Diffraction patterns observed by electron diffraction (microelectron It can be evaluated by the diffraction pattern of the CAAC-IGZO film. The pattern is shown in Figure 26C. Figure 26C shows the NBE pattern where the electron beam is incident parallel to the substrate. The diffraction pattern observed by the CAAC-IGZO film shown in Figure 26C is The composition is In:Ga:Zn=4:2:3 [atomic ratio]. In the diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0288] As shown in Figure 26C, the diffraction pattern of the CAAC-IGZO film shows multiple c-axis orientations. spots are observed.

[0289] [Oxide semiconductor structure] When focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in FIG. 26A. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors and pseudo-non-crystalline oxide semiconductors. amorphous-like oxide semiconductor (a-like OS) semiconductor), amorphous oxide semiconductor, etc.

[0290] Next, for details on the above-mentioned CAAC-OS, nc-OS, and a-like OS, Give an explanation.

[0291] [CAAC-OS] The CAAC-OS has multiple crystalline regions, each of which has its c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film. The direction normal to the surface on which the CAAC-OS film is formed or the direction normal to the surface of the CAAC-OS film. The crystalline region is a region in which the atomic arrangement has periodicity. When viewed as an arrangement, the crystalline region is also a region with a uniform lattice arrangement. S has a region where multiple crystalline regions are connected in the ab-plane direction, and this region has strain. The distortion is a distortion of the lattice arrangement in the region where multiple crystal regions are connected. A place where the orientation of the lattice arrangement changes between a uniform area and a uniform area with a different lattice arrangement. In other words, the CAAC-OS has a c-axis orientation and no clear orientation in the ab-plane direction. It is an oxide semiconductor that does not contain

[0292] Each of the plurality of crystalline regions is made up of one or more minute crystals (maximum diameter 10n If a crystalline region is made up of a single microcrystal, The maximum diameter of the crystalline region is less than 10 nm. When the crystallized region is formed, the size of the crystallized region may be approximately several tens of nanometers.

[0293] In-M-Zn oxide (where element M is aluminum, gallium, yttrium, or tin) In the case of titanium, CAAC-OS is one or more selected from the group consisting of indium and titanium. A layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as the In layer) A layered crystal structure (also called a layered structure) is formed by stacking a layer having the formula (hereinafter, the (M, Zn) layer) and a layer having the formula (hereinafter, the (M, Zn) layer). ) It should be noted that indium and element M can be substituted for each other. The (M,Zn) layer may contain indium. The In layer may contain the element M. The In layer may contain Zn. The layered structure may be, for example, It is observed as a lattice image in high-resolution TEM images.

[0294] For example, when the structure of the CAAC-OS film is analyzed using an XRD device, the θ / 2θ shift In the out-of-plane XRD measurement using a tuner, the peak indicating the c-axis orientation was = 31° or its vicinity. The position of the peak indicating the c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0295] In addition, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots (spots) ) is observed. Note that one spot and another spot are the result of the incident electron beam passing through the sample. The spot (also called the direct spot) is the center of symmetry, and the observed positions are point-symmetric. do.

[0296] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is a hexagonal lattice. The unit cell is not necessarily a regular hexagon, but may be a non-regular hexagon. The above distortion may have a lattice arrangement such as a pentagon or heptagon. In the OS, clear grain boundaries were confirmed even near the strain. In other words, the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the arrangement of oxygen atoms in the CAAC-OS is dense in the ab-plane direction. The metal atoms are replaced by other atoms, which changes the bond distance between the atoms. This is thought to be because distortion can be tolerated.

[0297] The crystal structure in which clear grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, trapping carriers and forming transistor on-states. Therefore, it is highly likely that this will cause a decrease in the on-state current and a decrease in the field-effect mobility. CAAC-OS, which has no visible grain boundaries, has a crystal structure suitable for the semiconductor layer of a transistor. It is one of the crystalline oxides that can be used to form CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferable. This is preferable because it can suppress the occurrence of grain boundaries more effectively than the material.

[0298] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to the decrease in electron mobility caused by the grain boundaries. In addition, the crystallinity of oxide semiconductors may be reduced due to the inclusion of impurities or the generation of defects. Therefore, CAAC-OS is similar to oxide semiconductors with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having a CAAC-OS are stable. Therefore, oxide semiconductors having CAAC-OS are heat-resistant and highly reliable. -OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process Therefore, using CAAC-OS for OS transistors will increase the flexibility of the manufacturing process. This makes it possible to

[0299] [nc-OS] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 In other words, nc-OS has a periodic atomic arrangement in the region of microscopic The size of the minute crystals is, for example, 1 nm or more and 10 nm or less. In particular, since the size of these tiny crystals is between 1 nm and 3 nm, they are also called nanocrystals. In nc-OS, there is no regularity in the crystal orientation between different nanocrystals. Therefore, depending on the analytical method, nc-OS may be classified as a-like In some cases, it is difficult to distinguish between an OS and an amorphous oxide semiconductor. For example, in the case of an nc-OS film, Structural analysis was performed using an XRD device. Out-of-place analysis using θ / 2θ scan In the XRD measurement, no peaks indicating crystallinity were detected. Electron diffraction using an electron beam with a probe diameter larger than that of nanocrystals (e.g., 50 nm or larger) When performing selected area electron diffraction (also known as selected area electron diffraction), a diffraction pattern resembling a halo pattern is observed. On the other hand, for the nc-OS film, particles with sizes close to or smaller than the nanocrystals were observed. Electron diffraction (nanobeam electron diffraction) using an electron beam with a lobe diameter (for example, 1 nm to 30 nm) When direct beam diffraction is performed, multiple beams are generated within a ring-shaped area centered on the direct spot. An electron diffraction pattern may be obtained in which several spots are observed.

[0300] [a-like OS] The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. Conductive. A-like OS has voids or low density regions. The OS has lower crystallinity than the nc-OS and CAAC-OS. The OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0301] [Oxide semiconductor composition] Next, the details of the CAC-OS will be explained. Regarding.

[0302] [CAC-OS] CAC-OS is, for example, a metal oxide in which the elements constituting the metal oxide are 0.5 nm or more and 10 nm or less. Preferably, a material unevenly distributed in a size of 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, it is assumed that one or more metal elements are unevenly distributed in a metal oxide, and the The region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm. A state where the mixture is at or near this size is also called a mosaic or patch state.

[0303] Furthermore, CAC-OS is a mosaic structure in which the material is separated into a first region and a second region. The first region is in a cloud-like shape, and the first region is distributed throughout the film (hereinafter also referred to as a cloud-like shape). In other words, the CAC-OS is a mixture of the first and second regions. It is a composite metal oxide having the following structure.

[0304] Here, the ratio of In to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide is The atomic ratios of In, Ga, and Zn are expressed as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is In this region, [In] is larger than [In] in the composition of the CAC-OS film. The second region is where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region has [In] higher than the [In] in the second region. The first region is larger than the second region, and [Ga] is smaller than [Ga] in the first region. In the second region, [Ga] is larger than [Ga] in the first region, and [In ] is a region smaller than [In] in the first region.

[0305] Specifically, the first region is mainly composed of indium oxide, indium zinc oxide, etc. The second region is a region in which the gallium oxide, gallium zinc oxide, etc. In other words, the first region is called a region where In is the main component. The second region can be rephrased as a region containing Ga as the main component. This can be done.

[0306] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0307] For example, in the case of CAC-OS, an In-Ga-Zn oxide, energy dispersive X-ray spectroscopy Law(EDX:Energy Dispersive X-ray spectrosco The EDX mapping obtained using the py) identified the region containing In as the main component (first region ) and a region (second region) mainly composed of Ga are unevenly distributed and mixed. It can be confirmed that:

[0308] When CAC-OS is used in a transistor, the conductivity due to the first region and the conductivity due to the second region are The insulating properties caused by the above work complementary to each other, resulting in a switching function (On / Off). In other words, CAC-OS is , a part of the material has a conductive function and a part of the material has an insulating function, and the whole of the material has a The material functions as a semiconductor. By separating the conductive function from the insulating function, Therefore, when using CAC-OS in transistors, This allows for a high on-state current (I on ), high field-effect mobility (μ), and good switching This allows for realizing a locking operation.

[0309] Oxide semiconductors have a variety of structures, each of which has different characteristics. Oxide semiconductors include amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, and CA Two or more of C-OS, nc-OS, and CAAC-OS may be included.

[0310] [Transistor Having an Oxide Semiconductor] Next, a case where the oxide semiconductor is used in a transistor will be described.

[0311] By using the oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized.

[0312] An oxide semiconductor with a low carrier concentration can be used for the channel formation region of a transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is preferably 1×10 18 c m -3 Preferably, it is 1×10 or less. 17 cm -3 It is more preferable that it is less than , 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 Less than More preferably, 1×10 12 cm -3 It is more preferable that the amount is less than 10 ... In addition, when the carrier concentration of the oxide semiconductor film is reduced, impurities in the oxide semiconductor film In this specification and the like, the impurity concentration is low, and the defect level density is low. A low density of defect states is called high purity intrinsic or substantially high purity intrinsic. An oxide semiconductor with a low concentration of arsenic is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. There are cases where this happens.

[0313] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states. Therefore, the trap level density may also be low.

[0314] In addition, it takes a long time for the charges trapped in the trap levels of the oxide semiconductor to disappear. Therefore, the trap level density is high. A transistor in which a channel formation region is formed in an oxide semiconductor has unstable electrical characteristics. There are cases where this happens.

[0315] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor is In order to reduce the impurity concentration in the oxide semiconductor, It is also preferable to reduce the impurity concentration in the film in contact with the film. Potassium metal, alkaline earth metal, iron, nickel, silicon, etc.

[0316] 〔impurities〕 Here, the influence of each impurity in an oxide semiconductor will be described.

[0317] When oxide semiconductors contain silicon or carbon, which are elements of Group 14, oxide Defect levels are formed in the semiconductor. The concentration of silicon and carbon in the oxide semiconductor and the silicon near the interface with the channel formation region of the oxide semiconductor and carbon concentration (Secondary Ion Mass Spectrometry (SIMS) The concentration obtained by spectrometry is calculated as 2 x 10 18 atoms / c m 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0318] In addition, when an alkali metal or an alkaline earth metal is contained in an oxide semiconductor, a defect level is formed. Therefore, alkali metals or alkaline earth metals are not included. A transistor using an oxide semiconductor that has been used in the past tends to be normally on. Therefore, the alkali metal or aluminum in the channel formation region of the oxide semiconductor obtained by SIMS The concentration of potassium earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0319] In addition, when nitrogen is contained in an oxide semiconductor, electrons that act as carriers are generated, and the carriers As a result, the concentration of nitrogen in the oxide semiconductor increases, making it easier to convert it into an n-type semiconductor. The transistor using the oxide semiconductor is likely to be normally on. If nitrogen is contained, trap levels may be formed. The electrical properties may become unstable. The nitrogen concentration in the channel formation region is set to 5×10 19 atoms / cm 3 Less than 5, preferably x10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Below Lower, more preferably 5 × 10 17 atoms / cm 3 Do the following:

[0320] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electrons acting as carriers are released. In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom, forming a carrier. Therefore, it is necessary to use an oxide semiconductor containing hydrogen. Therefore, the transistor tends to be normally on. It is preferable that the hydrogen in the formation region is reduced as much as possible. In the channel formation region of the nitride semiconductor, the hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 Less than, better Preferably 1 x 10 19 atoms / cm 3 less than 5×10 18 atom s / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0321] To use an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor This allows stable electrical properties to be imparted.

[0322] [Other semiconductor materials] The semiconductor materials that can be used for the oxide 530 are not limited to the metal oxides mentioned above. As the object 530, a semiconductor material having a band gap (a semiconductor that is not a zero-gap semiconductor) For example, semiconductors of elemental elements such as silicon, gallium arsenide, etc. Compound semiconductors, layered materials (also called atomic layer materials, two-dimensional materials, etc.) that function as semiconductors It is preferable to use a layered material that functions as a semiconductor. It is suitable for use in semiconductor materials.

[0323] In this specification, the term "layered material" is a general term for a group of materials having a layered crystal structure. The layered crystal structure is formed by layers formed by covalent bonds and ionic bonds, It is a structure in which layers are stacked through bonds weaker than covalent or ionic bonds, such as rubbing forces. Layered materials have high electrical conductivity within the unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, As a result, a transistor with a large on-state current can be provided.

[0324] Layered materials include graphene, silicene, and chalcogenides. Chalcogen is a general term for elements belonging to Group 16. They contain oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

[0325] For example, a transition metal chalcogenide that functions as a semiconductor may be used as the oxide 530. Specific examples of transition metal chalcogenides that can be used as the oxide 530 include: are molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe 2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS 2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically Examples include ZrSe2).

[0326] The configurations, structures, methods, etc. shown in this embodiment may be used in conjunction with the configurations shown in other embodiments and examples. The composition, structure, method, etc. can be used in appropriate combination.

[0327] (Sixth embodiment) In this embodiment, a semiconductor device on which the memory device of the present invention is mounted will be described with reference to FIGS. 27A and 27B. An example of a chip 1200, which is a type of semiconductor device, is shown. The chip 1200 includes multiple circuits ( In this way, multiple circuits (systems) are integrated into a single chip. The technology that integrates these is called System on Chip (SoC). There is a match.

[0328] As shown in FIG. 27A, the chip 1200 includes a CPU 1211, a GPU 1212, and one or more A plurality of analog arithmetic units 1213, one or more memory controllers 1214, one or more It has a plurality of interfaces 1215, one or more network circuits 1216, etc. .

[0329] The chip 1200 is provided with bumps (not shown), and as shown in FIG. 27B, The first surface of the printed circuit board (PCB) 1201 and In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201. and connects to the motherboard 1203.

[0330] The motherboard 1203 includes storage devices such as a DRAM 1221 and a flash memory 1222. The flash memory 1222 may be the semiconductor memory shown in the above embodiment. It is preferable to use the semiconductor device shown in the above embodiment as a flash memory 1. 222, the storage capacity of the flash memory 1222 can be increased. .

[0331] The CPU 1211 preferably has multiple CPU cores. It is preferable to have multiple GPU cores. Each of the CPUs 12 may have a memory for temporarily storing data. Even if a memory common to the GPU 1211 and the GPU 1212 is provided on the chip 1200, In addition, the GPU1212 is suitable for parallel calculation of large amounts of data, and is suitable for image processing and multiplication and accumulation. It can be used for calculations. The GPU 1212 is equipped with an image processing circuit and a multiply-and-accumulate circuit. This makes it possible to perform image processing and multiply-and-accumulate operations with low power consumption.

[0332] In addition, the CPU 1211 and GPU 1212 are mounted on the same chip, The wiring between PU1211 and GPU1212 can be shortened, and Data transfer to the GPU 1212, the memory of the CPU 1211 and the GPU 1212 After the data transfer between GPU1212 and the calculation in GPU1212, The calculation results can be transferred to 1 at high speed.

[0333] The analog calculation unit 1213 includes an A / D (analog / digital) conversion circuit and a D / A (digital The analog calculation unit 1213 has one or both of a digital / analog conversion circuit. The above-mentioned product-sum calculation circuit may be provided.

[0334] The memory controller 1214 is a circuit that functions as a controller for the DRAM 1221. and a circuit that functions as an interface with the flash memory 1222.

[0335] The interface 1215 includes a display device, a speaker, a microphone, a camera, a controller, and The controller has an interface circuit with external devices such as a mouse. Such interfaces include devices such as keyboards, game controllers, etc. , USB (Universal Serial Bus), HDMI (registered trademark) gh-Definition Multimedia Interface) It is possible.

[0336] The network circuit 1216 is connected to a LAN (Local Area Network) or the like. It has a network circuit for connecting to the network, and also has a circuit for network security. may have

[0337] The above circuits (systems) can be formed on the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, the manufacturing process can be increased. This eliminates the need for a ferroelectric capacitor, allowing chip 1200 to be manufactured at low cost.

[0338] A PCB 1201 on which a chip 1200 having a GPU 1212 is mounted, a DRAM 1221 The motherboard 1203 provided with the GPU module 1222 and the flash memory 1222 It can be called Rule 1204.

[0339] The GPU module 1204 includes a chip 1200 that uses SoC technology. In addition, because it has excellent image processing capabilities, it can be used on smartphones. Mobile devices such as smartphones, tablets, laptops, and portable (portable) game consoles It is suitable for use in mobile electronic devices. Deep neural networks (DNNs) and convolutional neural networks ( CNN), recurrent neural network (RNN), autoencoder, deep Boltzmann It can implement techniques such as deep belief networks (DBM) and deep belief networks (DBN). Therefore, the chip 1200 is an AI chip, or the GPU module 1204 is an AI system module. It can be used as a tool.

[0340] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. This can be done.

[0341] (Embodiment 7) In this embodiment mode, an application example of a semiconductor device using the memory device described in the above embodiment will be described. The storage device shown in the above embodiment is a memory card (for example, an SD card), a U Various removable storage devices such as USB memory and SSD (Solid State Drive) 28A to 28E show some configurations of removable storage devices. For example, the semiconductor device shown in the above embodiment is packaged. It is processed into memory chips and used in various storage devices and removable memory.

[0342] FIG. 28A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a carrier The board 1104 includes a chip 1102, a USB connector 1103, and a circuit board 1104. It is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 1105, The controller chip 1106 is attached to the memory chip 1105. The memory device or semiconductor device shown in the above embodiment can be incorporated.

[0343] FIG. 28B is a schematic diagram of the external appearance of an SD card, and FIG. 28C is a schematic diagram of the internal structure of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a board 1113. The substrate 1113 is housed in a housing 1111. For example, the substrate 1113 has: A memory chip 1114 and a controller chip 1115 are attached to the board 111. By providing a memory chip 1114 on the back side of the SD card 1110, the capacity of the SD card 1110 can be increased. In addition, a wireless chip having a wireless communication function may be provided on the substrate 1113. This allows the memory chip to communicate wirelessly between the host device and the SD card 1110. The data in the memory chip 1114 can be read and written. The memory device or semiconductor device described in the embodiment can be incorporated into the semiconductor device.

[0344] FIG. 28D is a schematic diagram of the external appearance of an SSD, and FIG. 28E is a schematic diagram of the internal structure of an SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The board 1153 is housed in the housing 1151. For example, the board 1153 may include a memory chip. 1154, memory chip 1155, and controller chip 1156 are attached. The memory chip 1155 is a working memory for the controller chip 1156, and A memory chip 1154 is also provided on the back side of the substrate 1153. By doing so, the capacity of the SSD 1150 can be increased. The memory device or semiconductor device described in the above embodiment can be incorporated into the semiconductor device.

[0345] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0346] (Embodiment 8) 29A to 29G show examples of memory devices or semiconductor devices according to one embodiment of the present invention. Specific examples of child devices are shown below.

[0347] <Electronic devices and systems> The memory device or semiconductor device according to one embodiment of the present invention can be incorporated into various electronic devices. Examples of electronic devices include information terminals, computers, smartphones, and Book terminals, television equipment, digital signage Electronic signs), large game machines such as pachinko machines, digital cameras, digital video cameras, Digital photo frames, mobile phones, portable game consoles, recording and playback devices, navigation systems The computer here includes a tablet, a computer system, a sound reproducing device, etc. In addition to laptop computers, notebook computers, and desktop computers, This includes large computers such as server systems.

[0348] The electronic device according to one embodiment of the present invention may include an antenna. This allows the display of images and information on the display unit. In the case where the device has a secondary battery, the antenna may be used for contactless power transmission.

[0349] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, etc.). , distance, light, liquid, magnetic, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared radiation) It may be possible.

[0350] The electronic device according to one embodiment of the present invention can have various functions. Still images, videos, text images, etc.) on the display, touch panel function, calendar It has the functions of displaying the date, time, etc., and running various software (programs). functions, wireless communication functions, and functions to read programs or data recorded on recording media. They may have abilities, etc.

[0351] [Information terminal] The memory device or the semiconductor device according to one embodiment of the present invention is used to program a microcontroller. Therefore, according to one aspect of the present invention, a memory device for holding a gram can be formed. The microcontroller chip can be made smaller.

[0352] FIG. 29A shows a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102, and an input interface. As a face, a touch panel is provided on the display unit 5102, and buttons are provided on the housing 5101. According to one aspect of the present invention, a miniaturized microcontroller is used. This allows for effective use of the limited space inside the mobile phone. A storage device according to one embodiment of the present invention may be used for the storage. This allows for a larger storage capacity per unit area.

[0353] 29B shows a notebook type information terminal 5200. The information terminal includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203. According to one aspect of the present invention, a miniaturized microcontroller is used to This allows for effective use of the limited space inside the information terminal. A storage device according to one embodiment of the present invention may be used for the storage. This allows for a larger storage capacity per unit area of ​​the memory.

[0354] In the above, a smartphone and a notebook type information terminal are used as examples of electronic devices. As shown in Figures 29A and 29B, the devices are not limited to smartphones and notebook computers. Other information terminals can be applied. Examples of information terminals include PDAs (Personal Digital Assistants) ant), desktop information terminals, and workstations.

[0355] [Game consoles] FIG. 29C shows a portable game machine 5300, which is an example of a game machine. 300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 530 5, operation keys 5306, etc. The housing 5302 and the housing 5303 are The connection part 5305 provided on the housing 5301 can be removed from another housing. By attaching it to the body (not shown), the image output on the display unit 5304 can be displayed on another video device. (not shown). At this time, the housings 5302 and 5303 Each of these can function as an operation unit. This allows multiple players to play at the same time. The boards of the housings 5301, 5302, and 5303 are A memory device or a semiconductor device according to one embodiment of the present invention is incorporated into a chip or the like. You can put it in.

[0356] FIG. 29D shows a stationary game machine 5400, which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire. do.

[0357] One embodiment of the present invention is applied to game machines such as a portable game machine 5300 and a stationary game machine 5400. By using such a miniaturized microcontroller, it is possible to reduce the space inside the game console. In addition, the storage of the portable game machine can be effectively utilized. Such a storage device or semiconductor device may be used. The storage capacity per area can be increased.

[0358] 29C and 29D show examples of game machines, such as a portable game machine and a stationary game machine. Although the microcontroller of one aspect of the present invention is illustrated in the figure, this is not a game machine. The microcontroller of one embodiment of the present invention can be applied to a game machine such as: For example, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), Examples include pitching machines for batting practice installed at sports facilities.

[0359] [Mainframe Computer] A memory device or a semiconductor device according to one embodiment of the present invention can be applied to a large-scale computer. can.

[0360] FIG. 29E is a diagram showing a supercomputer 5500, which is an example of a large computer. FIG. 29F shows a rack-mounted computer 5500 included in the supercomputer 5500. 502.

[0361] The Supercomputer 5500 consists of a rack 5501 and multiple rack-mounted computers. The computers 5502 are stored in a rack 5501. The computer 5502 is provided with a plurality of substrates 5504, on which the The microcontroller according to one aspect of the present invention can be mounted on the By using a microcontroller with a built-in microcontroller, the limited space of a large computer can be effectively utilized. In addition, the present invention can be applied to the storage of a large-scale computer. Such a storage device or semiconductor device may be used. The storage capacity per area can be increased.

[0362] 29E and 29F show a supercomputer as an example of a large computer. However, a large scale computer to which a microcontroller according to one aspect of the present invention is applied is The present invention is not limited to the above. Examples of such data include computers that provide services (servers), large general-purpose computers, Examples include computers (mainframes).

[0363] [electric appliances] FIG. 29G shows an electric refrigerator-freezer 5800, which is an example of an electric appliance. The cabinet 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0364] The memory device or semiconductor device according to one embodiment of the present invention is applied to an electric refrigerator-freezer 5800. For example, the miniaturized refrigerator-freezer 5800 according to one embodiment of the present invention may be used. By applying a microcontroller with It can be used for.

[0365] We have explained the electric refrigerator-freezer as an example of an electrical appliance, but other electrical appliances include: For example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water heaters, etc. Servers, heating and cooling appliances including air conditioners, washing machines, dryers, audiovisual equipment Examples include personal equipment.

[0366] The electronic devices described in the present embodiment, their functions, effects, etc. may be used in conjunction with other electronic devices. This can be combined with the above description as appropriate.

[0367] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible. [Example]

[0368] A prototype storage device 900 equivalent to the storage device 100B shown in the above embodiment was manufactured, and its operation was verified. FIG. 30A shows an optical microscope photograph of the top surface of the storage device 900. 1 shows a cross-sectional TEM photograph of a portion of a memory device 900.

[0369] <Circuit configuration of storage device 900> 31 shows a circuit diagram of the memory device 900. The memory device 900 includes a write transistor The transistors WTr1 to WTr5 are readout transistors. The transistors RTr1 to RTr4, the transistor STr1, and the transistor These transistors have a semiconductor layer in which a channel is formed. A transistor using CAAC-IGZO (also called a "CAAC-IGZO FET"). ) The channel length L of these transistors is 60 nm, and the channel width W is 60 nm. These transistors also have a back gate. .

[0370] The storage device 900 has capacities Cs1 to Cs4. The capacitances of the capacitors Cs1 to Cs4 are respectively The value is 3fF.

[0371] In the memory device 900, the transistor WTr1 is the same as the memory device 10 shown in the above embodiment. 0B, and the transistor RTr1 corresponds to the transistor 111[1] of the memory device 100B. The transistor STr1 corresponds to the transistor 112[1]. 1, and the transistor STr2 corresponds to the transistor 132. corresponds to the capacitance 113[1], and the node SN1 corresponds to the node ND[1].

[0372] The gate of the transistor WTr1 is electrically connected to the wiring WG1, and the gate of the transistor WTr2 The gate of transistor WTr1 is electrically connected to wiring WG2, and the gate of transistor WTr2 is electrically connected to wiring WG3. The gate of the transistor WTr4 is electrically connected to the wiring WG4. The gate of the transistor WTr5 is electrically connected to the wiring WG5. The back gates of the transistors WTr1 to WTr5 are electrically connected to the wiring WBG. The transistor WTr1 is electrically connected to the wiring WBL, and the transistor WTr5 is electrically connected to the wiring WSL. are electrically connected.

[0373] The gate of the transistor RTr1 is electrically connected to the node SN1. The gate of transistor RTr2 is electrically connected to node SN2. The gate of transistor RTr4 is electrically connected to node SN4. To be continued.

[0374] The back gate of the transistor RTr1 is electrically connected to the wiring CG1. The back gate of Tr2 is electrically connected to the wiring CG2, and the back gate of transistor RTr3 is The gate is electrically connected to the wiring CG3, and the back gate of the transistor RTr4 is connected to the wiring C The gate of the transistor STr1 is electrically connected to the wiring SEL1. The back gate of the transistor STr2 is electrically connected to the wiring RBG1. The gate is electrically connected to the wiring SEL2, and the back gate is electrically connected to the wiring RBG2. The transistor STr1 is electrically connected to the wiring RBL. r2 is electrically connected to the wiring RSL.

[0375] <Verifying write and read operations> 32A shows a timing chart used to verify the write operation. The H potential supplied to WG5 was 3.3V, and the L potential was -1.5V. The H potential was set to 1.2 V and the L potential was set to 0 V. The H potential supplied to the wiring WSL was The L potential supplied to the wiring WSL corresponds to Data "0". In FIG. 32A, Write SN1 to Write SN4 are , and indicates a period during which information is written to nodes SN1 to SN4.

[0376] 32B shows a timing chart used to verify the read operation. The H potential supplied to CG4 was 3.3 V, and the L potential was 0 V. H potential supplied to wiring RSL The H potential supplied to the wiring RBL was 3.3V and the L potential was 0V. It was set to V. The H potential supplied to wiring SEL1 and wiring SEL2 was 3.3 V, and the L potential was 0 V. It was set like this. Also, 1.0 V was supplied to wiring RBG1 and wiring RBG2. In FIG. 32B Read SN1 to Read SN4 indicate the period for reading the information held by nodes SN1 to SN4.

[0377] <Temperature Dependence of Off-Current of CAAC-IGZO FET> Here, FIG. 33A shows the temperature dependence of the off-current ( leakage current) of the CAAC-IGZO FET used in the memory device 900. The horizontal axis in FIG. 33A indicates the reciprocal of the temperature T, and the vertical axis indicates the off-current (Off-state Current) per 1 μm of the channel width. Also, FIG. 3 3A shows the result of measuring 2000 0 transistors (M = 20000) with a channel length L of 60 nm and a channel width W of 60 nm connected in parallel.

[0378] By performing an Arrhenius plot of the off-currents at 150 °C, 125 °C, 100 °C, and 85 °C, it was confirmed that the off-current at room temperature (R.T.) is approximately 2 [zA / μm].

[0379] FIG. 33B shows the measurement results of the retention time of the information written in the memory device 900 at 85 °C. The retention time is the time until the potential of node SN (any one of nodes SN1 to SN4) drops by 0.2 V from the potential when the transistor WTr (any one of transistors WTr1 to WTr5) electrically connected to the node SN is turned off. The horizontal axis in FIG. 33B is the retention time (Retention Time) and the vertical axis is the potential of node SN (potential V ). From FIG. 33B, in an environment of 85 °C SN ). From FIG. 33B, in an environment of 85 °C ​​​It can be seen that information can be retained for more than an hour at 85°C. , which is 50 times higher than at room temperature (see Figure 33A), data can be retained for about 2 days at room temperature. This suggests that...

[0380] <Verification of rewrite resistance> Next, the rewrite endurance of the storage device 900 was verified. G1 to wiring WG4 are supplied with −1.5V, and wiring WBL, wiring WBG, and wiring RBL 0V is supplied to the wiring CG1 through wiring CG3, 3.3V is supplied to the wiring RBG1 and wiring CG4. The test was carried out with 1V supplied to the line RBG2 and 1.2V supplied to the line RSL. In this state, the wiring WSL supplies the H potential (Data “1”) and the L potential (Data “0”) to the node SN4. The information (potential) written to the node SN4 is written to the wiring WG5. The signal is switched every time a signal (H potential) with a pulse width of 20 ns is supplied. 10 shows a timing chart of signals supplied to the wiring WSL.

[0381] Every time the number of writes reaches 10 to the power of X (X is a natural number greater than or equal to 0), Data is written to node SN4. a The potential V when "1" is written SN Then, Data “0” is written to node SN4. Potential V when wrapped SN From the Id-Vg characteristics of the transistor and the current value of the wiring RBL, I asked.

[0382] Figure 34B shows the verification results of rewrite endurance. The horizontal axis of Figure 34B shows the number of writes (Writ e cycle), and the vertical axis is the potential V SN As shown in FIG. 34B, the storage device 900 is Even after 13 times of writing, there is a clear potential difference (voltage It can be seen that a large window is obtained, indicating good rewrite endurance.

[0383] <Verification of writing tolerance> Next, the write disturb resistance of the storage device 900 was verified. The memory device 900 is electrically connected to the node SN through a transistor by one wire. It is possible to write information to separate nodes SN simultaneously from both the wiring WBL and the wiring WSL. In this case, the write operation of the adjacent node SN can affect the data being held. There is a concern that the

[0384] FIG. 35A is a timing chart illustrating an initial operation for verifying write disturbance resistance. As an initial operation, Data "0" is written to nodes SN1 and SN3. Data "1" is written to SN2 and node SN4, and this information is retained. Information was written to node SN1 and node SN2 from the wiring WBL (Write fr om WBL). Information was written to nodes SN3 and SN4 from the wiring WSL. (Write from WSL).

[0385] After that, the information of nodes SN1 and SN4 is repeatedly verified in the same way as in the verification of rewrite resistance. Figure 35B shows a timing chart for verifying the write disturbance resistance.

[0386] During the verification period, node SN2 holds Data “1” and node SN3 holds Data “ 0” is held. The number of writes (rewrites) to node SN1 and node SN4 is 1. Every time 0 is raised to the Xth power (X is a natural number greater than or equal to 0), the data is stored in nodes SN2 and SN3. The information (electric potential) stored in the memory was measured. Figure 36A shows the results of the verification of the resistance to writing errors. The horizontal axis of 6A shows the number of write cycles to nodes SN1 and SN4. le), and the vertical axis represents the potential V SN is.

[0387] As can be seen from FIG. 36A, even after 10 to the power of 9 times, there is no significant change in the potential at the nodes SN2 and SN3. Therefore, the storage device 900 does not have a Wr It was found that the CAAC-IGZO FE is less susceptible to ite disturbances. T has small parasitic capacitance such as fringe factors. Therefore, even if the capacitance Cs is small, It is assumed that it is less susceptible to disturbances.

[0388] <Shmoo plot of gate potential and write speed of transistor WTr> FIG. 36B shows a state where a voltage is applied to the gate of the write transistor WTr when writing information to the memory cell. The potential of the supplied signal V WG and a Shmoo plot of the pulse width of the signal. The horizontal axis is the pulse width of the signal (Write pulse width), and the vertical axis is the Place V WG In addition, in FIG. 36B, the potential V WG The combination of "PASS" and pulse width indicates that the information was not written correctly. The time combination is marked "FAIL."

[0389] From Figure 36B, the potential V WG If the voltage is 3.3V, information can be written even with a pulse width of 20ns. It can be seen that the operation is performed normally. If Data "1" is rewritten to Data "0", The same applies when Data "0" is rewritten to Data "1". The pulse width is This corresponds to the write speed. When information is written normally, the pulse width is short. The higher the value, the faster the writing speed.

[0390] Table 1 shows the prototype memory device 900 (This work), NAND flash, P A comparison table with CM and STT-MRAM is shown below.

[0391] [Table 1]

[0392] Generally, various memory devices are used in semiconductor devices such as computers depending on the application. Figure 37 shows various storage devices by layer. The higher the layer, the faster the access speed. The lower the storage device, the higher the storage capacity and recording density. In Figure 37, from the top layer onwards, the registers embedded in a processor such as a CPU are SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), 3D NA ND memory is shown.

[0393] The memory embedded as a register in a CPU or other processing unit is used for temporary storage of calculation results. Therefore, the frequency of access from the processor is high. A high operating speed is required. Also, registers are used to store setting information for the arithmetic processing unit. It also has Noh.

[0394] SRAM is used, for example, for caches. Caches are data stored in main memory. It has the function of duplicating and storing some of the information that is being used. It stores frequently used data in a cache. By replicating the data, you can increase the speed at which you can access the data.

[0395] DRAM is used for main memory, for example. Main memory is used for reading data from storage. DRAM has the function of storing programs and data. The recording density of DRAM is approximately 0 .1~0.3Gbit / mm 2 is.

[0396] 3D NAND memory is used for storage, for example. It has the function of storing important data and various programs used by the processing unit. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. The recording density of the memory device used for storage is approximately 0.6 to 6.0 Gbit / mm 2 is.

[0397] A memory device according to one embodiment of the present invention has high operation speed and can retain data for a long period of time. A storage device according to one aspect of the present invention is a storage device that has a hierarchy where a cache is located and a hierarchy where a main memory is located. It can be suitably used as a storage device located in a boundary area 901 that includes both layers. In addition, in a storage device according to one aspect of the present invention, a hierarchy in which a main memory is located and a storage are located. The storage device can be suitably used as a storage device located in the boundary area 902 including both the hierarchical level where the storage device is located. Cut.

[0398] <Device simulation of 3D OS NAND memory device> The CAAC-IGZO used in the storage device 900 can also be formed by the ALD method. This means that the transistor according to one embodiment of the present invention can be formed not only in the XY plane direction but also in three directions. This suggests that it is possible to fabricate the NA according to one embodiment of the present invention in the two-dimensional direction (Z-axis direction). A device that assumes a 3D OS NAND type storage device that has a 3D OS NAND type storage device. A device simulation was performed.

[0399] The device simulation was performed using Synopsys TCAD Sentaurus. FIG. 38 shows a two-dimensional structural diagram of the storage device 950 used in the device simulation. The device simulation is performed by dividing the two-dimensional structure shown in Figure 38 into two parts along the Z-axis (Z-axis The experiment was carried out assuming a cylindrical storage device 950 rotated 360° around the central axis (s). In the storage device 950, the conductors FG1 to FG4 correspond to the nodes SN1 to SN4. The dielectric FG4 is assumed. In addition, the IGZO layer of the inner active layer Impurities are introduced into the IGZO layer of the outer active layer. The doped region and the not doped region region) was set.

[0400] Table 2 shows the calculation parameters used in the device simulation.

[0401] [Table 2]

[0402] The calculation results for the write and read operations of the memory device 950 are shown in FIG. 39. Write Operation and Read Operation The potentials of the wiring RBL, wiring CG, wiring WG, and wiring WSL in The horizontal axis in Figure 39 represents elapsed time.

[0403] As shown in FIG. 39, the storage device 950 stores data in accordance with the same principle as the storage devices shown in the above embodiments. This confirmed that the prototype memory device 9 00 can be fabricated vertically, enabling further miniaturization and high integration. It was shown that:

[0404] This embodiment can be implemented by appropriately combining with the configurations described in other embodiments. is. [Explanation of symbols]

[0405] 100: memory device, 110: memory cell, 111: transistor, 112: transistor , 121: terminal, 122: terminal, 123: terminal, 131: transistor, 132: trans resistor, 133: terminal, 134: terminal, 200: semiconductor device, 210: driving circuit, 211 : Peripheral circuit, 212: Control circuit, 215: Peripheral circuit, 220: Memory array, 2 21: row decoder, 222: column decoder, 223: row driver, 224: column driver, 2 25: Input circuit, 226: Output circuit, 227: Sense amplifier, 228: Voltage generation circuit

Claims

[Claim 1] n memory cells (n is an integer of 3 or more), n first wirings, n second wirings, and a third wiring; The i-th memory cell (i is an integer equal to or greater than 2 and less than n) A first transistor [i], a second transistor [i], and a capacitor [i], The i-1th memory cell is A first transistor [i-1], a second transistor [i-1], and a capacitance [i-1], The i+1th memory cell is a first transistor [i+1], a second transistor [i+1], and a capacitor [i+1]; The gate of the first transistor [i] is electrically connected to the i-th first wiring, The source of the first transistor [i] is electrically connected to the drain of the first transistor [i-1], The drain of the first transistor [i] is electrically connected to the source of the first transistor [i+1]; The gate of the second transistor [i] is electrically connected to the drain of the first transistor [i], The source of the second transistor [i] is electrically connected to the drain of the second transistor [i-1], The drain of the second transistor [i] is electrically connected to the source of the second transistor [i+1]; a back gate of the second transistor [i] is electrically connected to the i-th second wiring, The back gate of the second transistor [i-1] is electrically connected to the (i-1)th second wiring, a back gate of the second transistor [i+1] is electrically connected to the (i+1)th second wiring; The capacitor [i] is provided between the gate of the second transistor [i] and the third wiring, The capacitance [i-1] is provided between the gate of the second transistor [i-1] and the third wiring, The memory device further comprises the capacitor [i+1] between the gate of the second transistor [i+1] and the third wiring.

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