Data compression circuit, memory system, and control method

Abstract

To provide a data compression circuit capable of reducing the circuit area.SOLUTION: A plurality of intermediate match candidate generation circuits of a data compression circuit generate intermediate match candidates by incrementing the intermediate match candidates based on match lengths when a distance corresponding to the match lengths received from corresponding intermediate match candidate selection circuits matches a distance corresponding to intermediate match candidates generated in the previous cycle and the received match lengths are greater than a threshold value. The plurality of intermediate match candidate generation circuits generate the match lengths as new intermediate match candidates when the distance corresponding to the received match lengths does not match a distance corresponding to the intermediate match candidates generated in the previous cycle or the received match lengths are equal to or less than the threshold value.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION Embodiments of the present invention relate to a data compression circuit, a memory system, and a control method. [Background technology]

[0002] In recent years, memory systems equipped with non-volatile memory have become widespread. Storing large amounts of data directly in such memory systems requires a memory system with a large storage capacity. For example, using such a memory system in a data center would require enormous costs.

[0003] Therefore, lossless compression of data is typically used to reduce the size of data written to a memory system.

[0004] A data compression circuit that performs this lossless compression of data has a high throughput if it can compress a large amount of data per unit time. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Application Publication No. 2007 / 0146173 [Patent Document 2] US Patent Application Publication No. 2014 / 0156790 [Patent Document 3] U.S. Patent No. 6,268,809 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a data compression circuit, a memory system, and a control method that can reduce the circuit area. [Means for solving the problem]

[0007] According to an embodiment, a data compression circuit compresses input first data. The data compression circuit includes a buffer, multiple match determination circuits, multiple match length calculation circuits, multiple intermediate match candidate selection circuits, and multiple intermediate match candidate generation circuits. The buffer has multiple registers, each storing a one-byte data unit. The multiple registers include one or more first registers into which data units included in the first data are sequentially stored for each cycle. The multiple match determination circuits correspond one-to-one to distances between the one or more first registers and registers storing data units stored earlier in the order than the data unit stored in the first register, and determine whether the data unit stored in the one or more first registers matches the earlier data unit. Each of the multiple match length calculation circuits corresponds to one or more match determination circuits among the multiple match determination circuits, and calculates a match length based on the determination result received from the corresponding one or more match determination circuits. Each of the plurality of intermediate match candidate selection circuits corresponds to two or more match length calculation circuits among the plurality of match length calculation circuits, and selects one match length from two or more match lengths received from the corresponding two or more match length calculation circuits. Each of the plurality of intermediate match candidate generation circuits corresponds to a respective one of the plurality of intermediate match candidate selection circuits, and generates an intermediate match candidate based on the match length selected by the corresponding intermediate match candidate selection circuit. Each of the plurality of intermediate match candidate generation circuits calculates match lengths with a larger bit width than the plurality of match length calculation circuits. Each of the plurality of intermediate match candidate generation circuits generates an intermediate match candidate by incrementing the match length corresponding to the intermediate match candidate generated in the previous cycle based on the match length, when the distance corresponding to the match length received from the corresponding intermediate match candidate selection circuit matches the distance corresponding to the intermediate match candidate generated in the previous cycle and the received match length is greater than a threshold.The plurality of intermediate match candidate generation circuits generate the match length as a new intermediate match candidate when the distance corresponding to the received match length does not match the distance corresponding to the intermediate match candidate generated in the previous cycle, or when the received match length is less than or equal to the threshold value. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram showing an example of the configuration of a memory system including a data compression circuit according to a first embodiment. [Figure 2] 2A and 2B are diagrams for explaining data compression processing and data decompression processing executed by a data compression circuit and a data decompression circuit according to the first embodiment. [Figure 3] FIG. 2 is a block diagram showing an example of the configuration of a dictionary coding unit of the data compression circuit according to the first embodiment. [Figure 4] FIG. 10 is a diagram for explaining a data compression process executed by a data compression circuit according to a comparative example. [Figure 5] FIG. 10 is a diagram showing an example of the configuration of a match length calculation circuit included in a data compression circuit according to a comparative example. [Figure 6] FIG. 2 is a diagram for explaining a data compression process executed by a data compression circuit according to the first embodiment. [Figure 7] FIG. 2 is a diagram showing an example of the configuration of an intermediate match candidate generation circuit included in the data compression circuit according to the first embodiment. [Figure 8] 4 is a flowchart showing the procedure of a data compression process executed by a data compression circuit according to the first embodiment. [Figure 9] FIG. 10 is a diagram for explaining a data compression process executed by a data compression circuit according to a second embodiment. [Figure 10] 10 is a flowchart showing the procedure of a data compression process executed by a data compression circuit according to a second embodiment. [Figure 11] FIG. 11 is a diagram for explaining a data compression process executed by a data compression circuit according to the third embodiment. [Figure 12]FIG. 11 is a diagram showing an example of the configuration of a match length calculation circuit included in a data compression circuit according to a third embodiment. [Figure 13] FIG. 11 is a diagram showing output data for input data in a match length calculation circuit included in a data compression circuit according to a third embodiment. [Figure 14] FIG. 11 is a diagram showing an example of the configuration of an intermediate match candidate generation circuit included in the data compression circuit according to the third embodiment. [Figure 15] 10 is a flowchart showing the procedure of a data compression process executed by a data compression circuit according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Each embodiment will be described below with reference to the drawings. (First embodiment) 1 is a block diagram showing an example of the configuration of an information processing system 1 including a memory system 3 including a data compression circuit 451 according to the first embodiment. The memory system 3 according to the first embodiment is a storage device including a nonvolatile memory.

[0010] The information processing system 1 includes a host device (host) 2 and a memory system 3. The host 2 and the memory system 3 can be connected via a bus 7.

[0011] The host 2 is an information processing device. The host 2 is, for example, a personal computer, a server computer, or a mobile terminal. The host 2 accesses the memory system 3. Specifically, the host 2 sends a write command to the memory system 3, which is a command requesting that data be written to the nonvolatile memory. The host 2 sends a read command to the memory system 3, which is a command requesting that data be read from the nonvolatile memory.

[0012] The memory system 3 is a semiconductor storage device configured to write data to and read data from a nonvolatile memory. The memory system 3 is communicatively connected to the host 2. The memory system 3 is realized by, for example, a solid-state device (SSD). The nonvolatile memory is, for example, a NAND flash memory 5.

[0013] The memory system 3 can be used as storage for the host 2. The memory system 3 may be built into the host 2, or may be connected to the host 2 via a cable or a network.

[0014] Communication between the memory system 3 and the host 2 is carried out via a bus 7. The bus 7 is primarily used for transmitting data and input / output commands (I / O commands) from the host 2 to the memory system 3, and for transmitting data and responses from the memory system 3 to the host 2. An I / O command is a command for writing or reading data to or from the nonvolatile memory. Examples of I / O commands include a write command for requesting writing data to the nonvolatile memory and a read command for requesting reading data from the nonvolatile memory.

[0015] The interface for connecting the memory system 3 and the host 2 is SCSI, Serial Attached SCSI (SAS), ATA (AT Attachment), Serial ATA (SATA), PCI Express TM (PCIe TM ), Ethernet TM , Fiber channel, NVM Express TM (NVMe TM ) and other standards.

[0016] Next, we will explain the internal configuration of the memory system 3. The memory system 3 includes a memory controller (controller) 4 and a NAND flash memory 5. The memory system 3 may further include a dynamic random access memory (DRAM) 6.

[0017] The controller 4 is a memory controller that controls the NAND flash memory 5 and the DRAM 6. The controller 4 is, for example, a control circuit such as a system-on-a-chip (SoC). The controller 4 is electrically connected to each of the NAND flash memory 5 and the DRAM 6. The controller 4 processes various commands received from the host 2. The controller 4 writes data to the NAND flash memory 5 by processing a write command. The controller 4 reads data from the NAND flash memory 5 by processing a read command. The controller 4 may have a built-in static random access memory (SRAM) or a DRAM. In this case, the DRAM 6 external to the controller 4 may not be provided.

[0018] The controller 4 functions as, for example, a flash translation layer (FTL) configured to perform data management and block management of the NAND flash memory 5. The data management performed by the FTL includes management of mapping information indicating the correspondence between each logical address and each physical address of the NAND flash memory 5. The block management includes management of bad blocks, wear leveling, and garbage collection.

[0019] The logical address is used by the host 2 to address a storage area in the memory system 3. The logical address is, for example, a logical block address (LBA).

[0020] The management of the mapping between each logical address and each physical address is performed using, for example, a logical-physical address conversion table. The controller 4 uses the logical-physical address conversion table to manage the mapping between each logical address and each physical address in specific management size units. A physical address corresponding to a certain logical address indicates a physical storage location in the NAND flash memory 5 where user data of this logical address is written. The logical-physical address conversion table may be loaded from the NAND flash memory 5 to the DRAM 6 when the memory system 3 is started up.

[0021] Data can be written to one page only once per P / E cycle. Therefore, the controller 4 writes updated user data corresponding to a certain logical address to a different physical storage location, rather than to the physical storage location where the previous user data corresponding to this logical address is stored. The controller 4 then invalidates the previous user data by updating the logical-physical address translation table so as to associate this logical address with this different physical storage location.

[0022] The controller 4 is also communicatively connected to the DRAM 6. The controller 4 writes data to the DRAM 6 and reads data from the DRAM 6.

[0023] The NAND flash memory 5 is a non-volatile memory. The NAND flash memory 5 is, for example, a flash memory with a three-dimensional structure. The NAND flash memory 5 includes a plurality of memory cells arranged in a matrix. The NAND flash memory 5 includes a plurality of blocks BLK0 to BLKm-1. Each of the blocks BLK0 to BLKm-1 is a unit of a data erase operation for erasing data. The data erase operation is also called an erase operation or simply an erase operation. Each of the blocks BLK0 to BLKm-1 is also called a physical block, a flash block, or a memory block.

[0024] Each of the blocks BLK0 to BLKm-1 includes multiple pages (here, pages P0 to Pn-1). Each page includes multiple memory cells connected to the same word line. Each of the pages P0 to Pn-1 is a unit of data write and read operations.

[0025] The DRAM 6 is a volatile memory. A part of the storage area of ​​the DRAM 6 is used, for example, to temporarily store information used to manage the memory system 3. Another part of the storage area of ​​the DRAM 6 can be used to temporarily store write data received from the host 2 or read data read from the NAND flash memory 5.

[0026] Next, we will explain an example of the internal configuration of the controller 4. The controller 4 includes a host interface (host I / F) 41, a CPU 42, a NAND interface (NAND I / F) 43, a DRAM interface (DRAM I / F) 44, and a compression / decompression device 45. These components are connected via an internal bus 40.

[0027] The host interface 41 is an interface circuit that executes communication with the host 2. For example, the host interface 41 receives I / O commands and data from the host 2. The host interface 41 also transmits data and responses to the host 2.

[0028] The CPU 42 is a processor. The CPU 42 controls the host interface 41, the NAND interface 43, the DRAM interface 44, and the compression / decompression device 45. The CPU 42 loads a control program (firmware) stored in the NAND flash memory 5 or a ROM (not shown) into the DRAM 6 or a RAM (not shown) in the controller 4. The CPU 42 performs various processes by executing this control program (firmware).

[0029] The NAND interface 43 is an interface circuit that executes access to the NAND flash memory 5 .

[0030] The NAND interface 43 is an interface circuit that executes access to the NAND flash memory 5. When the NAND flash memory 5 is composed of multiple NAND flash dies, the NAND interface 43 may be connected to each of these multiple NAND flash memory dies via multiple channels. By driving multiple NAND flash dies in parallel, it is possible to broaden the bandwidth of access to the entire NAND flash memory 5.

[0031] The DRAM interface 44 is an interface circuit that executes access to the DRAM 6. The DRAM interface 44 stores data in the DRAM 6 and reads data stored in the DRAM 6.

[0032] The compression / decompression device 45 is a device that performs data compression and data decompression, and includes a data compression circuit 451 and a data decompression circuit 452.

[0033] The data compression circuit 451 is a circuit that compresses data to be written to the NAND flash memory 5. The data compression circuit 451 compresses, for example, write data associated with a write command received from the host 2. The data compression circuit 451 compresses the write data using a lossless compression algorithm. Hereinafter, data obtained by compressing the write data will be referred to as compressed data. Examples of lossless compression algorithms include dictionary coding, entropy coding, and a combination of dictionary coding and entropy coding (referred to as deflate). Hereinafter, it is assumed that at least dictionary coding is used as the lossless compression algorithm.

[0034] The compressed data has a smaller size than the write data before compression. The larger the size of the write data compressed at one time by the data compression circuit 451, the smaller the ratio of the size of the compressed data to the size of the write data. In other words, the larger the size of the write data compressed at one time, the more efficiently the data compression circuit 451 can compress the write data. This is because the larger the size of the write data compressed at one time, the greater the amount of information that can be referenced in the compression process of the write data.

[0035] The data decompression circuit 452 is a circuit that generates uncompressed data by decompressing compressed data. The data decompression circuit 452 decompresses the compressed data read from the NAND flash memory 5 based on, for example, a read command received from the host 2.

[0036] Next, the data compression process and the data decompression process will be described. Fig. 2 is a diagram for explaining the data compression process and the data decompression process executed by the data compression circuit 451 and the data decompression circuit 452 according to the first embodiment.

[0037] Here, it is assumed that the data compression circuit 451 is configured to perform dictionary coding and entropy coding. In this case, the data compression circuit 451 includes a dictionary coding unit 4511 and an entropy coding unit 4512.

[0038] The dictionary-based coding unit 4511 performs dictionary-based coding on input data (uncompressed data).

[0039] Dictionary coding is a coding method that converts data to be compressed into a distance and a match length using a dictionary buffer that stores previously input data. Dictionary coding is also called dictionary compression. Examples of dictionary coding that can be used include LZ77 and LZSS.

[0040] If data matching the data to be compressed is present in the dictionary buffer, the dictionary-based encoding unit 4511 searches the dictionary buffer to obtain past data that at least partially matches the data to be compressed, and obtains a distance and a match length.The dictionary-based encoding unit then replaces the data to be compressed with the distance and the match length, and outputs the result of dictionary-based encoding.The distance is the distance from the location in the dictionary buffer where the data to be compressed is stored to the location where the obtained past data is stored.The match length is the length of the portion that matches between the obtained past data and the data to be compressed.In this way, the dictionary-based encoding unit 4511 can compress the data by converting the data to be compressed into a distance and a match length.

[0041] On the other hand, if there is no data in the dictionary buffer that matches the data to be compressed, the dictionary-based coding unit 4511 outputs the data to be compressed as is as a result of dictionary-based coding.

[0042] The entropy coding unit 4512 performs entropy coding on the input data.

[0043] Entropy coding converts the code length of input data depending on the frequency of occurrence of that data. In other words, the entropy coding unit 4512 can reduce the overall amount of code by utilizing differences in the frequency of occurrence of input data to assign codes of different code lengths to the input data.

[0044] The entropy coding unit 4512 uses, for example, Huffman coding as entropy coding. When Huffman coding is used, the entropy coding unit 4512 may perform static Huffman coding, which performs coding using a pre-constructed code tree, or may perform dynamic Huffman coding, which changes the code tree depending on the data to be Huffman coded. Alternatively, other entropy coding methods, such as arithmetic coding, may be used.

[0045] In the data compression circuit 451, in the data compression process, first, the dictionary coding unit 4511 performs dictionary coding on the input uncompressed data. Then, the entropy coding unit 4512 performs entropy coding on the result of the dictionary coding. In this way, the data compression circuit 451 generates compressed data. The generated compressed data is written to, for example, the NAND flash memory 5.

[0046] The data decompression circuit 452 includes an entropy decoding unit 4521 and a dictionary-based decoding unit 4522 .

[0047] The entropy decoding unit 4521 performs entropy decoding on the input data (compressed data) and sends the result of the entropy decoding to the dictionary-based decoding unit 4522.

[0048] The dictionary-based decoding unit 4522 performs dictionary-based decoding on the input data, thereby outputting uncompressed data.

[0049] In the data decompression process of the data decompression circuit 452, first, the entropy decoding unit 4521 performs entropy decoding on the compressed data read from the NAND flash memory 5. Then, the dictionary-based decoding unit 4522 performs dictionary-based decoding on the result of the entropy decoding. As a result, the data decompression circuit 452 generates uncompressed data.

[0050] Next, we will explain in detail an example configuration of the dictionary coding unit 4511. Fig. 3 is a block diagram showing an example configuration of the dictionary coding unit 4511 of the data compression circuit 451 according to the first embodiment.

[0051] The dictionary-based coding unit 4511 includes a dictionary buffer 45111, a plurality of match determination circuits 45112-1 to 45112-N, a plurality of match length calculation circuits 45113-1 to 45113-N, a match candidate selection circuit 45114, intermediate match candidate selection circuits 45115-1 to 45115-M, intermediate match candidate generation circuits 45116-1 to 45116-M, a match candidate processing circuit 45117, and a non-match input data insertion circuit 45118.

[0052] The dictionary buffer 45111, match determination circuit 45112, match length calculation circuit 45113, match candidate selection circuit 45114, intermediate match candidate selection circuit 45115, intermediate match candidate generation circuit 45116, match candidate processing circuit 45117, and non-match input data insertion circuit 45118 are realized by at least one of a register, an adder, a comparator, a selector, and other arithmetic units. The register is realized by, for example, a sequential circuit such as a flip-flop. The adder, comparator, selector, and other arithmetic units are realized by, for example, a combinational logic circuit.

[0053] The dictionary buffer 45111 is a shift register (which may also be referred to as a sliding buffer) that stores input data. The dictionary buffer 45111 has, for example, N+1 entries. Each entry is, for example, a register that stores one data unit. A data unit is also referred to as a symbol. The size of a data unit is, for example, 1 byte. N is an integer equal to or greater than 1, for example, 2048. Each entry is associated with an index indicating a value from 0 to N. Of the multiple entries, for example, the entry corresponding to 0 is a register in which the latest data unit of the input data is stored in order.

[0054] In the first embodiment, it is assumed that a data unit of one byte is stored in the dictionary buffer 45111 in each cycle. In this case, the data unit stored in each entry is shifted in each cycle to an entry corresponding to an index that is one larger. That is, the data unit stored in the entry corresponding to 0 is stored in the entry corresponding to 1 in the next cycle. The newest data unit is then stored in the entry corresponding to 0. As a result, the entry corresponding to a larger index stores an older data unit. Here, "older" refers to the data unit being stored earlier in the dictionary buffer 45111.

[0055] Furthermore, the distance in the dictionary buffer 45111 is represented by the difference between the indexes corresponding to each entry. For example, the distance between the entry corresponding to 0 and the entry corresponding to N is N.

[0056] The match determination circuit 45112 is a circuit that determines, for each cycle, whether two data units match. Each of the multiple match determination circuits 45112-1 to 45112-N corresponds to a respective entry corresponding to 1 to N in the dictionary buffer 45111. That is, each of the multiple match determination circuits 45112-1 to 45112-N corresponds to a respective distance between a register in the dictionary buffer 45111 in which a new data unit is stored and a register storing a data unit that precedes the data unit stored in the new register. Each of the multiple match determination circuits 45112-1 to 45112-N determines whether the data unit stored in the corresponding entry matches the data unit stored in the entry corresponding to 0. That is, the result of the determination by the match determination circuit 45112-N indicates whether a data unit at a distance N matches the latest data. Each of the plurality of match determination circuits 45112-1 to 45112-N transmits the determination result to the corresponding match length calculation circuit 45113.

[0057] The match length calculation circuit 45113 is a circuit that calculates the match length for the corresponding distance for each cycle. The match length calculation circuits 45113-1 to 45113-N correspond to distances 1 to N, respectively. Each of the match length calculation circuits 45113-1 to 45113-N receives a judgment result from the match judgment circuit 45112 corresponding to the same distance. Each of the match length calculation circuits 45113-1 to 45113-N calculates the match length based on the received judgment result. If the received judgment result indicates that the two data units match, the match length calculation circuit 45113 increments the match length by 1. If the received judgment result indicates that the two data units do not match, the match length calculation circuit 45113 resets the match length to 0. Then, the match length calculation circuit 45113 transmits the corresponding distance and match length to the corresponding intermediate match candidate selection circuit 45115.

[0058] The match candidate selection circuit 45114 is a circuit that selects a match candidate from multiple intermediate match candidates and match lengths. For example, the match candidate selection circuit 45114 selects the intermediate match candidate with the longest match length from among the intermediate match candidates output by each of the intermediate match candidate generation circuits 45116-1 to 45116-M described below as the match candidate. If there are multiple longest match lengths among the multiple match lengths, the match candidate selection circuit 45114 selects, for example, the match length with the shortest distance from the latest data unit as the match candidate. The match candidate selection circuit 45114 then transmits the selected match candidate to the match candidate processing circuit 45117.

[0059] The intermediate match candidate selection circuits 45115-1 to 45115-M are circuits that select one match length from multiple match lengths. Each of the intermediate match candidate selection circuits 45115-1 to 45115-M corresponds to two or more match length calculation circuits among the multiple match length calculation circuits 45113-1 to 45113-N. Each of the intermediate match candidate selection circuits 45115-1 to 45115-M selects, for example, the longest match length from a group of multiple match lengths received from the corresponding match length calculation circuit 45113. If there are multiple longest match lengths among the multiple match lengths, the intermediate match candidate selection circuit 45115 selects, for example, the match length with the shortest distance from the latest data unit as the match candidate. Then, each of the intermediate match candidate selection circuits 45115-1 to 45115-M transmits the selected intermediate match candidate to the corresponding intermediate match candidate generation circuit 45116-1 to 45116-M.

[0060] The intermediate match candidate generation circuits 45116-1 to 45116-M are circuits that calculate the match length of an intermediate match candidate at a corresponding distance for each cycle. The intermediate match candidate generation circuits 45116-1 to 45116-M correspond to the intermediate match candidate selection circuits 45115-1 to 45115-M, respectively. Each of the intermediate match candidate generation circuits 45116-1 to 45116-M receives a match length from the corresponding intermediate match candidate selection circuit 45115. If the distance corresponding to the received match length matches the distance corresponding to the match length received in the previous cycle and the received match length exceeds a threshold, each of the intermediate match candidate generation circuits 45116-1 to 45116-M generates an intermediate match candidate by incrementing the match length corresponding to the intermediate match candidate generated in the previous cycle by 1. Furthermore, if the distance corresponding to the received match length does not match the distance corresponding to the match length received in the previous cycle, or if the received match length is equal to or less than a threshold, each of the intermediate match candidate generation circuits 45116-1 to 45116-M generates an intermediate match candidate by associating the received match length with a new intermediate match candidate. The threshold is, for example, 0. Then, the intermediate match candidate generation circuits 45116-1 to 45116-M transmit the corresponding distance and match length to the match candidate selection circuit 45114.

[0061] The match candidate processing circuit 45117 is a circuit that processes input data based on the match candidates selected by the match candidate selection circuit 45114. For example, the match candidate processing circuit 45117 holds the match candidates selected by the match candidate selection circuit 45114 for each cycle. Then, for each cycle, the match candidate processing circuit 45117 compares the match candidate selected in the latest cycle with the match candidate selected in the previous cycle. Based on the result of this comparison, the match candidate processing circuit 45117 determines whether to adopt the match candidate selected and held in the previous cycle. For example, the match candidate processing circuit 45117 uses a method of discarding the match candidate from the previous cycle and holding the latest match candidate if there is an inconsistency, such as when the latest match candidate is an extended match length of the match candidate from the previous cycle. Alternatively, the match candidate processing circuit 45117 may concatenate match candidates when specific conditions are met, or may process input data using various other methods. This makes it possible to avoid data duplication due to multiple match candidates.

[0062] The non-match input data insertion circuit 45118 is a circuit that inserts non-match data into processed input data. For example, non-match data is data that has not been replaced by a match candidate. For input data that has been processed by the match candidate processing circuit 45117 based on a match candidate, the non-match input data insertion circuit 45118 inserts non-matching data units. This generates compressed data. The generated compressed data can then be input to the entropy coding unit 4512.

[0063] Hereinafter, for simplicity, data output by dictionary coding executed by dictionary coding unit 4511 will be referred to as compressed data, and dictionary coding will be referred to as data compression processing.

[0064] First, a comparative example will be described in which a dictionary-based coding unit performs data compression processing without using intermediate match candidates. Fig. 4 is a diagram for explaining the data compression processing performed by a data compression circuit according to the comparative example.

[0065] The latest data unit is input in each cycle to the entry of dictionary buffer 45111A corresponding to an index indicating 0. In addition, the data units stored in each entry of dictionary buffer 45111A are shifted to the subsequent entry in each cycle.

[0066] Each of the match determination circuits 45112A-1 to 45112A-N determines whether the data unit stored in the entry corresponding to 0 matches the data unit stored in each of the entries corresponding to 1 to N. Specifically, the match determination circuit 45112A-1 determines whether the data unit stored in the entry corresponding to 0 matches the data unit corresponding to the entry corresponding to 1 (i.e., the data unit whose distance is 1). The match determination circuit 45112A-2 determines whether the data unit stored in the entry corresponding to 0 matches the data unit corresponding to the entry corresponding to 2 (i.e., the data unit whose distance is 2). The match determination circuit 45112A-3 determines whether the data unit stored in the entry corresponding to 0 matches the data unit corresponding to the entry corresponding to 3 (i.e., the data unit whose distance is 3). The match determination circuits 45112A-N determine whether the data unit stored in the entry corresponding to 0 matches the data unit corresponding to the entry corresponding to N (i.e., the data unit whose distance is N).

[0067] Each of the match length calculation circuits 45113A-1 to 45113A-N calculates the match length based on the determination result output by the corresponding match determination circuit 45112A-1 to 45112A-N. Each of the match length calculation circuits 45113A-1 to 45113A-N in the comparative example calculates the match length using an 8-bit register.

[0068] An example of the configuration of the match length calculation circuit 45113A will be described with reference to Fig. 5. Fig. 5 is a diagram showing an example of the configuration of a match length calculation circuit included in a data compression circuit according to a comparative example. Although Fig. 5 shows a match length calculation circuit 45113A-1, each of the match length calculation circuits 45113A-2 to 45113A-N has a similar configuration to that of the match length calculation circuit 45113A-1.

[0069] The match length calculation circuit 45113A-1 has a selector 451131A and a register 451132A.

[0070] The selector 451131A selects the update of the match length based on the result of the determination.

[0071] Register 451132A is an 8-bit register that temporarily stores the most recent match length.

[0072] The match length calculation circuit 45113A-1 receives the result of the determination from the match determination circuit 45112A-1 every cycle. The result of the determination indicates whether the two data units match or do not match.

[0073] If the determination result indicates a mismatch, selector 451131A selects 0 and stores it in register 451132A. This updates the match length to 0.

[0074] If the determination result indicates a match, selector 451131A selects the saturated summed match length. This match length is a value obtained by adding 1 to the match length previously stored in register 451132A. If the match length stored in register 451132A is an upper limit value (e.g., 255), the upper limit value is maintained. Then, this saturated summed match length is stored in register 451132A.

[0075] Then, the match length calculation circuit 45113A-1 outputs the match length stored in the register 451132A for each cycle.

[0076] Returning to the explanation of Figure 4.

[0077] Match candidate selection circuit 45114A selects match candidates from the match lengths output from each of match length calculation circuits 45113A-1 to 45113A-N. For example, match candidate selection circuit 45114A selects the longest match length from among multiple match lengths as a match candidate. If there are two or more longest match lengths, match candidate selection circuit 45114A selects the match length with the shortest distance as a match candidate.

[0078] The match candidate processing circuit 45117A and the non-match input data insertion circuit 45118A generate compressed data based on the match candidates selected by the match candidate selection circuit 45114A.

[0079] In this way, in the comparative example, each of the N match length calculation circuits 45113A performs match length calculation with a bit width of 8 bits. Therefore, in order to achieve high throughput, the circuit area increases as the value of N increases.

[0080] In contrast, for example, the N match length calculation circuits 45113 in the first embodiment perform match length calculations with a bit width of 4 bits, which is half that of the comparative example, and then perform data compression processing using intermediate match candidates selected from the match lengths calculated with the bit width of 4 bits.

[0081] FIG. 6 is a diagram for explaining the data compression process executed by the data compression circuit according to the first embodiment.

[0082] In each cycle, the latest data unit is input to the entry corresponding to the index indicating 0 in the dictionary buffer 45111. In addition, the data units stored in each entry of the dictionary buffer 45111 are shifted to the subsequent entry in each cycle.

[0083] Each of the match determination circuits 45112-1 to 45112-N determines whether the data unit stored in the entry corresponding to 0 matches the data unit stored in each of the entries corresponding to 1 to N. Specifically, the match determination circuit 45112-1 determines whether the data unit stored in the entry corresponding to 0 matches the data unit corresponding to the entry corresponding to 1 (i.e., the data unit whose distance is 1). The match determination circuit 45112-2 determines whether the data unit stored in the entry corresponding to 0 matches the data unit corresponding to the entry corresponding to 2 (i.e., the data unit whose distance is 2). The match determination circuit 45112-3 determines whether the data unit stored in the entry corresponding to 0 matches the data unit corresponding to the entry corresponding to 3 (i.e., the data unit whose distance is 3). The match determination circuit 45112-N determines whether the data unit stored in the entry corresponding to 0 matches the data unit corresponding to the entry corresponding to N (i.e., the data unit whose distance is N).

[0084] Each of the match length calculation circuits 45113-1 to 45113-N calculates the match length based on the determination result output by the corresponding match determination circuit 45112-1 to 45112-N. Each of the match length calculation circuits 45113-1 to 45113-N in the first embodiment calculates the match length using a 4-bit register.

[0085] Each of the match length calculation circuits 45113 in the first embodiment calculates the match length in a manner similar to that of the match length calculation circuit 45113A in the comparative example. However, the match length calculation circuit 45113 in the first embodiment uses a 4-bit register instead of an 8-bit register. The upper limit of the match length calculated by the match length calculation circuit 45113 is 15. Therefore, the match length calculation circuit 45113 in the first embodiment is implemented using registers that are half the size of the match length calculation circuit 45113A in the comparative example.

[0086] Each of the match length calculation circuits 45113-1 to 45113-N transmits the match length stored in its register to the corresponding intermediate match candidate selection circuit 45115 every cycle. For example, if the maximum index value N is 2048 and the number M of intermediate match candidate selection circuits 45115 and intermediate match candidate generation circuits 45116 is 128, 16 match length calculation circuits 45113 correspond to one intermediate match candidate selection circuit 45115. Specifically, each of the match length calculation circuits 45113-1 to 45113-16 transmits the match length to the intermediate match candidate selection circuit 45115-1. Although not shown, each of the match length calculation circuits 45113-17 to 45113-32 transmits the match length to the intermediate match candidate selection circuit 45115-2. Furthermore, each of the match length calculation circuits 45113-2033 to 45113-N (2048) transmits a match length to the intermediate match candidate selection circuit 45115-M (128).

[0087] Each of the intermediate match candidate selection circuits 45115-1 through 45115-M selects one match candidate from the received match lengths. For example, each of the intermediate match candidate selection circuits 45115-1 through 45115-M selects the longest match length from the multiple match lengths it receives in each cycle. Then, each of the intermediate match candidate selection circuits 45115-1 through 45115-M transmits the selected match length and the distance corresponding to the match length to each of the intermediate match candidate generation circuits 45116-1 through 45116-M.

[0088] Each of the intermediate match candidate generation circuits 45116-1 to 45116-M generates an intermediate match candidate based on the received match length and distance.

[0089] The configuration of the intermediate match candidate generation circuit 45116 will be described with reference to Fig. 7. Fig. 7 is a diagram showing an example configuration of an intermediate match candidate generation circuit included in the data compression circuit according to the first embodiment. While Fig. 7 shows an intermediate match candidate generation circuit 45116-1, each of the intermediate match candidate generation circuits 45116-2 to 45116-N has a similar configuration to that of the intermediate match candidate generation circuit 45116-1.

[0090] The intermediate match candidate generation circuit 45116-1 has a register 451161, a selector 451162, and a register 451163.

[0091] Register 451161 is a register that temporarily stores the distance of the intermediate match candidate. Register 451161 temporarily stores, for example, 4-bit data.

[0092] The selector 451162 selects an update of the intermediate match candidate based on the result of the determination. The selector 451162 determines an update of the intermediate match candidate based on the result of the determination as to whether the distance of the latest intermediate match candidate is the same as the distance of the intermediate match candidate in the previous cycle and the length of the intermediate match candidate is greater than 0. 0 is, for example, a preset threshold value.

[0093] Register 451133 is a register that temporarily stores the length of the latest intermediate match candidate. Register 451133 temporarily stores 8-bit data.

[0094] The intermediate match candidate generation circuit 45116-1 receives the length (newLen) and distance (newX) of a match candidate from the intermediate match candidate selection circuit 45115-1 every cycle. The match candidate length (newLen) is 4-bit data. The distance (newX) is also 4-bit data.

[0095] The most recent distance received, newX, is stored in register 451161.

[0096] The intermediate match candidate generation circuit 45116-1 determines whether the conditions that newX and X are the same and newLen is greater than 0 are met, based on the length newLen and distance newX of the most recently received intermediate match candidate and the distance X stored in the register 451161.

[0097] If the above condition is not met, the selector 451162 selects newLen and outputs it to the register 451163. As a result, the match length becomes the same value as newLen.

[0098] If the above conditions are met, selector 451162 selects the saturated summed match length. This match length is the match length previously stored in register 451163 plus 1. If the match length stored in register 451163 is the upper limit value, the upper limit value is maintained. Then, this saturated summed match length is stored in register 451163.

[0099] Then, for each cycle, the intermediate match candidate generation circuit 45116 outputs the match length (Length) stored in the register 451163 and the distance (X) stored in the register 451161 as an intermediate match candidate. This allows the intermediate match candidate generation circuit 45116 to generate intermediate match candidates including an 8-bit wide match length based on the selected 4-bit wide match length.

[0100] Returning to the explanation of Figure 6, the match candidate selection circuit 45114 selects one match candidate from the multiple intermediate match candidates received from each of the intermediate match candidate generation circuits 45116-1 to 45116-M. For example, the match candidate selection circuit 45114 selects the intermediate match candidate having the longest match length as the match candidate from among the multiple intermediate match candidates. If there are two or more longest match lengths, the match candidate selection circuit 45114 selects the intermediate match candidate that has the longest match length and corresponds to the shortest distance as the match candidate.

[0101] The match candidate processing circuit 45117 and the non-match input data insertion circuit 45118 generate compressed data based on the match candidates selected by the match candidate selection circuit 45114 .

[0102] Next, the procedure of the process executed in each cycle in the data compression process in the first embodiment will be described. Fig. 8 is a flowchart showing the procedure of the data compression process executed by the data compression circuit in the first embodiment. The data compression process starts with the start of a cycle.

[0103] First, one data unit is input to an entry of dictionary buffer 45111 (step S11). For example, the latest data unit is input to the entry corresponding to the index indicating 0.

[0104] Each of the plurality of match determination circuits 45112 determines whether or not the two data units match, and transmits the determination result to the match length calculation circuit 45113 (step S12).

[0105] Each of the plurality of match length calculation circuits 45113 calculates a match length based on the determination result received in S12 (step S13). Each of the plurality of match length calculation circuits 45113 transmits the calculated match length to the corresponding intermediate match candidate selection circuit 45115.

[0106] Each of the multiple intermediate match candidate selection circuits 45115 selects one intermediate match candidate from the multiple received match lengths (step S14). Each of the multiple intermediate match candidate selection circuits 45115, for example, selects the longest match length from the multiple received match lengths as the intermediate match candidate. If there are two or more longest match lengths, the intermediate match candidate 45115 selects the match length corresponding to the shortest distance from among the longest match lengths as the intermediate match candidate. Then, each of the multiple intermediate match candidate selection circuits 45115 transmits the selected intermediate match candidate to the intermediate match candidate generation circuit 45116.

[0107] Each of the multiple intermediate match candidate generation circuits 45116 determines whether the distance of the received intermediate match candidate is the same as the distance of the intermediate match candidate in the previous cycle and the match length of the received intermediate match candidate is greater than 0 (step S15).

[0108] If the distance of the received intermediate match candidate is the same as the distance of the intermediate match candidate in the previous cycle and the match length of the received intermediate match candidate is greater than 0 (Yes in S15), the intermediate match candidate generation circuit 45116 increments the match length of the intermediate match candidate by 1 (step S16).

[0109] If the distance of the received intermediate match candidate is different from the distance of the intermediate match candidate in the previous cycle, or if the match length of the received intermediate match candidate is 0 (No in S15), the intermediate match candidate generation circuit 45116 records the match length of the received intermediate match candidate (step S17).

[0110] Then, each of the plurality of intermediate match candidate generation circuits 45116 transmits an intermediate match candidate to the match candidate selection circuit 45114 .

[0111] The match candidate selection circuit 45114 selects a match candidate from the received intermediate match candidates (step S18).

[0112] As described above, in the data compression circuit 451 according to the first embodiment, the match length calculation circuits 45113, the number of which corresponds to the upper limit of the indexes in the dictionary buffer 45111, each calculate a match length with a narrow bit width (e.g., 4 bits). The intermediate match candidate selection circuit 45115 selects M intermediate match candidates from the calculated N match lengths. Then, the intermediate match candidate generation circuit 45116 calculates a match length with a wide bit width (e.g., 8 bits) for each of the selected intermediate match candidates.

[0113] Here, assume that N is 2048 and M is 128. In this case, if each of the 2048 match length calculation circuits performs calculations with a bit width of 8 bits, a circuit including a register capable of holding 2048 pieces of data (8 bits) is required.

[0114] In contrast, in the data compression circuit according to the first embodiment, each of the 2048 match length calculation circuits 45113 performs calculations with a bit width of 4 bits, and therefore requires a circuit including a register capable of holding 2048 pieces of data (4 bits x 4 bits). Furthermore, each of the 128 intermediate match candidate generation circuits 45116 performs calculations with a bit width of 8 bits, and therefore requires an additional circuit including a register capable of holding 128 pieces of data (8 bits x 8 bits). However, the additional circuit area required to generate intermediate match candidates is much smaller than the circuit area that can be reduced. Therefore, the data compression circuit 451 according to the first embodiment can reduce the circuit area.

[0115] Although the description has been given here of a case where the match length calculation circuit 45113 calculates the match length with a bit width of 4 bits and the intermediate match candidate generation circuit 45116 calculates the match length with a bit width of 8 bits, the match length calculation circuit 45113 may calculate the match length using an A-bit register and the intermediate match candidate generation circuit 45116 may calculate the match length using a B-bit register, where B is an integer greater than A.

[0116] (Second embodiment) Generally, in dictionary-based coding, the closer the distance to the latest data unit, the higher the possibility of a match. In dictionary-based coding that generates intermediate match candidates as described in the first embodiment, for example, when a match length that was not selected as an intermediate match candidate in the previous cycle is newly selected as an intermediate match candidate, if the match length calculation circuit has already reached its upper limit, it will be unable to calculate the match length that has been saturated and will result in incomplete compression.

[0117] Therefore, the data compression circuit 451 in the second embodiment calculates the match length with a wide bit width as in the comparative example when the distance is less than a certain value and there is a high possibility of a match, and generates intermediate match candidates as in the first embodiment when the distance is greater than or equal to a certain value.

[0118] Most of the configuration of the data compression circuit 451 according to the second embodiment is similar to that of the data compression circuit 451 according to the first embodiment. The following description will focus on the differences from the data compression circuit 451 according to the first embodiment.

[0119] FIG. 9 is a diagram for explaining the data compression process executed by the data compression circuit according to the second embodiment.

[0120] Each of the match length calculation circuits 45113-1 to 45113-N calculates a match length based on the determination result output by the corresponding match determination circuit 45112-1 to 45112-N. Of the match length calculation circuits 45113-1 to 45113-N in the second embodiment, the match length calculation circuit 45113 corresponding to a distance equal to or greater than the threshold calculates the match length using an A-bit register, and the match length calculation circuit 45113 corresponding to a distance less than the threshold calculates the match length using a B-bit register. B is an integer greater than A. For example, A is 4 and B is 8. Also, FIG. 9 shows a case where the threshold is 17.

[0121] In other words, the match length calculation circuits 45113-1 to 45113-16 in the second embodiment have the same configuration as the match length calculation circuit 45113A in the comparative example, and the match length calculation circuits 45113-17 to 45113-N in the second embodiment have the same configuration as the match length calculation circuit 45113 in the first embodiment.

[0122] Then, each of the match length calculation circuits 45113-1 to 45113-16 transmits the match length stored in its register to the match candidate selection circuit 45114-1 for each cycle. The match length stored in the register is, for example, a match length calculated with a bit width of 8 bits.

[0123] The match candidate selection circuit 45114-1 selects one match candidate from the multiple match lengths it receives. The match candidate selection circuit 45114-1 selects the largest match length as the match candidate. If there are two or more largest match lengths, the match candidate selection circuit 45114-1 selects, for example, the match length with the shortest distance among the largest match lengths as the match candidate. The match candidate selection circuit 45114-1 transmits the selected match candidate to the match candidate selection circuit 45114-2.

[0124] Each of the match length calculation circuits 45113-17 to 45113-N transmits the match length stored in its register to the corresponding intermediate match candidate selection circuit 45115 every cycle. The match length stored in the register is, for example, a match length calculated with a bit width of 4 bits. For example, if the maximum index value N is 2048 and the number M of intermediate match candidate selection circuits 45115 and intermediate match candidate generation circuits 45116 is 127, 16 match length calculation circuits 45113 correspond to one intermediate match candidate selection circuit 45115. Specifically, each of the match length calculation circuits 45113-17 to 45113-32 outputs the match length to the intermediate match candidate selection circuit 45115-1. Although not shown, each of the match length calculation circuits 45113-33 to 45113-64 outputs the match length to the intermediate match candidate selection circuit 45115-2. Furthermore, each of the match length calculation circuits 45113-2033 to 45113-N (2048) outputs a match length to the intermediate match candidate selection circuit 45115-M (127).

[0125] Each of the intermediate match candidate selection circuits 45115-1 to 45115-M selects one match candidate from the input match lengths and outputs the length of the selected match length and the distance corresponding to the match length to each of the intermediate match candidate generation circuits 45116-1 to 45116-M.

[0126] Each of the intermediate match candidate generation circuits 45116-1 to 45116-M generates an intermediate match candidate based on the input match length and distance.

[0127] Then, for each cycle, the intermediate match candidate generation circuit 45116 transmits to the match candidate selection circuit 45114-2 the match length (Length) stored in the register and the distance (X) stored in the register 451161. The match length of the output intermediate match candidate is, for example, the match length calculated with a bit width of 8 bits.

[0128] The match candidate selection circuit 45114-2 selects one match candidate from the match candidates received from the match candidate selection circuit 45114-1 and the multiple intermediate match candidates received from each of the intermediate match candidate generation circuits 45116-1 to 45116-M. The match candidate selection circuit 45114-2 selects, for example, the match candidate that includes the longest match length from among the match candidates and the multiple intermediate match candidates. If there are two or more longest match lengths, the match candidate selection circuit 45114 selects the one that includes the longest match length and corresponds to the shortest distance as the match candidate.

[0129] Then, the match candidate processing circuit 45117 and the non-match input data insertion circuit 45118 generate compressed data based on the match candidate selected by the match candidate selection circuit 45114-2.

[0130] Next, the procedure of the process executed in each cycle in the data compression process in the second embodiment will be described. Fig. 10 is a flowchart showing the procedure of the data compression process executed by the data compression circuit according to the second embodiment. The data compression process starts with the start of a cycle.

[0131] First, one data unit is input to an entry of dictionary buffer 45111 (step S21). For example, the latest data unit is input to the entry corresponding to the index indicating 0.

[0132] Each of the plurality of match determination circuits 45112 determines whether or not the two data units match, and transmits the determination result to the match length calculation circuit 45113 (step S22).

[0133] Each of the multiple match length calculation circuits 45113 calculates a match length based on the judgment result received in S22 (step S23). Here, a match length calculation circuit whose distance is less than the threshold calculates the match length with a wide bit width (e.g., 8 bits). On the other hand, a match length calculation circuit whose distance is equal to or greater than the threshold calculates the match length with a narrow bit width (e.g., 4 bits).

[0134] Here, for the plurality of match length calculation circuits 45113, the procedure proceeds to step S25 or step S26 based on whether the distance corresponding to each match length calculation circuit 45113 is equal to or greater than the threshold value (step S24).

[0135] Each of the two or more match length calculation circuits 45113 whose distance is less than the threshold (No in step S24) transmits the calculated match length to the match candidate selection circuit 45114-1.

[0136] The match candidate selection circuit 45114-1, which has received the match length, selects one match candidate from the received match lengths (step S25). For example, the match candidate selection circuit 45114-1 selects the longest match length from the multiple match lengths it has received as the match candidate. If there are two or more longest match lengths, the match candidate selection circuit 45114-1 selects the match length with the shortest distance from among the longest match lengths as the match candidate. Then, each match candidate selection circuit 45114-1 transmits the selected match candidate to the match candidate selection circuit 45114-2.

[0137] Each of the two or more match length calculation circuits 45113 whose distance is equal to or greater than the threshold value (Yes in step S24) transmits the calculated match length to the corresponding intermediate match candidate selection circuit 45115.

[0138] Each of the multiple intermediate match candidate selection circuits 45115 selects one intermediate match candidate from the multiple received match lengths (step S26). Each of the multiple intermediate match candidate selection circuits 45115, for example, selects the longest match length from the multiple received match lengths as the intermediate match candidate. If there are two or more longest match lengths, the intermediate match candidate 45115 selects the match length with the shortest distance from among the longest match lengths as the intermediate match candidate. Then, each of the multiple intermediate match candidate selection circuits 45115 transmits the selected intermediate match candidate to the intermediate match candidate generation circuit 45116.

[0139] Each of the multiple intermediate match candidate generation circuits 45116 determines whether the distance of the received intermediate match candidate is the same as the distance of the intermediate match candidate in the previous cycle and the match length of the received intermediate match candidate is greater than 0 (step S27).

[0140] If the distance of the received intermediate match candidate is the same as the distance of the intermediate match candidate in the previous cycle and the match length of the received intermediate match candidate is greater than 0 (Yes in S27), the intermediate match candidate generation circuit 45116 increments the match length of the intermediate match candidate by 1 (step S28).

[0141] If the distance of the received intermediate match candidate is different from the distance of the intermediate match candidate in the previous cycle, or if the match length of the received intermediate match candidate is 0 (No in S27), the intermediate match candidate generation circuit 45116 records the match length of the received intermediate match candidate (step S28).

[0142] Then, each of the plurality of intermediate match candidate generation circuits 45116 transmits an intermediate match candidate to the match candidate selection circuit 45114-2.

[0143] The match candidate selection circuit 45114 selects one match candidate from the match candidates received from the match candidate selection circuit 45114-1 in S25 and the intermediate match candidates received from the intermediate match candidate generation circuit 45116 in S28 and S29 (step S30).

[0144] As described above, in the data compression circuit 451 according to the second embodiment, when the distance is less than a certain value, the match length calculation circuit 45113 can calculate the match length with a wide bit width immediately after outputting the judgment result. When the distance is equal to or greater than a certain value, the data compression circuit 451 according to the first embodiment can calculate the match length with a narrow bit width and then generate intermediate match candidates with a wide bit width.

[0145] This avoids a drop in compression performance at close distances where matching is easier. Furthermore, the bit width used in the match length calculation circuit for positions where the distance is greater than a certain value can be halved, which also reduces the circuit area.

[0146] (Third embodiment) In the third embodiment, it is assumed that two or more bytes of data are stored in the dictionary buffer 45111 in each cycle. In other words, two or more data units are input to the dictionary buffer 45111 in one cycle. The data compression circuit 451 according to the third embodiment determines whether each of the multiple data units newly stored in the dictionary buffer 45111 matches a data unit stored in the dictionary buffer 45111 prior to that data unit. The following description assumes that four bytes of data are stored in the dictionary buffer 45111 in each cycle. However, the size of the data stored in the dictionary buffer 45111 in each cycle may be two or three bytes, or may be five or more bytes.

[0147] Most of the configuration of the data compression circuit 451 according to the third embodiment is similar to that of the data compression circuit 451 according to the first embodiment. The following description will focus on the differences from the data compression circuit 451 according to the first embodiment.

[0148] FIG. 11 is a diagram for explaining the data compression process executed by the data compression circuit according to the third embodiment.

[0149] In the dictionary buffer 45111, the latest data unit is stored in the entry corresponding to the index indicating 0. For example, when four data units (i.e., 4 bytes of data) are stored in the dictionary buffer 45111 in each cycle, the data units stored in each entry are shifted to the entry corresponding to the index that is 4 larger. In other words, the data unit stored in the entry corresponding to 0 will be shifted up to the entry corresponding to 4 after one cycle has passed.

[0150] The data compression circuit according to the third embodiment includes a plurality of match determination circuits 45112-01 to 45112-3N. Each of the match determination circuits 45112 determines whether two data units match. The match determination circuit 45112-IJ determines whether the data unit stored in the entry corresponding to I matches the data unit stored in the entry corresponding to J. Specifically, the match determination circuit 45112-01 determines whether the data unit stored in the entry corresponding to 0 matches the data unit stored in the entry corresponding to 1. The match determination circuit 45112-02 determines whether the data unit stored in the entry corresponding to 0 matches the data unit stored in the entry corresponding to 2. The match determination circuit 45112-37 determines whether the data unit stored in the entry corresponding to 3 matches the data unit stored in the entry corresponding to 7.

[0151] Then, each match determination circuit 45112 transmits the determination result to the corresponding match length calculation circuit 45113. Each match determination circuit 45112 transmits the determination result to the match length calculation circuit 45113 corresponding to the same distance. The match determination circuit 45112-IJ corresponds to the distance (JI). Therefore, the match determination circuit 45112-IJ transmits the determination result to the match length calculation circuit 45113-(JI). Specifically, the match determination circuits 45112-01, 12, 23, and 34 transmit the determination result to the match length calculation circuit 45113-1. The match determination circuits 45112-02, 13, 24, and 35 transmit the determination result to the match length calculation circuit 45113-2. The match determination circuits 45112-03, 14, 25, and 36 transmit the determination result to the match length calculation circuit 45113-3. The match determination circuits 45112-04, 15, 26, and 37 send the determination results to the match length calculation circuit 45113-4.

[0152] Each of the match length calculation circuits 45113 calculates a match length based on the judgment results received from the corresponding four match judgment circuits 45112.

[0153] An example of the configuration of the match length calculation circuit 45113 will be described with reference to Fig. 12. Fig. 12 is a diagram showing an example of the configuration of the match length calculation circuit 45113 included in the data compression circuit according to the third embodiment. Although Fig. 12 shows the configuration of the match length calculation circuit 45113-n, the other match length calculation circuits 45113 also have the same configuration as the match length calculation circuit 45113-n.

[0154] The match length calculation circuit 45113 - n includes a register 451131 and a calculation circuit 451132 .

[0155] Register 451131 is a 4-bit register that temporarily stores the most recent match length.

[0156] Based on the input judgment result, the calculation circuit 451132 outputs a match candidate including the distance, the match length, and the latest end of the match range.

[0157] The match length calculation circuit 45113-n receives the determination results Y0 to Y3 of the match determination circuits 45112-0n, 1(n+1), 2(n+2), and 3(n+3). The determination result Y0, which is the determination result of the match determination circuit 45112-0n, indicates 1 if the data unit stored in the entry corresponding to 0 matches the data unit stored in the entry corresponding to n, and indicates 0 if they do not match. The determination result Y1, which is the determination result of the match determination circuit 45112-1(n+1), indicates 1 if the data unit stored in the entry corresponding to 1 matches the data unit stored in the entry corresponding to n+1, and indicates 0 if they do not match. The determination result Y2, which is the determination result of the match determination circuit 45112-2(n+2), indicates 1 if the data unit stored in the entry corresponding to 2 matches the data unit stored in the entry corresponding to n+2, and indicates 0 if they do not match. The judgment result Y3 of the match judgment circuit 45112-3(n+3) indicates 1 if the data unit stored in the entry corresponding to 3 matches the data unit stored in the entry corresponding to n+3, and indicates 0 if they do not match.

[0158] The calculation circuit 451132 of the match length calculation circuit 45113-n performs match length calculation based on the received judgment results Y0 to Y3. The match length calculation by the calculation circuit 451132 will be described with reference to FIG. 13. Below, the input to the calculation circuit 451132 will be represented as input (Y3, Y2, Y1, Y0), and the output returned by the calculation circuit 451132 will be represented as output (Ypos, Len, LenNext). Ypos is the latest end of the match length, Len is the match length, and LenNext is the carried-over match length. The carried-over match length is the match length that can be added to the match length in the next cycle.

[0159] For example, calculation circuit 451132 returns output (0, 0, 0) for input (0, 0, 0, 0). For inputs of other patterns, calculation circuit 451132 returns an output corresponding to the input, as shown in FIG.

[0160] The latest end Ypos of the match range indicates the position corresponding to the latest end of the match length that continues from the match length of the previous cycle among the multiple indexes for which the judgment results have been output in the current cycle.

[0161] LenPre is the match length carried over in the previous cycle. The calculation circuit 451132 obtains the carried over match length LenPre from the register 451131 as needed.

[0162] The value output by the calculation circuit 451132 as the carry-over match length LenNext is stored in the register 451131. The carry-over match length LenNext stored in the register 451131 is used as the carry-over match length LenPre in the next cycle.

[0163] Then, based on the calculation result by the calculation circuit 451132, the match length calculation circuit 45113-n transmits a match candidate including the distance X (= n), the match length Len, and the latest end Ypos of the match length to the corresponding intermediate match candidate selection circuit 45115. Returning to the description of FIG.

[0164] Each of intermediate match candidate selection circuits 45115-1 to 45115-M selects one match candidate from the received match length, and outputs the selected match candidate to each of intermediate match candidate generation circuits 45116-1 to 45116-M.

[0165] Each of the intermediate match candidate generation circuits 45116-1 to 45116-M generates an intermediate match candidate based on the distance X, match length Len, and latest end Ypos of the match length contained in the input match candidate.

[0166] The configuration of the intermediate match candidate generation circuit 45116 will be described with reference to Fig. 14. Fig. 14 is a diagram showing an example of the configuration of an intermediate match candidate generation circuit included in a data compression circuit according to the third embodiment. While Fig. 14 shows an intermediate match candidate generation circuit 45116-1, each of the intermediate match candidate generation circuits 45116-2 to 45116-N has a configuration similar to that of the intermediate match candidate generation circuit 45116-1.

[0167] The intermediate match candidate generation circuit 45116-1 according to the third embodiment includes a register 451161, a selector 451162, a register 451163, and a register 451164.

[0168] Register 451161 is a register that temporarily stores the distance X of the intermediate match candidate. Register 451161 temporarily stores, for example, 4-bit data.

[0169] The selector 451162 selects an update of the intermediate match candidate based on the result of the determination. The selector 451162 determines whether to update the intermediate match candidate based on the result of the determination of whether the distance of the latest intermediate match candidate is the same as the distance of the intermediate match candidate in the previous cycle, and the match length of the intermediate match candidate is greater than 7. Here, the threshold value compared with the match length of the intermediate match candidate may be 4 or greater, which is a value that can determine that the match range is continuous from the previous cycle. If the threshold value is 7, the selector 451162 only needs to determine the value of the most significant bit of the match length newLen. The threshold value may also be a power of 2 and greater than 4.

[0170] Register 451163 is a register that temporarily stores the length of the latest intermediate match candidate. Register 451163 temporarily stores 8-bit data.

[0171] Register 451134 is a register that temporarily stores the latest end of the match length. Register 451164 temporarily stores 2-bit data.

[0172] The intermediate match candidate generation circuit 45116-1 receives the length (newLen), distance (newX), and latest end of the match length (newYpos) of the match candidate from the intermediate match candidate selection circuit 45115-1 every cycle. The match candidate length newLen is 4-bit data. The distance newX is also 4-bit data. The latest end of the match length newYpos is 2-bit data.

[0173] The most recent distance received, newX, is stored in register 451161.

[0174] The latest end of the received match length, newYpos, is stored in register 451164.

[0175] The intermediate match candidate generation circuit 45116-1 determines whether the conditions that newX and X are the same and newLen is greater than 7 are met, based on the length newLen and distance newX of the most recently received intermediate match candidate and the distance X stored in the register 451161.

[0176] If the above condition is not met, the selector 451162 selects newLen and outputs it to the register 451163. As a result, the match length becomes the same value as newLen.

[0177] If the above conditions are met, selector 451162 selects the saturated summed match length. This match length is the match length previously stored in register 451163 plus 4-newYpos. If the match length stored in register 451163 is the upper limit value, the upper limit value is maintained. Then, this saturated summed match length is stored in register 451163.

[0178] Then, the intermediate match candidate generation circuit 45116 transmits the match length (Length) stored in the register 451163, the distance (X) stored in the register 451161, and the latest end of the match length (Ypos) stored in the register 451161 every cycle.

[0179] Returning to the description of Fig. 11, the match candidate selection circuit 45114 selects one match candidate from the plurality of intermediate match candidates received from each of the intermediate match candidate generation circuits 45116-1 to 45116-M. For example, the match candidate selection circuit 45114 selects the intermediate match candidate having the longest match length as the match candidate from among the plurality of intermediate match candidates. If there are two or more longest match lengths, the match candidate selection circuit 45114 selects the intermediate match candidate having the longest match length and corresponding to the shortest distance as the match candidate.

[0180] The match candidate processing circuit 45117 and the non-match input data insertion circuit 45118 generate compressed data based on the match candidates selected by the match candidate selection circuit 45114 .

[0181] Next, the procedure of processing executed in each cycle in the data compression processing in the third embodiment will be described. Fig. 15 is a flowchart showing the procedure of the data compression processing executed by the data compression circuit according to the third embodiment. The data compression processing starts with the start of a cycle.

[0182] First, a plurality of data units are input to the entries of dictionary buffer 45111 (step S31). For example, the latest data unit is input to each of the entries corresponding to indexes indicating 0 to 3.

[0183] Each of the plurality of match determination circuits 45112 determines whether the two data units match, and transmits the determination result to the match length calculation circuit 45113 (step S32). For each of the data units input in S31, it is determined whether it matches a data unit already stored in the dictionary buffer 45111 for each distance.

[0184] Each of the plurality of match length calculation circuits 45113 calculates a match length based on the result of the determination received in S32 (step S33). Each of the plurality of match length calculation circuits 45113 transmits the calculated match length to the corresponding intermediate match candidate selection circuit 45115.

[0185] Each of the multiple intermediate match candidate selection circuits 45115 selects one intermediate match candidate from the multiple received match lengths (step S34). Each of the multiple intermediate match candidate selection circuits 45115, for example, selects the longest match length from the multiple received match lengths as the intermediate match candidate. If there are two or more longest match lengths, the intermediate match candidate 45115 selects the match length with the shortest distance from among the longest match lengths as the intermediate match candidate. Then, each of the multiple intermediate match candidate selection circuits 45115 transmits the selected intermediate match candidate to the intermediate match candidate generation circuit 45116.

[0186] Each of the multiple intermediate match candidate generation circuits 45116 determines whether the distance of the received intermediate match candidate is the same as the distance of the intermediate match candidate in the previous cycle and the match length of the received intermediate match candidate is greater than 7 (step S35).

[0187] If the distance of the received intermediate match candidate is the same as the distance of the intermediate match candidate in the previous cycle and the match length of the received intermediate match candidate is greater than 7 (Yes in S35), the intermediate match candidate generation circuit 45116 increments the match length of the intermediate match candidate by the latest end Ypos of the 4-match range (step S36).

[0188] If the distance of the received intermediate match candidate is different from the distance of the intermediate match candidate in the previous cycle, or if the match length of the received intermediate match candidate is 7 or less (No in S35), the intermediate match candidate generation circuit 45116 records the match length of the received intermediate match candidate (step S37).

[0189] Then, each of the plurality of intermediate match candidate generation circuits 45116 transmits an intermediate match candidate to the match candidate selection circuit 45114 .

[0190] The match candidate selection circuit 45114 selects a match candidate from the received intermediate match candidates (step S38).

[0191] As described above, according to the data compression circuit 451 of the third embodiment, even if two or more data units are input to the dictionary buffer 45111 per cycle, it is possible to realize a configuration in which, as in the first embodiment, match length calculation is performed with a narrow bit width and then intermediate match candidates are generated with a wide bit width.

[0192] In the third embodiment, as in the data compression circuit according to the first embodiment, each of the 2048 match length calculation circuits 45113 performs calculations with a bit width of 4 bits, and therefore requires a circuit including a register capable of holding 2048 pieces of data (4 bits). In addition, each of the 128 intermediate match candidate generation circuits 45116 performs calculations with a bit width of 8 bits, and therefore requires an additional circuit including a register capable of holding 128 pieces of data (8 bits). However, since the bit width of each of the 2048 match length calculation circuits 45113 is halved, the circuit area is significantly reduced, and therefore the data compression circuit 451 according to the third embodiment can reduce the circuit area.

[0193] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0194] 1...information processing system, 2...host, 3...memory system, 4...controller, 5...NAND flash memory, 6...DRAM, 7...bus, 40...internal bus, 41...host interface, 42...CPU, 43...NAND interface, 44...DRAM interface, 45...compression / expansion device, 451...data compression circuit, 452...data expansion circuit, 4511...dictionary coding unit, 4512...entropy coding unit, 45111...dictionary buffer, 45112...match determination circuit, 45113...match length calculation circuit, 45114...match candidate selection circuit, 45115...intermediate match candidate selection circuit, 45116...intermediate match candidate generation circuit, 45117...match candidate processing circuit, 45118...non-match input data insertion circuit.

Claims

1. a data compression circuit that compresses input first data, a buffer having a plurality of registers each storing a one-byte data unit; the plurality of registers include one or more first registers into which data units included in the first data are sequentially stored for each cycle; a plurality of match determination circuits corresponding to distances between the one or more first registers and a register storing a data unit that is stored earlier in the order of storage than the data unit stored in the first register, the match determination circuits determining whether or not the data unit stored in the one or more first registers matches the data unit that is stored earlier in the order of storage; a plurality of match length calculation circuits, each corresponding to one or more of the plurality of match determination circuits, for calculating a match length based on a determination result received from the corresponding one or more match determination circuits; a plurality of intermediate match candidate selection circuits, each of which corresponds to two or more match length calculation circuits among the plurality of match length calculation circuits and selects one match length from two or more match lengths received from the corresponding two or more match length calculation circuits; a plurality of intermediate match candidate generation circuits, each corresponding to a respective one of the plurality of intermediate match candidate selection circuits, for generating intermediate match candidates based on match lengths selected by the corresponding intermediate match candidate selection circuit; each of the plurality of intermediate match candidate generation circuits calculates a match length with a bit width larger than that of the plurality of match length calculation circuits; each of the plurality of intermediate match candidate generation circuits generates an intermediate match candidate by incrementing a match length corresponding to the intermediate match candidate generated in the previous cycle based on the match length when a distance corresponding to the match length received from a corresponding intermediate match candidate selection circuit matches a distance corresponding to the intermediate match candidate generated in the previous cycle and the received match length is greater than a threshold; configured to generate the match length as a new intermediate match candidate if the distance corresponding to the received match length does not match the distance corresponding to the intermediate match candidate generated in a previous cycle or if the received match length is less than or equal to the threshold. Data compression circuit.

2. each of the plurality of match length calculation circuits is configured to correspond to one of the plurality of intermediate match candidate selection circuits; For each of the cycles a first register of one of the buffers receives one data unit; the plurality of match length calculation circuits add 1 to the match length when the determination result indicates a match; resetting the match length if the determination result indicates a mismatch; the plurality of intermediate match candidate generation circuits generate an intermediate match candidate by adding 1 to the intermediate match candidate when the distance corresponding to the received match length matches a distance corresponding to an intermediate match candidate generated in a previous cycle and the received match length is greater than 0; configured to generate the match length as a new intermediate match candidate if the distance corresponding to the received match length does not match the distance corresponding to the intermediate match candidate generated in a previous cycle or if the received match length is zero.

2. The data compression circuit of claim 1.

3. a match candidate selection circuit that selects one intermediate match candidate as a match candidate from the plurality of intermediate match candidates generated by the plurality of intermediate match candidate generation circuits; 3. The data compression circuit according to claim 2.

4. Among the plurality of match length calculation circuits, one or more first match length calculation circuits corresponding to a distance equal to or greater than a first distance are configured to correspond to any of the plurality of intermediate match candidate selection circuits; Among the plurality of match length calculation circuits, one or more second match length calculation circuits corresponding to distances less than the first distance are configured to calculate match lengths using the same bit width as the intermediate match candidate generation circuit; The data compression circuit a first match candidate selection circuit configured to select one match candidate from the one or more match lengths calculated by each of the one or more second match length calculation circuits; a second match candidate selection circuit that selects one match candidate from the selected one match candidate and the plurality of intermediate match candidates generated by the plurality of intermediate match candidate generation circuits; 2. The data compression circuit of claim 1.

5. The buffer receives N data units for each cycle, N is an integer of 2 or more, each of the plurality of intermediate match candidate generation circuits is configured to generate a match length corresponding to the intermediate match candidate based on the selected match length and a most recent end of the match length; 2. The data compression circuit of claim 1.

6. a match candidate selection circuit that selects one intermediate match candidate as a match candidate from the plurality of intermediate match candidates generated by the plurality of intermediate match candidate generation circuits; 6. The data compression circuit according to claim 5.

7. The plurality of intermediate match candidate generation circuits include: if the distance corresponding to the received match length matches the distance corresponding to the intermediate match candidate generated in the previous cycle and the received match length is greater than N, generating an intermediate match candidate by adding a value based on the received match length and the latest end of the received match length to the match length corresponding to the intermediate match candidate generated in the previous cycle; if the distance corresponding to the received match length does not match the distance corresponding to the intermediate match candidate generated in the previous cycle, or if the received match length is less than or equal to N, generating the received match length as a new intermediate match candidate.

6. The data compression circuit according to claim 5.

8. M is greater than N and is a power of 2; The plurality of intermediate match candidate generation circuits include: if the distance corresponding to the received match length matches the distance corresponding to the intermediate match candidate generated in the previous cycle and the received match length is greater than or equal to M, generate an intermediate match candidate by adding a value based on the received match length and the latest end of the received match length to the match length corresponding to the intermediate match candidate generated in the previous cycle; configured to generate the received match length as a new intermediate match candidate if the distance corresponding to the received match length does not match the distance corresponding to the intermediate match candidate generated in a previous cycle or if the received match length is less than M; 6. The data compression circuit according to claim 5.

9. a memory controller including the data compression circuit of claim 1 and a processor; a non-volatile memory that stores data under the control of the memory controller, The data compression circuit a match candidate processing circuit for processing the first data based on the selected match candidate; a non-match input data insertion circuit for inserting non-match data into the processed data; an entropy encoding circuit for generating compressed data by entropy encoding the data into which the non-matched data has been inserted; The memory controller configured to write the generated compressed data to the non-volatile memory; Memory system.

10. A control method for controlling a data compression circuit that compresses input first data, comprising: For each cycle, sequentially storing one or more data units included in the first data in a buffer having a plurality of registers each storing a one-byte data unit; determining whether or not each of the one or more data units matches a data unit stored earlier than each of the one or more data units for each distance in the buffer; calculating a plurality of match lengths for each of the distances based on the result of the determination; selecting a longest match length from a plurality of groups of two or more match lengths from the calculated plurality of match lengths; generating intermediate match candidates by incrementing match lengths corresponding to the intermediate match candidates generated in the previous cycle based on the selected match lengths, if the corresponding distances of the selected match lengths match the distances corresponding to the intermediate match candidates generated in the previous cycle and the selected match lengths are greater than a threshold; generating each of the selected match lengths as new intermediate match candidates if the corresponding distance does not match a distance corresponding to an intermediate match candidate generated in a previous cycle or if the selected match length is less than or equal to the threshold. Control method.

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