Clock time difference measurement device and method, and signal generation device and signal generation method

Abstract

To measure a time difference between two clocks under test with high precision using the D-DMTD method even when the frequency of one of the two clocks under test is an integer multiple of the other.SOLUTION: A clock time difference measurement device includes: a first sampling circuit 10 that samples a first clock on the basis of an offset clock to generate a first sampling signal; a second sampling circuit 20 that samples a second clock on the basis of the offset clock to generate a second sampling signal; a phase difference overflow detection circuit 30 that detects a phase difference overflow between the first sampling signal and the offset clock and outputs a third sampling signal; and a signal division / phase difference overflow detection circuit 40 that divides the second sampling signal into z pieces to generate z divided signals, detects a phase difference overflow between the divided signals and the offset clock to generate a fourth sampling signal, and further combines the fourth sampling signals to generate a fifth sampling signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a clock time difference measurement device and method for measuring the time difference between two clocks, and a signal generation device and signal generation method. [Background technology]

[0002] Various methods have been proposed to measure the time difference between two clocks under test, and ever higher accuracy is required. Examples of existing methods include the real-time sampling method, the delay insertion method, and the D-DMTD (Digital Dual Mixer Time Difference Method).

[0003] The real-time sampling method is a technique in which a sampling clock with a significantly higher frequency than the two clocks under test is used to sample each of the clocks under test, and the time difference is measured using the results. The measurement resolution of the time difference depends on the sampling frequency of the sampling clock. For example, if a resolution of 10 μs is required, a sampling frequency of 100 kHz is sufficient, but if an ultra-high resolution of 10 ps is required, a sampling frequency of an extremely high frequency of 100 GHz is required. Clock generators and samplers with a high frequency of 100 GHz are expensive.

[0004] The delay insertion method generates delayed clock B' by delaying one of two clocks A and B (for example, B) using a variable delay device or other variable delay means. Then, the logical value of delayed clock B' is continuously sampled at the timing of the rising edge of clock A. The result is a constant value of either "L" or "H." If the delay amount of the delay means is gradually increased, the sampled logical value will invert at a certain timing. In particular, the time difference between the two clocks A and B can be calculated using the delay amount setting at the moment the logical value inverts from "H" to "L."

[0005] The delay insertion method can be used not only when the frequencies of the two clocks A and B under test match, but also when one has a frequency that is an integer multiple of the other. However, there is a problem in that the measurement resolution of the time difference depends on the delay setting resolution of the delay means. Also, if the frequency of the clock under test is low (the period is large) compared to the maximum delay of the variable delay insertion means, it becomes difficult to measure the time difference.

[0006] The D-DMTD method measures the time difference between clocks A and B under test by continuously sampling the logic values ​​of clocks A and B at the rising edges of offset clock C, which has a frequency slightly different from that of clocks A and B under test. The D-TMTD method can measure the time difference between clocks A and B under test with high resolution without using an extremely high-frequency sampling clock like that used in the real-time sampling method, but it has the problem that it can only be used when the frequencies of the two clocks A and B under test are the same. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] Wlostowski, T. Precise time and frequency transfer in a White Rabbit network. Master's thesis, Warsaw University of Technology, 2011. Summary of the Invention [Problem to be solved by the invention]

[0008] The present invention provides a clock time difference measurement device and method, as well as a signal generation device and signal generation method, that can measure the time difference between two clocks under test with high accuracy using the D-DMTD method, even if the frequency of one of the clocks under test is an integer multiple of the frequency of the other. [Means for solving the problem]

[0009] A clock time difference measurement device according to the present invention measures the time difference between a first clock and a second clock, wherein the second clock has a frequency that is 1 / z (z is an integer equal to or greater than 1) of the frequency of the first clock. This device includes: a first sampling circuit that samples the first clock based on an offset clock that has a frequency slightly different from that of the first clock to generate a first sampling signal; a second sampling circuit that samples the second clock based on the offset clock to generate a second sampling signal; a phase difference overflow detection circuit that detects a phase difference overflow between the first sampling signal and the offset clock and outputs a third sampling signal; a signal division / phase difference overflow detection circuit that divides the second sampling signal into z divided signals to generate z divided signals, detects a phase difference overflow between the divided signals and the offset clock to generate a fourth sampling signal, and further combines the fourth sampling signals to generate a fifth sampling signal; and a time difference counter that counts the time difference between the first clock and the second clock based on the third sampling signal and the fifth sampling signal.

[0010] In a preferred configuration example, the signal division / phase difference overflow detection circuit may further include a counter that counts a count value k that indicates the number of rising edges of the offset clock. One of the z divided signals corresponding to the remainder obtained by dividing the count value k by z may be input to the time difference counter.

[0011] As another preferred configuration example, the signal division / phase difference overflow detection circuit may further include a counter that counts a count value k indicating the number of rising edges of the offset clock, and a control signal generation unit that generates z control signals whose logic changes depending on the remainder when the count value k is divided by z. In this case, one of the z control signals is set to a first logic, and the remaining z-1 control signals are set to a second logic. The signal division / phase difference overflow detection circuit generates the fourth sampling signal based on a divided signal corresponding to the control signal set to the first logic. The signal division / phase difference overflow detection circuit may further include z latch circuits that latch the z divided signals, and z phase difference overflow detection circuits that are provided corresponding to the z latch circuits and detect a phase difference overflow between the divided signal from the latch circuit and the offset clock. The fourth sampling signal may be generated based on a signal from at least one of the z latch circuits and the z phase difference overflow detection circuits.

[0012] A clock time difference measurement method according to the present invention is a clock time difference measurement method for measuring the time difference between a first clock and a second clock. The second clock has a frequency that is 1 / z (z is an integer equal to or greater than 1) of the frequency of the first clock. The clock time difference measurement method includes the steps of: sampling the first clock based on an offset clock whose frequency is slightly different from that of the first clock to generate a first sampling signal; sampling the second clock based on the offset clock to generate a second sampling signal; detecting an overflow of a phase difference between the first sampling signal and the offset clock to generate a third sampling signal; dividing the second sampling signal into z divided signals to generate z divided signals, detecting an overflow of a phase difference between the second sampling signal and the offset clock to generate a fourth sampling signal, and combining the fourth sampling signals to generate a fifth sampling signal; and counting the time difference between the first clock and the second clock based on the third sampling signal and the fifth sampling signal. [Effects of the Invention]

[0013] According to the present invention, even if the frequency of one of two clocks under measurement is an integer multiple of the frequency of the other, the time difference between the clocks under measurement can be measured with high precision using the D-DMTD method. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a block diagram illustrating the configuration of a clock time difference measurement device according to an embodiment of the present invention. [Figure 2] 2 is a block diagram illustrating an example of the configuration of a signal division / phase difference overflow detection circuit 40. FIG. [Figure 3] 1 is a block diagram showing a specific example of the circuit configuration of a signal division / phase difference overflow detection circuit 40. FIG. [Figure 4]FIG. 4 is a schematic diagram illustrating that the configuration of FIG. 3 can be applied to measuring the time difference between clocks A (frequency fA) and B (frequency fB=fA / z (z is an integer equal to or greater than 1)). [Figure 5] 10 is a schematic diagram illustrating a method for measuring a time difference by detecting a change in the phase difference pCB. FIG. [Figure 6] 10 is a schematic diagram illustrating a method for measuring a time difference by detecting a change in the phase difference pCB. FIG. [Figure 7] FIG. 1 is a block diagram illustrating the configuration of a conventional clock time difference measurement device using the D-DMTD method. [Figure 8] FIG. 1 is a schematic diagram illustrating the principle of a conventional clock time difference measurement device using the D-DMTD method. [Figure 9] FIG. 1 is a schematic diagram illustrating the principle of a conventional clock time difference measurement device using the D-DMTD method. [Figure 10] 1 is a schematic diagram illustrating a counter to which the clock time difference measurement device of the present embodiment can be applied; [Figure 11] 1 is a schematic diagram illustrating a counter to which the clock time difference measurement device of the present embodiment can be applied; DETAILED DESCRIPTION OF THE INVENTION

[0015] The present embodiment will now be described with reference to the accompanying drawings. The accompanying drawings illustrate embodiments consistent with the principles of the present disclosure. However, these drawings are intended to aid in understanding the present disclosure and are not intended to limit the present disclosure in any way. The description in this specification is merely exemplary and does not limit the scope or application of the present disclosure. The present embodiment has been described in sufficient detail to enable those skilled in the art to implement the present disclosure, but it should be understood that other implementations and forms are possible, and that changes in configuration and structure and substitutions of various elements are possible without departing from the scope and spirit of the technical concept of the present disclosure. Therefore, the following description should not be construed as being limited thereto.

[0016] The clock time difference measurement device according to this embodiment measures the time difference between clocks under test using the D-DMTD method. However, by employing a configuration to be described later, the device according to this embodiment is capable of measuring not only when the clocks under test have the same frequency, but also when one frequency is an integer multiple of the other. To explain this point, we will first explain a clock time difference measurement device using the conventional D-DMTD method, and then explain the clock time difference measurement device according to this embodiment.

[0017] [Clock time difference measurement device using conventional D-DMTD method] 7, the configuration of a clock time difference measurement device 1C will be described using the conventional D-DMTD method. This device 1C is configured with an offset clock generation unit 5, a first sampling circuit 10, a second sampling circuit 20, a first phase difference overflow detection circuit 30, a second phase difference overflow detection circuit 40C, and a time difference counter 50, and is configured to measure the same frequency f A , f B (f A =f B ), with the same period T A , T B (T A =T B , T A =1 / f A , T B =1 / f B ) to measure the time difference between test clocks A and B.

[0018] The offset clock generator 5 receives the clock A to be measured and generates a clock having a frequency f A A frequency slightly shifted from f C (frequency f B The frequency f is slightly shifted from the frequency z times C ) is generated. The offset clock C has a frequency f C For example, f C =f A×N / (N+1) (N is an integer called the vernier constant). The vernier constant N can be freely determined by the user. The larger the vernier constant N, the smaller the frequency difference between the clock under test A and the offset clock C. The offset clock generation unit 5 can generally be realized using a common technique such as a Phase Locked Loop (PLL). The clock under test A is sometimes called the reference clock.

[0019] The first sampling circuit 10 and the second sampling circuit 20 sample the clocks A and B under test using the offset clock C as the sampling clock, and generate a beat signal A' (with a frequency |f C -f A |), B'(frequency |f C -f B The first sampling circuit 10 and the second sampling circuit 20 can be configured using, for example, a D flip-flop circuit (D-FF) built into an electronic device such as an FPGA, but are not limited to this.

[0020] The first phase difference overflow detection circuit 30 detects a phase difference overflow between the beat signal A' and the offset clock C, and outputs a pulse signal A" that rises at the detection timing. The detection of a "phase difference overflow" will be described in detail later, but it means detecting the timing when the phase difference between two signals crosses the boundary between the periods of one signal. Furthermore, the second phase difference overflow detection circuit 40C detects an overflow of the phase difference between the beat signal B' and the offset clock C, and outputs a pulse signal B" that rises at the detection timing. The first phase difference overflow detection circuit 30 and the second phase difference overflow detection circuit 40C can also have a function of removing glitch noise contained in the beat signal A' or B'. When glitch noise is superimposed on the beat signals A' and B', it may be impossible to detect the timing of the phase difference overflow of the beat signals A' and B'. In such cases, the glitch noise removal function becomes effective. The phase difference overflow detection circuits 30 and 40C can be configured as digital circuits, and therefore can be implemented using various D-FFs, LUTs, and the like that are built into electronic devices such as FPGAs.

[0021] Finally, the time difference counter 50 receives the pulse signals A″ and B″ as inputs, measures the count difference at which the rising edges of the respective signals occur, and calculates the time difference d between the two clocks A and B to be measured based on the results. BA The time difference counter 50 can also be configured as a digital circuit, and therefore can be implemented using various D-FFs, LUTs, and the like built into electronic devices such as FPGAs.

[0022] The details of the D-DMTD method are explained below. As shown in Figure 8, the time of any rising edge of the offset clock C is defined as t=0. At this time, the clock waveforms of the measurement target clocks A, B, and offset clock C are respectively expressed as v A (t), v B (t), v C If (t), it can be expressed as follows:

[0023]

number

[0024] However, T A , T B , T C are the periods of the clock under test A, the clock under test B, and the offset clock C (T A =1 / f A , T B =1 / f B , T C =1 / f C ). Also, d AC is the initial time difference of clock A relative to offset clock C, and d BC is the initial time difference of clock B relative to offset clock C.

[0025] Here, a variable (count value) k is defined as a variable indicating the number of rising edges of the offset clock C. As shown in FIG. 8, the number k of the rising edge of the offset clock C at t=0 is set to k=0, and subsequent rising edges are also assigned (labeled) with k in ascending order. The time t and the variable k are expressed as t=kT C The relationship is as follows: The values ​​χ of the measured clocks A, B, and offset clock C at each k A (k), χ B (k), χ C (k) can be expressed as the following equation [Equation 2].

[0026]

number

[0027] Also, the time t elapsed from the time t=0 of the kth rising edge of clocks A, B, and C is AC (k), t BC (k), t CC (k) can be expressed by the following equation [Equation 3].

[0028]

number

[0029] Also, the phase difference p of clock A and B with respect to the offset clock C CA (k), p CB (k) can be expressed by the following formula [Equation 4]. Note that mod(a, b) ∈ R is a function that returns r satisfying a = qb + r (q ∈ Z, 0 ≤ r < b).

[0030]

Equation

[0031] Thus, the values χ of various clocks at each count value k can be calculated as in the following formula [Equation 5]. A (k), χ B (k), χ C (k). χ A (k), χ B (k) represents the sampling value when the measured clocks A and B are sampled at the rising edge of the k-th offset clock C.

[0032]

Equation

[0033] As shown in FIG. 9, the phase difference p between clock A and the offset clock C CA increases by T A / N each time the number of k increases. However, the phase difference p CA does not exceed the period T A of clock A, and is set to a value of 0 ≤ p CA < T A . The beat signal A’ is a signal that rises when the phase difference p CA crosses the boundary of the period T A (the phase difference overflows) (in the example of FIG. 9, the rise of the beat signal A’ occurs at p CA (11)). Also, when the phase difference p CA exceeds the period TA Crossing the boundary is called phase difference overflow.

[0034] In this way, beat signals A' and B' are signals with a period N times that of clocks A and B, so by measuring the time difference between beat signals A' and B' using clock C, it is possible to measure the time difference between the original clocks A and B. This is further explained using mathematical formulas below.

[0035] It is calculated which m-th rising edge of the beat signals A' and B' corresponds to which k-th rising edge of the offset clock C. To do this, it is calculated which rising edges of the clock C sandwich the rising edge of the beat signal A'. A (k)=1 and χ A The variable k for which (k-1)=0 holds true satisfies the following equation [Mathematical formula 6].

[0036]

number

[0037] If k0 is the timing at which the first rising edge (m=0) of beat signal A' is detected, then the detection of the mth rising edge of beat signal A' can be said to occur at the timing k=k0+mN. Therefore, if k0 is found, the relationship between m and k can be found. Solving the inequality in [Equation 7] below for l, we obtain l>Nd AC / T A The smallest l that satisfies this condition can be found and this smallest l can be identified as k0. k0 can be calculated as shown in the following [Equation 8], and since k = k0 + mN, it can be calculated as shown in [Equation 9].

[0038]

number

number

number

[0039] This k is k A (m) can be defined as follows. Similarly, for beat signal B', k B The phase difference overflow detection circuits 30 and 40C can calculate the phase difference χ sampled by the sampling circuits 10 and 20. A , χ B Based on k A (m), k B Calculate and output (m).

[0040] The above is an explanation using mathematical formulas, but in an actual circuit, the sampled χ A , χ B The value of is monitored for each variable (count value) k, and χ A (k)=1 and χ A By sending a pulse every time (k-1)=0 is satisfied, k A (m) equivalent signal A” is output. B The same is true for signal B" equivalent to (m). Although not included in the above equation, in an actual circuit, the signal sampled by the sampling circuit may contain glitch noise. The phase difference overflow detection circuits 30 and 40C can remove this glitch noise. The signal k obtained after removing the glitch noise is A (m), k B Based on (m), the time difference between clocks A' and B' can be calculated. B (m), k A Subtracting (m) gives the following equation [Number 10]:

[0041]

number

[0042] Therefore, the time difference d between the clocks A and B under test is BA is calculated using the following equation [Equation 11].

[0043]

number

[0044] The above [Equation 10] and [Equation 11] are expressed as follows: In a clock time difference measurement device using the conventional D-DMTD method, the frequencies f A , f B On the other hand, this embodiment is also applicable when the frequency of one of the clocks A and B to be measured is an integer (z) times that of the other.

[0045] The configuration of the clock time difference measurement device of this embodiment will be described with reference to Figure 1. The same components as those in the conventional clock time difference measurement device are given the same reference numerals in Figure 1, so duplicated explanations will be omitted below. Here, when the frequency of the clock A to be measured is f A and the frequency of the clock B under test is f B is f A Here, the case where the value is 1 / z (z is an integer of 1 or more) will be explained as an example.

[0046] As shown in FIG. 1, the clock time difference measurement device 1 of this embodiment includes a signal division / phase difference overflow detection circuit 40 instead of the phase difference overflow detection circuit 40C. The other configurations are the same as those of the conventional device 1C. This signal division / phase difference overflow detection circuit 40 detects a frequency f A frequency f at 1 / z (z is an integer greater than or equal to 1) B (=f A The clock signal B' is sampled using an offset clock C and has a frequency of 1 / z. The signal B' is then divided into z signals, and a phase difference overflow between the z divided signals and the offset clock C is detected. A pulse signal corresponding to the detected signal is generated, and the pulse signals are then combined to output a signal B".

[0047] An example of the configuration of this signal division / phase difference overflow detection circuit 40 will be described with reference to FIG. 2. The signal division / phase difference overflow detection circuit 40 includes a signal division unit 41, z phase difference overflow detection circuits 42(0) to 42(z-1), and a signal merging unit 43. As will be described later, when z is 2 or greater, the signal B' output from the second sampling circuit 20 is a signal to which the caliper measurement principle cannot be applied and cannot be directly input to the phase difference overflow detection circuit. For this reason, in this embodiment, the signal division / phase difference overflow detection circuit 40 divides this signal B' into signals to which the caliper measurement principle can be applied, performs a phase difference overflow detection operation on the divided signals to generate pulse signals, and then performs an operation of combining the pulse signals.

[0048] Specifically, the signal dividing unit 41 of the signal dividing / phase difference overflow detection circuit 40 divides the signal B' into z signals B' in accordance with a rule to be described later. y=0 , B' y=1 , …, B' y=z-1 The individual signals B' after division are y=0 , B' y=1 , …, B' y=z-1 are signals to which the measurement principle of a vernier caliper can be applied, and therefore can be input to the phase difference overflow detection circuits 42(0), 42(1), ..., 42(z-1) respectively to be used for detecting phase difference overflow. Signal B" as the result of phase difference overflow detection y=0 , B” y=1 , …, B” y=z-1 are combined (merged) in the signal merging unit 43 to output a pulse signal B". Then, regardless of the value of z, this pulse signal B" has the same properties as the signal A" derived from the clock A, and can be input to the time difference counter 50 in the subsequent stage. Details of the signal processing here will be described later. Note that the signal division / phase difference overflow detection circuit 40 can also be provided with a glitch noise removal function, similar to the phase difference overflow detection circuit 40C.

[0049] 3 shows a specific example of the configuration of the signal division / phase difference overflow detection circuit 40 shown in the block diagram of FIG. 2. As an example, the signal division / phase difference overflow detection circuit 40 includes z chip-enable D flip-flop circuits 41 (41(0) to 41(z-1)), z phase difference overflow detection circuits 42 (42(0) to 42(z-1)), an OR gate 43, a control signal generation unit 44, and a counter 45. The z D flip-flop circuits 41 (41(0) to 41(z-1)), the control signal generation unit 44, and the counter 45 correspond to the signal division unit 41 in FIG. 2. The z phase difference overflow detection circuits 42(0) to 42(z-1) correspond to the z phase difference overflow detection circuits 42(0) to 42(z-1) in FIG. 2. The OR gate 43 corresponds to the signal merge unit 43 in FIG. 2. The z circuits may be collectively referred to simply as "D flip-flop circuits 41" and "phase difference overflow detection circuits 42."

[0050] The number z of D flip-flop circuits 41 and phase difference overflow detection circuits 42 is determined by the frequency f A and the frequency f of the clock B under test B It is determined by the relationship (1 / z) between the frequency f B =f A / z clock B as well as frequency f B =f A , f B =f A / 2, f B =f A / 3, …, f B = 1 / (z-1), the clock B under test can also be measured. In this case, some of the D flip-flop circuits 41 and phase difference overflow detection circuits 42 are set to an inactive state, and the remaining D flip-flop circuits 41 and phase difference overflow detection circuits 42 are operated, thereby making it possible to measure the time difference between the clocks A and B to be measured.

[0051] Counter 45 is an unsigned counter that is set to its maximum value initially and counts up by one at each rising edge of offset clock C. The first rising edge of offset clock C causes count value k of counter 45 to become k=0 (due to overflow). In other words, the rising edge that increments count value k of counter 45 to k=0 can be labeled as k=0.

[0052] Thereafter, the count value k of the counter 45 is counted up as k=1, 2, 3, ... at each rising edge of the offset clock C, and similarly, the rising edges are labeled as k=1, 2, 3, .... In this way, the counter 45 can label the rising edges of the offset clock C with the count value k. The count value k of the counter 45 is used in the control signal generator 44 at the subsequent stage. The control signal generator 44 generates a control signal, c, in accordance with the count value k. y=0 (k), …, c y=z-1 (k) to generate the control signal c y=i (k) (i=0 to z-1) are generated according to the following rule: For each k, z control signals c y=i (k) becomes 1 (first logic), and the other z-1 control signals c y=i (k) becomes 0 (second logic).

[0053]

number

[0054] The D flip-flop circuit 41(i) (i=0 to z-1) receives the offset clock C as a clock, and the input terminal D receives the signal B′ (=χ B (k)) is input, and the signal B' is output from the output terminal Q. y=i Furthermore, the chip enable terminal CE outputs the control signal c as a chip enable signal. y=iThe D flip-flop circuit 41(i) reads the input signals from the chip enable terminal CE and the input terminal D at every rising edge of the offset clock C, and outputs the output signal Q(k) (=B') according to the rule shown in the following [Equation 13]. y=i =χ B,y=i Update (l).

[0055]

number

[0056] That is, the D flip-flop circuit 41(i) outputs the immediately preceding chip enable signal C at each rising edge of the offset clock C. y=i The value of (k-1) is checked, and if it is 1 (first logic), the value of the output signal Q(k) is updated to the value of the previous input signal D(k-1), and if it is 0 (second logic), the value of the output signal Q(k) remains unchanged as the original output signal Q(k-1) regardless of the input signal D.

[0057] The phase difference overflow detection circuit 42(i) (i=0 to z−1) generates a control signal c y=i The value of (k) is checked, and only if it is 1 (first logic), the output signal B' is generated. y=i =χ B,y=i (l) is taken inside. As shown in the above [Equation 13], the control signal c y=i (k) becomes 1 (first logic) only when the count value k satisfies k=zl+i (l is an integer). Therefore, even if the driving clock of 42(i) of the phase difference overflow detection circuit is the offset clock C, B,y=i Then, by detecting a phase difference overflow in each phase difference overflow detection circuit 42(i), a pulse signal B" y=i is obtained.

[0058] The OR gate 43 outputs these pulse signals B" y=i(i=0 to z-1) and outputs a composite signal B″. The z input signals of the OR gate 43 are the pulse signal B″ obtained by the phase difference overflow detection circuit 42. y=i (l) are input to the OR gate 43. Then, the OR gate 43 outputs the input B y=i (l) is calculated and output. At this time, when focusing on an arbitrary l, z pulse signals χ B,y=i At most, only one of (l) will be 1. In other words, the pulses do not overlap, so the result of ORing z signals and the pulse signal B y=i In this way, the z signals B" are generated by arranging the z signals B" in time series order and synthesizing them into a single pulse signal. y=i By merging these signals, a single synthesized pulse signal B″ can be obtained. The resulting pulse signal B″ can be used as an input to the time difference counter 50, regardless of the value of z.

[0059] Next, referring to FIG. 4, the configuration of FIG. 3 is a clock A under test (frequency f A ) and B(frequency f B =f A / z (z is an integer equal to or greater than 1)). Figure 4 shows the case where z=3 and the frequency f B =f A / 3 clock B with one period T B The bottom row of Figure 4 shows a clock that is coherent with clock B and has a frequency of f ZB =3×f B =f A , period T 3B =T B The clock zB shown in the upper row, Row 1, and the middle row, Row 2, has a period of T B However, this period T B The time is divided into three parts, and the parts are shown as Area 0, 1, and 2 in the order of time. The length of each part is T B / 3.

[0060] Frequency f of clocks A and B to be measured A , f B is f B =f A / z (z is an integer greater than or equal to 1), the frequency f B z times the frequency zf B =f A If we consider a clock zB that has a coherent relationship with clock B, and if we can practically measure the time difference between clock A and clock zB, then we can also measure the time difference between clocks A and B based on that. In the clock time difference measurement device 1 of this embodiment, a virtual clock zB (with a frequency zf B =f A ) to generate the frequency f A , f B is f B =f A / z (z is an integer equal to or greater than 1), the time difference between the clocks A and B to be measured can be measured. The above operations by the counter 45 and the control signal generator 44 result in a state equivalent to generating this virtual clock zB.

[0061] The period T of the measured clocks A and B and the offset clock C A , T B , T C The relationship can be expressed as follows:

[0062]

number

[0063] Substituting this into [Equation 3], we obtain the following [Equation 15].

[0064]

number

[0065] Here, the phase difference p of clock B with respect to offset clock C is CBWhen the change in the count value k is calculated, the phase difference p CB The change in can be expressed as follows [Equation 16].

[0066]

number

[0067] The first term of this [Equation 16] (T B / z), when z≠1, the phase difference p CB does not increase. The vernier constant N determines the granularity of the measurement, but when z≠1, that granularity is lost and the caliper measurement principle does not work properly, so the D-DMTD method cannot be applied. On the other hand, if the increment of the count value k is set to z (instead of 1), the amount of change in the phase difference can be expressed by the following equation [Equation 17]. As shown in [Equation 17], the phase difference p for each increment z CB By focusing on the change in the phase difference p CB Since the time difference between clocks A and B increases, the measurement principle of a caliper can be applied to measure the time difference between clocks A and B. The calculation of [Equation 17] is performed by the control signal generator 44 of the clock time difference measurement device shown in FIG. 1, which generates the control signal c shown in [Equation 12] according to the count value k of the counter 45. y=i This can be done by outputting (k).

[0068]

number

[0069] Looking at the upper row 0 of Figure 4, the initial phase difference between clock B and offset clock C is p CB (0), and then, as the count value k increases, the phase difference becomes T B / 3+T B / 3N, and the phase difference p CB (1), p. CB (2)... are determined in order (thick dividing lines in Figure 4).

[0070] On the other hand, the period T of the clock zB shown in the lower part of Fig. 3B is T 3B =T B / 3, and clock zB is coherent with clock B, so t0=t BC (0)=t 3BC (0), and the initial phase difference of each is p CB (0)=mod(t0, T B ), p C3B (0)=mod(t0, T 3B ) Also, T 3B <T B Therefore, p C3B (0)≦p CB (0) holds. In the case of Figure 4, p CB (0) <T B / 3, so p C3B (0)=p CB (0) and the initial phase difference between clock B and clock zB is the same.

[0071] The change in phase difference at every z interval shown in [Equation 17] can be confirmed by looking at each area vertically in Figure 4. For example, in Area 0, p CB (0), p CB As shown in (3), we can see the phase difference where k is a multiple of 3. Similarly, in Area 1, we can see the phase difference where k is (multiple of 3 + 1), and in Area 2, we can see the phase difference where k is (multiple of 3 + 2).

[0072] Period T of clock zB 3B By knowing the timing when the right end of B In the example of Figure 4, the period T of clock zB is first detected. 3B The right end of is exceeded at the timing of k=3 (p C3B (3)) This timing can be detected from only one of the information of areas Area0 to Area2.

[0073] If we focus only on the area Area0 (looking at Area0 vertically), the phase difference in Area0 is T 3B / N=T B / 3N, so the phase difference at the left end of Area 0 (p CB The phase difference (in phase with (3)) will return to the same value when the value of k is increased by another 3N. This timing can be detected by monitoring the change in the phase difference only when the remainder when the count value k is divided by 3 is 0. In Area 1, this timing can be detected by monitoring the change in the phase difference only when the count value k is divided by 3 is 1. In Area 2, this timing can be detected by monitoring the change in the phase difference only when the remainder when the count value k is divided by 3 is 2. In this way, in any of Areas 0 to 2, the phase difference p CB is the period T B By detecting the timing at which the time exceeds k, the time difference between clocks A and B can be detected. This detection operation is equivalent to detecting a change in the phase difference of the virtual clock zB for each increment of k=1 (one-to-one correspondence).

[0074] Next, a change in the phase difference will be described with reference to Fig. 5. In Fig. 5, the change in the phase difference for each of the areas Area0 to Area2 is shown in a plurality of columns. In Fig. 5 as well, the initial phase difference p CB (0) and the initial phase difference p of clock zB C3B (0) is consistent. The phase difference change for each area Area0 to Area2 is as shown in [Equation 16], where the value of k is z=3 and the phase difference is T B / N=zT A The initial phase difference between Area1 and Area2 is p CB (1), p. CB (2), and the value of k is z=3, and the phase difference is T B / N.

[0075] In the D-DMTD method, the phase difference between the measured clock B and the offset clock C is B It is important to capture the timing when the period TB the right end of, or period T 3B In Figure 5, the phase difference is B The first time that the number exceeds k is when k=2(p C3B (2) and p CB This is the timing following (2). According to this embodiment, this timing can be detected exactly from the phase difference change in one of the areas Area0 to Area2.

[0076] An observation window is set for the signal zB. The observation window is set to the period T 3B =T B The observation window is used to observe clock B by dividing it into 3 / 3. One observation window contains one piece of phase difference information p CB For example, in FIG. 5, the observation window for the area Area2 includes only the phase difference p CB Only (2) is included, and other phase difference information is not included.

[0077] When observing an increase in phase difference with each increase in k, the observation window moves downward and to the right with each increase in k. CB (0)=p C3B (0), so p C3B (k)=mod(p CB (k), T 3B ) holds. This means that the change in the phase difference within the observation window is the phase difference p C3B This shows that the increase in phase difference is consistent with the increase in (k). In other words, we can say that the following [Property 1] holds true for the increase in phase difference.

[0078] [Property 1] The phase difference p between signal zB and offset clock C CzB (k) and the phase difference mod(p CzB (k),T ZB ) have the same timing of phase difference overflow (one-to-one correspondence).

[0079] When detecting the timing of phase difference overflow, the phase difference p CB It is preferable to consider the timing when p reaches the rightmost end of the observation window. CB (2) has reached the rightmost end of the observation window. In signal zB, a phase difference overflow is detected at the next timing k=3. CB Since the area at the right end of the observation window is Area2, the phase difference p CB Monitor changes in T B The timing when the phase difference p CB The change in x B Of (k), only the value where the remainder when k is divided by 3 is extracted. B,y=2 This can be detected by monitoring when the value changes from 0 to 1.

[0080] The actual detection is at the timing of k=5, and the phase difference p CB However, this delay is small enough that it does not cause any problems in terms of detection accuracy when detecting the time difference between clocks A and B. Similarly, the phase difference p C3B The timing of overflow for k=8, 13, 18, ... can also be detected by observing the areas Area0 to 2. In the example of FIG. 5, the timing of overflow can be detected by observing the area Area2 for k=3, the area Area1 for k=8, the area Area0 for k=13, and the area Area2 for k=18. In this way, by observing the areas Area0 to 2, the timing of overflow can be detected by observing the area Area2 for k=3, the area Area0 for k=8, and the area Area2 for k=13. C3B All overflows of

[0081] In the example in Figure 5, p C3B (0)=p CB The condition was to set the virtual signal zB so that it becomes (0), but in reality, C3B (0) <T 3B <p CB(0) is also possible. In this case, as shown in Figure 6, R = mod(p CB (0), T 3B )=p C3B (0) is set as the correction value R, and the initial phase difference p CB By adjusting the correction value R, the first observation window is set to the area Area1 (or Area2) instead of the area Area0, and the phase difference p CB By observing the change in the phase difference, it is possible to monitor the timing at which the change in the phase difference exceeds the rightmost end of the observation window.

[0082] In FIG. 6, a situation is considered in which the phase difference in the observation window reaches the rightmost end of the observation window, similar to the case in FIG. 5. In the example of FIG. 6, a situation occurs in which the phase difference reaches the rightmost end of the observation window set in area Area0. However, even if the overflow of the change in the phase difference in area Area0 is monitored, this timing cannot be detected. This is because the phase difference p CB (2) to p CB In the change of (5), the period T of clock B B This is because it does not cross the rightmost boundary of

[0083] However, going back from the timing when the phase difference reaches the rightmost end of the observation window, there is always a time within z-1=2 that is equal to the period T B There is a timing when the boundary of the observation window is crossed. The total length of the observation window is T B On the other hand, the phase difference p CB T B If the boundary is crossed, the phase difference within the observation window will reach the rightmost end within the timing of z-1 = 2. This fact and [Property 1] also confirm the following [Property 2].

[0084] [Property 2] Phase difference p of signal zB CzB The phase difference overflow of (k) and the phase difference overflow of the entire area Area0, ..., Areaz-1 correspond one-to-one.

[0085] Finally, we will discuss the timing error of phase difference overflow. If the timing when the phase difference reaches the rightmost end of the observation window is count value k, then the phase difference overflow of signal zB occurs at k+1. On the other hand, the corresponding phase difference overflow in Area i (i = 0 to z-1) occurs at k-l+z (0 ≦ l ≦ z-1). Therefore, the following property 3 ultimately holds true.

[0086] [Property 3] The overflow of the phase difference of Area i (i = 0 to z-1) is the phase difference p CzB It is delayed by a maximum of z-1 timings from the overflow of (k).

[0087] As a result of the above, although there is a possibility that the phase difference overflow detection may be delayed, it is possible to capture the phase difference overflow of signal zB. Furthermore, if N is set large enough, it is possible to reduce this delay to a size that can be ignored. One implementation example that realizes the above [Property 2] and [Property 3] is the structure shown in Figure 3.

[0088] A counter to which the clock time difference measurement device of this embodiment can be applied will be described with reference to Figures 10 and 11. This counter is a multi-bit or single-bit counter, and a clock A for driving the counter is input to this counter.

[0089] Each time the logic of clock A transitions from "0" to "1" (a rising edge occurs), the counter counts up. Ideally, the timing of the rising edge of clock A and the timing when the counter counts up should be simultaneous, but in reality, due to delay times in the components that make up the counter, In the White Rabbit project, this delay is expressed as a time lag φ trans In order to achieve highly accurate time synchronization, the time difference φ trans needs to be measured.

[0090] A counter like the one shown in Figure 10 can be used as a high-resolution "clock." By supplying a clock with a frequency of, for example, 125 MHz as clock A to this counter, the output counter value can be used as a high-resolution clock with a minimum resolution of 8 ns.

[0091] In the White Rabbit project, in order to realize an ultra-high resolution clock of less than 1 ns, not only is a counter with a resolution of 8 ns used, but the phase value of clock A driving the counter is also used as an element of the clock. For example, if the phase of the counter driving clock at a certain moment can be measured with a resolution of 10,000 divisions, or 2π / 10,000 [rad], the clock resolution based on the phase difference will be an ultra-high resolution of 0.8 ps. In this case, as shown in Figure 11, the time difference between driving clock A and the output value (count value) of the counter, that is, the time difference φ trans Therefore, in order to correct the time difference of the clock, the time difference φ trans The higher the precision and accuracy of the measurement, the more accurate the clock can be.

[0092] time difference φ trans is the delay (time difference) from the timing of the rising edge of driving clock A until the counter output value is actually updated (counted up). If we focus on the least significant bit of the counter output value, we can see that the logic changes from 0, 1, 0, 1, ... at each rising edge of driving clock A. If we consider this transition as a clock, we can consider the least significant bit of the counter output as a clock with half the frequency of driving clock A. Then, let the frequency of driving clock A be f A When the frequency f A clock and frequency f A If we can measure the time difference between the clocks of φ / 2, we can calculate the time difference between the measured time difference and φ trans In other words, z=2, and the clock time difference measurement device described above can be applied.

[0093] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0094] 1, 1C...Clock time difference measurement device 5...Offset clock generator 10, 20... Sampling circuit 30, 40C...Phase difference overflow detection circuit 40...Signal division / phase difference overflow detection circuit 41...Signal division unit 42 (42(0)~(z-1))...Phase difference overflow detection circuit 43... Signal merge section 44...Control signal generation unit 45...Counter 50...Time difference counter

Claims

1. A clock time difference measurement device that measures a time difference between a first clock and a second clock, the second clock has a frequency that is 1 / z (z is an integer equal to or greater than 1) of the frequency of the first clock; a first sampling circuit that samples the first clock based on an offset clock that has a frequency slightly different from that of the first clock to generate a first sampling signal; a second sampling circuit that samples the second clock based on the offset clock to generate a second sampling signal; a phase difference overflow detection circuit that detects a phase difference overflow between the first sampling signal and the offset clock and outputs a third sampling signal; a signal division / phase difference overflow detection circuit that divides the second sampling signal into z division signals to generate z division signals, detects a phase difference overflow between the division signals and the offset clock to generate a fourth sampling signal, and further combines the fourth sampling signals to generate a fifth sampling signal; a time difference counter that counts the time difference between the first clock and the second clock based on the third sampling signal and the fifth sampling signal; A clock time difference measurement device comprising:

2. The signal division / phase difference overflow detection circuit comprises: a counter that counts a count value k that indicates the number of rising edges of the offset clock; 2. The clock time difference measurement device according to claim 1, wherein the fifth sampling signal is generated based on at least one of the z divided signals corresponding to a remainder when the count value k is divided by z.

3. The signal division / phase difference overflow detection circuit comprises: a counter that counts a count value k that indicates the number of rising edges of the offset clock; and a control signal generation unit that generates z control signals whose logic changes depending on the remainder when the count value k is divided by z, one of the z control signals is set to a first logic and the remaining z-1 control signals are set to a second logic; 2. The clock time difference measurement device according to claim 1, wherein the signal division / phase difference overflow detection circuit generates the fourth sampling signal based on a divided signal corresponding to the control signal set to the first logic level.

4. The signal division / phase difference overflow detection circuit includes z latch circuits that latch the z divided signals; 4. The clock time difference measurement device according to claim 3, further comprising z phase difference overflow detection circuits provided corresponding to the z latch circuits, each detecting a phase difference overflow between the divided signal from the latch circuit and the offset clock.

5. 5. The clock time difference measurement device according to claim 4, wherein the signal division / phase difference overflow detection circuit generates the fifth sampling signal based on a signal from at least one of the z latch circuits and the z phase difference overflow detection circuits.

6. 1. A clock time difference measurement method for measuring a time difference between a first clock and a second clock, comprising: the second clock has a frequency that is 1 / z (z is an integer equal to or greater than 1) of the frequency of the first clock; The clock time difference measurement method includes: Sampling the first clock based on an offset clock having a frequency slightly different from that of the first clock to generate a first sampling signal; sampling the second clock based on the offset clock to generate a second sampling signal; detecting an overflow of a phase difference between the first sampling signal and the offset clock to generate a third sampling signal; dividing the second sampling signal into z division signals to generate z division signals, detecting an overflow of a phase difference between the division signals and the offset clock to generate a fourth sampling signal, and further combining the fourth sampling signals to generate a fifth sampling signal; and counting the time difference between the first clock and the second clock based on the third sampling signal and the fifth sampling signal.

7. further comprising a step of counting a count value k indicating the number of rising edges of the offset clock; 7. The clock time difference measuring method according to claim 6, wherein the fifth sampling signal is generated based on at least one of the z divided signals corresponding to a remainder when the count value k is divided by z.

8. The method further comprises the steps of: counting a count value k indicating the number of rising edges of the offset clock; and generating z control signals whose logic changes depending on the remainder when the count value k is divided by z, one of the z control signals is set to a first logic and the remaining z-1 control signals are set to a second logic; 7. The clock time difference measuring method according to claim 6, wherein the fourth sampling signal is generated based on a divided signal corresponding to the control signal set to the first logic level.

9. a signal dividing unit that divides a first sampling signal obtained by sampling the clock into z pieces based on an offset clock having a frequency slightly different from z times the frequency of the clock, to generate z divided signals; a phase difference overflow detection circuit that detects a phase difference overflow between the divided signal and the offset clock and generates a second sampling signal; a signal merging unit that combines the second sampling signals to generate a third sampling signal.

10. a counter that counts a count value k that indicates the number of rising edges of the offset clock; 10. The signal generating device according to claim 9, wherein the third sampling signal is generated based on at least one of the z divided signals corresponding to a remainder when the count value k is divided by z.

11. a counter that counts a count value k that indicates the number of rising edges of the offset clock; and a control signal generation unit that generates z control signals whose logic changes depending on the remainder when the count value k is divided by z, one of the z control signals is set to a first logic and the remaining z-1 control signals are set to a second logic; The signal generating device according to claim 9 , wherein the second sampling signal is generated based on a divided signal corresponding to the control signal set to the first logic.

12. a step of dividing a first sampling signal obtained by sampling the clock based on an offset clock having a frequency slightly different from z times the frequency of the clock into z divided signals; detecting an overflow of a phase difference between the divided signal and the offset clock to generate a second sampling signal; and combining the second sampling signals to generate a third sampling signal.

13. further comprising a step of counting a count value k indicating the number of rising edges of the offset clock; The signal generating method according to claim 12 , further comprising generating the third sampling signal based on at least one of the z divided signals corresponding to a remainder when the count value k is divided by z.

14. a step of counting a count value k indicating the number of rising edges of the offset clock; and generating z control signals whose logic changes depending on the remainder when the count value k is divided by z, one of the z control signals is set to a first logic and the remaining z-1 control signals are set to a second logic; The signal generating method according to claim 12 , wherein the second sampling signal is generated based on a divided signal corresponding to the control signal set to the first logic.

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