A three-stage positive feedback comparator circuit based on fast timing and electronic equipment

Abstract

This invention relates to the field of integrated circuit technology and discloses a three-stage positive feedback comparator circuit and electronic device based on fast timing. The circuit includes a first-stage positive feedback module, a second-stage triggering and clocking module, a second-stage positive feedback amplification module, and a third-stage positive feedback latching module. By employing a three-stage positive feedback structure, this invention places the corresponding differential signal nodes in the same feedback loop at each stage, significantly enhancing the comparator's amplification rate and metastability suppression capability. Furthermore, by introducing a fast timing control mechanism, the second-stage amplification, clock reset generation, and third-stage latching operations can be executed in parallel, effectively shortening the critical path delay and significantly improving the overall comparison speed. The electronic device includes the aforementioned comparator circuit. This invention effectively solves the bottlenecks of traditional comparators in terms of speed and reliability and is suitable for high-speed, high-precision data conversion systems.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology and discloses a three-stage positive feedback comparator circuit and electronic device based on fast timing. Background Technology

[0002] With the rapid development of high-speed data conversion chips, system-on-chips, and sensor interfaces, the performance requirements for successive approximation analog-to-digital converters (SAR ADCs) are constantly increasing, especially in terms of conversion speed and energy efficiency. As the most critical speed bottleneck module in SAR ADCs, the performance of the comparator directly determines the sampling rate and accuracy stability of the entire conversion system.

[0003] To improve comparison speed, traditional solutions typically employ multi-stage positive feedback structures. Taking a typical three-stage positive feedback comparator as an example, the first stage initially amplifies the input differential signal, while the second and third stages sequentially amplify and latch the signal. However, this traditional structure has two inherent performance limitations: First, in terms of circuit architecture, usually only the first stage of positive feedback places the differential signal nodes within the same feedback loop for coordinated amplification, while the subsequent second and third stages often fail to fully utilize the cross-coupling feedback mechanism of the differential pairs. This results in insufficient amplification capability for small input voltage differences and weak metastability suppression performance, thus affecting comparison accuracy and decision speed. Second, in terms of timing control, its workflow exhibits a strictly serialized characteristic; that is, each stage of positive feedback, clock generation, and reset operation must wait for the previous stage to complete before starting. This makes the total delay time of a single comparison cycle a linear sum of the delays of each stage, which cannot meet the stringent conversion rate requirements of modern high-speed ADCs.

[0004] Although existing research has made partial improvements through techniques such as device size optimization or the introduction of background calibration, the fundamental limitations stemming from circuit structure and timing logic have not yet been overcome. Therefore, there is an urgent need for an innovative comparator design that can enhance the differential positive feedback capability throughout the entire path from an architectural perspective and achieve parallelization of critical operations from a timing perspective, thereby fundamentally achieving a simultaneous improvement in speed and reliability. Summary of the Invention

[0005] In view of this, this application provides a three-stage positive feedback comparator circuit and electronic device based on fast timing, so as to enhance the differential positive feedback capability of the whole path in terms of circuit structure and realize the parallel triggering of key operations in terms of timing control, thereby synergistically improving the comparator's speed, accuracy and metastability suppression capability.

[0006] A three-stage positive feedback comparator circuit based on fast timing, comprising:

[0007] The first-stage positive feedback module receives a differential input signal and a comparison clock signal, and switches to the comparison phase under the control of the comparison clock signal. In the comparison phase, it compares and amplifies the differential input signal based on the internal first-stage positive feedback loop, and outputs a first intermediate control signal and a first output differential signal.

[0008] The second-level trigger and clock module receives the comparison clock signal and the first intermediate control signal, and is used to generate an enable signal according to the first intermediate control signal, and control the reset of the comparison clock signal and generate a latch clock signal based on the enable signal.

[0009] The second-stage positive feedback amplification module receives the first output differential signal and the enable signal, and is used to latch and amplify the first output differential signal through its internal second-stage positive feedback loop under the control of the enable signal, and output the second output differential signal.

[0010] The third-stage positive feedback latch module receives the second output differential signal, the latch clock signal, and the reset signal. Under the control of the latch clock signal, it latches the second output differential signal through the third-stage positive feedback latch network formed by the cross-coupling connection between multiple D flip-flops inside it, and outputs the corresponding digital output signal.

[0011] Optionally, the first-stage positive feedback module includes a first NMOS transistor MN0, a second NMOS transistor MN1, a third NMOS transistor MN2, a fourth NMOS transistor MN3, a fifth NMOS transistor MN4, a sixth NMOS transistor MN5, a seventh NMOS transistor MN6, an eighth NMOS transistor MN7, a ninth NMOS transistor MN8, a first PMOS transistor MP0, a second PMOS transistor MP1, a third PMOS transistor MP2, a fourth PMOS transistor MP3, a fifth PMOS transistor MP4, a sixth PMOS transistor MP5, a first inverter INV0, a ​​second inverter INV1, a third inverter INV2, and a fourth inverter INV3;

[0012] In this configuration, the gate of the first NMOS transistor MN0 receives the comparison clock signal, its source is grounded, and its drain is connected to the sources of the second NMOS transistor MN1 and the third NMOS transistor MN2. The gates of the second NMOS transistor MN1 and the third NMOS transistor MN2 respectively receive the first differential input signal VIP and the second differential input signal VIN, which together constitute the differential input signal. The drain of the second NMOS transistor MN1 is connected to the drain of the first PMOS transistor MP0, the gate of the fifth PMOS transistor MP4, the gate of the eighth NMOS transistor MN7, and the gate of the fourth NMOS transistor MN3, and outputs an intermediate control signal VP1. The drain of the third NMOS transistor MN2 is connected to the drain of the second PMOS transistor MP1, the gate of the sixth PMOS transistor MP5, the gate of the ninth NMOS transistor MN8, and the gate of the fifth NMOS transistor MN4, and outputs an intermediate control signal VN1.

[0013] The intermediate control signal VP1 and the intermediate control signal VN1 together constitute the first intermediate control signal;

[0014] The gates of the first PMOS transistor MP0 and the second PMOS transistor MP1 receive the comparison clock signal, and their sources are connected to the power supply voltage.

[0015] The sources of the third PMOS transistor MP2 and the fourth PMOS transistor MP3 are respectively connected to the drains of the fifth PMOS transistor MP4 and the sixth PMOS transistor MP5; the sources of the fifth PMOS transistor MP4 and the sixth PMOS transistor MP5 are connected to the power supply voltage; the drain of the third PMOS transistor MP2 is connected to the gate of the fourth PMOS transistor MP3, the gate of the seventh NMOS transistor MN6, the drain of the sixth NMOS transistor MN5, the drain of the fourth NMOS transistor MN3, and the input terminal of the second inverter INV1, forming a first internal positive feedback node; the drain of the fourth PMOS transistor MP3 is connected to the gate of the third PMOS transistor MP2, the gate of the sixth NMOS transistor MN5, the drain of the seventh NMOS transistor MN6, the drain of the fifth NMOS transistor MN4, and the input terminal of the first inverter INV0, forming a second internal positive feedback node.

[0016] A first internal positive feedback signal VP is generated at the first internal positive feedback node, and a second internal positive feedback signal VN is generated at the second internal positive feedback node;

[0017] The sources of the sixth NMOS transistor MN5 and the seventh NMOS transistor MN6 are grounded; the sources of the fourth NMOS transistor MN3 and the fifth NMOS transistor MN4 are grounded.

[0018] The sources of the eighth NMOS transistor MN7 and the ninth NMOS transistor MN8 are grounded, and their drains are connected to the sources of the third PMOS transistor MP2 and the fourth PMOS transistor MP3, respectively.

[0019] The output terminal of the first inverter INV0 is connected to the input terminal of the third inverter INV2, and the output terminal of the third inverter INV2 outputs a differential signal VOUTN; the output terminal of the second inverter INV1 is connected to the input terminal of the fourth inverter INV3, and the output terminal of the fourth inverter INV3 outputs a differential signal VOUTP. The differential signals VOUTN and VOUTP together constitute the first output differential signal.

[0020] Optionally, the second-stage trigger and clock module includes the eleventh PMOS transistor MP11, the tenth PMOS transistor MP10, the tenth NMOS transistor MN9, the fifth inverter INV4, the sixth inverter INV5, the eighth inverter INV8, a comparator clock generation module, and a SAR logic clock generation module.

[0021] The gates of the eleventh PMOS transistor MP11 and the tenth PMOS transistor MP10 respectively receive the intermediate control signal VP1 and the intermediate control signal VN1, and their sources jointly receive the comparison clock signal.

[0022] The gate of the tenth NMOS transistor MN9 is connected to the output terminal of the eighth inverter INV8, and its source is grounded; the drains of the eleventh PMOS transistor MP11 and the tenth PMOS transistor MP10 are connected to the input terminal of the fifth inverter INV4 together with the drain of the tenth NMOS transistor MN9.

[0023] The input terminal of the eighth inverter INV8 receives the comparison clock signal;

[0024] The output of the fifth inverter INV4 is connected to the input of the sixth inverter INV5 and outputs a first internal enable signal VA1N; the output of the sixth inverter INV5 outputs a second internal enable signal VA1.

[0025] The first internal enable signal VA1N and the second internal enable signal VA1 together constitute the enable signal;

[0026] The input terminal of the comparator clock generation module receives the second internal enable signal VA1, and its output terminal is connected to the comparison clock signal node to control the reset of the comparison clock signal.

[0027] The input terminal of the SAR logic clock generation module receives the second internal enable signal VA1, and the output terminal outputs the latch clock signal.

[0028] Optionally, the second-stage positive feedback amplification module includes the seventh PMOS transistor MP6, the eighth PMOS transistor MP7, the ninth PMOS transistor MP8, the twelfth PMOS transistor MP9, the eleventh NMOS transistor MN10, the twelfth NMOS transistor MN11, the seventh inverter INV6, and the ninth inverter INV7.

[0029] The gates of the seventh PMOS transistor MP6 and the twelfth PMOS transistor MP9 receive the first internal enable signal VA1N, and the gates of the eighth PMOS transistor MP7 and the ninth PMOS transistor MP8 receive the second internal enable signal VA1.

[0030] The source of the eighth PMOS transistor MP7 and the ninth PMOS transistor MP8 are connected to the power supply voltage.

[0031] The gates of the eleventh NMOS transistor MN10 and the twelfth NMOS transistor MN11 receive the second internal enable signal VA1;

[0032] The source of the seventh PMOS transistor MP6 is connected to the drain of the twelfth NMOS transistor MN11, the drain of the eighth PMOS transistor MP7, and the input of the seventh inverter INV6.

[0033] The source of the twelfth PMOS transistor MP9 is connected to the source of the eleventh NMOS transistor MN10, the drain of the ninth PMOS transistor MP8, and the input of the ninth inverter INV7.

[0034] The output terminal of the seventh inverter INV6 is connected to the drain of the twelfth PMOS transistor MP9 and the drain of the eleventh NMOS transistor MN10, and outputs a differential signal VOUTQ.

[0035] The output terminal of the ninth inverter INV7 is connected to the drain of the seventh PMOS transistor MP6 and the source of the twelfth NMOS transistor MN11, and outputs a differential signal VOUTO.

[0036] The differential signal VOUTQ and the differential signal VOUTO together constitute the second output differential signal;

[0037] The input terminals of the seventh inverter INV6 and the ninth inverter INV7 are cross-coupled to each other's output nodes, forming a second-stage positive feedback loop.

[0038] Optionally, the third-level positive feedback latch module includes multiple D flip-flops, which include: a first left-side D flip-flop DFF1, a second left-side D flip-flop DFF2 to a tenth left-side D flip-flop DFF2, a first right-side D flip-flop DFF1, a second right-side D flip-flop DFF2 to a tenth right-side D flip-flop DFF2;

[0039] Wherein, the data input terminal D of all the left-side D flip-flops receives the differential signal VOUTQ, and the data input terminal D of all the right-side D flip-flops receives the differential signal VOUTO;

[0040] The first clock input CLK1 of the first left-side D flip-flop DFF1 and the first right-side D flip-flop DFF1 receives the reset signal RST, and the second clock input CLK2 receives the most significant bit latch clock signal CLK from the latch clock signal. <9> ;

[0041] The first clock input CLK1 of the second left-side D flip-flop DFF2 to the tenth left-side D flip-flop DFF2 and the second right-side D flip-flop DFF2 to the tenth right-side D flip-flop DFF2 sequentially receives the CLK from the latched clock signal. <9> To CLK <1> The second clock terminal CLK2 sequentially receives CLK from the latched clock signal. <8> To CLK <0> This allows for cascading triggering.

[0042] The output terminal Q of the first left-side D flip-flop DFF1 outputs the most significant bit digital signal VOP. <9> The outputs Q of the second left-hand D flip-flop DFF2 to the tenth left-hand D flip-flop DFF2 sequentially output the remaining digital signals VOP. <8> To VOP <0> ;

[0043] The output terminal Q of the first right-side D flip-flop DFF1 outputs the most significant bit digital signal VON. <9> The outputs Q of the second right-hand D flip-flop DFF2 to the tenth right-hand D flip-flop DFF2 sequentially output the remaining digital signals VON. <8> To VON <0> ;

[0044] The digital signal VOP <9> To VOP <0> and VON <9> To VON <0> Together they constitute the digital output signal;

[0045] The first internal port VO1 of the first left-side D flip-flop DFF1 is connected to the second internal port VO2 of the first right-side D flip-flop DFF1, and the second internal port VO2 of the first left-side D flip-flop DFF1 is connected to the first internal port VO1 of the first right-side D flip-flop DFF1.

[0046] The first internal port VO1 of each of the second left-hand D flip-flops DFF2 to the tenth left-hand D flip-flops DFF2 is connected to the second internal port VO2 of the corresponding D flip-flops in the second right-hand D flip-flops DFF2 to the tenth right-hand D flip-flops DFF2; the second internal port VO2 of each of the second left-hand D flip-flops DFF2 to the tenth left-hand D flip-flops DFF2 is connected to the first internal port VO1 of the corresponding D flip-flops in the second right-hand D flip-flops DFF2 to the tenth right-hand D flip-flops DFF2.

[0047] The third-stage positive feedback latch module is formed between the left-side D flip-flop and the corresponding right-side D flip-flop through the cross connection of the internal ports VO1 and VO2.

[0048] Optionally, both the first left-side D flip-flop DFF1 and the first right-side D flip-flop DFF1 include a main latch circuit and a clock generation circuit. The main latch circuit includes a first transmission gate, a second transmission gate, a third transmission gate, a tenth inverter INV9, an eleventh inverter INV10, a thirteenth inverter INV13, a thirteenth PMOS transistor MP12, and a thirteenth NMOS transistor MN12. The clock generation circuit includes a twelfth inverter INV11, a fourteenth inverter INV12, and a NOR gate.

[0049] The first transmission gate is composed of a sixteenth NMOS transistor MN15 and a sixteenth PMOS transistor MP15 connected in parallel. The gate of the sixteenth NMOS transistor MN15 receives the first internal clock signal CLK0, and the gate of the sixteenth PMOS transistor MP15 receives the first internal clock inversion signal CLK0N. The sources of the sixteenth NMOS transistor MN15 and the sixteenth PMOS transistor MP15 together form the data input terminal D of the D flip-flop DFF1. The drains of the two are connected to the input terminal of the tenth inverter INV9 and form the second internal port VO2 of the D flip-flop DFF1.

[0050] The output of the tenth inverter INV9 is connected to the input of the eleventh inverter INV10 and the thirteenth inverter INV13; the output of the eleventh inverter INV10 constitutes the output Q of the D flip-flop DFF1.

[0051] The source of the thirteenth PMOS transistor MP12 is connected to the power supply voltage, the drain is connected to the second internal port VO2, and the gate is connected to the upper end of the second transmission gate and the drain of the thirteenth NMOS transistor MN12.

[0052] The source of the thirteenth NMOS transistor MN12 is grounded, and its gate is connected to the first clock terminal CLK1 to receive the reset signal RST.

[0053] The second transmission gate is composed of a fifteenth NMOS transistor MN14 and a fifteenth PMOS transistor MP14 connected in parallel. The gate of the fifteenth NMOS transistor MN14 is connected to the second clock terminal CLK2 to receive the most significant bit latch clock signal CLK in the latch clock signal. <9> The gate of the fifteenth PMOS transistor MP14 receives the most significant bit latch clock signal CLK. <9> The inverted signal CLK2N, the source of the fifteenth NMOS transistor MN14 and the fifteenth PMOS transistor MP14 together form the first internal port VO1, and the drain of both are connected to the gate of the thirteenth PMOS transistor MP12 and the drain of the thirteenth NMOS transistor MN12.

[0054] The third transmission gate is formed by the fourteenth NMOS transistor MN13 and the fourteenth PMOS transistor MP13 connected in parallel. The gate of the fourteenth NMOS transistor MN13 receives the first internal clock inverted signal CLK0N, and the gate of the fourteenth PMOS transistor MP13 receives the first internal clock CLK0. The sources of the fourteenth NMOS transistor MN13 and the fourteenth PMOS transistor MP13 are connected to the second internal port VO2, and the drains are connected to the output terminal of the thirteenth inverter INV13.

[0055] In the clock generation circuit, the first input terminal of the NOR gate is connected to the first clock terminal CLK1 to receive the reset signal RST, and the second input terminal is connected to the second clock terminal CLK2 to receive the most significant bit latch clock signal CLK. <9> The output terminal is connected to the input terminal of the twelfth inverter INV11 and outputs the first internal clock inversion signal CLK0N; the output terminal of the twelfth inverter INV11 outputs the first internal clock CLK0; the input terminal of the fourteenth inverter INV12 is connected to the second clock terminal CLK2 to receive the most significant bit latched clock signal CLK. <9> The output terminal outputs the highest bit latch clock signal CLK. <9> The inverted signal CLK2N.

[0056] Optionally, the second left-side D flip-flop DFF2 to the tenth left-side D flip-flop DFF2 and the second right-side D flip-flop DFF2 to the tenth right-side D flip-flop DFF2 all include a main latch circuit and a clock generation circuit. The main latch circuit includes a first transmission gate, a second transmission gate, a third transmission gate, a fifteenth inverter INV14, a sixteenth inverter INV15, a seventeenth inverter INV16, a twentieth PMOS transistor MP19, and a twentieth NMOS transistor MN19.

[0057] The clock generation circuit includes an eighteenth inverter INV17, a nineteenth inverter INV18, a twentieth inverter INV19, and a NAND gate;

[0058] The first transmission gate is composed of the nineteenth NMOS transistor MN18 and the nineteenth PMOS transistor MP18 connected in parallel. The gate of the nineteenth NMOS transistor MN18 receives the first internal clock inversion signal CLK0N, and the gate of the nineteenth PMOS transistor MP18 receives the first internal clock signal CLK0. The sources of the nineteenth NMOS transistor MN18 and the nineteenth PMOS transistor MP18 together form the data input terminal D of the D flip-flop DFF2. The drains of the two are connected to the input terminal of the fifteenth inverter INV14 and form the second internal port VO2.

[0059] The output of the fifteenth inverter INV14 is connected to the input of the sixteenth inverter INV15 and the seventeenth inverter INV16; the output of the sixteenth inverter INV15 constitutes the output Q of the D flip-flop DFF2;

[0060] The source of the twentieth PMOS transistor MP19 is connected to the power supply voltage, the drain is connected to the second internal port VO2, and the gate is connected to the upper end of the second transmission gate and the drain of the twentieth NMOS transistor MN19.

[0061] The source of the twentieth NMOS transistor MN19 is grounded, and its gate receives the signal CLK1N.

[0062] The second transmission gate is formed by the parallel connection of the eighteenth NMOS transistor MN17 and the eighteenth PMOS transistor MP17. The gate of the eighteenth NMOS transistor MN17 is connected to the second clock terminal CLK2 to receive the latch clock signal. The gate of the eighteenth PMOS transistor MP17 receives the signal CLK2N. The sources of the eighteenth NMOS transistor MN17 and the eighteenth PMOS transistor MP17 together form the first internal port VO1. The drains of the two are connected to the gate of the twentieth PMOS transistor MP19 and the drain of the twentieth NMOS transistor MN19.

[0063] The third transmission gate is composed of the seventeenth NMOS transistor MN16 and the seventeenth PMOS transistor MP16 connected in parallel. The gate of the seventeenth NMOS transistor MN16 receives the first internal clock signal CLK0, and the gate of the seventeenth PMOS transistor MP16 receives the first internal clock inversion signal CLK0N. The sources of the seventeenth NMOS transistor MN16 and the seventeenth PMOS transistor MP16 are connected to the second internal port VO2, and the drains are connected to the output terminal of the seventeenth inverter INV16.

[0064] In the clock generation circuit, the input of the nineteenth inverter INV18 is connected to the second clock terminal CLK2, and the output terminal is the output signal CLK2N, which is connected to the first input of the NAND gate; the second input of the NAND gate is connected to the first clock terminal CLK1; the first clock terminal CLK1 is also connected to the input of the eighteenth inverter INV17, and the output of the eighteenth inverter INV17 outputs the signal CLK1N; the output of the NAND gate outputs the first internal clock inverted signal CLK0N and is connected to the input of the twentieth inverter INV19, and the output of the twentieth inverter INV19 outputs the first internal clock CLK0.

[0065] Optionally, signal CLK1N is the inverted signal of the signal received by the first clock port CLK1; signal CLK2N is the inverted signal of the signal received by the second clock port CLK2.

[0066] Optionally, the comparator circuit is configured as follows:

[0067] When the comparison clock signal is low, the first-stage positive feedback module is in the reset phase, and the first intermediate control signal output by it is maintained at a high level; the enable signal output by the second-stage trigger and clock module is invalid, the second-stage positive feedback amplification module is disabled, and the third-stage positive feedback latch module maintains its latching state.

[0068] When the comparison clock signal jumps from low level to high level, the first stage positive feedback module enters the comparison phase and responds based on the voltage difference between the differential input signals, so that the intermediate control signal VP1 and intermediate control signal VN1 output by it are pulled down from high level at different speeds.

[0069] The second-level trigger and clock module generates an effective enable signal based on the pull-down speed difference between the intermediate control signal VP1 and the intermediate control signal VN1;

[0070] When the enable signal is valid, the following operations are performed simultaneously: the second-stage positive feedback amplification module is started to latch and amplify the first output differential signal, and the comparator clock generation module and SAR logic clock generation module inside the second-stage trigger and clock module are started to start timing.

[0071] After a fixed delay, the comparator clock generation module pulls the comparison clock signal low from high level, and at the same time, the SAR logic clock generation module outputs a valid latch clock signal.

[0072] When the comparison clock signal goes low again, the first-stage positive feedback module enters the reset phase again. At the same time, the third-stage positive feedback latch module latches the second output differential signal output by the second-stage positive feedback amplifier module under the control of the latch clock signal.

[0073] An electronic device comprising a three-stage positive feedback comparator circuit based on fast timing as described in any of the preceding claims.

[0074] In summary, due to the adoption of the above technical solutions, the beneficial effects of the present invention include at least the following:

[0075] By constructing cross-coupled positive feedback loops based on differential nodes in the three-stage amplification structure throughout the entire path, minute differences in the input signal can be amplified collaboratively and efficiently at each stage, significantly enhancing the suppression of metastability and thus improving comparison accuracy and decision reliability. Simultaneously, through an innovative fast timing control mechanism, the startup of the second-stage amplification module, the generation of the clock reset signal, and the triggering of the third-stage latch module can be executed in parallel. This effectively "hides" the inherent delays of the second and third stages in traditional serial timing within the clock and reset operation periods, thereby significantly shortening the single comparison cycle without sacrificing stability and achieving a significant improvement in comparison speed. Furthermore, the clearly defined modular design with well-defined timing facilitates portability and optimization in SAR ADCs with different process and performance requirements, enhancing the practicality and applicability of this technology. Attached Figure Description

[0076] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0077] Figure 1 This is a block diagram of the comparator circuit structure of the present invention;

[0078] Figure 2 This is a schematic diagram of the first-stage positive feedback module of the present invention;

[0079] Figure 3 This is the timing diagram of the first-stage positive feedback module of the present invention;

[0080] Figure 4 This is a schematic diagram of the second-level triggering and clocking module of the present invention;

[0081] Figure 5 This is a schematic diagram of the second-stage positive feedback amplification module of the present invention;

[0082] Figure 6 This is a schematic diagram of the third-stage positive feedback latch module of the present invention;

[0083] Figure 7 This is a schematic diagram of the main latch circuit of the D flip-flop DFF1 in the latch module of the present invention;

[0084] Figure 8 This is a schematic diagram of the clock generation circuit of the D flip-flop DFF1 in the latch module of the present invention;

[0085] Figure 9 This is a schematic diagram of the main latch circuit of the D flip-flop DFF2 in the latch module of the present invention;

[0086] Figure 10 This is a schematic diagram of the clock generation circuit of the D flip-flop DFF2 in the latch module of the present invention;

[0087] Figure 11 This is a timing diagram of the comparator of the present invention;

[0088] Figure 12 This is the timing diagram of the D flip-flop DFF1 of the present invention;

[0089] Figure 13 This is the timing diagram of the D flip-flop DFF2 of the present invention. Detailed Implementation

[0090] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0091] In this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element. Example 1

[0092] As can be seen from the above background technology, traditional SARADC comparators based on multi-stage positive feedback structures face two fundamental bottlenecks when pursuing higher speed and accuracy: First, in terms of circuit architecture, the subsequent positive feedback fails to fully utilize the collaborative amplification mechanism of differential signals, resulting in limited ability to suppress metastability and restricting comparison accuracy; Second, in terms of timing control, its serial workflow causes the delay of each stage to accumulate linearly, which severely limits further improvement in comparison speed.

[0093] In existing technologies, although improvements can be made by optimizing device size or introducing complex calibration circuits, these often only partially alleviate a single problem and frequently come at the cost of sacrificing power consumption, area, or design flexibility. They fail to simultaneously overcome the two major challenges of speed and reliability from the perspective of synergistic optimization of circuit structure and timing control.

[0094] Therefore, this application provides a three-stage positive feedback comparator circuit based on fast timing, such as... Figure 1 , Figure 2 , Figure 4 , Figure 5 and Figure 6 As shown, it includes: a first-stage positive feedback module, a second-stage trigger and clock module, a second-stage positive feedback amplification module, and a third-stage positive feedback latch module.

[0095] The first-stage positive feedback module is used to receive the differential input signal VIP / VIN and the comparison clock signal CLK. Under the control of the comparison clock signal CLK, it enters the comparison phase and uses its internal first-stage positive feedback loop to initially amplify and lock the small difference between the differential input signals VIP / VIN, and outputs the first intermediate control signal VP1 / VN1 and the first output differential signal VOUTP / VOUTN.

[0096] The second-level trigger and clock module is used to receive the comparison clock signal CLK and the first intermediate control signal VP1 / VN1, generate an enable signal VA1 / VA1N based on the pull-down speed difference between the intermediate control signal VP1 and the intermediate control signal VN1, and control the reset of the comparison clock signal CLK and generate the latch clock signal CLK<9:0> based on the enable signal.

[0097] The second-stage positive feedback amplification module is used to receive the first output differential signal VOUTP / VOUTN and the enable signal VA1 / VA1N. When the enable signal is valid, the first output differential signal is further latched and amplified through its internal second-stage positive feedback loop, and the output second output differential signal VOUTQ / VOUTO with a larger swing and more stable output is generated.

[0098] The third-stage positive feedback latch module is used to receive the second output differential signal VOUTQ / VOUTO, the latch clock signal CLK<9:0>, and the reset signal RST. Under the control of the latch clock signal, the second output differential signal is finally digitally latched through the third-stage positive feedback latch network formed by the cross-coupling connection of the internal ports VO1 / VO2 between the D flip-flop arrays on the left and right sides, and the corresponding digital output signal VOP<9:0> / VON<9:0> is output.

[0099] Furthermore, during circuit power-on initialization or when a completely new analog-to-digital conversion process needs to begin, the reset signal RST is set to an active level (e.g., high level). This signal directly acts on the corresponding clock terminals (CLK1) of the first left-hand D flip-flop DFF1 and the first right-hand D flip-flop DFF1 in the third-stage positive feedback latch module.

[0100] When RST is active, it forces the two most significant D flip-flops into a defined reset state, typically initializing their internal nodes and output Q to a preset logic level (e.g., resetting the output low or breaking their internal positive feedback loop and placing it in a known state). This ensures that before the comparator begins operation, its most significant bit output, and any subsequent logic that might be affected by it (such as the SAR logic state machine), is at a clean and consistent starting point. This guarantees that the successive approximation process starts from the correct initial state, avoiding transition errors caused by random initial states of the latches.

[0101] In other D flip-flops (DFF2), their reset or initialization is typically accomplished through cascaded clock control logic. Therefore, the reset signal RST primarily provides a global, synchronous initialization control for the entire comparator digital output section (especially the most significant bit), and is one of the key signals for reliable system startup and operation.

[0102] The specific circuit of the first-stage positive feedback module can be as follows: Figure 2 As shown, it includes: first NMOS transistor MN0, second NMOS transistor MN1, third NMOS transistor MN2, fourth NMOS transistor MN3, fifth NMOS transistor MN4, sixth NMOS transistor MN5, seventh NMOS transistor MN6, eighth NMOS transistor MN7, and ninth NMOS transistor MN8;

[0103] First PMOS transistor MP0, second PMOS transistor MP1, third PMOS transistor MP2, fourth PMOS transistor MP3, fifth PMOS transistor MP4, sixth PMOS transistor MP5;

[0104] First inverter INV0, second inverter INV1, third inverter INV2 and fourth inverter INV3;

[0105] The gate of the first NMOS transistor MN0 receives the comparison clock signal CLK, its source is grounded, and its drain is connected to the source of the second NMOS transistor MN1 and the third NMOS transistor MN2. The gates of the second NMOS transistor MN1 and the third NMOS transistor MN2 respectively receive the first differential input signal VIP and the second differential input signal VIN. The drain of the second NMOS transistor MN1 is connected to the drain of the first PMOS transistor MP0, the gate of the fifth PMOS transistor MP4, the gate of the eighth NMOS transistor MN7, and the gate of the fourth NMOS transistor MN3, and outputs an intermediate control signal VP1. The drain of the third NMOS transistor MN2 is connected to the drain of the second PMOS transistor MP1, the gate of the sixth PMOS transistor MP5, the gate of the ninth NMOS transistor MN8, and the gate of the fifth NMOS transistor MN4, and outputs an intermediate control signal VN1.

[0106] The gates of the first PMOS transistor MP0 and the second PMOS transistor MP1 receive the comparison clock signal CLK, and their sources are connected to the power supply voltage VDD.

[0107] The sources of the third PMOS transistor MP2 and the fourth PMOS transistor MP3 are respectively connected to the drains of the fifth PMOS transistor MP4 and the sixth PMOS transistor MP5; the sources of the fifth PMOS transistor MP4 and the sixth PMOS transistor MP5 are connected to the power supply voltage VDD; the drain of the third PMOS transistor MP2 is connected to the gate of the fourth PMOS transistor MP3, the gate of the seventh NMOS transistor MN6, the drain of the sixth NMOS transistor MN5, the drain of the fourth NMOS transistor MN3, and the input terminal of the second inverter INV1, forming a first internal positive feedback node VP; the drain of the fourth PMOS transistor MP3 is connected to the gate of the third PMOS transistor MP2, the gate of the sixth NMOS transistor MN5, the drain of the seventh NMOS transistor MN6, the drain of the fifth NMOS transistor MN4, and the input terminal of the first inverter INV0, forming a second internal positive feedback node VN.

[0108] The sources of the sixth NMOS transistor MN5 and the seventh NMOS transistor MN6 are grounded; the sources of the fourth NMOS transistor MN3 and the fifth NMOS transistor MN4 are grounded.

[0109] The sources of the eighth NMOS transistor MN7 and the ninth NMOS transistor MN8 are grounded, and their drains are connected to the sources of the third PMOS transistor MP2 and the fourth PMOS transistor MP3, respectively.

[0110] The output of the first inverter INV0 is connected to the input of the third inverter INV2, and the output of the third inverter INV2 outputs a differential signal VOUTN; the output of the second inverter INV1 is connected to the input of the fourth inverter INV3, and the output of the fourth inverter INV3 outputs a differential signal VOUTP.

[0111] The intermediate control signal VP1 and intermediate control signal VN1 together constitute the first intermediate control signal. The differential signal VOUTN and differential signal VOUTP together constitute the first output differential signal.

[0112] Under the control of the comparison clock signal CLK, the voltage difference between the first differential input signal VIP and the second differential input signal VIN is converted into a pull-down speed difference between VP1 and VN1. Through the cross-coupled positive feedback loop formed by the third PMOS transistor MP2, the fourth PMOS transistor MP3, the sixth NMOS transistor MN5, and the seventh NMOS transistor MN6, this speed difference is rapidly amplified into a large voltage difference at nodes VP and VN, and then output after being buffered by the inverter chain.

[0113] The detailed circuit of the second-stage trigger and clock module is as follows: Figure 4 As shown, it includes:

[0114] Eleventh PMOS transistor MP11, tenth PMOS transistor MP10, tenth NMOS transistor MN9, fifth inverter INV4, sixth inverter INV5, eighth inverter INV8, comparator clock generation module and SAR logic clock generation module.

[0115] The gates of the eleventh PMOS transistor MP11 and the tenth PMOS transistor MP10 receive the intermediate control signal VP1 and the intermediate control signal VN1, respectively, and their sources receive the comparison clock signal CLK.

[0116] The gate of the tenth NMOS transistor MN9 is connected to the output terminal of the eighth inverter INV8, and its source is grounded; the drains of the eleventh PMOS transistor MP11 and the tenth PMOS transistor MP10 are connected to the input terminal of the fifth inverter INV4 together with the drain of the tenth NMOS transistor MN9.

[0117] The input of the eighth inverter INV8 receives the comparison clock signal CLK.

[0118] The output of the fifth inverter INV4 is connected to the input of the sixth inverter INV5 and outputs a first internal enable signal VA1N; the output of the sixth inverter INV5 outputs a second internal enable signal VA1.

[0119] The first internal enable signal VA1N and the second internal enable signal VA1 together constitute the enable signal.

[0120] The input of the comparator clock generation module is connected to the output (VA1) of the sixth inverter INV5, and its output is connected to the node of the comparison clock signal CLK, used to control the reset of the comparison clock signal CLK. Specifically, when VA1 is valid (goes high), after a fixed delay Tc, the module drives the comparison clock signal CLK to change from high level to low level.

[0121] The input of the SAR logic clock generation module is connected to the output (VA1) of the sixth inverter INV5, and is used to generate the latch clock signal CLK<9:0>. Specifically, after VA1 is valid, and after a fixed delay Tc, the module sequentially outputs valid latch clock signals (such as CLK). <9> CLK <8> wait).

[0122] The second-stage trigger and clock module utilizes the pull-down speed difference between VP1 and VN1 to create current competition between the eleventh PMOS transistor MP11 and the tenth PMOS transistor MP10, converting the analog speed information into digital enable signals VA1 / VA1N, and synchronously triggering the subsequent comparison clock signal reset and latch clock generation process accordingly.

[0123] The detailed circuit of the second-stage positive feedback amplifier module is as follows: Figure 5 As shown, it includes:

[0124] The seventh PMOS transistor MP6, the eighth PMOS transistor MP7, the ninth PMOS transistor MP8, and the twelfth PMOS transistor MP9.

[0125] The eleventh NMOS transistor MN10, the twelfth NMOS transistor MN11, the seventh inverter INV6, and the ninth inverter INV7.

[0126] The gates of the seventh PMOS transistor MP6 and the twelfth PMOS transistor MP9 receive the first internal enable signal VA1N, and the gates of the eighth PMOS transistor MP7 and the ninth PMOS transistor MP8 receive the second internal enable signal VA1.

[0127] The source terminals of the eighth PMOS transistor MP7 and the ninth PMOS transistor MP8 are connected to the power supply voltage VDD.

[0128] The gates of the eleventh NMOS transistor MN10 and the twelfth NMOS transistor MN11 receive the second internal enable signal VA1.

[0129] The source of the seventh PMOS transistor MP6 is connected to the drain of the twelfth NMOS transistor MN11, the drain of the eighth PMOS transistor MP7, and the input of the seventh inverter INV6.

[0130] The source of the twelfth PMOS transistor MP9 is connected to the source of the eleventh NMOS transistor MN10, the drain of the ninth PMOS transistor MP8, and the input of the ninth inverter INV7.

[0131] The output terminal of the seventh inverter INV6 is connected to the drain of the twelfth PMOS transistor MP9 and the drain of the eleventh NMOS transistor MN10, and outputs the differential signal VOUTQ.

[0132] The output terminal of the ninth inverter INV7 is connected to the drain of the seventh PMOS transistor MP6 and the source of the twelfth NMOS transistor MN11, and outputs the differential signal VOUTO.

[0133] The input terminals of the seventh inverter INV6 and the ninth inverter INV7 are cross-coupled to each other's output nodes, that is, the input terminal of INV6 is connected to the output terminal (VOUT0) of INV7, and the input terminal of INV7 is connected to the output terminal (VOUTQ) of INV6, thereby forming a second-stage positive feedback loop.

[0134] The differential signal VOUTQ and the differential signal VOUTO together constitute the second output differential signal.

[0135] When the enable signal VA1 / VA1N is valid, the module is activated and the output signal (voltage / current form of VOUTP / VOUTN) from the first-stage amplification module is further amplified and shaped through the strong positive feedback latch composed of INV6 and INV7, and the second output differential signals VOUTQ and VOUTO are output rail to rail, providing clean input for the digital latch.

[0136] The overall architecture of the third-level positive feedback latch module is as follows: Figure 6 As shown, it includes multiple D flip-flops, which include: a first left-side D flip-flop DFF1, a second left-side D flip-flop DFF2 to a tenth left-side D flip-flop DFF2, a first right-side D flip-flop DFF1, a second right-side D flip-flop DFF2 to a tenth right-side D flip-flop DFF2.

[0137] All the data input terminals D of the left-side D flip-flops receive the differential signal VOUTQ, and all the data input terminals D of the right-side D flip-flops receive the differential signal VOUTO.

[0138] The first clock input CLK1 of the first left-side D flip-flop DFF1 and the first right-side D flip-flop DFF1 receives the reset signal RST, and the second clock input CLK2 receives the most significant bit latch clock signal CLK from the latch clock signal. <9> .

[0139] The first clock input CLK1 of the second left-side D flip-flop DFF2 to the tenth left-side D flip-flop DFF2 and the second right-side D flip-flop DFF2 to the tenth right-side D flip-flop DFF2 sequentially receives CLK from the latched clock signal. <9> To CLK <1> The second clock input CLK2 sequentially receives CLK from the latched clock signal. <8> To CLK <0> To enable cascading triggering.

[0140] Specifically, for the first (i.e., the second most important) D flip-flop DFF2: its first clock input CLK1 receives the latch clock signal CLK. <9> Its second clock input, CLK2, receives the latched clock signal CLK. <8> .

[0141] For the second D flip-flop DFF2: its first clock input CLK1 receives the latch clock signal CLK. <8> Its second clock input, CLK2, receives the latched clock signal CLK. <7> .

[0142] Following this pattern, the CLK1 pin of the subsequent D flip-flops sequentially receives CLK. <7> CLK <6> ... CLK <1> The CLK2 terminal receives CLK sequentially. <6> CLK <5> ... CLK <0> .

[0143] For the last bit (the tenth bit, i.e., the least significant bit) of the D flip-flop DFF2: its first clock input CLK1 receives the latch clock signal CLK. <1> Its second clock input, CLK2, receives the latched clock signal CLK. <0> .

[0144] In short, the first clock terminal CLK1 of the i-th DFF2 (i starts counting from 1, corresponding to bits from the second most significant bit to the least significant bit) receives the latch clock signal CLK<10-i>, and its second clock terminal CLK2 receives the latch clock signal CLK<9-i>.

[0145] This cascaded connection method ensures that the successive approximation logic of the SAR ADC can latch each comparison result into the corresponding D flip-flop in the correct timing.

[0146] The output terminal Q of the first left-side D flip-flop DFF1 outputs the most significant bit digital signal VOP. <9> The outputs Q of the second left-hand D flip-flop DFF2 to the tenth left-hand D flip-flop DFF2 sequentially output the remaining digital signals VOP. <8> To VOP <0> .

[0147] The output terminal Q of the first right-side D flip-flop DFF1 outputs the most significant bit digital signal VON. <9> The outputs Q of the second right-hand D flip-flop DFF2 to the tenth right-hand D flip-flop DFF2 sequentially output the remaining digital signals VON. <8> To VON <0> .

[0148] The key connection for forming the third-level positive feedback latch structure is as follows: the first internal port VO1 of the first left-side D flip-flop DFF1 is connected to the second internal port VO2 of the first right-side D flip-flop DFF1, and the second internal port VO2 of the first left-side D flip-flop DFF1 is connected to the first internal port VO1 of the first right-side D flip-flop DFF1; the first internal port VO1 of each of the second left-side D flip-flops DFF2 to the tenth left-side D flip-flops DFF2 is connected to the second internal port VO2 of the corresponding D flip-flop in the second right-side D flip-flops DFF2 to the tenth right-side D flip-flops DFF2; and the second internal port VO2 of each of the second left-side D flip-flops DFF2 to the tenth left-side D flip-flops DFF2 is connected to the first internal port VO1 of the corresponding D flip-flop in the second right-side D flip-flops DFF2 to the tenth right-side D flip-flops DFF2.

[0149] Under the control of the latch clock CLK<9:0>, this module not only completes the sampling and storage (latching) of the second output differential signal, but also forms a third-level positive feedback network across the differential path between the left and right flip-flops during the latching stage through the cross connection of VO1 and VO2, forcing the output to converge quickly and deterministically to the correct logic state, thus completing the conversion from analog signal to final digital codeword.

[0150] Working principle

[0151] Combination Figure 1 , Figure 3 and Figure 11 The comparator circuit operates as follows within one complete bit cycle:

[0152] Reset Phase: When the externally input comparison clock signal CLK is low, the circuit is in the reset phase. The first PMOS transistor MP0 and the second PMOS transistor MP1 in the first-stage positive feedback module are turned on, pre-charging nodes VP1 and VN1 to high. Simultaneously, the fourth NMOS transistor MN3 and the fifth NMOS transistor MN4 are turned on, resetting the internal positive feedback nodes VP and VN to low, and the outputs VOUTP and VOUTN are also low. At this time, the tenth NMOS transistor MN9 in the second-stage trigger module is turned on, forcing VA1N high and VA1 low, thus disabling the second-stage positive feedback amplification module. The third-stage latch module retains the latch result from the previous cycle.

[0153] Comparison Start-up and First-Stage Amplification: When CLK jumps to a high level, the circuit enters the comparison phase. The first NMOS transistor MN0 is turned on, the first PMOS transistor MP0 and the second PMOS transistor MP1 are turned off, and VP1 and VN1 are pulled down through the second NMOS transistor MN1 and the third NMOS transistor MN2.

[0154] Due to the voltage difference between VIP and VIN, VP1 and VN1 are pulled down at different speeds. During the T1 time period of the timing sequence, due to the conduction of the fifth PMOS transistor MP4 and the sixth PMOS transistor MP5, the first internal positive feedback node VP and the second internal positive feedback node VN are simultaneously pulled up from the low level of the reset phase, forming a brief overlapping rise period. At the end of the T1 time period, the second-stage trigger and clock module generates a valid enable signal VA1 based on the initial speed difference between VP1 and VN1.

[0155] Subsequently, during the Tc time period after VA1 becomes active, the cross-coupled positive feedback pairs within the first stage (the third PMOS transistor MP2, the fourth PMOS transistor MP3, and the sixth NMOS transistor MN5, the seventh NMOS transistor MN6) further amplify and ultimately lock the initial speed difference, causing a sharp divergence in the voltages of VP and VN: the voltage of one node (such as VP) continues to rise rapidly, while the voltage of the other node (such as VN) begins to fall. This final locking process of the first stage is completed within the Tc time period and is executed in parallel with the operation of the second-stage amplification module during this time period. This, in turn, generates large-amplitude, well-defined first output differential signals VOUTP and VOUTN through the inverter chain (INV0-INV3).

[0156] Second-stage triggering and parallel operation: The pull-down speed difference between VP1 and VN1 simultaneously acts on the eleventh PMOS transistor MP11 and the tenth PMOS transistor MP10 of the second-stage triggering module, causing them to compete for conduction, thereby changing the intermediate node voltage and ultimately causing VA1N to jump low and VA1 to jump high. This transition edge is the key timing innovation of this invention. At the instant VA1 goes high, two events are triggered simultaneously and in parallel:

[0157] Event A (Signal Path): Immediately enable the second-stage positive feedback amplifier module. Once activated, this module quickly locks and re-amplifies the output signals of the first stage (represented by the states VOUTP / VOUTN), outputting stable second-stage differential signals VOUTQ and VOUTO.

[0158] Event B (Timing Path): Immediately activate the internal delay circuits of the comparator clock generation module and the SAR logic clock generation module to begin timing for a fixed duration Tc.

[0159] Reset, latch, and cycle completion:

[0160] After a delay of Tc, the comparator clock generation module outputs a drive signal, pulling CLK low from a high level, forcing the circuit to end the comparison phase and begin the next reset phase. The first-stage module then begins its reset process.

[0161] Similarly, after the Tc delay, the SAR logic clock generation module outputs the valid latch clock signal corresponding to the current bit. In the first bit cycle, the output at this time is the most significant bit latch clock CLK. <9> It then becomes high. CLK <9> The high-level signal controls the first left-hand D flip-flop DFF1 and the first right-hand D flip-flop DFF1 in the third-stage positive feedback latch module to enter the latching state. At this time, the stable values ​​of VOUTQ and VOUTO are sampled, and through the third-stage positive feedback network formed by the cross-coupling of the VO1 / VO2 ports inside the D flip-flops and between DFF1, the output bit VOP is latched. <9> and VON <9> It is locked quickly and reliably.

[0162] Meanwhile, CLK remains low, the circuit enters the reset phase, the first and second stage positive feedback modules begin resetting, and the VA1 signal goes low after a delay in Tr. During this reset phase, as the most significant bit latching completes, the SAR logic clock generation module prepares the latch clock for the next bit based on the successive approximation sequence. After the next round of comparison is completed and after another Tc delay, the second most significant bit latch clock CLK... <8> The voltage then goes high, triggering the corresponding second left-hand D flip-flop DFF2 and second right-hand D flip-flop DFF2 to enter latching mode, completing the latching of the second most significant bit. This process repeats sequentially, with the latching clock starting from CLK. <9> To CLK <0> The latches proceed sequentially until all bits are latched.

[0163] The key to this mechanism is that the latching operation of each bit (with an inherent delay of T3) is scheduled to be executed within the reset phase after the comparison of that bit, thus running completely in parallel with the reset process (Tr) of the comparator module, effectively eliminating the serial waiting time required for latching operations in traditional designs.

[0164] This embodiment uses:

[0165] A three-stage fully differential positive feedback loop is constructed: In the first stage (VP / VN nodes are cross-coupled through the third PMOS transistor MP2, the fourth PMOS transistor MP3, the sixth NMOS transistor MN5, and the seventh NMOS transistor MN6), the second stage (VOUTQ / VOUTO nodes are cross-coupled through the seventh inverter INV6 and the ninth inverter INV7), and the third stage (cross-interconnected through the D flip-flop VO1 / VO2 ports), the differential signal pairs are placed in the same positive feedback loop, ensuring that the signal differences can obtain a strong synergistic amplification effect in each stage.

[0166] The design incorporates a fast triggering mechanism based on speed competition: the analog speed information output from the first stage (VP1 / VN1 pull-down speed difference) is used to directly generate a digital enable signal (VA1) through the current competition between the eleventh PMOS transistor MP11 and the tenth PMOS transistor MP10. This replaces the traditional method of waiting for the voltage to be established before triggering subsequent steps, greatly reducing the trigger delay.

[0167] Implement precise parallel timing control: Utilize the rising edge of a single enable signal VA1 to synchronously trigger the signal path (second-stage amplification) and the timing path (clock generation module), so that the working time (T2) of the second-stage amplification module completely overlaps with the fixed delay time (Tc) of the clock generation module, rather than being executed sequentially. Example 2

[0168] This embodiment provides a detailed circuit implementation of the two D flip-flops (DFF1 and DFF2) used in the third-stage positive feedback latch module described in Embodiment 1. By specifically revealing the internal structure of these two customized D flip-flops, the formation mechanism of the third-stage positive feedback latch network is further clarified.

[0169] The specific circuit of D flip-flop DFF1

[0170] The first left-side D flip-flop DFF1 and the first right-side D flip-flop DFF1 have the same internal structure. For example... Figure 7 and Figure 8 As shown, each DFF1 includes a main latch circuit and a clock generation circuit.

[0171] Main latch circuit

[0172] The main latch circuit includes a first transmission gate, a second transmission gate, a third transmission gate, a tenth inverter INV9, an eleventh inverter INV10, a thirteenth inverter INV13, a thirteenth PMOS transistor MP12, and a thirteenth NMOS transistor MN12.

[0173] The first transmission gate is constructed by connecting the sixteenth NMOS transistor MN15 and the sixteenth PMOS transistor MP15 in parallel. The gate of the sixteenth NMOS transistor MN15 receives the first internal clock signal CLK0, and the gate of the sixteenth PMOS transistor MP15 receives the first internal clock inversion signal CLK0N. The sources of the sixteenth NMOS transistor MN15 and the sixteenth PMOS transistor MP15 together form the data input terminal D of the D flip-flop DFF1, and their drains are connected to the input terminal of the tenth inverter INV9, forming the second internal port VO2.

[0174] The output of the tenth inverter INV9 is connected to the inputs of the eleventh inverter INV10 and the thirteenth inverter INV13. The output of the eleventh inverter INV10 constitutes the output Q of the D flip-flop DFF1.

[0175] The source of the thirteenth PMOS transistor MP12 is connected to the power supply voltage VDD, the drain is connected to the second internal port VO2, and the gate is connected to the upper end of the second transmission gate and the drain of the thirteenth NMOS transistor MN12.

[0176] The source of the thirteenth NMOS transistor MN12 is grounded, and its gate is connected to the first clock port CLK1 to receive the reset signal RST.

[0177] The second transmission gate is constructed by connecting the fifteenth NMOS transistor MN14 and the fifteenth PMOS transistor MP14 in parallel. The gate of the fifteenth NMOS transistor MN14 is connected to the second clock terminal CLK2 to receive the most significant bit latch clock signal CLK in the latch clock signal. <9> The gate of the fifteenth PMOS transistor MP14 receives the most significant bit latch clock signal CLK. <9> The inverted signal CLK2N. The sources of the fifteenth NMOS transistor MN14 and the fifteenth PMOS transistor MP14 together form the first internal port VO1, and their drains are connected to the gate of the thirteenth PMOS transistor MP12 and the drain of the thirteenth NMOS transistor MN12.

[0178] The third transmission gate is formed by connecting the fourteenth NMOS transistor MN13 and the fourteenth PMOS transistor MP13 in parallel. The gate of the fourteenth NMOS transistor MN13 receives the inverted signal CLK0N of the first internal clock signal, and the gate of the fourteenth PMOS transistor MP13 receives the first internal clock signal CLK0. The sources of the fourteenth NMOS transistor MN13 and the fourteenth PMOS transistor MP13 are connected to the second internal port VO2, and their drains are connected to the output of the thirteenth inverter INV13.

[0179] Clock generation circuit

[0180] The clock generation circuit includes a twelfth inverter INV11, a fourteenth inverter INV12, and a NOR gate.

[0181] The first input terminal of the NOR gate is connected to the first clock port CLK1 to receive the reset signal RST, and the second input terminal is connected to the second clock port CLK2 to receive the most significant bit latch clock signal CLK. <9> The output of the NOR gate is connected to the input of the twelfth inverter INV11, and outputs the first internal clock inversion signal CLK0N.

[0182] The output of the twelfth inverter INV11 outputs the first internal clock signal CLK0.

[0183] The input of the fourteenth inverter INV12 is connected to the second clock port CLK2 to receive the most significant bit latch clock signal CLK. <9> The output terminal outputs the highest bit latch clock signal CLK. <9> The inverted signal CLK2N.

[0184] Working principle

[0185] like Figure 12 As shown, the operation of DFF1 is divided into three stages:

[0186] Reset Phase: When the reset signal RST received by the first clock terminal CLK1 is high, and the latch clock signal CLK received by the second clock terminal CLK2 is high... <9> When the clock signal is low, the NOR gate in the clock generation circuit outputs a low level, making the first internal clock CLK0 high and its inverted signal CLK0N low; simultaneously, the output CLK2N of the fourteenth inverter INV12 is high. In this state, the first transmission gate is turned off because CLK0 is high and CLK0N is low, disconnecting the data input D; the second transmission gate is turned off because CLK2 is low and CLK2N is high, disconnecting the internal port VO1; the third transmission gate is turned on because CLK0N is low and CLK0 is high, resetting the second internal port VO2 to a high level through the output of the thirteenth inverter INV13, thereby resetting the final output Q to a low level.

[0187] Transmission phase: When RST is low and CLK is high <9> When CLK2 is low, the NOR gate outputs a high level, making CLK0 low, CLK0N high, and CLK2N high. In this state, the first transmission gate is turned on because CLK0 is low and CLK0N is high, and the signal at the data D terminal is transmitted to the internal node VO2, and after being buffered by INV9 and INV10, it affects the output Q; the second transmission gate remains off because CLK2 is low and CLK2N is high; the third transmission gate is off because CLK0N is high and CLK0 is low.

[0188] Latching and positive feedback phase: When RST is low and CLK <9> When the output goes high, the NOR gate outputs a low level, making CLK0 high and CLK0N low; simultaneously, CLK2N goes low. In this state, the first transmission gate is turned off because CLK0 is high and CLK0N is low, completely disconnecting the data input path; the second transmission gate is turned on because CLK2 is high and CLK2N is low, physically connecting VO1 of the left DFF1 with the corresponding VO2 of the right DFF1, thus forming a third-stage positive feedback loop across the differential path between the left and right flip-flops; the third transmission gate is turned on because CLK0N is low and CLK0 is high, forming a local latching feedback within DFF1. The powerful differential positive feedback network and the internal feedback work together to force the outputs of the left and right DFF1 to converge quickly and lock to the final logic state determined by the second output differential signal (VOUTQ / VOUTO) during the transmission phase.

[0189] The specific circuit of D flip-flop DFF2

[0190] The second left-side D flip-flop DFF2 to the tenth left-side D flip-flop DFF2 and the corresponding right-side D flip-flop DFF2 have the same internal structure. For example... Figure 9 and Figure 10 As shown, each DFF2 includes a main latch circuit and a clock generation circuit.

[0191] Main latch circuit

[0192] The main latch circuit includes a first transmission gate, a second transmission gate, a third transmission gate, a fifteenth inverter INV14, a sixteenth inverter INV15, a seventeenth inverter INV16, a twentieth PMOS transistor MP19, and a twentieth NMOS transistor MN19.

[0193] The first transmission gate is constructed by connecting the nineteenth NMOS transistor MN18 and the nineteenth PMOS transistor MP18 in parallel. The gate of the nineteenth NMOS transistor MN18 receives the first internal clock inversion signal CLK0N, and the gate of the nineteenth PMOS transistor MP18 receives the first internal clock signal CLK0. The sources of the nineteenth NMOS transistor MN18 and the nineteenth PMOS transistor MP18 together form the data input terminal D of the D flip-flop DFF2, and their drains are connected to the input terminal of the fifteenth inverter INV14, forming the second internal port VO2.

[0194] The output of the fifteenth inverter INV14 is connected to the inputs of the sixteenth inverter INV15 and the seventeenth inverter INV16. The output of the sixteenth inverter INV15 constitutes the output Q of the D flip-flop DFF2.

[0195] The source of the twentieth PMOS transistor MP19 is connected to the power supply voltage VDD, the drain is connected to the second internal port VO2, and the gate is connected to the upper end of the second transmission gate and the drain of the twentieth NMOS transistor MN19.

[0196] The source of the twentieth NMOS transistor MN19 is grounded, and its gate receives the signal CLK1N.

[0197] The second transmission gate is formed by a parallel connection of an eighteenth NMOS transistor MN17 and an eighteenth PMOS transistor MP17. The gate of the eighteenth NMOS transistor MN17 is connected to the second clock port CLK2 to receive the latched clock signal, and the gate of the eighteenth PMOS transistor MP17 receives the signal CLK2N. The sources of the eighteenth NMOS transistor MN17 and the eighteenth PMOS transistor MP17 together form the first internal port VO1, and their drains are connected to the gate of the twentieth PMOS transistor MP19 and the drain of the twentieth NMOS transistor MN19.

[0198] The third transmission gate is formed by connecting the seventeenth NMOS transistor MN16 and the seventeenth PMOS transistor MP16 in parallel. The gate of the seventeenth NMOS transistor MN16 receives the first internal clock signal CLK0, and the gate of the seventeenth PMOS transistor MP16 receives the first internal clock inversion signal CLK0N. The sources of the seventeenth NMOS transistor MN16 and the seventeenth PMOS transistor MP16 are connected to the second internal port VO2, and their drains are connected to the output of the seventeenth inverter INV16.

[0199] Clock generation circuit

[0200] The clock generation circuit includes an eighteenth inverter INV17, a nineteenth inverter INV18, a twentieth inverter INV19, and a NAND gate.

[0201] The input of the nineteenth inverter INV18 is connected to the second clock port CLK2, and the output of the inverter CLK2N is connected to the first input of the NAND gate.

[0202] The second input terminal of the NAND gate is connected to the first clock port CLK1.

[0203] The first clock port CLK1 is also connected to the input terminal of the eighteen inverters INV17, and the output terminal of the eighteen inverters INV17 outputs the signal CLK1N.

[0204] The output of the NAND gate outputs the first internal clock inverted signal CLK0N, and is connected to the input of the twentieth inverter INV19.

[0205] The output of the twentieth inverter INV19 outputs the first internal clock signal CLK0.

[0206] Furthermore, the signal CLK1N is the inverted signal of the signal received by the first clock port CLK1; the signal CLK2N is the inverted signal of the signal received by the second clock port CLK2.

[0207] Working principle

[0208] like Figure 13 As shown, DFF2 also operates in three stages, but its clock control logic differs from that of DFF1 to accommodate cascading triggering requirements:

[0209] Reset Phase: When the first clock input CLK1 is low and the second clock input CLK2 is low, in the clock generation circuit, the output CLK1N of the 18th inverter INV17 is high, and the output CLK2N of the 19th inverter INV18 is high. The two inputs of the NAND gate (CLK1 low, CLK2N high) make its output high, that is, the first internal clock inversion signal CLK0N is high. After this high level is inverted by the 20th inverter INV19, the first internal clock signal CLK0 is low. In this state, the first transmission gate is turned off because CLK0 is low and CLK0N is high; the second transmission gate is turned off because CLK2 is low and CLK2N is high; the third transmission gate is turned on because CLK0 is low and CLK0N is high, resetting the second internal port VO2 to high level through the output of the 17th inverter INV16, thereby resetting the output Q to low level.

[0210] Transmission Phase: When CLK1 is high and CLK2 is low, CLK1N is low and CLK2N is high. The NAND gate outputs a low level because its inputs CLK1 and CLK2N are high, therefore CLK0N is low and CLK0 is high. In this state, the first transmission gate is turned on because CLK0 is high and CLK0N is low, and the signal at data D is transmitted to internal node VO2, and after being buffered by INV14 and INV15, it affects the output Q; the second transmission gate is turned off because CLK2 is low and CLK2N is high; the third transmission gate is turned off because CLK0 is high and CLK0N is low.

[0211] Latching and Positive Feedback Stage: When CLK1 is high and CLK2 is high, CLK1N is low and CLK2N is low. The NAND gate outputs a high level because its input CLK1 is high and CLK2N is low, thus the first internal clock inverting signal CLK0N is high; after passing through inverter INV19, the first internal clock signal CLK0 is low. At this time, although the internal clock state (CLK0N=high, CLK0=low) is the same as in the reset stage, the key difference is that CLK2 is high (CLK2N is low). In this state, the first transmission gate is turned off because CLK0 is low and CLK0N is high; the second transmission gate is turned on because CLK2 is high and CLK2N is low, thus achieving cross-connection with the internal ports (VO1 / VO2) of the opposite D flip-flop, forming a third-stage positive feedback latch network; the third transmission gate is turned on because CLK0 is low and CLK0N is high, providing internal latching feedback. A strong positive feedback network forces the output to converge and lock quickly. Example 3

[0212] Embodiment 3 of this application provides an electronic device, which includes a three-stage positive feedback comparator circuit based on fast timing as described in Embodiment 1 or Embodiment 2.

[0213] The electronic device may be, but is not limited to, a high-speed, high-precision analog-to-digital converter, a system-on-a-chip, a communication transceiver chip, a front-end acquisition circuit for medical imaging equipment, or a precision test and measurement instrument. The comparator circuit, as a key signal processing unit, can significantly improve the overall performance of the device, especially in applications requiring high-speed, high-precision data conversion.

[0214] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0215] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

[0216] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A three-stage positive feedback comparator circuit based on fast timing, characterized in that, include: The first-stage positive feedback module receives the differential input signal and the comparison clock signal, and switches to the comparison phase under the control of the comparison clock signal; In the comparison phase, the differential input signal is compared and amplified based on the internal first-stage positive feedback loop, and a first intermediate control signal and a first output differential signal are output. The second-level trigger and clock module receives the comparison clock signal and the first intermediate control signal, and is used to generate an enable signal according to the first intermediate control signal, and control the reset of the comparison clock signal and generate a latch clock signal based on the enable signal. The second-stage positive feedback amplification module receives the first output differential signal and the enable signal, and is used to latch and amplify the first output differential signal through its internal second-stage positive feedback loop under the control of the enable signal, and output the second output differential signal. The third-stage positive feedback latch module receives the second output differential signal, the latch clock signal, and the reset signal. Under the control of the latch clock signal, it latches the second output differential signal through the third-stage positive feedback latch network formed by the cross-coupling connection between multiple D flip-flops inside it, and outputs the corresponding digital output signal.

2. The three-stage positive feedback comparator circuit based on fast timing as described in claim 1, characterized in that, The first-stage positive feedback module includes a first NMOS transistor MN0, a second NMOS transistor MN1, a third NMOS transistor MN2, a fourth NMOS transistor MN3, a fifth NMOS transistor MN4, a sixth NMOS transistor MN5, a seventh NMOS transistor MN6, an eighth NMOS transistor MN7, a ninth NMOS transistor MN8, a first PMOS transistor MP0, a second PMOS transistor MP1, a third PMOS transistor MP2, a fourth PMOS transistor MP3, a fifth PMOS transistor MP4, a sixth PMOS transistor MP5, a first inverter INV0, a ​​second inverter INV1, a third inverter INV2, and a fourth inverter INV3; In this configuration, the gate of the first NMOS transistor MN0 receives the comparison clock signal, its source is grounded, and its drain is connected to the sources of the second NMOS transistor MN1 and the third NMOS transistor MN2. The gates of the second NMOS transistor MN1 and the third NMOS transistor MN2 respectively receive the first differential input signal VIP and the second differential input signal VIN, which together constitute the differential input signal. The drain of the second NMOS transistor MN1 is connected to the drain of the first PMOS transistor MP0, the gate of the fifth PMOS transistor MP4, the gate of the eighth NMOS transistor MN7, and the gate of the fourth NMOS transistor MN3, and outputs an intermediate control signal VP1. The drain of the third NMOS transistor MN2 is connected to the drain of the second PMOS transistor MP1, the gate of the sixth PMOS transistor MP5, the gate of the ninth NMOS transistor MN8, and the gate of the fifth NMOS transistor MN4, and outputs an intermediate control signal VN1. The intermediate control signal VP1 and the intermediate control signal VN1 together constitute the first intermediate control signal; The gates of the first PMOS transistor MP0 and the second PMOS transistor MP1 receive the comparison clock signal, and their sources are connected to the power supply voltage. The sources of the third PMOS transistor MP2 and the fourth PMOS transistor MP3 are respectively connected to the drains of the fifth PMOS transistor MP4 and the sixth PMOS transistor MP5; the sources of the fifth PMOS transistor MP4 and the sixth PMOS transistor MP5 are connected to the power supply voltage; the drain of the third PMOS transistor MP2 is connected to the gate of the fourth PMOS transistor MP3, the gate of the seventh NMOS transistor MN6, the drain of the sixth NMOS transistor MN5, the drain of the fourth NMOS transistor MN3, and the input terminal of the second inverter INV1, forming a first internal positive feedback node; the drain of the fourth PMOS transistor MP3 is connected to the gate of the third PMOS transistor MP2, the gate of the sixth NMOS transistor MN5, the drain of the seventh NMOS transistor MN6, the drain of the fifth NMOS transistor MN4, and the input terminal of the first inverter INV0, forming a second internal positive feedback node. A first internal positive feedback signal VP is generated at the first internal positive feedback node, and a second internal positive feedback signal VN is generated at the second internal positive feedback node; The sources of the sixth NMOS transistor MN5 and the seventh NMOS transistor MN6 are grounded; the sources of the fourth NMOS transistor MN3 and the fifth NMOS transistor MN4 are grounded. The sources of the eighth NMOS transistor MN7 and the ninth NMOS transistor MN8 are grounded, and their drains are connected to the sources of the third PMOS transistor MP2 and the fourth PMOS transistor MP3, respectively. The output terminal of the first inverter INV0 is connected to the input terminal of the third inverter INV2, and the output terminal of the third inverter INV2 outputs a differential signal VOUTN; the output terminal of the second inverter INV1 is connected to the input terminal of the fourth inverter INV3, and the output terminal of the fourth inverter INV3 outputs a differential signal VOUTP. The differential signals VOUTN and VOUTP together constitute the first output differential signal.

3. The three-stage positive feedback comparator circuit based on fast timing as described in claim 1, characterized in that, The second-stage trigger and clock module includes an eleventh PMOS transistor MP11, a tenth PMOS transistor MP10, a tenth NMOS transistor MN9, a fifth inverter INV4, a sixth inverter INV5, an eighth inverter INV8, a comparator clock generation module, and a SAR logic clock generation module. The gates of the eleventh PMOS transistor MP11 and the tenth PMOS transistor MP10 respectively receive the intermediate control signal VP1 and the intermediate control signal VN1, and their sources jointly receive the comparison clock signal. The gate of the tenth NMOS transistor MN9 is connected to the output terminal of the eighth inverter INV8, and its source is grounded; the drains of the eleventh PMOS transistor MP11 and the tenth PMOS transistor MP10 are connected to the input terminal of the fifth inverter INV4 together with the drain of the tenth NMOS transistor MN9. The input terminal of the eighth inverter INV8 receives the comparison clock signal; The output of the fifth inverter INV4 is connected to the input of the sixth inverter INV5 and outputs a first internal enable signal VA1N; the output of the sixth inverter INV5 outputs a second internal enable signal VA1. The first internal enable signal VA1N and the second internal enable signal VA1 together constitute the enable signal; The input terminal of the comparator clock generation module receives the second internal enable signal VA1, and its output terminal is connected to the comparison clock signal node to control the reset of the comparison clock signal. The input terminal of the SAR logic clock generation module receives the second internal enable signal VA1, and the output terminal outputs the latch clock signal.

4. The three-stage positive feedback comparator circuit based on fast timing as described in claim 1, characterized in that, The second-stage positive feedback amplification module includes the seventh PMOS transistor MP6, the eighth PMOS transistor MP7, the ninth PMOS transistor MP8, the twelfth PMOS transistor MP9, the eleventh NMOS transistor MN10, the twelfth NMOS transistor MN11, the seventh inverter INV6, and the ninth inverter INV7; The gates of the seventh PMOS transistor MP6 and the twelfth PMOS transistor MP9 receive the first internal enable signal VA1N, and the gates of the eighth PMOS transistor MP7 and the ninth PMOS transistor MP8 receive the second internal enable signal VA1. The source of the eighth PMOS transistor MP7 and the ninth PMOS transistor MP8 are connected to the power supply voltage. The gates of the eleventh NMOS transistor MN10 and the twelfth NMOS transistor MN11 receive the second internal enable signal VA1; The source of the seventh PMOS transistor MP6 is connected to the drain of the twelfth NMOS transistor MN11, the drain of the eighth PMOS transistor MP7, and the input of the seventh inverter INV6. The source of the twelfth PMOS transistor MP9 is connected to the source of the eleventh NMOS transistor MN10, the drain of the ninth PMOS transistor MP8, and the input of the ninth inverter INV7. The output terminal of the seventh inverter INV6 is connected to the drain of the twelfth PMOS transistor MP9 and the drain of the eleventh NMOS transistor MN10, and outputs a differential signal VOUTQ. The output terminal of the ninth inverter INV7 is connected to the drain of the seventh PMOS transistor MP6 and the source of the twelfth NMOS transistor MN11, and outputs a differential signal VOUTO. The differential signal VOUTQ and the differential signal VOUTO together constitute the second output differential signal; The input terminals of the seventh inverter INV6 and the ninth inverter INV7 are cross-coupled to each other's output nodes, forming a second-stage positive feedback loop.

5. The three-stage positive feedback comparator circuit based on fast timing as described in claim 1, characterized in that, The third-level positive feedback latch module includes multiple D flip-flops, which include: a first left-side D flip-flop DFF1, a second left-side D flip-flop DFF2 to a tenth left-side D flip-flop DFF2, a first right-side D flip-flop DFF1, a second right-side D flip-flop DFF2 to a tenth right-side D flip-flop DFF2; Wherein, the data input terminal D of all the left-side D flip-flops receives the differential signal VOUTQ, and the data input terminal D of all the right-side D flip-flops receives the differential signal VOUTO; The first clock input CLK1 of the first left-side D flip-flop DFF1 and the first right-side D flip-flop DFF1 receives the reset signal RST, and the second clock input CLK2 receives the most significant bit latch clock signal CLK from the latch clock signal. <9> ; The first clock input CLK1 of the second left-side D flip-flop DFF2 to the tenth left-side D flip-flop DFF2 and the second right-side D flip-flop DFF2 to the tenth right-side D flip-flop DFF2 sequentially receives the CLK from the latched clock signal. <9> To CLK <1> The second clock terminal CLK2 sequentially receives CLK from the latched clock signal. <8> To CLK <0> This allows for cascading triggering. The output terminal Q of the first left-side D flip-flop DFF1 outputs the most significant bit digital signal VOP. <9> The outputs Q of the second left-hand D flip-flop DFF2 to the tenth left-hand D flip-flop DFF2 sequentially output the remaining digital signals VOP. <8> To VOP <0> ; The output terminal Q of the first right-side D flip-flop DFF1 outputs the most significant bit digital signal VON. <9> The outputs Q of the second right-hand D flip-flop DFF2 to the tenth right-hand D flip-flop DFF2 sequentially output the remaining digital signals VON. <8> To VON <0> ; The digital signal VOP <9> To VOP <0> and VON <9> To VON <0> Together they constitute the digital output signal; The first internal port VO1 of the first left-side D flip-flop DFF1 is connected to the second internal port VO2 of the first right-side D flip-flop DFF1, and the second internal port VO2 of the first left-side D flip-flop DFF1 is connected to the first internal port VO1 of the first right-side D flip-flop DFF1. The first internal port VO1 of each of the second left-hand D flip-flops DFF2 to the tenth left-hand D flip-flops DFF2 is connected to the second internal port VO2 of the corresponding D flip-flops in the second right-hand D flip-flops DFF2 to the tenth right-hand D flip-flops DFF2; the second internal port VO2 of each of the second left-hand D flip-flops DFF2 to the tenth left-hand D flip-flops DFF2 is connected to the first internal port VO1 of the corresponding D flip-flops in the second right-hand D flip-flops DFF2 to the tenth right-hand D flip-flops DFF2. The third-stage positive feedback latch module is formed between the left-side D flip-flop and the corresponding right-side D flip-flop through the cross connection of the internal ports VO1 and VO2.

6. The three-stage positive feedback comparator circuit based on fast timing according to claim 5, characterized in that, Both the first left-side D flip-flop DFF1 and the first right-side D flip-flop DFF1 include a main latch circuit and a clock generation circuit. The main latch circuit includes a first transmission gate, a second transmission gate, a third transmission gate, a tenth inverter INV9, an eleventh inverter INV10, a thirteenth inverter INV13, a thirteenth PMOS transistor MP12, and a thirteenth NMOS transistor MN12. The clock generation circuit includes a twelfth inverter INV11, a fourteenth inverter INV12, and a NOR gate. The first transmission gate is composed of a sixteenth NMOS transistor MN15 and a sixteenth PMOS transistor MP15 connected in parallel. The gate of the sixteenth NMOS transistor MN15 receives the first internal clock signal CLK0, and the gate of the sixteenth PMOS transistor MP15 receives the first internal clock inversion signal CLK0N. The sources of the sixteenth NMOS transistor MN15 and the sixteenth PMOS transistor MP15 together form the data input terminal D of the D flip-flop DFF1. The drains of the two are connected to the input terminal of the tenth inverter INV9 and form the second internal port VO2 of the D flip-flop DFF1. The output of the tenth inverter INV9 is connected to the input of the eleventh inverter INV10 and the thirteenth inverter INV13; the output of the eleventh inverter INV10 constitutes the output Q of the D flip-flop DFF1. The source of the thirteenth PMOS transistor MP12 is connected to the power supply voltage, the drain is connected to the second internal port VO2, and the gate is connected to the upper end of the second transmission gate and the drain of the thirteenth NMOS transistor MN12. The source of the thirteenth NMOS transistor MN12 is grounded, and its gate is connected to the first clock terminal CLK1 to receive the reset signal RST. The second transmission gate is composed of a fifteenth NMOS transistor MN14 and a fifteenth PMOS transistor MP14 connected in parallel. The gate of the fifteenth NMOS transistor MN14 is connected to the second clock terminal CLK2 to receive the most significant bit latch clock signal CLK in the latch clock signal. <9> The gate of the fifteenth PMOS transistor MP14 receives the most significant bit latch clock signal CLK. <9> The inverted signal CLK2N, the source of the fifteenth NMOS transistor MN14 and the fifteenth PMOS transistor MP14 together form the first internal port VO1, and the drain of both are connected to the gate of the thirteenth PMOS transistor MP12 and the drain of the thirteenth NMOS transistor MN12. The third transmission gate is formed by the fourteenth NMOS transistor MN13 and the fourteenth PMOS transistor MP13 connected in parallel. The gate of the fourteenth NMOS transistor MN13 receives the first internal clock inverted signal CLK0N, and the gate of the fourteenth PMOS transistor MP13 receives the first internal clock CLK0. The sources of the fourteenth NMOS transistor MN13 and the fourteenth PMOS transistor MP13 are connected to the second internal port VO2, and the drains are connected to the output terminal of the thirteenth inverter INV13. In the clock generation circuit, the first input terminal of the NOR gate is connected to the first clock terminal CLK1 to receive the reset signal RST, and the second input terminal is connected to the second clock terminal CLK2 to receive the most significant bit latch clock signal CLK. <9> The output terminal is connected to the input terminal of the twelfth inverter INV11 and outputs the first internal clock inversion signal CLK0N; the output terminal of the twelfth inverter INV11 outputs the first internal clock CLK0; the input terminal of the fourteenth inverter INV12 is connected to the second clock terminal CLK2 to receive the most significant bit latched clock signal CLK. <9> The output terminal outputs the highest bit latch clock signal CLK. <9> The inverted signal CLK2N.

7. The three-stage positive feedback comparator circuit based on fast timing as described in claim 5, characterized in that, The second left-side D flip-flop DFF2 to the tenth left-side D flip-flop DFF2 and the second right-side D flip-flop DFF2 to the tenth right-side D flip-flop DFF2 all include a main latch circuit and a clock generation circuit. The main latch circuit includes a first transmission gate, a second transmission gate, a third transmission gate, a fifteenth inverter INV14, a sixteenth inverter INV15, a seventeenth inverter INV16, a twentieth PMOS transistor MP19, and a twentieth NMOS transistor MN19. The clock generation circuit includes an eighteenth inverter INV17, a nineteenth inverter INV18, a twentieth inverter INV19, and a NAND gate; The first transmission gate is composed of the nineteenth NMOS transistor MN18 and the nineteenth PMOS transistor MP18 connected in parallel. The gate of the nineteenth NMOS transistor MN18 receives the first internal clock inversion signal CLK0N, and the gate of the nineteenth PMOS transistor MP18 receives the first internal clock signal CLK0. The sources of the nineteenth NMOS transistor MN18 and the nineteenth PMOS transistor MP18 together form the data input terminal D of the D flip-flop DFF2. The drains of the two are connected to the input terminal of the fifteenth inverter INV14 and form the second internal port VO2. The output of the fifteenth inverter INV14 is connected to the input of the sixteenth inverter INV15 and the seventeenth inverter INV16; the output of the sixteenth inverter INV15 constitutes the output Q of the D flip-flop DFF2; The source of the twentieth PMOS transistor MP19 is connected to the power supply voltage, the drain is connected to the second internal port VO2, and the gate is connected to the upper end of the second transmission gate and the drain of the twentieth NMOS transistor MN19. The source of the twentieth NMOS transistor MN19 is grounded, and its gate receives the signal CLK1N. The second transmission gate is formed by the parallel connection of the eighteenth NMOS transistor MN17 and the eighteenth PMOS transistor MP17. The gate of the eighteenth NMOS transistor MN17 is connected to the second clock terminal CLK2 to receive the latch clock signal. The gate of the eighteenth PMOS transistor MP17 receives the signal CLK2N. The sources of the eighteenth NMOS transistor MN17 and the eighteenth PMOS transistor MP17 together form the first internal port VO1. The drains of the two are connected to the gate of the twentieth PMOS transistor MP19 and the drain of the twentieth NMOS transistor MN19. The third transmission gate is composed of the seventeenth NMOS transistor MN16 and the seventeenth PMOS transistor MP16 connected in parallel. The gate of the seventeenth NMOS transistor MN16 receives the first internal clock signal CLK0, and the gate of the seventeenth PMOS transistor MP16 receives the first internal clock inversion signal CLK0N. The sources of the seventeenth NMOS transistor MN16 and the seventeenth PMOS transistor MP16 are connected to the second internal port VO2, and the drains are connected to the output terminal of the seventeenth inverter INV16. In the clock generation circuit, the input of the nineteenth inverter INV18 is connected to the second clock terminal CLK2, and the output terminal is the output signal CLK2N, which is connected to the first input of the NAND gate; the second input of the NAND gate is connected to the first clock terminal CLK1; the first clock terminal CLK1 is also connected to the input of the eighteenth inverter INV17, and the output of the eighteenth inverter INV17 outputs the signal CLK1N; the output of the NAND gate outputs the first internal clock inverted signal CLK0N and is connected to the input of the twentieth inverter INV19, and the output of the twentieth inverter INV19 outputs the first internal clock CLK0.

8. The three-stage positive feedback comparator circuit based on fast timing according to claim 7, characterized in that, The signal CLK1N is the inverted signal of the signal received by the first clock terminal CLK1; the signal CLK2N is the inverted signal of the signal received by the second clock terminal CLK2.

9. The three-stage positive feedback comparator circuit based on fast timing according to claim 2, characterized in that, The comparator circuit is configured as follows: When the comparison clock signal is low, the first-stage positive feedback module is in the reset phase, and the first intermediate control signal output by it is maintained at a high level; the enable signal output by the second-stage trigger and clock module is invalid, the second-stage positive feedback amplification module is disabled, and the third-stage positive feedback latch module maintains its latching state. When the comparison clock signal jumps from low level to high level, the first stage positive feedback module enters the comparison phase and responds based on the voltage difference between the differential input signals, so that the intermediate control signal VP1 and intermediate control signal VN1 output by it are pulled down from high level at different speeds. The second-level trigger and clock module generates an effective enable signal based on the pull-down speed difference between the intermediate control signal VP1 and the intermediate control signal VN1; When the enable signal is valid, the following operations are performed simultaneously: the second-stage positive feedback amplification module is started to latch and amplify the first output differential signal, and the comparator clock generation module and SAR logic clock generation module inside the second-stage trigger and clock module are started to start timing. After a fixed delay, the comparator clock generation module pulls the comparison clock signal low from high level, and at the same time, the SAR logic clock generation module outputs a valid latch clock signal. When the comparison clock signal goes low again, the first-stage positive feedback module enters the reset phase again. At the same time, the third-stage positive feedback latch module latches the second output differential signal output by the second-stage positive feedback amplifier module under the control of the latch clock signal.

10. An electronic device, characterized in that, Includes a three-stage positive feedback comparator circuit based on fast timing as described in any one of claims 1 to 9.

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