Improved current sensing and regulation for stepper motor drives

Abstract

An integrated circuit (100A) includes an H-bridge circuit (102) having a first output node (OUT1) for coupling to the high-side terminal of an inductor (103) and a second output node (OUT2) for coupling to the low-side terminal of the inductor. A current-sensing FET (SNS-DRV) is coupled between a current source (110) and a lower supply voltage to provide a reference current (Itrip), including a peak current limit at the sensing node. A current-sensing comparator (104) has a first input coupled to the sensing node, a second input coupled to the second output node, and an output (113) coupled to send an output signal to a driver control circuit. A FET linearity detection circuit (112) is coupled to receive the gate voltage (LS2) of an active low-side power FET (Mls2) and has an output (CMP EN) coupled to enable the current-sensing comparator when the active low-side power FET operates in the linear region.

Description

Background Technology

[0001] In a stepper motor, the motor position is controlled by adjusting the current in two or more motor windings. Different stepper motor designs can have different numbers of windings, with the current waveform in each winding leading or lagging behind the current waveforms associated with the other windings. While many aspects of current regulation are well understood, problematic control areas remain. Summary of the Invention

[0002] The disclosed embodiments provide a FET linearity detection circuit that tracks the gate voltage on an active low-side power FET to determine when blanking is turned off and a current-sensing comparator is enabled. The current-sensing comparator can be enabled when the active low-side power FET is in the linear region. In one embodiment, the current-sensing comparator is enabled when the voltage on the gate of the active low-side power FET is greater than a threshold voltage lower than the digital upper limit supply voltage.

[0003] In one aspect, an embodiment of an integrated circuit is disclosed. The integrated circuit includes: an H-bridge circuit comprising a first high-side power field-effect transistor (FET) coupled in series with a first low-side power FET between a motor supply voltage and a lower supply voltage, and a second high-side power FET coupled in series with a second low-side power FET between the motor supply voltage and the lower supply voltage; a first output node between the first high-side power FET and the first low-side power FET for coupling to a high-side terminal of an inductor; and a second output node between the second high-side power FET and the second low-side power FET for coupling to a low-side terminal of an inductor; a current-sensing FET coupled between a current source and the lower supply voltage to provide a reference current, the reference current including a peak current limit at a sensing node between the current source and the current-sensing FET; a current-sensing comparator including a first input coupled to the sensing node, a second input coupled to the second output node, and an output coupled to send an output signal to a driver control circuit; and a FET linearity detection circuit coupled to receive the gate voltage of the second low-side power FET and having an output coupled to enable the current-sensing comparator when the second low-side power FET operates in the linear region.

[0004] In another aspect, an embodiment of a system is disclosed. The system includes: a stepper motor having a first inductor and a second inductor; a first H-bridge circuit including a first high-side power FET coupled in series with a first low-side power FET between a motor power supply voltage and a lower power supply voltage, and a second high-side power FET coupled in series with a second low-side power FET between the motor power supply voltage and the lower power supply voltage; a first output node between the first high-side power FET and the first low-side power FET for coupling to a high-side terminal of the first inductor; and a second output node between the second high-side power FET and the second low-side power FET for coupling to a low-side terminal of the first inductor; and a first current inductor. The device comprises: a current sensing FET coupled between a current source and a lower supply voltage to provide a reference current, the reference current including a peak current limit at a first sensing node between the current source and the first current sensing FET; a first current sensing comparator including a first input coupled to the first sensing node, a second input coupled to a second output node, and an output coupled to send an output signal to a driver control circuit; and a first FET linearity detection circuit coupled to receive the gate voltage of a second low-side power FET and having an output coupled to enable the first current sensing comparator when the second low-side power FET operates in the linear region.

[0005] In another aspect, an embodiment of a method for operating a stepper motor is disclosed. The method includes: attaching a first output node in an H-bridge circuit to a high-side terminal of an inductor, the first output node being located between a first high-side power FET coupled to a motor power supply voltage and a first low-side power FET coupled to a lower power supply voltage; attaching a second output node in the H-bridge circuit to a low-side terminal of an inductor, the second output node being located between a second high-side power FET coupled to a motor power supply voltage and a second low-side power FET coupled to a lower power supply voltage; and when the H-bridge circuit is operating in a drive mode, tracking the gate voltage on the second low-side power FET to determine when the second low-side power FET is operating in a linear region, and when the second low-side power FET is operating in a linear region, enabling a first current-sensing comparator coupled to compare the current at the second output node with a peak current limit. Attached Figure Description

[0006] Embodiments of this disclosure are shown by way of example and not by way of limitation in the accompanying drawings, wherein similar reference numerals indicate similar elements. It should be noted that different references to “an” or “one” embodiments in this disclosure do not necessarily refer to the same embodiment, and such references may mean at least one. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is assumed that such a feature, structure, or characteristic, in combination with other embodiments, is implemented within the knowledge of those skilled in the art, whether or not it is explicitly described. As used herein, the term “coupled” is intended to mean an indirect or direct electrical connection, and unless limited to “communicatively coupled,” it may include a wireless connection. Thus, if a first device is coupled to a second device, the connection may be via a direct electrical connection or via an indirect electrical connection via other devices and connections.

[0007] The accompanying drawings are incorporated in and form part of this specification to illustrate one or more exemplary embodiments of this disclosure. Various advantages and features of this disclosure will be understood from the following detailed description, taken in conjunction with the appended claims and with reference to the accompanying drawings, wherein:

[0008] Figure 1A An integrated circuit with an H-bridge circuit and a FET linear detection circuit providing adaptive blanking is shown according to an embodiment of the present disclosure;

[0009] Figure 1B An example of a FET linear detection circuit according to an embodiment of the present disclosure is depicted;

[0010] Figure 1C The voltages on the active low-side power FET and the second output node OUT2 are depicted when the drive mode is started.

[0011] Figure 1D An example of a FET linear detection circuit according to an embodiment of the present disclosure is depicted;

[0012] Figure 1E Depicting by Figure 1A The current regulation device provides timely termination of blanking time and no overshoot;

[0013] Figures 2A-2C A method of operating a stepper motor according to embodiments of the present disclosure is described;

[0014] Figure 3A An H-bridge and a current sensing circuit with current sensing during fast decay mode are shown according to an embodiment of the present disclosure.

[0015] Figure 3BAn H-bridge according to an embodiment of the present disclosure and a current sensing circuit having current sensing during both drive mode and fast decay mode are shown, and drive mode operation is depicted.

[0016] Figure 3C An H-bridge according to an embodiment of the present disclosure and a current sensing circuit having current sensing during both drive mode and fast decay mode are shown, and fast decay mode operation is depicted.

[0017] Figure 4A and Figure 4B The present disclosure describes improvements to inductor current using the disclosed current sensing circuit in several example cases according to embodiments of the present disclosure.

[0018] Figure 5A A method of operating a stepper motor according to embodiments of the present disclosure is described;

[0019] Figure 5B and Figure 5C Additional elements in a method of operating a stepper motor according to embodiments of the present disclosure are described;

[0020] Figure 6 A schematic diagram illustrating a system including a current regulating device according to an embodiment of the present disclosure;

[0021] Figure 7A An example of current control via the current in each of the two coils of a stepper motor and in each step is shown.

[0022] Figure 7B Showing Figure 7A An example of current control within each step of the current graph;

[0023] Figure 8 A baseline implementation of a current regulation circuit that can be used with a stepper motor is described;

[0024] Figure 9 The H-bridge circuit is depicted and the current flow in each of the three phases is shown;

[0025] Figure 10 The inductor current and voltage at the second output node OUT2 are depicted when the H-bridge switches from fast decay mode to drive mode, and it is shown that blanking is required at the start of drive mode.

[0026] Figure 11A It describes the overshoot that may occur when the blanking time is too long;

[0027] Figure 11B A potential overshoot result is described; and

[0028] Figure 12A and Figure 12B The potential problems that may arise from using a fixed decay time are described. Detailed Implementation

[0029] Specific embodiments of the invention will now be described in detail with reference to the accompanying drawings. Numerous specific details are set forth in the following detailed description of embodiments of the invention to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.

[0030] Stepper motor operation

[0031] Stepper motors typically have two coils, or inductors, arranged at a 90-degree angle between them. For smooth operation, the current through each coil needs to have a 90-degree phase separation to generate a rotating magnetic field for the rotor to follow. Although square waves or sine waves can be used to regulate the current in the coils, current regulation using a sine wave profile offers smoother operation and increased position resolution. For the purposes of this disclosure, current regulation in a single winding is referred to as an example of current regulation in each winding.

[0032] In the current implementation, the current waveform in a given motor winding is shaped by the output of a digital-to-analog converter (sine DAC). The DAC output waveform, when viewed at sufficient magnification, is formed in a stepped pattern. For each digital input code (“DAC code”), the ideal DAC maintains the corresponding analog output voltage level. Figure 7A A graph 700A depicts the output current in the two coils of a stepper motor, where coil "A" provides a current Aout following a sine wave and coil "B" provides a current Bout following a cosine wave. In the example shown, each quadrant of the current signal is divided into sixteen (16) steps. Applications requiring higher positional accuracy can utilize larger step numbers, such as 256, 1024, or 4096 microsteps.

[0033] In the case of a stepper motor, each DAC input code results in a different mechanical rotational position of the stepper motor rotor. Therefore, any particular portion of the waveform will rise in steps to increase the current and fall in steps to decrease the current. Once a DAC input code is applied and the winding current reaches a level corresponding to the top of a DAC step rise or the bottom of a DAC step fall, the level of the winding current is regulated to prevent any further mechanical rotation or vibration of the rotor until a different DAC input code is applied. Without this regulation, factors such as variations in power supply voltage and changes in the mechanical load on the stepper motor can cause the winding current to change during the desired step duration.

[0034] At each step in the waveform, such as step 705 circled in curve 700A, multiple pulse width modulation cycles can occur, such as... Figure 7B The curve graph 700B is shown. Curve graph 700B depicts the current, such as current Bout, when current regulation is provided by the driver control unit. In this example, the driver control unit uses a peak current regulation scheme. As the coil is provided with a new rising step, current Bout rises in drive mode until the current regulation circuit can detect that the current has reached a new peak current limit identified as Itrip. The current then decays for a period of time in either a fast decay mode or a slow decay mode; then the drive and decay cycles alternate to maintain the desired current.

[0035] Figure 8 A baseline implementation of a current regulation circuit 800 for an inductor that can be used to drive a stepper motor is depicted. The current regulation circuit 800 includes an H-bridge circuit 802 that includes a first high-side power FET Mhs1 coupled in series with a first low-side power FET Mls1 between a motor supply voltage Vm and a lower supply voltage, which may be ground. A first output node OUT1 is located between the first high-side power FET Mhs1 and the first low-side power FET Mls1. The H-bridge circuit 802 also includes a second high-side power FET Mhs2 coupled in series with a second low-side power FET Mls2 between the motor supply voltage Vm and the lower supply voltage; a second output node OUT2 is located between the second high-side power FET Mhs2 and the second low-side power FET Mls2. During operation, an inductor 803 is coupled between the first output node OUT1 and the second output node OUT2, and the current through the inductor 803 is used to drive, for example, a stepper motor. Corresponding gate control signals HS1, LS1, HS2, and LS2 are provided for the power FETs Mhs1, Mls1, Mhs2, and Mls2.

[0036] The current regulation circuit 800 also includes a digital-to-analog (sine-DAC) circuit 808, a voltage-to-current (V2I) operational amplifier 810, a drive-mode current sensing FET SNS-DRV, a current sensing comparator 804, and a driver control circuit 806. A microstepping indexer 807 has an output coupled to the DAC circuit 808, which is also coupled to receive an analog reference voltage VREF. The output of the DAC circuit 808 is coupled to the input of the V2I operational amplifier 810. The drive-mode current sensing FET SNS-DRV is coupled between the V2I operational amplifier 810 and the lower supply voltage, and the gate of the drive-mode current sensing FET SNS-DRV is coupled to the gate of a second low-side power FET Mls2. A sensing node 812 is located between the V2I operational amplifier 810 and the drive-mode current sensing FET SNS-DRV. The current sensing comparator 804 has a first input coupled to a second output node, a second input coupled to the sensing node 812, and an output coupled to the driver control circuit 806.

[0037] exist Figure 8 In the example shown, the current regulation circuit 800 operates in drive mode, where the first high-side power FET Mhs1 and the second low-side power FET Mls2 are turned on. Inductor current Iout flows from the motor supply voltage Vm through the first high-side power FET Mhs1, inductor 803, and the second low-side power FET Mls2 to the lower supply voltage, thereby increasing the inductor current Iout through inductor 803. During operation, microstepping indexer 807 provides microstepping indexer bits, which are sequences of DAC codes corresponding to the desired shape of the current waveform associated with one or more stepper motor position commands. DAC circuit 808 receives these microstepping indexer bits and an analog reference voltage VREF. DAC circuit 808 converts the current DAC code into an analog voltage setpoint Vtrip, which is provided to V2I operational amplifier 810, which in turn provides the peak current limit Itrip corresponding to the current microstep. Since the drive mode sensing FET SNS_DRV is also turned on during drive mode, sensing node 812 reflects the value of the peak current limit Itrip. The current-sensing comparator 804 compares the current at the second output node OUT2 with the peak current limit Itrip to determine when to shut down the drive mode. The comparison result is sent to the driver control circuit 806, which provides gate control signals HS1, HS2, LS1, and LS2 to control the power FETs in the H-bridge circuit. When the current-sensing comparator 804 detects that the inductor current Iout is greater than the peak current limit Itrip, the drive mode ends and the decay mode begins.

[0038] Figure 9 The H-bridge circuit 900 is depicted, and three conduction modes that can be used to drive a stepper motor are shown: Drive Mode (DRV), Fast Decay Mode (FD), and Slow Decay Mode (SD). In Drive Mode, the first high-side power FET Mhs1 and the second low-side power FET Mls2 are turned on to drive the current from the motor supply voltage Vm through the first high-side power FET Mhs1, inductor 903, and the second low-side power FET Mls2 to the lower supply voltage, as indicated by the solid arrows. The current in inductor 903 ramps up at a rate of Vm / L, where L is the inductance of inductor 903. After the initial blanking period at the start of Drive Mode (explained further below), the current through inductor 903 is compared with the peak current limit Itrip, for example using a comparator (such as the current sensing comparator 804 of the current regulation circuit 800). As previously described, Drive Mode is turned off when the inductor current Iout exceeds the value of the peak current limit Itrip. The H-bridge circuit is then controlled to enter either Fast Decay Mode or Slow Decay Mode.

[0039] In the fast decay mode, the second high-side FET Mhs2 and the first low-side power FET Mls1 are turned on. Due to the inductance of inductor 903, current flows from the lower supply voltage through the first low-side power FET Mls1, inductor 903, and the second high-side power FET Mhs2 to the motor supply voltage Vm, as shown by the dashed arrow, but decays at a slope of -Vm / L. In one embodiment, the fast decay mode operates for a fixed time before re-entering the drive mode.

[0040] In slow decay mode, both the first high-side power FET Mhs1 and the second high-side power FET Mhs2 are turned off, and both the first low-side power FET Mls1 and the second low-side power FET Mls2 are turned on. This allows current to travel in a loop from the lower supply voltage through the first low-side power FET Mls1, inductor 903, and the second low-side power FET Mls2 back to the lower supply voltage, as indicated by the curved arrow. As the name suggests, in slow decay mode, the current through inductor 903 does not decay as rapidly as in fast decay mode.

[0041] Adaptive blanking time

[0042] Although the inductor current Iout can be compared with the peak current limit Itrip immediately after the start of drive mode, an accurate comparison result cannot be obtained immediately due to noise in the circuit. Figure 10This illustrates the problem. Graph 1000 depicts the inductor current Iout and the voltage at the second output node OUT2 during the end of the fast decay mode and the beginning of the drive mode. During the end of the fast decay mode, the inductor current Iout decreases at a steady rate, while the voltage at the output node stabilizes at approximately the motor power supply voltage Vm.

[0043] When the fast decay mode is turned off at time T1, the voltage on the second output node OUT2 drops rapidly to zero, while the inductor current Iout continues to move downward briefly before starting to rise again as the drive mode takes effect. When the voltage on the second output node OUT2 reaches zero, ringing may be present in the signal before the voltage begins to rise.

[0044] In order to achieve Figure 8 The current sensing circuit shown provides accurate measurements. The second low-side power FET Mls2 needs to operate in the linear region, where the voltage at the second output node is close to zero. After the drive mode begins, the second output node OUT2 must be allowed to slew from the motor supply voltage Vm to 0, for example, around time T2, before attempting to sense the current in inductor 803 through the second low-side power FET Mls2. This means the blanking time should always be greater than the driver's transition time.

[0045] Determining an appropriate blanking time has proven difficult, especially when the current regulation system is expected to operate across a range of motor voltages and inductors. Providing a longer blanking time, i.e., waiting a longer period after the start of drive mode before sensing, can in some cases cause the inductor current Iout to exceed the peak current limit Itrip. Figure 11A A graph 1100A depicts an instance of this occurring. The inductor current Iout exceeds the peak current limit Itrip before the blanking time Tblank completes. In some embodiments, such as when the decay time Toff is a fixed value, an excessively long blanking time can lead to loss of regulation and runaway current in subsequent cycles. This problem is more pronounced during regulation of lower current levels and higher motor supply voltage to inductance ratios (i.e., Vm / L). On the other hand, providing an excessively short blanking time can cause the drive mode to shut off prematurely and result in unregulated inductor current Iout. This current distortion makes the motion or stepper motor coarser, leading to vibration, audible noise, and angular errors. An example of this uneven motion is shown in... Figure 11B The curve graph is shown in 1100B.

[0046] While the blanking time of a stepper motor driver depends primarily on the slew rate of the switching node, drivers for stepper motors supporting the automotive and industrial markets are expected to offer a wide range of programmable slew rates, for example, from 10V / μs to 150V / μs, to meet criteria such as lower electromagnetic interference (EMI) and optimal power dissipation. Furthermore, the slew rate can vary by approximately thirty percent (30%) with process and temperature variations.

[0047] Many stepper motor driver circuits use a fixed blanking time, derived from the maximum value of simulation data and dependent on variations in slew rate with process, temperature, device type, and to some extent, the motor supply voltage Vm. Typically, this blanking time is chosen for the worst-case scenario and is therefore longer than required in many other cases. Choosing a blanking time based on the worst-case scenario can lead to current distortion problems and / or current runaway. Some driver circuits have programmable blanking times for both lower and higher currents. At lower current levels, much less noise is generated, thus requiring a lower blanking time to prevent current runaway. However, programmable blanking times place the burden of selecting the blanking time based on the motor being used on the customer.

[0048] Attempting to have a fixed blanking time can lead to numerous problems, as different slew rate options require different blanking times. For a device family, design time and digital logic modifications are extensive to support different blanking times for various slew rates. On some devices, customers can change the slew rate by adjusting the resistor provided on the pin. In this case, programming the blanking time is difficult. A blanking time limit can be selected to accommodate the worst-case corner to prevent false tripping, but this choice will typically result in a blanking time longer than desired and may lead to the aforementioned current distortion problems and / or current runaway.

[0049] Furthermore, due to device modeling limitations, a mismatch between the conversion rate in silicon and the simulated conversion rate can result in functional failures during current sensing. Choosing a higher blanking time imposes limitations on the maximum stepping frequency and maximum rotational speed of the stepper motor. Therefore, optimizing the blanking time is crucial.

[0050] Figure 1AAn H-bridge and current sensing circuit 100A with an adaptive blanking FET linearity detection circuit 112 is depicted according to an embodiment of the present disclosure. The H-bridge and current sensing circuit 100A includes an H-bridge circuit 102 having an inductor 103 coupled between a first output node OUT1 and a second output node OUT2. The H-bridge and current sensing circuit 100A also includes a microstepping indexer 107, a DAC circuit 108, a V2I operational amplifier 110, a drive-mode current sensing FET SNS-DRV, and a current sensing comparator 104. Although not specifically shown in the current sensing circuit 100A, except for the H-bridge receiving the motor voltage Vm, the indexer 107, DAC 108, V2I operational amplifier 110, drive-mode current sensing FET SNS-DRV, current sensing comparator 104, and FET linearity detection circuit 112 are all powered by a digital on-supply voltage DVDD, which in one embodiment is 5V. Microstepping indexer 107 and analog reference voltage VREF are coupled to provide input to DAC circuit 108. The output of DAC circuit 108 is coupled to the input of V2I operational amplifier 110. Drive-mode current sensing FET SNS-DRV is coupled between V2I operational amplifier 110 and the lower supply voltage, and the gate of drive-mode current sensing FET SNS-DRV is coupled to the gate of second low-side power FET M1s2. Sensing node 111 is located between V2I operational amplifier 110 and drive-mode current sensing FET SNS-DRV. Current sensing comparator 104 has a first input coupled to second output node OUT2, a second input coupled to sensing node 111, and an output coupled to provide output signal 113 to driver control circuitry (not specifically shown).

[0051] When the H-bridge and current sensing circuit 100A operate in drive mode, the first high-side power FET Mhs1 and the second low-side power FET Mls2 are turned on and the inductor current Iout flows as indicated by arrow 114. Operation in drive mode continues as previously described, wherein the microstepping indexer 107 provides indexer bits, which are a sequence of DAC codes corresponding to the desired shape of the current waveform. The DAC circuit 108 receives these microstepping indexer bits and an analog reference voltage VREF, converts the current DAC code into an analog voltage setpoint Vtrip, and provides the analog voltage setpoint Vtrip to the V2I operational amplifier 110. During drive mode, the drive-mode current sensing FET SNS-DRV is turned on, causing the V2I operational amplifier 110 to couple to the lower supply voltage to provide a peak current limit Itrip corresponding to the current microstep. Sensing node 111 provides the value of the peak current limit Itrip to the second input node of the current sensing comparator 804, which compares the current at the second output node OUT2 with the peak current limit Itrip. When the current sensing comparator 104 detects that the inductor current Iout is greater than the peak current limit Itrip, the current sensing comparator 104 sends a high value to the driver control circuit, causing the drive mode to end and the decay mode to begin.

[0052] When both low-side power FETs are active, the FET linearity detection circuit operates either with the active low-side power FET in the H-bridge circuit or with the second low-side power FET. The operation of the FET linearity detection circuit during drive mode is described herein; however, embodiments of the FET linearity detection circuit can also operate during fast decay or slow decay modes, as will be discussed further below. In the H-bridge and current sensing circuit 100A, the FET linearity detection circuit 112 is coupled to receive the second low-side gate control signal LS2 as input and provides the comparator enable signal CMP_EN to the current sensing comparator 104. The FET linearity detection circuit 112 provides adaptive blanking by enabling current sensing at the current sensing comparator 104 after the second low-side power FET Mls2 transitions from the “saturation” region to the “linear” region. In one embodiment, the FET linearity detection circuit 112 makes this determination by detecting when the gate of the second low-side power FET LS2 becomes greater than a threshold voltage lower than the digital supply voltage DVDD.

[0053] Figure 1CA graph 100C depicts the voltage across the second low-side gate control signal LS2 and the voltage across the second output node OUT2 when the second low-side power FET Mls2 is turned on; this brief period is divided into three separate time periods. In the first time period, the voltage across the second low-side gate control signal LS2 begins to rise and crosses the threshold voltage Vth, causing the second low-side power FET Mls2 to turn on. In the second time period, the second low-side gate control signal LS2 is at a Miller plateau and does not rise; during the third time period, the second low-side gate control signal LS2 begins to rise again.

[0054] In drive mode, the voltages on both the first high-side gate control signal HS1 and the second low-side gate control signal LS2 go high, and the voltage on the second output node OUT2 transitions from high to low. As shown in graph 100C, the second low-side gate control signal LS2 remains in the Miller plateau region during the transition of the second output node OUT2. The FET linearity detection circuit 112 detects that the voltage has passed the end of the Miller plateau, indicating that the second low-side power FET Mls2 is entering the linear region, and therefore indicating that the blanking time requirement has ended.

[0055] Figure 1B An embodiment of a FET linear sensing circuit 100B is depicted, which can use the knowledge shown in the graph 100C to determine when to enable the comparator enable signal CMP_EN. In the FET linear sensing circuit 100B, a sensing P-type field-effect transistor (PFET) M3 is coupled in series with a current sink 115 between the digital upper supply voltage DVDD and the lower supply voltage. During adaptive blanking used in drive mode, the gate of the sensing PFET M3 is coupled to the gate of a second low-side power FET Mls2 to receive a second low-side gate control signal LS2. A Schmitt trigger 116 is also coupled between the digital upper supply voltage DVDD and the lower supply voltage. The Schmitt trigger has an input coupled to a gate sensing node 118 located between the sensing PFET M3 and the current sink 115, and an output coupled to provide a comparator enable signal CS_EN, which enables the current sensing comparator 104.

[0056] During the operation of the H-bridge and current sensing circuit 100A, when the H-bridge circuit 102 is in fast decay mode, causing the second low-side gate control signal LS2 to be low, the detection PFET M3 turns on and provides current to the current sink 115, which keeps the voltage on the gate sensing node 118 high. The Schmitt trigger 116 generates a low signal on the comparator enable signal CMP_EN, causing the current sensing comparator 104 to be disabled. When the H-bridge circuit 102 starts driving mode, the second low-side gate control signal LS2 begins to rise, and when it reaches a threshold voltage Vt lower than the digital power supply voltage DVDD, the detection PFET M3 turns off. Because the current sink 115 continues to draw current from the gate sensing node 118, the voltage on the gate sensing node 118 will go low, and the Schmitt trigger 116 will provide a high signal on the comparator enable signal CMP_EN, thereby triggering a comparison between the inductor current Iout and the peak current limit Itrip.

[0057] Figure 1D The second low-side control signal LS2 and the comparator enable signal CMP_EN are depicted during the drive mode. Initially, both the second low-side control signal LS2 and the comparator enable signal CMP_EN are low, but as the second low-side power FET Mls2 is turned on, the second low-side control signal LS2 ramps up. When the second low-side control signal LS2 becomes greater than the value of DVDD-Vt, the comparator enable signal CMP_EN goes high, ending blanking and initiating current sensing. When the drive mode ends, the second low-side control signal LS2 falls below DVDD-Vt, the comparator enable signal CMP_EN turns off, and the current sensing comparator 104 is disabled until the next time the second low-side power FET Mls2 is turned on. Therefore, the FET linearity detection circuit 100B, as an example of the FET linearity detection circuit 112, provides an adaptive blanking period independent of the slew rate. The blanking time can be optimized to avoid premature sensing or current runaway.

[0058] Figure 1E An example curve 100E depicts the inductor current Iout when the FET linear sensing circuit 112 is used in conjunction with the H-bridge circuit 102. Unlike curve 1100A, where the inductor current Iout in curve 100E has a excessively long blanking period, curve 1100A shows a reduced blanking period Tblank. This shorter blanking period allows the current sensing comparator 104 to detect in a timely manner that the inductor current Iout has reached the peak current limit Itrip and triggers the start of a fast decay mode. This avoids problems such as current runaway.

[0059] Figure 2AA method 200 for operating a stepper motor according to an embodiment of the present disclosure is described. The method begins by attaching a first output node 205 to a high-side terminal of an inductor and attaching a second output node 210 to a low-side terminal of an inductor in an H-bridge circuit. The first output node is located between a first high-side power FET coupled to a motor power supply voltage and a first low-side power FET coupled to a lower power supply voltage. The second output node is located between a second high-side power FET coupled to a motor power supply voltage and a second low-side power FET coupled to a lower power supply voltage. When the H-bridge circuit operates in drive mode, the gate voltage on the second low-side power FET is tracked 215 to determine when the second low-side power FET operates in the linear region. When the second low-side power FET operates in the linear region, a first current-sensing comparator 220 is enabled. The first current-sensing comparator is coupled to compare the inductor current Iout at the second output node OUT2 with a peak current limit Itrip.

[0060] Although the above description pertains to the operation in drive mode, adaptive blanking can also be used in both slow decay mode and fast decay mode. The operation in slow decay mode is as follows: Figure 2B As shown in the diagram, when the H-bridge circuit operates in slow decay mode, the gate voltage on the second low-side power FET (225) is tracked to determine when the second low-side power FET operates in linear mode. When the second low-side power FET operates in linear mode, the first current-sensing comparator (230) is enabled, which is now coupled to compare the current at the second output node with a first valley current limit.

[0061] like Figure 2C As shown, when the H-bridge circuit operates in fast decay mode, the gate voltage on the first low-side power FET (235) is tracked to determine when the first low-side power FET operates in linear mode. When the first low-side power FET operates in linear mode, the second current-sensing comparator (240) is enabled. The second current-sensing comparator is coupled to compare the current at the first output node combined with a first valley current limit against the lower supply voltage. It will be understood that when the reference current used by the comparator is a hysteretic reference current carrying both the peak current limit (Itrip) and the valley current limit (Ivalley), Figure 2B and Figure 2C The method shown is operable.

[0062] The disclosed FET linear detection circuit and associated method for operating a stepper motor can provide one or more of the following advantages:

[0063] • Independent of the driver's slew rate;

[0064] • Independent of algorithms used for current regulation, such as fixed off time, fixed frequency, ripple control, etc.;

[0065] • Removing fixed timers for each of multiple different conversion rates allows for simplified circuitry, area savings, reduced digital complexity, and shorter design time for product families;

[0066] • By not choosing a pessimistic blanking time, errors in average motor current and current runaway problems are avoided;

[0067] • The minimum drive time is automatically scaled using the output current, and zero-crossing distortion can be mitigated by limiting the drive time at low current steps;

[0068] When the H-bridge circuit transitions from drive mode to slow decay mode, the second output node OUT2 already has a value of zero, preventing a transition. In this case, the FET linear detection circuit 112 already provides a high value, resulting in no blanking time. This response is ideal. Because existing technology does not track the gate voltage, existing circuits would add a blanking time without considering the transition.

[0069] Current sensing in fast decay mode

[0070] When the desired waveform requires decreasing steps, the inductor current Iout needs to decrease to the next lower level at each step. In ripple control schemes, a fast decay mode is activated when a decreasing step occurs to reach the lower level as quickly as possible. However, existing designs do not sense current during the fast decay mode. Instead, after a fixed time in the fast decay mode, the driver enters a drive mode to sense the current.

[0071] Figure 12A A graph 1200A depicts this problem in a motor with high inductance. Graph 1200A depicts the peak current limit Itrip, the inductor current Iout, and the step indicator Step. Initially, the inductor current Iout describes the current when the continuous drive mode drives the current to the value of the peak current limit Itrip, and then allows the current to decay for a fixed amount of time. At time Ta, the step indicator Step provides a pulse to indicate the desired new step, which in the illustrated embodiment is a step down. As the value of the peak current limit Itrip steps down, the inductor current Iout is set to decay for a fixed period of 2μs in a fast decay mode, and then the H-bridge circuit is placed in drive mode for a sufficiently long time to pass the blanking time and measure the inductor current Iout. Therefore, the alternation of the fast decay cycle with the drive mode increases the total time spent reaching the next lower level, instead of the desired rapid decrease to the next lower level. This produces torque ripple.

[0072] like Figure 12B As shown in graph 1200B, low-inductance motors may exhibit different problems. In this case, a fast decay period of 2μs is again utilized. However, each time the step indicator Step provides a pulse and the peak current limit Itrip value decreases, the inductor current Iout decreases much more than expected during the fast decay mode, instead of taking a long time to decay to the next level. This excessive decay results in huge current ripple, which distorts the current waveform. As shown in graphs 1200A and 1200B, the delay-based approach to the fast decay time cannot be optimized across motor parameters.

[0073] The problem shown in graphs 1200A and 1200B is due to the inability to sense the inductor current Iout in fast decay mode. If the current through the motor could be reliably sensed in fast decay mode, the time-based method could be eliminated, and the current could be regulated more precisely. The problem with sensing the inductor current Iout during fast decay mode is that the voltage across the inductor is negative, which presents a challenge for current detection.

[0074] Figure 3A An H-bridge and current sensing circuit 300A is depicted, comprising an H-bridge circuit 301 that receives a motor power supply voltage Vm as an upper power supply voltage and a current sensing circuit 303 that receives a digital power supply voltage DVDD as an upper power supply voltage. The current sensing circuit 303 is coupled to detect a valley current limit during fast decay mode and includes a microstepping indexer 307, a DAC circuit 308, a V2I operational amplifier 310, a fast decay mode current sensing FET SNS-FD, and a current sensing comparator 304. The microstepping indexer 307 and an analog reference voltage VREF are coupled to provide an input to the DAC circuit 308. The DAC circuit 308 is coupled to the input of the V2I operational amplifier 310. The fast decay mode current sensing FET SNS-FD is coupled between the V2I operational amplifier 310 and the first output node OUT1, and the gate of the fast decay mode current sensing FET SNS-FD is coupled to the gate of the first low-side power FET Mls1. Sensing node 311 is located between V2I operational amplifier 310 and fast decay mode current sensing FETSNS-FD. Current sensing comparator 304 has a first input coupled to sensing node 311, a second input coupled to the lower supply voltage, and an output coupled to send output signal 313 to driver control circuitry (not specifically shown).

[0075] Because the current at the first output node OUT1 is negative during the fast decay mode, the current at the first output node OUT1 is added to the valley current limit Ivalley and provided to the first input of the current sensing comparator 304. The combined current sensed at sensing node 311 is compared with the lower supply voltage (e.g., 0V) to detect when the combined current crosses zero. In one embodiment, the H-bridge and current sensing circuit 300A can be combined with the current regulation circuit 800 such that the current sensing comparator 804 is a first current sensing comparator for regulating the current during the drive mode, and the current sensing comparator 104 is a second current sensing comparator for regulating the current during the fast decay mode. With both peak current limit Itrip and valley current limit Ivalley utilized, the current sensing comparator 804 can also be used to sense the current during the slow decay mode when both the first low-side power FET Mls1 and the second low-side power FET Mls2 are turned on.

[0076] Another embodiment of the H-bridge and current sensing circuit 300B Figure 3B and Figure 3C The H-bridge and current sensing circuit 300B1 are shown in the diagram. Figure 3B The diagram shows settings for the drive mode, and the H-bridge and current sensing circuit 300B2 are shown in... Figure 3C The diagram shows a setup for the fast decay mode. Using an H-bridge and current sensing circuit 300B, current sensing can be performed in both drive mode and fast decay mode using a single current sensing comparator 320. Figure 3B and Figure 3C The depicted H-bridge and current sensing circuit 300B is part of an integrated circuit (IC) chip 321 that includes H-bridge circuit 322 and current sensing circuit 324. Four pins on the IC chip 321 are shown in the H-bridge and current sensing circuit 300B, namely pins P1-P4. The first pin P1 can be coupled to the motor power supply voltage Vm to provide the motor power supply voltage to the H-bridge. The second pin P2 is coupled to the first output node OUT1 and can also be coupled to the high-side terminal of the first inductor 326 of the stepper motor 328. The third pin P3 is coupled to the second output node OUT2 and can also be coupled to the low-side terminal of the first inductor 326. The fourth pin P4 is coupled to provide the lower power supply voltage and, in one embodiment, can be coupled to the ground plane. A second copy of the H-bridge and current sensing circuit 300B (not specifically shown) is typically present on the IC chip 321 and can be coupled to the terminal of the second inductor 330 in the stepper motor 328, but will receive a control signal that provides a waveform offset from that of the H-bridge and current sensing circuit 300B.

[0077] The current sensing circuit 324 includes a current source CS1, which is coupled in series with a sensing node SNS-DUAL between the digital supply voltage DVDD and a first switchable node SW1. The first switchable node SW1 can be switchably coupled to a first output node OUT1 or the lower supply voltage. A sensing node 332 is located between the current source CS1 and the first switchable node SW1 and is coupled to a first input of a current sensing comparator 320. A second input of the current sensing comparator 320 is coupled to a second switchable node SW2. The second switchable node SW2 can be switchably coupled to the lower supply voltage or to a second output node OUT2. As will be discussed further below, the current source CS1 provides a hysteresis reference current. At each step in the desired waveform, the current source CS1 is able to provide both a corresponding peak current limit and a corresponding valley current limit.

[0078] like Figure 3B As shown, the H-bridge and current sensing circuit 300B1 operate in drive mode, where current moves through the H-bridge circuit 322 and the first inductor 326 as indicated by arrow 334. The second output node OUT2 provides a second output voltage V2, which is equal to Iout * Rds(on), where Iout is the inductor current and Rds(on) is the source / drain on-resistance of the primary FET, which in drive mode is the second low-side power FET Mls2. The second output node OUT2 is coupled to the second input of the current sensing comparator 320 in drive mode via a second switchable node SW2, and the first switchable node SW1 is coupled to the lower supply voltage. During drive mode, the current source CS1 provides a peak current limit Itrip. The current sensing comparator 320 therefore compares the current at the second output node OUT2 with the peak current limit Itrip, and when the current at the second output node OUT2 becomes greater than the peak current limit Itrip, an output signal 319 is sent to the driver circuit (not specifically shown) to end the drive mode. Although not specifically shown, the configuration in the H-bridge and current sensing circuit 300B1 can also be used to provide adaptive blanking during slow decay mode when both the first low-side FET Mls1 and the second low-side FET Mls2 are active. In this case, the current source CS1 provides a current representing the valley current limit.

[0079] like Figure 3CAs shown, the H-bridge and current sensing circuit 300B2 operate in fast decay mode, where current moves through H-bridge circuit 322 and first inductor 326 as indicated by arrow 336. First output node OUT1 provides a first output voltage V1 equal to –Iout*Rds(on), where again Iout is the inductor current and Rds(on) is the source / drain on-resistance of the primary FET, which in fast decay mode is the first low-side power FET Mls1. In fast decay mode, first output node OUT1 is coupled to the sensing node 332 and the first input of current sensing comparator 320 via a first switchable node SW1, and a second switchable node SW2 is coupled to the lower supply voltage. During fast decay mode, current source CS1 provides a valley current limit Ivalley, such that current sensing comparator 320 compares the combined valley current limit Ivalley on first output node OUT1 with zero, and when the combined current crosses zero, sends an output signal 319 to driver circuitry (not specifically shown) to end fast decay mode.

[0080] Although not specifically shown in these figures, each of the H-bridge and current sensing circuits 300A, 300B may include a FET linear detection circuit to determine when the corresponding current sensing comparator 304, 320 is enabled. Figure 3A In this circuit, the FET linear detection circuit can be coupled to receive the gate voltage on the first low-side power FET Mls1 and coupled to comparator 304 to provide a comparator enable signal. Figure 3B In this circuit, the FET linear detection circuit can be switchably coupled to receive the gate voltage on the first low-side power FET Mls1 during the fast decay mode and the gate voltage on the second low-side power FET Mls2 during the drive mode and the slow decay mode.

[0081] Figure 12A and Figure 12B The problems that may occur when current cannot be sensed in fast decay mode have been described. Figure 4A and Figure 4B The inductor current Iout is depicted when current sensing is used in fast decay mode; Figure 4A Depicting and Figure 12A Similar situations and Figure 4B Depicting and Figure 12B A similar situation. In Figure 4A and Figure 12A Of the two, the motor has high inductance. When each rapid decay period uses 2μs and then switches to drive mode, it results in a slow descent to the new setting. Figure 4AIn this mode, due to the use of current sensing in fast decay mode, the inductor current Iout is able to continue in fast decay mode until it reaches the valley current limit Ivalley, resulting in a faster drop to a new level.

[0082] exist Figure 4B and Figure 12B Of the two, the motor has low inductance. When no current sensing is available during the fixed rapid decay period, the inductor current Iout may drop well below the peak current limit Itrip before the motor switches to drive mode to determine its value. Figure 4B In the fast decay mode, by using valley current limiting and current sensing, the inductor current Iout does not drop below the expected value and can provide smoother operation.

[0083] Figure 5A A method 500A for operating a stepper motor according to an embodiment of the present disclosure is described. Method 500A begins by attaching a first output node 505 to the high-side terminal of an inductor and attaching a second output node 510 to the low-side terminal of an inductor in an H-bridge circuit. The first output node is located between a first high-side power FET coupled to a motor power supply voltage and a first low-side power FET coupled to a lower power supply voltage, and the second output node is located between a second high-side power FET coupled to a motor power supply voltage and a second low-side power FET coupled to a lower power supply voltage.

[0084] Method 500A further includes, during the fast decay mode, coupling a current source 515 to provide valley current limiting, the current source being coupled to a current sensing node, which is also coupled to a first input of a current sensing comparator. The method also includes coupling the current sensing node 520 to a first output node and coupling a second input of the current sensing comparator to a lower supply voltage.

[0085] Method 500A can be used when the H-bridge and current sensing circuit is configured as H-bridge and current sensing circuit 300A or as H-bridge and current sensing circuit 300B. Figure 5B and Figure 5C Additional elements are added to method 500A, but are only utilized when current sensing is performed during both drive mode and fast decay mode using a single current-sensing comparator. In this case, during drive mode, a current source is coupled 525 to provide peak current limiting. The current-sensing node is coupled 530 to the lower supply voltage, and the second input of the current-sensing comparator is coupled to the second output node. During slow decay mode, the current source is coupled 535 to provide valley current limiting; the current-sensing node is coupled 540 to the second output node, and the second input of the current-sensing comparator is coupled to the lower supply voltage.

[0086] Using fast-decaying current sensing provides better current regulation across all variations in motor supply voltage Vm and inductance L. Furthermore, using a single comparator to measure both peak and valley current limits provides increased accuracy in ripple measurement.

[0087] Figure 6 A system 600 is depicted, which may include one or more of H-bridge and current sensing circuits 100A, 300A, 300B1, and 300B2. System 600 includes an IC chip 602 coupled to a drive stepper motor 604 by controlling the inductor current through a first inductor 606 and a second inductor 608. Alternatively, the IC chip may be used to drive bidirectional current through two external loads. In an alternative embodiment, the two external loads are a first brushed DC motor 603 and a second brushed DC motor 605.

[0088] Multiple pins provide inputs and outputs to IC chip 602, although only a few are indicated here. Several first pins P1 are coupled to the motor power supply voltage Vm, and several fourth pins P4 are coupled to the ground plane to provide the lower power supply voltage. Second pin P2 is coupled to the high-side terminal of the first inductor 606, and pin P3 is coupled to the low-side terminal of the first inductor 606. Similarly, fifth pin P5 is coupled to the high-side terminal of the second inductor 608, and sixth pin P6 is coupled to the low-side terminal of the second inductor 608.

[0089] Within IC chip 602, power supply circuit 610 receives motor voltage Vm and distributes power to other circuits on IC chip 602. Power supply circuit 610 may include, for example, a charge pump and a voltage regulator for the digital on-distribution power supply voltage DVDD. Control input circuit 612 receives logic control signals for controlling the H-bridge circuit. These logic control signals may include, for example, enable signals and pulse width modulation (PWM) control. Both power supply circuit 610 and control input circuit 612 are coupled to digital core circuit 616. Digital core circuit 616 is coupled to send control signals to first gate driver circuit 620 and second gate driver circuit 622.

[0090] The first gate driver 620 is coupled to the H-bridge and current sensing circuit 624 to provide control signals for the H-bridge FET and to receive current sensing information. The H-bridge and current sensing circuit 624 is coupled to the high-side terminal of the first inductor 606 via a second pin P2 and to the low-side terminal of the first inductor 606 via a third pin P3. The current sensing element in the H-bridge and current sensing circuit 624 is also coupled to the current sensing comparator 625 for comparison with a first reference voltage Vref1.

[0091] Similarly, the second gate driver 622 is coupled to the H-bridge and current sensing circuit 626 to provide control signals for the associated H-bridge FET and to receive current sensing information. The H-bridge and current sensing circuit 626 is coupled to the high-side terminal of the second inductor 608 via pin 5 P5 and to the low-side terminal of the second inductor 608 via pin 6 P6. The current sensing element in the H-bridge and current sensing circuit 626 is also coupled to the current sensing comparator 627 for comparison with the second reference voltage Vref2.

[0092] IC chip 602 also includes: analog voltage reference input circuitry 614, coupled to receive voltage reference signals for each gate driver; protection circuitry 628, which monitors conditions such as overcurrent, undervoltage, and overtemperature; and fault output circuitry 630, which provides communication of any faults detected by protection circuitry 628. IC chip 602, and more specifically, the H-bridge and current sensing circuitry 624, 626, can be combined with FET linearity detection circuitry to provide adaptive blanking, such as FET linearity detection circuitry 100B. IC chip can also incorporate current sensing, alone or in combination with adaptive blanking, in fast decay mode. The comparator used for current sensing during fast decay mode can be dedicated to current sensing in fast decay mode, as shown in current sensing circuitry 303, or can be shared between drive mode and fast decay mode, as shown in current sensing circuitry 324.

[0093] The applicant has disclosed methods, circuits, systems, and IC chips for providing adaptive blanking that is independent of the driver's slew rate and the algorithm used for current regulation. The applicant has also disclosed methods, circuits, systems, and IC chips for providing current sensing in fast decay mode, enabling faster descent to lower steps without falling below desired steps. Adaptive blanking and current sensing in fast decay mode can be used separately or in combination to provide more robust current sensing. Using these tools, motor operation can be smoother and quieter.

[0094] Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or example. The detailed description above should not be construed as implying that any particular component, element, step, action, or function is essential and must be included within the scope of the claims. Unless expressly stated otherwise, references to singular elements are not intended to mean "one and only one," but rather "one or more." All structural and functional equivalents of the elements of the above embodiments known to those skilled in the art are expressly incorporated herein by reference and are intended to be covered by these claims. Therefore, those skilled in the art will recognize that the exemplary embodiments described herein can be practiced with various modifications and alterations within the spirit and scope of the appended claims.

Claims

1. An integrated circuit comprising: an H-bridge circuit including a first high-side power field effect transistor (FET) coupled in series with a first low-side power FET between a motor supply voltage and a lower supply voltage, and a second high-side power FET coupled in series with a second low-side power FET between the motor supply voltage and the lower supply voltage, a first output node between the first high-side power FET and the first low-side power FET for coupling to a high-side terminal of an inductor, and a second output node between the second high-side power FET and the second low-side power FET for coupling to a low-side terminal of the inductor; a current sense FET coupled between a current source and the lower supply voltage to provide a reference current at a sense node between the current source and the current sense FET, the reference current including a peak current limit; a current sense comparator including a first input coupled to the sense node, a second input coupled to the second output node, and an output coupled to send an output signal to a driver control circuit; and a FET linearity detection circuit coupled to receive a gate voltage of the second low-side power FET, and having an output coupled to enable the current sense comparator when the second low-side power FET is operating in a linear region, wherein the FET linearity detection circuit includes: a detection FET coupled in series with a current sink between a digital upper supply voltage and the lower supply voltage, a gate of the detection FET coupled to the gate of the second low-side power FET; and a Schmitt trigger coupled between the digital upper supply voltage and the lower supply voltage, the Schmitt trigger having an input coupled to a gate sense node between the detection FET and the current sink and having an output coupled to enable the current sense comparator.

2. The integrated circuit of claim 1, wherein the FET linearity detection circuit is coupled to enable the current sense comparator when the gate voltage rises above a value that is one threshold voltage below the digital upper supply voltage.

3. The integrated circuit of claim 1, wherein a gate of the current sense FET is coupled to a gate of the second low-side power FET.

4. The integrated circuit of claim 1, wherein the current source includes a digital-to-analog converter (DAC) coupled to a voltage-to-current operational amplifier coupled to provide the reference current.

5. The integrated circuit of claim 1, wherein the reference current is a hysteresis reference current that further includes a valley current limit.

6. The integrated circuit of claim 5, wherein the FET linearity detection circuit is switchably coupled to a gate of the first low-side power FET to enable the current sense comparator when the first low-side power FET is operating in a linear region.

7. A system comprising: a stepper motor having a first inductor and a second inductor; a first H-bridge circuit including a first high-side power FET coupled in series with a first low-side power FET between a motor supply voltage and a lower supply voltage and a second high-side power FET coupled in series with a second low-side power FET between the motor supply voltage and the lower supply voltage, a first output node between the first high-side power FET and the first low-side power FET for coupling to a high-side terminal of the first inductor, and a second output node between the second high-side power FET and the second low-side power FET for coupling to a low-side terminal of the first inductor; a first current sense FET coupled between a current source and the lower supply voltage to provide a reference current at a first sense node between the current source and the first current sense FET, the reference current including a peak current limit; a first current sense comparator including a first input coupled to the first sense node, a second input coupled to the second output node, and an output coupled to send an output signal to a driver control circuit; and a first FET linearity detection circuit coupled to receive a gate voltage of the second low-side power FET and having an output coupled to enable the first current sense comparator when the second low-side power FET is operating in a linear region, wherein the FET linearity detection circuit includes: a detection FET coupled in series with a current sink between a digital upper supply voltage and the lower supply voltage, a gate of the detection FET coupled to the gate of the second low-side power FET; and a Schmitt trigger coupled between the digital upper supply voltage and the lower supply voltage, the Schmitt trigger having an input coupled to a gate sense node between the detection FET and the current sink and having an output coupled to enable the current sense comparator.

8. The system of claim 7, wherein the current source includes a first digital-to-analog converter (DAC) coupled to provide a first reference voltage and a first operational amplifier coupled to receive the first reference voltage and provide a first reference current.

9. The system of claim 8, wherein the first reference current is a hysteresis reference current that further includes a valley current limit.

10. The system of claim 7, further comprising: a second H-bridge circuit including a third high-side power FET coupled in series with a third low-side power FET between the motor supply voltage and the lower supply voltage and a fourth high-side power FET coupled in series with a fourth low-side power FET between the motor supply voltage and the lower supply voltage, a third output node between the third high-side power FET and the third low-side power FET for coupling to a high-side terminal of the second inductor, and a fourth output node between the fourth high-side power FET and the fourth low-side power FET for coupling to a low-side terminal of the second inductor; a second current sense FET coupled between a second current source and the lower supply voltage to provide a second reference current at a second sense node between the second current source and the second current sense FET, the second reference current comprising a second peak current limit; a second current sense comparator comprising a first input coupled to the second sense node, a second input coupled to the fourth output node, and an output coupled to send a second output signal to the driver control circuit; and a second FET linear detection circuit coupled to receive a gate voltage of the fourth low side power FET and having an output coupled to enable the second current sense comparator when the fourth low side power FET is operating in the linear region.

11. A method of operating a stepper motor, the method comprising: attaching a first output node in an H-bridge circuit to a high side terminal of an inductor, the first output node between a first high side power FET coupled to a motor supply voltage and a first low side power FET coupled to a lower supply voltage; attaching a second output node in the H-bridge circuit to a low side terminal of the inductor, the second output node between a second high side power FET coupled to the motor supply voltage and a second low side power FET coupled to the lower supply voltage; and when the H-bridge circuit is operating in a drive mode, tracking a gate voltage on the second low side power FET to determine when the second low side power FET is operating in a linear region, and when the second low side power FET is operating in the linear region, enabling a first current sense comparator coupled to compare a current at the second output node to a peak current limit, and when the H-bridge circuit is operating in a fast decay mode, tracking the gate voltage on the first low side power FET to determine when the first low side power FET is operating in the linear region, and when the first low side power FET is operating in the linear region, enabling a second current sense comparator coupled to compare a combination of the current at the first output node and a valley current limit to the lower supply voltage.

12. The method of claim 11, further comprising: when the H-bridge circuit is operating in a slow decay mode, tracking the gate voltage on the second low side power FET to determine when the second low side power FET is operating in the linear region, and when the second low side power FET is operating in the linear region, enabling the first current sense comparator coupled to compare the current at the second output node to a valley current limit.

13. The method of claim 11, wherein the first current sense comparator and the second current sense comparator are a single comparator.

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