User-configurable SLC memory size

Abstract

To provide devices and methods for, in storage systems with dynamic single-level cell (SLC) buffers, enabling a user to adjust sizes of the SLC buffers at runtime without interfering with operation of a file system.SOLUTION: An electronic storage system has: one or more substrates; and a controller coupled to the one or more substrates and including logic. The logic is configured to: control 21 access to a NAND-based storage medium 12 that includes a first cell region with a first number of levels and a second region with a second number of levels that is different from the first number of levels; determine 22 logical block address (LBA) locations that correspond to a user-configurable capacity placeholder; and adjust 23 respective sizes of the first cell region and the second cell region at runtime based on the LBA locations.SELECTED DRAWING: Figure 3

Description

[Background technology]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of U.S. Patent Application No. 17 / 231,893, filed April 15, 2021, which is incorporated herein by reference in its entirety.

[0002] A single-level cell (SLC) buffer may include a NAND flash memory (NAND memory) configured with multiple cells, each containing one bit of data. A tri-level cell (TLC) memory may include a NAND memory configured with multiple cells, each containing three bits of data. A quad-level cell (QLC) memory may include a NAND memory configured with multiple cells, each containing four bits of data. The number of bits per cell may generally depend on how many distinct voltage levels are used during program operations associated with writing to, reading from, and / or erasing the cells. Thus, for a TLC memory, to support three bits per cell, eight voltage levels may be used to distinguish between eight possible combinations of ones and zeros (e.g., 000, 001, 010, 011, 100, 101, 110, 111) for writing to the cell.

[0003] Some storage systems include a technology that determines a programmable eviction rate associated with a storage device and converts a portion of the SLC region in the storage device to a multi-level cell (MLC) region according to the programmable eviction rate. MLC may include TLC (e.g., 3-bit or 8-level MLC), QLC (e.g., 4-bit or 16-level MLC), etc. For example, the amount of the portion converted to MLC region varies gradually depending on the percent capacity filled in the storage device.

[0004] Some storage systems may include dynamic SLC memory controller technology, such as a controller that determines, at runtime, the amount of valid data in the dynamic portion of the SLC region and adjusts, at runtime, the size of the dynamic portion of the SLC region based on the determined amount of valid data in the dynamic portion of the SLC region.

[0005] Some storage systems may include multi-level memory repurposing techniques, for example, a memory controller may reprovision persistent storage media in response to a request to change the configuration of the persistent storage media. [Brief explanation of the drawings]

[0006] The subject matter described herein is illustrated by way of example, and not by way of limitation, in the accompanying drawings. For simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Furthermore, where considered appropriate, reference numerals have been repeated among the drawings to indicate corresponding or analogous elements. The drawings are as follows:

[0007] [Figure 1] FIG. 1 is a block diagram of an example electronic storage system according to one embodiment.

[0008] [Figure 2] FIG. 1 is a block diagram of an example of an electronic device, according to one embodiment.

[0009] [Figure 3] 1 is a flowchart illustrating an example of a storage control method according to one embodiment.

[0010] [Figure 4] FIG. 1 is an illustration of an example process flow according to one embodiment.

[0011] [Figure 5] FIG. 10 is an illustration of another example of a process flow according to one embodiment.

[0012] [Figure 6] FIG. 1 is a block diagram of an example storage system according to one embodiment.

[0013] [Figure 7] FIG. 2 is a block diagram of another example of a computing system according to one embodiment.

[0014] [Figure 8] FIG. 1 is a block diagram of an example solid-state drive (SSD) device, according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] One or more embodiments or implementations are now described with reference to the accompanying drawings. While particular configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present description. It will be apparent to those skilled in the art that the techniques and / or arrangements described herein may also be used in a variety of other systems and applications other than those described herein.

[0016] Although the following description describes various implementation examples that may be manifested in architectures such as, for example, system-on-chip (SoC) architectures, implementation of the techniques and / or arrangements described herein is not limited to a particular architecture and / or computing system and may be implemented by any architecture and / or computing system of similar purpose. For example, the techniques and / or arrangements described herein may be implemented by various architectures using, for example, multiple integrated circuit (IC) chips and / or packages, and / or various computing devices and / or consumer electronics (CE) devices such as set-top boxes, smartphones, etc. Furthermore, although the following description may include numerous specific details, such as, for example, logic implementations, types and interrelationships of system components, and logic partitioning / integration options, claimed subject matter can be practiced without such specific details. In other instances, some material, such as, for example, control structures and complete software instruction sequences, may not be shown in detail in order to avoid obscuring the material disclosed herein.

[0017] The material disclosed herein may be implemented in hardware, firmware, software, or any combination thereof. The material disclosed herein may also be implemented as instructions stored on a machine-readable medium, which can be read and executed by one or more processors. A machine-readable medium may include any medium and / or mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, machine-readable media may include read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustic, or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others.

[0018] References herein to "one implementation," "one implementation," "one exemplary implementation," etc. indicate that the described implementation may include a particular feature, structure, or characteristic, but that not every embodiment necessarily includes such a particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same implementation. Furthermore, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is stated that it is within the knowledge of one skilled in the art that such feature, structure, or characteristic may also be provided in connection with other implementations, whether or not explicitly described herein.

[0019] Various embodiments described herein may include memory components and / or interfaces to memory components. Such memory components may include volatile and / or nonvolatile (NV) memory. Volatile memory may be a storage medium that requires power to maintain the state of data stored on the medium. Non-limiting examples of volatile memory may include various types of RAM, such as dynamic RAM (DRAM) or static RAM (SRAM). One particular type of DRAM may be used in memory modules and is synchronous dynamic RAM (SDRAM). NV memory (NVM) may be a storage medium that does not require power to maintain the state of data stored on the medium. In one embodiment, the memory device may include a block-addressable memory device, such as one based on NAND technology. In one embodiment, the memory device may or may not include a memory device using NAND flash memory or other memory with multiple threshold levels. A memory device may refer to the die itself and / or a packaged memory product.

[0020] Referring to FIG. 1 , one embodiment of an electronic storage system 10 may include a NAND-based storage medium 12 including a first cell region 12a having a first number of levels and a second region 12b having a second number of levels different from the first number of levels, and a controller 11 communicatively coupled to the NAND-based storage medium 12. The controller 11 may include logic 13 that determines logical block address (LBA) locations corresponding to user-configurable capacity placeholders and adjusts the sizes of the first cell region 12a and the second cell region 12b at runtime based on the LBA locations. In some embodiments, the logic 13 may be further configured to enable a user-configurable size of the first cell region 12a in response to a command. For example, the logic 13 may be configured to reserve a range of LBAs to manage capacity conversion between the first cell region 12a and the second cell region 12b.

[0021] In some embodiments, logic 13 may be further configured to store user data in NAND-based storage medium 12 when this function is enabled. For example, logic 13 may be configured to convert blocks in second cell area 12b to blocks in first cell area 12a and move data in second cell area 12b to the converted blocks in first cell area 12a. In any of the embodiments herein, controller 11 and NAND-based storage medium 12 may be incorporated into a solid-state drive (SSD).

[0022] Embodiments of each of the above system components, such as the controller 11, the NAND-based storage medium 12, and the logic 13, may be implemented in hardware, software, or any suitable combination thereof. For example, hardware implementations may include configurable logic, such as a programmable logic array (PLA), a field programmable gate array (FPGA), or a complex programmable logic device (CPLD), or fixed-function logic hardware using circuit technologies, such as an application-specific integrated circuit (ASIC), complementary metal-oxide semiconductor (CMOS), or transistor-transistor logic (TTL) technology, or any combination thereof. Embodiments of the controller 11 may include a general-purpose controller, a special-purpose controller, a memory controller, a storage controller, a microcontroller, a general-purpose processor, a special-purpose processor, a central processing unit (CPU), an execution unit, or the like. In some embodiments, the NAND-based storage medium 12, the logic 13, and / or other system memory may be located within or co-located (e.g., on the same die) with various components, including the controller 11.

[0023] Alternatively, or in addition, all or a portion of these components may be implemented in one or more modules as a set of logic instructions stored in a machine-readable or computer-readable storage medium (e.g., RAM, ROM, programmable ROM (PROM), firmware, flash memory, etc.) for execution by a processor or computing device. For example, computer program code for carrying out operations of the components may be written in any combination of one or more programming languages ​​applicable / suitable for the operating system (OS), including object-oriented programming languages ​​such as Python®, Perl, Java®, Smalltalk®, C++, C#, etc., and conventional procedural programming languages ​​such as the “C” programming language or similar programming languages. For example, NAND-based storage medium 12, other NAND-based storage media, or other system memory may store an instruction set that, when executed by controller 11, causes system 10 to implement one or more components, features, or aspects of system 10 (e.g., logic 13, determining LBA locations corresponding to user-configurable capacity placeholders, adjusting the respective sizes of first cell area 12a and second cell area 12b at runtime based on the LBA locations, etc.).

[0024] Referring now to FIG. 2 , one embodiment of electronic device 14 may include one or more substrates 15 and a controller 16 coupled to one or more substrates 15. Controller 16 may include logic 17, which controls access to a NAND-based storage medium including a first cell region having a first number of levels and a second region having a second number of levels different from the first number of levels, determines LBA locations corresponding to user-configurable capacity placeholders, and adjusts the sizes of the first cell region and the second cell region at runtime based on the LBA locations. In some embodiments, logic 17 may be further configured to enable a user-configurable size of the first cell region in response to a command. For example, logic 17 may be configured to reserve a range of LBAs to manage capacity conversion between the first cell region and the second cell region.

[0025] In some embodiments, logic 17 may be further configured to store user data in the NAND-based storage medium when this function is enabled. For example, logic 17 may be configured to convert blocks of the second cell region to blocks of the first cell region and move data from the second cell region to the converted blocks of the first cell region. In any of the embodiments herein, controller 16 and the NAND-based storage medium may be incorporated into an SSD.

[0026] Embodiments of logic 17 may be implemented in, for example, a system, apparatus, computer, device, etc., as described herein. More specifically, hardware implementations of logic 17 may include configurable logic, such as PLA, FPGA, CPLD, or fixed-function logic hardware using circuit technologies, such as ASIC, CMOS, or TTL technology, or any combination thereof. Alternatively, or additionally, logic 17 may be implemented in one or more modules as a set of logic instructions stored in a machine-readable or computer-readable storage medium, such as RAM, ROM, PROM, firmware, flash memory, etc., for execution by a processor or computing device. For example, computer program code for carrying out operations of the components may be written in any combination of one or more programming languages ​​applicable / appropriate to the OS, including object-oriented programming languages ​​such as Python, Perl, Java, Smalltalk, C++, C#, etc., and conventional procedural programming languages ​​such as the “C” programming language or similar programming languages.

[0027] For example, logic 17 may be implemented in a semiconductor device, which may include one or more substrates 15 to which logic 17 is coupled. In some embodiments, logic 17 may be at least partially implemented in a semiconductor substrate (e.g., silicon, sapphire, gallium arsenide, etc.) in one or more of configurable logic and fixed-function hardware logic. For example, logic 17 may include a transistor array and / or other integrated circuit components coupled to substrate 15 with transistor channel regions disposed within substrate 15. The interface between logic 17 and substrate 15 need not be an abrupt junction. Logic 17 may be considered to include an epitaxial layer grown on an initial wafer of substrate 15.

[0028] 3 , one embodiment of a method 20 for controlling storage may include controlling access to a NAND-based storage medium including a first cell region having a first number of levels and a second region having a second number of levels different from the first number of levels at block 21, determining LBA locations corresponding to user-configurable capacity placeholders at block 22, and adjusting the sizes of the first cell region and the second cell region at runtime based on the LBA locations at block 23. Some embodiments of method 20 may further include enabling a user-configurable size of the first cell region in response to a command at block 24. For example, method 20 may include reserving a range of LBAs to manage capacity conversion between the first cell region and the second cell region at block 25.

[0029] In some embodiments, method 20 may further include storing user data on the NAND-based storage medium when this feature is enabled, at block 26. For example, method 20 may include converting blocks of the second cell region to blocks of the first cell region, at block 27, and moving data from the second cell region to the converted blocks of the first cell region, at block 28. In any of the embodiments herein, the NAND-based storage medium may be incorporated into an SSD, at block 29.

[0030] Embodiments of method 20 may be implemented in, for example, a system, apparatus, computer, device, etc., as described herein. More specifically, hardware implementations of method 20 may include configurable logic, such as PLA, FPGA, CPLD, coarse-grained reconfigurable fabric (CGRA), or fixed-function logic hardware using circuit technologies, such as ASIC, CMOS, or TTL technology, or any combination thereof. Alternatively, or additionally, method 20 may be implemented in one or more modules as a set of logic instructions executed by a processor or computing device, stored in a machine-readable or computer-readable storage medium, such as RAM, ROM, PROM, firmware, flash memory, etc. For example, computer program code for carrying out operations of the components may be written in any combination of one or more programming languages ​​applicable / appropriate to the OS, including object-oriented programming languages ​​such as Python, Perl, Java, Smalltalk, C++, C#, etc., and conventional procedural programming languages, such as the “C” programming language or similar programming languages.

[0031] For example, method 20 may be implemented in a computer-readable medium as described in connection with Examples 22-28 below. Embodiments of method 20, or portions thereof, may be implemented in firmware, an application (e.g., through an application programming interface (API)), or driver software running in an operating system (OS). Additionally, logic instructions may include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, state configuration data, configuration data for integrated circuits, state information for individualizing electronic circuits and / or other structural components specific to hardware (e.g., a host processor, central processing unit / CPU, microcontroller, etc.).

[0032] Some embodiments advantageously provide a technique that enables user configuration of SLC buffer / cache size while preserving user data for a NAND storage device. Typically, when provisioning a NAND storage device with multiple bits per cell, an SLC cache or buffer may be provisioned to improve device performance. However, because each cell dedicated to the SLC buffer only has one bit, the overall capacity of the drive is reduced. File systems and partition systems rely on drive capacity to allocate portions of their data structures. Because the overall capacity of the device is determined based on the size of the SLC buffer, users cannot resize the amount of SLC according to their own needs without risking data loss and file system corruption. User selection of a tradeoff between performance (e.g., SLC size) and overall capacity (e.g., QLC size, TLC size, etc.) can be made at the time of provisioning. To change the user-selected tradeoff, the contents of the drive must be erased.

[0033] In storage systems with dynamic SLC buffers, the size of the SLC buffer can be adjusted at runtime. However, this adjustment is not user-configurable. The user cannot choose how the drive trades performance for capacity, and the user cannot commit to a certain amount of SLC on the drive. Storage systems with multilevel memory repurposing techniques (e.g., just-in-time block repurposing) may be able to reconfigure storage media based on user requests, but typically require taking the drive offline and changing the drive's reported capacity, which disrupts file system operations. Advantageously, some embodiments provide techniques that overcome one or more of the aforementioned problems.

[0034] In some embodiments, a host software component, such as a storage driver, can be utilized to create a file in a file system of a storage device. The created file will contain no data. After the created file and its associated LBA location are communicated to the SSD's firmware, the SSD can increase its SLC buffer by a corresponding amount based on the NAND erase block (EB) characteristics of the individual device. In an SLC-QLC device, for example, the increase will correspond to a 4:1 ratio.

[0035] It is advantageous for users to control SLC configurability. For example, if a user has a QLC-based SSD and knows that an application will use less than one-quarter (1 / 4) of the SSD's capacity, some embodiments allow the user to configure the storage system to be 100% SLC without losing any user data already on the drive. If the user later needs more capacity, the user can undo this operation or provision drives with a different ratio, if desired, again without losing or corrupting any data currently on the device.

[0036] The reclaimed SLC may be utilized for any useful storage need. For example, an application may utilize an embodiment that dedicates the freed SLC to an intelligent caching solution (e.g., not just as a write buffer). It is advantageous for SSD devices to be shipped with the ability to utilize their maximum capacity (e.g., a corresponding preferred cost / gigabyte (GB) value). When deployed, users can reconfigure the tradeoff between performance and capacity at runtime as needed while preserving user data.

[0037] In some embodiments, host software drivers and file systems can be utilized to provide mechanisms that allow users to make seamless trade-offs between capacity and performance. For example, a capacity placeholder or padding file can be created to make certain SSD LBA ranges inaccessible to the rest of the system (e.g., OS, other applications, etc.) and instead reserve them for firmware (FW) management of capacity conversion between QLC and SLC to achieve the desired trade-off. For example, because SLC access provides better performance than QLC, a user may choose to trade off increased SLC capacity.

[0038] In some embodiments, the padding file is created if the corresponding feature is enabled. For example, the LBA range may be sent to the SSD via a vendor-specific command, and then the padding file will be opened for reserved exclusive access by some daemon service at each OS initialization. After the SSD's FW receives the LBA range and determines how many new SLC blocks need to be created, the FW creates additional SLCs by moving data from current SLC blocks to new SLC blocks as needed. The padding file will exist if the corresponding feature is enabled.

[0039] Referring to FIG. 4 , one embodiment of a process flow 40 illustrates how a user can reconfigure a 1 terabyte (TB) drive. Before enabling the user-configurable SLC capacity feature, the entire 1 TB of the drive may be available to the OS and file system. After the user enables this feature and requests the maximum SLC capacity, 100% of the drive is converted to SLC storage. For a QLC drive, this results in 256 GB of SLC capacity (e.g., a 4:1 capacity reduction from the 1024 GB of a drive converted from QLC to SLC) with much better read and write access performance. A 768 GB padding file is created as a capacity placeholder to occupy the remainder of the original 1 TB. Advantageously, the padding file allows the drive to appear to the OS and file system as if the SSD had not changed. Even though the drive has been reconfigured, no hardware reprovisioning is required to account for the physical change in capacity, and the system can continue to operate normally.

[0040] Referring to FIG. 5 , one embodiment of process flow 50 shows another example of how a user can reconfigure a 1 TB drive. Before enabling the user-configurable SLC capacity feature, the entire 1 TB of the drive may be available to the OS and file system. After the user enables the feature and requests 50% SLC capacity, 50% of the drive is converted to SLC storage. For a QLC drive, this results in 128 GB of SLC capacity (e.g., a 4:1 capacity reduction from the 512 GB of the drive converted from QLC to SLC) with much better read and write access performance. A 384 GB padding file is created as a capacity placeholder to occupy the remainder of the original 512 GB converted to SLC. Advantageously, the padding file allows the drive to appear to the OS and file system as if the SSD had not changed. Even though the drive has been reconfigured, no hardware reprovisioning is required to account for the physical change in capacity, and the system can continue to operate normally.

[0041] In some embodiments, the actual division of the specified ratio may be set by the user in a graphical user interface (GUI). For example, the interface may query the drive's specific NAND cell characteristics. The interface may also determine and communicate capacity trade-offs to the user. As illustrated in FIGS. 4 and 5, in a QLC SSD, this function requires reserving four bits for every reclaimed SLC bit. In a NAND SSD that supports multiple formats in addition to SLC and QLC, an embodiment of this function may be configured to convert between other supported formats (e.g., two-level cell (MLC), TLC, etc.).

[0042] Referring to FIG. 6 , one embodiment of a storage system 60 may include a file system with multiple files. The file system creates files that translate to LBA locations. The LBA locations are then translated by the SSD's FW to NAND cell locations using a logical-to-physical (L2P) table. The SSD may also include a certain number of SLCs that are used by the SSD's FW as a buffer / cache. In some embodiments, when a user-configured feature is enabled, the SSD's FW creates locations in the L2P that do not map to physical NAND locations (e.g., identified as reclaimed LBAs in FIG. 6 ). These locations are allocated to padding files, so the SSD's FW knows that these locations cannot be mapped to valid data. Therefore, the SSD's FW can create more SLCs (e.g., identified as reclaimed SLCs in FIG. 6 ) to improve storage device performance. For example, if an SSD has enough QLC blocks for 1 TB, but the user reserves 512 GB of that space when the user enables the user-configured feature, the SSD's FW can safely use the 512 GB worth of QLC capacity for 128 GB of SLC blocks. These embodiments utilize the L2P indirection table in the SSD to point to the location of the padding file and its relative locations, so fragmentation of the padding file is not an issue.

[0043] In some embodiments, when utilizing a padding file as a capacity placeholder to reserve space in this manner, there is some risk that the LBA locations assigned to the padding file will be changed. In some embodiments, changes to the LBA locations assigned to the padding can be detected by the SSD's FW itself via a fail-safe function, and the function can be automatically rolled back. In some embodiments, the fail-safe function refers to detecting a write that occurred to a reserved LBA and then correcting the mapping of SLCs back to QLCs. If the SSD's FW ever receives a write (or, for example, a TRIM) request to any LBA within the reserved LBA range, the SSD's FW can immediately cancel the function internally (e.g., disable the user-configured function), convert any valid SLC data within that range to QLC, and return to a NAND configuration without any reclaimed SLCs (e.g., the configuration before the user enabled this function, or the original configuration). Note that because the SSD can return zeros (e.g., similar to what an SSD does when reading a trimmed location), it is safe to issue reads to the padding file on the host system.

[0044] For example, if a file system is mounted as a data drive on an OS that does not recognize this feature and the firmware erases or overwrites an LBA previously reserved, a write request to an LBA within the reserved range may occur. Another possibility for activating the failsafe function is file system corruption. The process of reverting this function may activate the SSD's NAND garbage collection process, which converts SLC back to QLC, causing temporary performance degradation but no data loss. For example, this conversion process can be performed by utilizing the appropriate operation code (e.g., opcode) or function set that can convert the entire NAND die to the desired format (e.g., SLC, MLC, TLC, QLC, etc.). The SSD's firmware identifies the target block and the target format. The SSD's firmware first converts the NAND die to the target format and then issues a specific operation (e.g., erase, program, or read) to the target block. The conversion process can be performed on a per-target block basis, and the SSD's firmware maintains the target format for each target block.

[0045] In addition to enabling and disabling user-configured features, associated host software can be responsible for minimizing the conditions that trigger the fail-safe and recovering from the fail-safe when they occur. To facilitate this, padding files should be assigned to the most restrictive file system access properties to preclude the most problematic programs or users from triggering the fail-safe. Host file system features such as file system compression that may interfere with user-configured features should be disabled, and problematic operations such as write, move, file create, or file delete should be intercepted and handled by appropriate host file system filters.

[0046] For the system to function properly, the LBA location of the padding file in the filesystem must match what is designated as reclaimed in the SSD firmware's L2P. To ensure this, at power-on, the host software manually requests this information from the SSD and checks for any discrepancies. If the SSD firmware detects a mismatch, it notifies the host driver.

[0047] Based on the mismatch notification, the host driver can either disable the feature entirely or attempt to correct the mismatch. Correcting the mismatch is only possible if there is still enough unused capacity to create a padding file of the desired size. For example, on a system without the protective host software for this feature, if a user deletes a 512GB padding file and then fills the SSD to less than 512GB free, the 512GB padding file cannot be created. In this case, the feature is simply disabled.

[0048] In some embodiments, no pre-OS or Unified Extensible Firmware Interface (UEFI) driver components are required because there is no need to access padding files before the OS is up and running (e.g., host SW components for user-configured functionality are not needed until OS initialization).

[0049] In an alternative embodiment, a separate padding partition may be used instead of a padding file as a capacity placeholder for the reclaimed portion of the SSD's capacity. Using a padding partition as a capacity placeholder may be similar to using a padding file, except that the user may want to consume capacity to create more SLCs. In this situation, the original data partition may have its files spread across a larger LBA space, and there may not be enough free space at the beginning or end of the partition to sufficiently shrink the data partition. For certain files, such as paging files, it may not even be possible to move the file during runtime. Therefore, an "offline" environment, such as UEFI, may be required to move these types of protected files. In either embodiment, the data layout of the SSD's LBA space is used to reserve locations that are known to be unused and unmapped so that the SSD can allocate faster SLCs rather than those configured by the user.

[0050] The techniques described herein may be provided in a variety of computing systems (including, for example, non-portable computing devices such as desktops, workstations, servers, rack systems, etc., portable computing devices such as smartphones, tablets, ultra-portable personal computers (UMPCs), laptop computers, Ultrabook computing devices, smart watches, smart glasses, smart bracelets, etc., and / or client / edge devices such as Internet of Things (IoT) devices (e.g., sensors, cameras, etc.)).

[0051] 7, one embodiment of computing system 100 may include one or more processors 102-1 through 102-N (generally referred to herein as "multiple processors 102" or "processor 102"). The multiple processors 102 may communicate via an interconnect or bus 104. Each processor 102 may include various components, only some of which will be described with reference to processor 102-1 for clarity. Accordingly, each of the remaining processors 102-2 through 102-N may include the same or similar components described with reference to processor 102-1.

[0052] In some embodiments, processor 102-1 may include one or more processor cores 106-1 through 106-M (referred to herein as “cores 106” or more generally as “cores 106”), cache 108 (which may be a shared cache or a private cache in various embodiments), and / or router 110. Processor cores 106 may be implemented on a single integrated circuit (IC) chip. Additionally, the chip may include one or more shared and / or private caches (e.g., cache 108), buses or interconnects (e.g., bus or interconnect 112), logic 170, memory controllers, or other components.

[0053] In some embodiments, routers 110 may be used to communicate between various components of processor 102-1 and / or system 100. Additionally, processor 102-1 may include more than one router 110. Furthermore, multiple routers 110 may communicate to enable data routing between various components internal or external to processor 102-1.

[0054] The cache 108 may store data (e.g., including instructions) utilized by one or more components (e.g., cores 106) of the processor 102-1. For example, the cache 108 may locally cache data stored in the memory 114 for faster access by the components of the processor 102. As shown in FIG. 7, the memory 114 may communicate with the processor 102 via the interconnect 104. In some embodiments, the (possibly shared) cache 108 may have various levels; for example, the cache 108 may be a mid-level cache and / or a last-level cache (LLC). Additionally, each of the cores 106 may include a level 1 (L1) cache (116-1) (generally referred to herein as “L1 cache 116”). The various components of the processor 102-1 may communicate directly with the cache 108 through a bus (e.g., bus 112) and / or a memory controller or hub.

[0055] 7, memory 114 may be coupled to other components of system 100 through memory controller 120. Memory 114 may include volatile memory and may be referred to interchangeably as main memory or system memory. Although memory controller 120 is shown coupled between interconnect 104 and memory 114, memory controller 120 may be located elsewhere in system 100. For example, in some embodiments, memory controller 120, or portions thereof, may be provided in one of multiple processors 102.

[0056] System 100 can communicate with other devices / systems / networks via network interface 128 (e.g., communicating with a computer network and / or cloud 129 via a wired or wireless interface). For example, network interface 128 may include an antenna (not shown) for communicating with network / cloud 129 wirelessly (e.g., via an Institute of Electrical and Electronics Engineers (IEEE) 802.11 interface (including IEEE 802.11a / b / g / n / ac, etc.), a cellular interface, 3G, 4G, LTE, Bluetooth, etc.).

[0057] System 100 may also include a storage device, such as SSD 130, coupled to interconnect 104 via SSD controller logic 125. Accordingly, logic 125 may control access to SSD 130 by various components of system 100. Additionally, although logic 125 is shown in FIG. 7 as being directly coupled to interconnect 104, logic 125 may alternatively communicate with one or more other components of system 100 via a storage bus / interconnect (e.g., a Serial Advanced Technology Attachment (SATA) bus, a Peripheral Component Interconnect (PCI) (or PCI Express (PCIe) interface), NVM Express (NVMe), etc.) (e.g., when a storage bus is coupled to interconnect 104 via some other logic, such as a bus bridge, a chipset, etc.). Additionally, logic 125 may be incorporated into memory controller logic (e.g., as described with reference to FIG. 8) or may be provided in the same integrated circuit (IC) device (e.g., on the same circuit board device as SSD 130 or in the same housing as SSD 130) in various embodiments.

[0058] Additionally, logic 125 and / or SSD 130 may be coupled to one or more sensors (not shown) to receive information (e.g., in the form of one or more bits or signals) indicative of the status or value of a value detected by the one or more sensors. These sensors may be located in proximity to components of system 100 (or other computing systems described herein), including cores 106, interconnect 104 or 112, components external to processor 102, SSD 130, the SSD bus, the SATA bus, logic 125, logic 160, logic 170, etc., to sense variations in various factors that affect the power / thermal behavior of the system / platform, such as temperature, operating frequency, operating voltage, power consumption, and / or communication activity between cores.

[0059] FIG. 8 illustrates a block diagram of various components of SSD 130, according to one embodiment. As illustrated in FIG. 8, logic 160 may be located in various locations, such as within SSD 130 or controller 382, ​​and may include similar technology as described in connection with FIG. 7. SSD 130 includes controller 382 (which further includes one or more processor cores or processors 384 and memory controller logic 386), cache 138, RAM 388, firmware storage 390, and one or more memory devices 392-1 through 392-N (collectively, memory 392, which may include NAND media or other types of non-volatile memory). Memory 392 is coupled to memory controller logic 386 via one or more memory channels or buses. SSD 130 also communicates with logic 125 via an interface (such as a SATA, SAS, PCIe, NVMe, etc.). Processor 384 and / or controller 382 may compress / decompress data being written to or read from memory devices 392-1 through 392-N.

[0060] As illustrated in Figures 7 and 8, SSD 130 may include logic 160, which may be in the same housing as SSD 130 and / or fully integrated on the printed circuit board (PCB) of SSD 130. System 100 may also include logic 170 that is external to SSD 130. One or more of the features / aspects / operations described with reference to Figures 1-6 may be performed by one or more of the components of Figures 7 and / or 8. Also, one or more of the features / aspects / operations of Figures 1-6 may be programmed into firmware 390. Furthermore, SSD controller logic 125 may also include logic 160. Advantageously, logic 160 and / or logic 170 may include technology for implementing one or more aspects of system 10 (FIG. 1), apparatus 14 (FIG. 2), method 20 (FIG. 3), process flow 40 (FIG. 4), process flow 50 (FIG. 5), storage system 60 (FIG. 6), and / or any of the functionality described herein. For example, logic 170 may include technology for implementing host device / computer system / agent-related aspects of the various embodiments described herein, and logic 160 may include technology for implementing storage device-related aspects of the various embodiments described herein.

[0061] For example, memory 392 may include a NAND-based storage medium including a first cell region (e.g., SLC) having a first number of levels and a second region (e.g., QLC) having a second number of levels different from the first number of levels. Logic 160 in controller 382 may be configured to determine LBA locations corresponding to user-configurable capacity placeholders (e.g., padding files, padding partitions, etc.) and adjust the sizes of the first cell region and the second cell region at runtime based on the LBA locations. In some embodiments, logic 160 may be further configured to enable a user-configurable size of the first cell region in response to a command (e.g., a vendor-specific command). For example, logic 160 may be configured to reserve a range of LBAs to manage capacity conversion between the first cell region and the second cell region.

[0062] In some embodiments, logic 160 may be further configured to store user data in memory 392 when this feature is enabled. For example, logic 160 may be configured to transform blocks of the second cell region into blocks of the first cell region and move data of the second cell region into the transformed blocks of the first cell region.

[0063] In other embodiments, SSD 130 may be replaced with any suitable storage / memory / technology / media. In some embodiments, logic 160 / 170 may be coupled to one or more substrates (e.g., silicon, sapphire, gallium arsenide, printed circuit board (PCB), etc.) and may include channel regions of transistors disposed within the one or more substrates. In other embodiments, SSD 130 may include two or more types of storage media. For example, the majority of the storage may be NAND, and may also include some faster, finer-granularity accessible (e.g., byte-addressable) NVM. SSD 130 may alternatively or additionally include persistent volatile memory (e.g., DRAM or SRAM backed up by a battery or capacitor). For example, SSD 130 may include power loss protection (PLI) technology using an energy storage capacitor. The energy storage capacitor can provide enough energy (power) to complete any ongoing commands and ensure that any data in the DRAM / SRAM is recorded to non-volatile NAND media. The capacitor can act as a backup battery for persistent volatile memory. As shown in Figures 7 and 8, functions or aspects of logic 160 and / or logic 170 may be distributed throughout system 100 and / or co-located with / integrated with various components of system 100.

[0064] [Additional points to note and examples]

[0065] Example 1 includes an electronic device, the device comprising: one or more substrates; and a controller coupled to the one or more substrates, where the controller includes logic to control access to a NAND-based storage medium including a first cell region having a first number of levels and a second region having a second number of levels different from the first number of levels; determine logical block address locations corresponding to user-configurable capacity placeholders; and adjust the sizes of each of the first cell region and the second cell region at runtime based on the logical block address locations.

[0066] Example 2 includes the apparatus of example 1, wherein the logic further enables user configuration of a size of the first cell region in response to a command.

[0067] Example 3 includes the apparatus of example 2, wherein the logic further reserves a range of logical block addresses for managing capacity translation between the first cell region and the second cell region.

[0068] Example 4 includes the apparatus of any of Examples 2-3, wherein the logic is further configured to store user data on the NAND-based storage medium when the feature is enabled.

[0069] Example 5 includes the apparatus of example 4, wherein the logic further converts the blocks of the second cell region into the blocks of the first cell region.

[0070] Example 6 includes the apparatus of example 5, wherein the logic further moves data in the second cell region to the transformed block in the first cell region.

[0071] Example 7 includes the apparatus of any of examples 1 to 6, wherein the controller and the NAND-based storage medium are incorporated into a solid-state drive.

[0072] Example 8 includes an electronic storage system, the system comprising: a NAND-based storage medium including a first cell region having a first number of levels and a second region having a second number of levels different from the first number of levels; and a controller communicatively coupled to the NAND-based storage medium, the controller including logic that determines logical block address locations corresponding to user-configurable capacity placeholders and adjusts the sizes of each of the first cell region and the second cell region at runtime based on the logical block address locations.

[0073] Example 9 includes the system of example 8, wherein the logic further enables user configuration of the size of the first cell region in response to a command.

[0074] Example 10 includes the system of example 9, wherein the logic further reserves a range of logical block addresses for managing capacity translation between the first cell region and the second cell region.

[0075] Example 11 includes the system of any of Examples 9-10, wherein the logic is further configured to store user data on the NAND-based storage medium when the feature is enabled.

[0076] Example 12 includes the system of example 11, wherein the logic further converts the blocks of the second cell region into the blocks of the first cell region.

[0077] Example 13 includes the system of example 12, wherein the logic further moves data in the second cell region to the transformed block in the first cell region.

[0078] Example 14 includes the system of any of examples 8-13, wherein the controller and the NAND-based storage medium are incorporated into a solid-state drive.

[0079] Example 15 includes a method for controlling storage, the method including controlling access to a NAND-based storage medium including a first cell region having a first number of levels and a second region having a second number of levels different from the first number of levels, determining logical block address locations corresponding to user-configurable capacity placeholders, and adjusting sizes of each of the first cell region and the second cell region at runtime based on the logical block address locations.

[0080] Example 16 includes the method of example 15, further comprising enabling a user-configurable size of the first cell region in response to a command.

[0081] Example 17 includes the method of example 16, further comprising reserving a range of logical block addresses for managing capacity translation between the first cell region and the second cell region.

[0082] Example 18 includes the method of any of examples 16-17, further comprising storing user data on the NAND-based storage medium when the feature is enabled.

[0083] Example 19 includes the method of example 18, further comprising converting the blocks of the second cell area into the blocks of the first cell area.

[0084] Example 20 includes the method of example 19, further comprising moving data of the second cell region to the transformed block of the first cell region.

[0085] Example 21 includes the method of any of examples 15 to 20, wherein the NAND-based storage medium is incorporated into a solid-state drive.

[0086] Example 22 includes at least one non-transitory machine-readable medium, the medium comprising a plurality of instructions that, when executed on a computing device, cause the computing device to control access to a NAND-based storage medium including a first cell region having a first number of levels and a second region having a second number of levels different from the first number of levels, determine logical block address locations corresponding to user-configurable capacity placeholders, and adjust sizes of each of the first cell region and the second cell region at runtime based on the logical block address locations.

[0087] Example 23 includes at least one non-transitory machine-readable medium as described in Example 22, further comprising a plurality of instructions that, in response to being executed on the computing device, cause the computing device to enable a user-configurable size of the first cell region in response to a command.

[0088] Example 24 includes at least one non-transitory machine-readable medium as described in Example 23, further comprising a plurality of instructions that, in response to being executed on the computing device, cause the computing device to reserve a range of logical block addresses for managing capacity translation between the first cell region and the second cell region.

[0089] Example 25 includes at least one non-transitory machine-readable medium according to any of Examples 23-24, further comprising a plurality of instructions that, in response to being executed on the computing device, cause the computing device to store user data on the NAND-based storage medium when this function is enabled.

[0090] Example 26 includes at least one non-transitory machine-readable medium as described in Example 25, further comprising a plurality of instructions that, in response to being executed on the computing device, cause the computing device to convert blocks of the second cell region into blocks of the first cell region.

[0091] Example 27 includes at least one non-transitory machine-readable medium as described in Example 26, further comprising a plurality of instructions that, in response to being executed on the computing device, cause the computing device to move data from the second cell region to the transformed block of the first cell region.

[0092] Example 28 includes the at least one non-transitory machine-readable medium of any of Examples 22 to 27, wherein the NAND-based storage medium is incorporated into a solid-state drive.

[0093] Example 29 includes a storage controller apparatus, the apparatus comprising: means for controlling access to a NAND-based storage medium including a first cell area having a first number of levels and a second area having a second number of levels different from the first number of levels; means for determining logical block address locations corresponding to user-configurable capacity placeholders; and means for adjusting sizes of each of the first cell area and the second cell area at runtime based on the logical block address locations.

[0094] Example 30 includes the apparatus of example 29, further comprising means for enabling user configuration of the size of the first cell region in response to a command.

[0095] Example 31 includes the apparatus of example 30, further comprising means for reserving a range of logical block addresses to manage capacity conversion between the first cell area and the second cell area.

[0096] Example 32 includes the apparatus of any of Examples 30-31, further comprising: means for storing user data on the NAND-based storage medium when the feature is enabled.

[0097] Example 33 includes the apparatus of example 32, further comprising means for converting the second block of cells into the first block of cells.

[0098] Example 34 includes the apparatus of example 33, further comprising means for moving data of the second cell region to the transformed block of the first cell region.

[0099] Example 35 includes the apparatus of any of examples 29 to 34, wherein the NAND-based storage medium is incorporated into a solid-state drive.

[0100] The term "coupled" may be used herein to refer to any type of direct or indirect relationship between the components in question and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical, or other connections. Additionally, terms such as "first," "second," etc. may be used herein for ease of description only and do not have any particular temporal or chronological meaning unless otherwise indicated.

[0101] In the present application and claims, a series of items followed by the term “one or more of” may refer to any combination of the listed terms. For example, the phrases “one or more of A, B, and C” and “one or more of A, B, or C” may both refer to A; B; C; A and B; A and C; B and C; or A, B, and C. Various components of the systems described herein may be implemented in software, firmware, and / or hardware, and / or any combination thereof. For example, various components of the systems or devices described herein may be provided, at least in part, in the hardware of a computing SoC, such as may be found in a computing system such as a smartphone. Those skilled in the art will recognize that the systems described herein may include additional components not depicted in the corresponding figures. For example, the systems described herein may include additional components, such as bitstream multiplexer or demultiplexer modules, not depicted for clarity.

[0102] Although an implementation of the example processes described herein may include performing all of the operations shown in the order shown, the disclosure is not limited in this respect, and in various examples, an implementation of the example processes herein may include only a subset of the operations shown, operations performed in an order different from that shown, or additional operations.

[0103] Additionally, any one or more of the operations described herein may be performed in response to instructions provided by one or more computer program products. Such program products may include, for example, signal-bearing media providing instructions that, when executed by a processor, can result in the functions described herein. A computer program product may be provided on one or more machine-readable media in any form. Thus, for example, a processor including one or more graphics processing units or processor cores may execute one or more of the example process blocks herein in response to program code and / or instructions or instruction sets transmitted to the processor by one or more machine-readable media. In general, a machine-readable medium may carry software in the form of program code and / or instructions or instruction sets that can cause any of the devices and / or systems described herein to implement at least a portion of the operations described herein and / or any portion of the devices, systems, or any modules or components described herein.

[0104] In any implementation described herein, the term "module" refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. Software may be embodied as a software package, code, and / or instruction set or instructions, and in any implementation described herein, "hardware" may include, for example, hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, and / or firmware storing instructions executed by programmable circuitry, alone or in any combination. These modules may be embodied collectively or individually as circuitry (e.g., integrated circuits (ICs), systems-on-chips (SoCs), etc.) that form part of a larger system.

[0105] Various embodiments may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, application specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), logic gates, registers, semiconductor devices, chips, microchips, and chipsets. Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (APIs), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. The determination of whether an embodiment is implemented using hardware and / or software elements may depend on any number of factors, such as desired computation rate, power level, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints.

[0106] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium that represent various logic within a processor, and that, when read by a machine, cause the machine to create logic for performing the techniques described herein. Such representations, known as IP cores, may be stored on tangible machine-readable media and supplied to various customers or manufacturing facilities for loading into manufacturing machines that actually create the logic or processor.

[0107] While certain features described herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Accordingly, various modifications of the implementations described herein and other implementations that may be apparent to those skilled in the art to which this disclosure pertains are deemed to be within the spirit and scope of the present disclosure.

[0108] It will be recognized that these embodiments are not limited to the embodiments so described, but may be practiced with modification and alteration without departing from the scope of the appended claims. For example, the above-described embodiments may include a particular combination of features. However, the above-described embodiments are not limited in this respect, and in various implementations, the above-described embodiments may include implementing only a subset of such features, implementing such features in a different order, implementing such features in different combinations, and / or implementing additional features beyond those expressly recited. The scope of these embodiments should, therefore, be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled. The present embodiment also includes the following items. (Item 1) 1. An electronic device, comprising: one or more substrates; and a controller coupled to the one or more substrates, the controller comprising logic, the logic comprising: controlling access to a NAND-based storage medium including a first cell area having a first number of levels and a second cell area having a second number of levels different from the first number of levels; determining logical block address locations corresponding to the user-configurable capacity placeholders; adjusting the sizes of the first cell region and the second cell region at runtime based on the logical block address location; An apparatus comprising: (Item 2) the logic further comprising: Item 1 , the device described in item 1, enabling a function to user-configure the size of the first cell area in response to a command. (Item 3) the logic further comprising: Item 3. The device of item 2, reserving a range of logical block addresses to manage capacity conversion between the first cell area and the second cell area. (Item 4) the logic further comprising: 3. The device of claim 2, wherein the device stores user data on the NAND-based storage medium when the function is enabled. (Item 5) the logic further comprising: Item 5. The apparatus of item 4, which converts the block of the second cell area into the block of the first cell area. (Item 6) the logic further comprising: Item 6. The apparatus of item 5, wherein data of the second cell region is moved to the transformed block of the first cell region. (Item 7) Item 1, wherein the controller and the NAND-based storage medium are incorporated into a solid-state drive. (Item 8) 1. An electronic storage system comprising: a NAND-based storage medium including a first cell region having a first number of levels and a second cell region having a second number of levels different from the first number of levels; and a controller communicatively coupled to the NAND-based storage medium, the controller comprising logic, the logic comprising: determining logical block address locations corresponding to the user-configurable capacity placeholders; adjusting the sizes of the first cell region and the second cell region at runtime based on the logical block address location; A system comprising: (Item 9) the logic further comprising: Item 10. The system of item 8, wherein the system enables a user-configurable size of the first cell region in response to a command. (Item 10) the logic further comprising: 10. The system of claim 9, wherein a range of logical block addresses is reserved for managing capacity conversion between the first cell region and the second cell region. (Item 11) the logic further comprising: 10. The system of claim 9, wherein when the feature is enabled, user data is stored on the NAND-based storage medium. (Item 12) the logic further comprising: Item 12. The system of item 11, wherein the second block of cell area is transformed into the first block of cell area. (Item 13) the logic further comprising: Item 13. The system of item 12, further comprising: moving data of the second cell region to the transformed block of the first cell region. (Item 14) Item 9. The system of item 8, wherein the controller and the NAND-based storage medium are incorporated into a solid-state drive. (Item 15) 1. A method for controlling storage, comprising: controlling access to a NAND-based storage medium including a first cell region having a first number of levels and a second cell region having a second number of levels different from the first number of levels; determining logical block address locations corresponding to user-configurable capacity placeholders; and adjusting the size of each of the first cell region and the second cell region at run time based on the logical block address location. A method for providing the above. (Item 16) moreover, Item 16. The method of item 15, comprising enabling a function for user-configuring the size of the first cell region in response to a command. (Item 17) moreover, Item 17. The method of item 16, comprising reserving a range of logical block addresses to manage capacity translation between the first cell region and the second cell region. (Item 18) moreover, Item 17. The method of item 16, comprising storing user data on the NAND-based storage medium when the feature is enabled. (Item 19) moreover, Item 19. The method of item 18, comprising converting the second block of cell area into the first block of cell area. (Item 20) moreover, 20. The method of claim 19, further comprising moving data of the second cell region to the transformed block of the first cell region.

Claims

1. 1. An electronic device, comprising: a NAND-based storage medium including a first cell area having a first number of levels and a second cell area having a second number of levels different from the first number of levels; a controller coupled to the NAND-based storage medium; The controller includes at least determining logical block address locations corresponding to the capacity placeholders; adjusting the sizes of the first cell area and the second cell area based on the logical block address location; It is configured as follows: Device.

2. The controller further comprises: The apparatus of claim 1 , configured to enable user configuration of the size of the first cell region in response to a command.

3. The controller further comprises:

3. The apparatus of claim 2, configured to reserve a range of logical block addresses to manage capacity translation between the first cell region and the second cell region.

4. The controller further comprises: The device of claim 2 , configured to store user data on the NAND-based storage medium when the feature is enabled.

5. The controller further comprises:

5. The apparatus of claim 4, configured to transform the blocks of the second cell area into transformed blocks of the first cell area.

6. The controller further comprises:

6. The apparatus of claim 5, configured to move data from the second cell region to the conversion block of the first cell region.

7. The apparatus of claim 1 , wherein the controller and the NAND-based storage medium are incorporated into a solid-state drive.

8. 1. An electronic storage system comprising: a non-volatile storage medium including a first cell region having a first number of levels and a second cell region having a second number of levels different from the first number of levels; a controller coupled to the non-volatile storage medium; The controller includes at least determining logical block address locations corresponding to the capacity placeholders; adjusting the sizes of the first cell area and the second cell area based on the logical block address location; It is configured as follows: system.

9. The controller further comprises: The system of claim 8 , configured to enable user configuration of the size of the first cell region in response to a command.

10. The controller further comprises:

10. The system of claim 9, configured to reserve a range of logical block addresses to manage capacity translation between the first cell region and the second cell region.

11. The controller further comprises: The system of claim 9 , configured to store user data on the non-volatile storage medium when the feature is enabled.

12. The controller further comprises: The system of claim 11 configured to convert the second block of cell area into the first block of cell area.

13. The controller further comprises:

13. The system of claim 12, configured to move data from the second cell region to the transformed block of the first cell region.

14. The system of claim 8 , wherein the controller and the non-volatile storage medium are incorporated into a solid-state drive.

15. 1. A method for controlling storage, comprising: determining logical block address locations corresponding to the capacity placeholders; adjusting the size of each of the first cell area and the second cell area based on the logical block address location; Equipped with the first cell area and the second cell area are included in a non-volatile storage medium, the first cell area having a first number of levels, and the second cell area having a second number of levels different from the first number of levels; method.

16. 16. The method of claim 15, further comprising enabling a user-configurable size of the first cell region in response to a command.

17. 17. The method of claim 16, further comprising reserving a range of logical block addresses to manage capacity translation between the first cell region and the second cell region.

18. 17. The method of claim 16, further comprising storing user data in the non-volatile storage medium when the feature is enabled.

19. 20. The method of claim 18, further comprising converting the second block of cell area to the first block of cell area.

20. 20. The method of claim 19, further comprising moving data from the second cell region to the transformed block of the first cell region.

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