Semiconductor substrate, and method for manufacturing semiconductor device

Abstract

To provide a semiconductor substrate, and a method for manufacturing a semiconductor device that reduces cracks and defects occurring in a main body.SOLUTION: A semiconductor substrate 10 comprises a main substrate 1, a seed section SD positioned above the main substrate 1, and a first conductor section 8F and a second semiconductor section 8S arranged in the first direction (Y-direction), the first semiconductor section and the second semiconductor section are in contact with the seed section SD, and the seed section SD has the first direction (Y-direction) as its longitudinal direction. A hollow space VD is positioned between the main substrate 1, the first semiconductor section 8F, and the second semiconductor section.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor substrates and the like. [Background technology]

[0002] Patent Document 1 discloses a technique for forming a semiconductor device layer (including an active layer) in a floating state above a main substrate such as a silicon substrate by using an ELO (Epitaxial Lateral Overgrowth) method. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-32863 Summary of the Invention

[0004] The semiconductor substrate according to the present disclosure comprises a main substrate, a seed portion located above the main substrate, and first and second semiconductor portions aligned in a first direction, the first and second semiconductor portions being in contact with the seed portion, the seed portion having the first direction as its longitudinal direction, and a hollow portion being located between the main substrate and the first and second semiconductor portions. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a plan view showing a configuration of a semiconductor substrate according to an embodiment of the present invention. [Figure 2A] 1 is a cross-sectional view showing a configuration of a semiconductor substrate according to an embodiment of the present invention. [Figure 2B] 1 is a cross-sectional view showing a configuration of a semiconductor substrate according to an embodiment of the present invention. [Figure 3] 1A to 1C are plan views showing an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present invention. [Figure 4] 1 is a flowchart showing an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present invention. [Figure 5]1 is a block diagram showing an example of a semiconductor substrate manufacturing apparatus according to an embodiment of the present invention; [Figure 6] 1 is a flowchart illustrating an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 1 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to an embodiment of the present invention; [Figure 8] 1 is a schematic diagram illustrating a configuration of an electronic device according to an embodiment of the present invention. [Figure 9] FIG. 1 is a plan view showing a configuration of a semiconductor substrate according to a first embodiment. [Figure 10] FIG. 10 is a cross-sectional view taken along the arrow cc in FIG. 9. [Figure 11] FIG. 10 is a cross-sectional view taken along the arrow dd in FIG. 9. [Figure 12] 3A to 3C are plan views showing a step of dividing the semiconductor device into individual pieces in the first embodiment. [Figure 13] 4A to 4C are cross-sectional views showing a step of dividing the semiconductor device into individual pieces in the first embodiment. [Figure 14A] 4 is a cross-sectional view showing another configuration of the semiconductor substrate according to the first embodiment. FIG. [Figure 14B] 4 is a cross-sectional view showing another configuration of the semiconductor substrate according to the first embodiment. FIG. [Figure 15] 4 is a plan view showing another configuration of the semiconductor substrate according to the first embodiment. FIG. [Figure 16] 1 is a flowchart showing a method for manufacturing a template substrate in the first embodiment. [Figure 17] 17A to 17C are cross-sectional views showing the manufacturing method of FIG. 16. [Figure 18] 10 is a flowchart showing another method for manufacturing the template substrate in the first embodiment. [Figure 19] 19A to 19C are cross-sectional views showing the manufacturing method of FIG. 18. [Figure 20] 3 is a flowchart showing a method for manufacturing a semiconductor substrate in the first embodiment. [Figure 21] 21A to 21C are cross-sectional views showing the manufacturing method of FIG. 20. [Figure 22] 4 is a plan view showing another configuration of the semiconductor substrate according to the first embodiment. FIG. [Figure 23] 4 is a plan view showing another configuration of the semiconductor substrate according to the first embodiment. FIG. [Figure 24] 5A to 5C are cross-sectional views showing another method for manufacturing the semiconductor substrate in the first embodiment. [Figure 25] FIG. 10 is a plan view showing the configuration of a semiconductor substrate according to a second embodiment. [Figure 26] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor substrate according to a second embodiment. [Figure 27] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor substrate according to a second embodiment. [Figure 28] FIG. 10 is a schematic cross-sectional view showing the configuration of Example 4. [Figure 29] FIG. 10 is a cross-sectional view showing an example of application of the fourth embodiment to an electronic device. [Figure 30] FIG. 10 is a schematic cross-sectional view showing the configuration of Example 5. [Figure 31] FIG. 10 is a plan view showing a semiconductor substrate according to a sixth embodiment. [Figure 32] 10 is a cross section showing a semiconductor substrate of Example 6. DETAILED DESCRIPTION OF THE INVENTION

[0006] [Semiconductor substrate] FIG. 1 is a plan view showing the configuration of first and second semiconductor portions of a semiconductor substrate according to this embodiment. FIGS. 2A and 2B are cross-sectional views showing the configuration of a semiconductor substrate according to this embodiment. As shown in FIGS. 1, 2A, and 2B, a semiconductor substrate 10 (semiconductor wafer) according to this embodiment includes a main substrate 1, a seed portion SD located above the main substrate 1, and a first semiconductor portion 8F and a second semiconductor portion 8S arranged in a first direction (Y direction). The first semiconductor portion 8F and the second semiconductor portion 8S are in contact with the seed portion SD. The seed portion SD has the Y direction as its longitudinal direction. A hollow portion (void portion) VD is located between the main substrate 1 and the first semiconductor portion 8F and the second semiconductor portion 8S. In the present disclosure, the first semiconductor portion 8F and the second semiconductor portion 8S may be a first semiconductor layer 8F and a second semiconductor layer 8S formed in a layered structure.

[0007] An upwardly protruding convex portion 1Q is provided on the upper surface 1f of the main substrate, and the seed portion SD is located on the convex portion 1Q. A mask pattern 6 having an opening K and a mask portion 5 is provided above the main substrate 1, and in plan view, the opening K and the seed portion SD overlap, and a hollow portion VD is located between the first and second semiconductor portions 8F / 8S and the mask portion 5.

[0008] The first semiconductor portion 8F includes a first floating portion P1 facing the main substrate 1 across the hollow portion VD, and the second semiconductor portion 8S includes a second floating portion P2 facing the main substrate 1 across the hollow portion VD, with the first floating portion P1 and the second floating portion P2 being separated. The first semiconductor portion 8F includes a third floating portion P3 that pairs with the first floating portion P1, and the first floating portion P1 and the third floating portion P3 are aligned in a second direction (X direction) perpendicular to the first direction (Y direction) in a floating state (no support member below, in a state in contact with the hollow portion). The second semiconductor portion 8S includes a fourth floating portion P4 that pairs with the second floating portion P2, and the second floating portion P2 and the fourth floating portion P4 are aligned in a floating state in the X direction.

[0009] The first semiconductor portion 8F includes a first base portion BF located on the seed portion SD, and the first base portion BF is located between and connected to the first and third floating portions P1 and P3. The second semiconductor portion 8S includes a second base portion BS located on the seed portion SD, and the second base portion BS is located between and connected to the second and fourth floating portions P2 and P4.

[0010] The first floating part P1 includes a tether part T1 connected to the first base part BF and a main part H1 connected to the tether part T1, and the tether part T1 has a length in the Y direction smaller than that of the main part H1. The third floating part P3 includes a tether part T3 connected to the first base part BF and a main part H3 connected to the tether part T3, and the tether part T3 has a length in the Y direction smaller than that of the main part H3. Note that the configuration of the tether part T1 is not limited to this. The tether part T1 may have the same length in the Y direction as the main part H1 and a smaller thickness (size in the Z direction) than that of the main part H1. Furthermore, the tether part T1 may have a length in the Y direction smaller than that of the main part H1 and a smaller thickness than that of the main part H1.

[0011] The semiconductor substrate 10 includes a third conductor portion 8T located on the seed portion SD, and the first base portion BF and the second base portion BS are connected via the third semiconductor portion 8T. In the present disclosure, the third conductor portion 8T is formed in a layer shape, and may hereinafter be referred to as a third conductor layer 8T.

[0012] In the semiconductor substrate 10, multiple layered members are stacked on the main substrate 1, and the stacking direction can be referred to as the "upward direction." Also, viewing the semiconductor substrate 10 from a line of sight parallel to the normal direction of the semiconductor substrate 10 can be referred to as a "planar view." A semiconductor substrate refers to a substrate that includes a semiconductor portion, and the main substrate 1 may be a semiconductor or a non-semiconductor. The main substrate 1, mask pattern 6, and layered first seed portion S1 may be collectively referred to as the template substrate 7.

[0013] The first and second semiconductor portions 8F and 8S include nitride semiconductors. A nitride semiconductor can be expressed as AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and examples include GaN, AlGaN, AlGaInN, and InGaN. The first and second semiconductor portions 8F and 8S may be doped (e.g., n-type containing donors) or undoped.

[0014] The first and second semiconductor portions 8F and 8S can be formed using the ELO (Epitaxial Lateral Overgrowth) method. In the ELO method, for example, as shown in FIGS. 2A and 2B, a heterogeneous substrate having a lattice constant different from that of a GaN-based semiconductor is used as the main substrate 1, a nitride semiconductor is used for the seed portion SD, and an inorganic compound film is used for the mask portion 5, and the first semiconductor portion 8F including a GaN-based semiconductor can be grown in the lateral direction (X direction) from the first base portion BF above (in the air) the mask portion 5. In this case, the thickness direction (Z direction) of the first semiconductor portion 8F is oriented in the lateral direction (X direction) of the GaN-based crystal. <0001> The longitudinal direction (first direction, Y direction) of the seed portion SD and opening K, which are longitudinal shapes, can be set to the <1-100> direction (m-axis direction) of the GaN-based crystal, and the width direction (second direction, X direction) of the seed portion SD and opening K can be set to the <11-20> direction (a-axis direction) of the GaN-based crystal. The layer formed by the ELO method (including the first and second semiconductor portions 8F, 8S, etc.) is sometimes referred to as the ELO semiconductor portion 8.

[0015] The first semiconductor portion 8F formed by the ELO method includes a low-dislocation portion (first floating portion P1) that overlaps the mask portion 5 in plan view and has relatively few threading dislocations, and a first base portion BF that overlaps the seed SD of the opening K in plan view and has relatively more threading dislocations than the low-dislocation portion. The low-dislocation portion may have a higher non-threading dislocation density than the threading dislocation density. When a layered active portion (hereinafter simply referred to as an active layer) is included above the first semiconductor portion 8F, for example, the light-emitting region of the active layer can be provided so as to overlap the low-dislocation portion in plan view.

[0016] Threading dislocations are dislocations (defects) that extend from the lower surface or interior of the first semiconductor portion 8F to its surface or surface layer along the thickness direction (Z direction) of the first semiconductor portion 8F. Threading dislocations can be observed by performing CL (cathode luminescence) measurement on the surface layer (parallel to the c-plane) of the first semiconductor portion 8F. Non-threading dislocations are dislocations that are measured by CL in a cross section taken along a plane parallel to the thickness direction (for example, the m-plane), and are mainly basal plane (c-plane) dislocations.

[0017] A layered functional section 9 is provided on at least the first and second semiconductor sections 8F and 8S. The functional layer 9 (hereinafter simply referred to as the functional layer) may be a single layer or a laminate. The functional layer 9 may have at least one of the following functions: a function as a component of a semiconductor device; a function to protect against external forces; a function to protect against static electricity; a function to prevent the intrusion of foreign substances such as water and oxygen; a function to protect against etchants and the like; an optical function; and a sensing function. The functional layer 9 may also be formed on the side surfaces (end faces) of the first and second semiconductor sections 8F and 8S.

[0018] 1, 2A, and 2B, the first floating portion P1 of the first semiconductor portion 8F that contacts the hollow portion VD (but does not contact the seed portion SD) and the second floating portion P2 of the second semiconductor portion 8S that contacts the hollow portion VD (but does not contact the seed portion SD) are separated from each other. This facilitates the singulation process for obtaining semiconductor devices including main body portions H1 and H3 from the semiconductor substrate 10. For example, the main body portion H1 of the first floating portion P1 can be separated from the semiconductor substrate 10 by simply breaking the tether portion T1. Furthermore, because the main body portion H1 is floating above the main substrate 1, stress from the main substrate 1 is alleviated, reducing cracks and defects in the main body portion H1. Furthermore, by floating the main body portion H1 above the main substrate 1 and disposing a mask portion 5 that functions as a selective growth mask (deposition suppression mask) below the main body portion H1, the main body portion H1 becomes a low-dislocation portion, and an active region (e.g., a light-emitting region) can be formed so as to overlap with the low-dislocation portion in plan view. The threading dislocation density of the low-dislocation portion is, for example, 5×10 6 [pcs / cm 2 ] or less, and the size of the main body portion H1 in the X direction can be 10 μm or more. Furthermore, the main body portion H1 and the tether portion T1 can be formed by a simple process such as etching after forming the ELO semiconductor portion.

[0019] [Manufacturing of semiconductor substrates] FIG. 3 is a plan view illustrating an example of a method for manufacturing a semiconductor substrate according to this embodiment. FIG. 4 is a flowchart illustrating an example of a method for manufacturing a semiconductor substrate according to this embodiment. In the method for manufacturing a semiconductor substrate illustrated in FIGS. 3 and 4, after preparing a template substrate 7, an ELO semiconductor portion (air bridge structure) 8 that is not in contact with the mask pattern 6 is formed on the template substrate 7. Then, the ELO semiconductor portion 8 is patterned (e.g., etched) using photolithography to form first and second semiconductor portions 8F and 8S. This process forms a first floating portion P1 including a main body portion H1 and a tether portion T1, and a second floating portion P2 separated from the first floating portion P1. Note that a process for forming a functional layer 9 can be performed before or after the process for patterning the ELO semiconductor portion 8.

[0020] FIG. 5 is a block diagram showing an example of a semiconductor substrate manufacturing apparatus according to this embodiment. The semiconductor substrate manufacturing apparatus 70 of FIG. 5 includes a semiconductor portion forming unit 72 that performs a process of forming first and second semiconductor portions 8F-8S on a template substrate 7, and a control unit 74 that controls the semiconductor portion forming unit 72. The semiconductor portion forming unit 72 forms an ELO semiconductor portion 8 that does not contact the mask pattern 6, and then performs a process of patterning the ELO semiconductor portion 8 using, for example, photolithography to form the first and second semiconductor portions 8F-8S. The semiconductor substrate manufacturing apparatus 70 may also be configured to form a functional layer 9.

[0021] The semiconductor portion forming unit 72 may include an MOCVD apparatus and a patterning apparatus, and the control unit 74 may include a processor and a memory. The control unit 74 may be configured to control the semiconductor portion forming unit 72 by executing a program stored in, for example, an internal memory, a communication device capable of communication, or an accessible network, and this program and a recording medium on which this program is stored are also included in this embodiment.

[0022] [Semiconductor device manufacturing] Fig. 6 is a flowchart showing an example of a method for manufacturing a semiconductor device according to this embodiment. In the method for manufacturing a semiconductor device shown in Fig. 6, after the step of preparing a semiconductor substrate 10, a step of breaking the tether portions T1 and the like to separate the main body portions H1 and the like from the semiconductor substrate 10 is performed to obtain a semiconductor device.

[0023] Fig. 7 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to this embodiment. The semiconductor device manufacturing apparatus 80 in Fig. 7 includes a semiconductor device generation unit 82 and a control unit 84 that controls the semiconductor device generation unit 82. The semiconductor device generation unit 82 performs a step of breaking the tether portion T1 to separate the main body portion HT from the semiconductor substrate 10, thereby obtaining a semiconductor device. The semiconductor device manufacturing apparatus 80 may also be configured to form the functional layer 9.

[0024] [Semiconductor Devices] The main body portion H1 separated from the semiconductor substrate 10 can function as a semiconductor device. Specific examples of semiconductor devices include a light-emitting diode (LED), a semiconductor laser, a Schottky diode, a photodiode, and a transistor (including a power transistor and a high electron mobility transistor).

[0025] [Electronic equipment] 8 is a schematic diagram showing the configuration of an electronic device according to this embodiment. The electronic device 30 in Fig. 8 includes a semiconductor device 20 including a main body H1, a drive substrate 23 on which the semiconductor device 20 is mounted, and a control circuit 25 that controls the drive substrate 23.

[0026] Examples of the electronic device 30 include a display device, a laser emitting device (including a Fabry-Perot type and a surface emitting type), a lighting device, a communication device, an information processing device, a sensing device, and a power control device.

[0027] Example 1 (Overall composition) Fig. 9 is a plan view showing the configuration of a semiconductor substrate according to Example 1. Fig. 10 is a cross-sectional view taken along the line cc in Fig. 9. Fig. 11 is a cross-sectional view taken along the line dd in Fig. 9. As shown in Figs. 9 to 11, the semiconductor substrate 10 according to Example 1 includes a main substrate 1, a seed portion SD located above the main substrate 1, and a first semiconductor portion 8F and a second semiconductor portion 8S aligned in the Y direction, the first semiconductor portion 8F and the second semiconductor portion 8S being in contact with the seed portion SD, and a hollow portion (void portion) VD being located between the main substrate 1 and the first semiconductor portion 8F and the second semiconductor portion 8S.

[0028] The first semiconductor portion 8F includes a first floating portion P1 that contacts the hollow portion VD, and the second semiconductor portion 8S includes a second floating portion P2 that contacts the hollow portion VD, with the first floating portion P1 and the second floating portion P2 being separated. The first semiconductor portion 8F also includes a third floating portion P3 that pairs with the first floating portion P1, with the first floating portion P1 and the third floating portion P3 aligned in a floating state in the X direction. The first semiconductor portion 8F also includes a first base portion BF located on the seed portion SD, and the first base portion BF is located between the first and third floating portions P1 and P3 and connected to them.

[0029] In Example 1, the length of the first floating portion P1 in the X direction is greater than the thickness of the first floating portion P1. A protrusion 1Q protruding upward is provided on the upper surface 1F of the main substrate, and the seed portion SD is located on the protrusion 1Q, and the length of the first floating portion P1 in the X direction is greater than the height of the protrusion 1Q. The first floating portion P1 includes a tether portion T1 connected to the first base portion BF and a main body portion H1 connected to the tether portion T1, and the length of the tether portion T1 in the Y direction is shorter than that of the main body portion H1.

[0030] The semiconductor substrate 10 includes a functional layer 9 that overlaps the first floating portion P1 in a planar view. The functional layer 9 overlaps the main body portion H1 and the tether portion T1 in a planar view. The length of the tether portion T1 in the Y direction is greater than the thickness of the tether portion T1. The length of the tether portion T1 in the Y direction is equal to or less than half the length of the main body portion H1 in the Y direction.

[0031] The functional layer 9 is not limited to a configuration in which it overlaps the main body portion H1 and the tether portion T1 in a planar view. It may also be a configuration in which the functional layer 9 does not overlap the tether portion T1 in a planar view, i.e., the functional layer 9 is stacked on the main body portion H1 but not on the tether portion T1. This configuration makes it easier for the tether portion T1 to break during singulation.

[0032] The semiconductor substrate 10 has a mask pattern 6 having an opening K and a mask portion 5 (selective growth mask) above the main substrate 1, and the opening K overlaps with the seed portion SD in plan view. A hollow portion VD is located between the first semiconductor portion 8F and the mask portion 5. The mask portion 5 covers the end face of the seed portion SD. That is, the upper surface of the seed portion SD contacts the first base portion BF, the lower surface of the seed portion SD contacts the upper surface (protrusion 1Q) of the main substrate 1, and the end face (side surface) is covered by the mask portion 5. Therefore, the semiconductor portion 8F does not contact the end face of the seed portion SD.

[0033] 12 is a plan view showing a process of singulating the semiconductor device in Example 1. FIG. 13 is a cross-sectional view showing the process of singulating the semiconductor device in Example 1. As shown in FIGS. 12 and 13, for example, by breaking the tether portions T1 to T3, the main body portion H1 of the first floating portion P1 and the main body portion H3 of the third floating portion P3 are separated from the semiconductor substrate 10, thereby obtaining the semiconductor device 20. A part Tf of the tether portion T1 may remain on one side surface of the semiconductor device 20, and an anchor film 9a (described later) may remain on the other side surface.

[0034] The tether portions T1 and T3 can be broken by applying downward pressure to the functional layer 9 from above (pushing) or by using a laser. They can also be broken by controlling the temperature of the semiconductor substrate 10. For example, a Peltier element can be used to cool the semiconductor substrate 10 with adhesive tape attached. At this time, the adhesive tape, which generally has a larger thermal expansion coefficient than the semiconductor, contracts significantly, applying stress to the tether portions T1 and T3. Another method involves bonding a support substrate to the semiconductor substrate 10 and mechanically applying an upward force to the tether portions T1 and T3 to break them.

[0035] (Main board) The main substrate 1 can be a heterogeneous substrate having a lattice constant different from that of the GaN-based semiconductor. Examples of heterogeneous substrates include single-crystal silicon (Si) substrates, sapphire (Al2O3) substrates, and silicon carbide (SiC) substrates. The surface orientation of the main substrate 1 is, for example, the (111) surface of a silicon substrate, the (0001) surface of a sapphire substrate, or the 6H-SiC (0001) surface of a SiC substrate. These are merely examples, and any main substrate and surface orientation that allows the growth of an ELO semiconductor portion can be used.

[0036] (Seed section) The seed portion SD is a growth starting point for the ELO semiconductor portion, and may be made of a nitride semiconductor (GaN-based semiconductor, AlN, InAlN, InN, etc.), silicon carbide (SiC), etc. For example, aluminum nitride (AlN) locally formed on a convex portion of the main substrate 1, which is a silicon substrate or silicon carbide substrate, can be used as the seed portion SD. Alternatively, a GaN-based semiconductor locally formed on a convex portion of the main substrate 1, which is a silicon carbide substrate, can be used as the seed portion SD.

[0037] FIG. 14A is a cross-sectional view showing another configuration of the semiconductor substrate according to Example 1. As shown in FIG. 14A, a seed portion SD made of a GaN-based semiconductor may be locally formed on a convex portion of a main substrate 1, which is a silicon substrate, via a buffer portion 2B (e.g., AlN). When a silicon substrate is used as the main substrate 1 and a GaN-based semiconductor is used as the seed portion SD, the two (silicon substrate and GaN-based semiconductor) may melt together. Therefore, providing a buffer portion 2B such as AlN can suppress this melting. Furthermore, providing a buffer portion 2B whose lattice constant is close to that of a GaN-based semiconductor can also be expected to improve the crystallinity of the seed portion SD. AlN formed at a low temperature (800°C or less) may be used as the buffer portion 2B. This improves the crystallinity of the seed portion SD (e.g., a GaN-based semiconductor). The seed portion SD and the buffer portion 2B may be formed by a method other than the MOCVD method, such as a sputtering method. This can reduce consumable costs, depreciation costs, and productivity. FIG. 14B is a cross-sectional view showing another configuration of the semiconductor substrate according to Example 1. As shown in FIG. 14B, a seed portion SD may be provided on a part of the upper surface of the protrusion 1Q.

[0038] (Mask pattern) The mask pattern 6 has a mask portion 5 and an opening K, and the seed portion SD is exposed at the opening K. The opening K may be a plurality of slits extending in the Y direction, with the mask portion 5 positioned between adjacent openings K. FIG. 15 is a plan view showing another configuration of the semiconductor substrate according to the first embodiment. As shown in FIG. 15, the openings K and the seed portion SD may be separated in the Y direction. That is, a plurality of seed portions SD with the Y direction as their longitudinal direction are aligned in the Y direction. This forms a plurality of ELO semiconductor portions aligned in the Y direction, which can relieve stress generated mainly between the main substrate 1 and the first semiconductor portion 8F. This reduces the occurrence of defects and cracks in the first semiconductor portion 8F. Furthermore, warping of the main substrate 1 is reduced, making it easier to increase the diameter of the main substrate 1. The mask portion 5 and the opening K refer to portions with and without a mask body, and the mask portion 5 may or may not be layered. The mask pattern 6 may be a mask layer. The entire opening K does not have to be surrounded by the mask portion 5.

[0039] The mask portion 5 may be a single layer film containing one of silicon oxide (SiOx), titanium nitride (TiN, etc.), silicon nitride (SiNx), silicon oxynitride (SiON), and a metal film with a high melting point (e.g., 1000°C or higher), or a laminated film containing at least two of these. While a small amount of silicon oxide may decompose or evaporate during the formation of the ELO semiconductor portion and become incorporated into the ELO semiconductor portion, silicon nitride and silicon oxynitride films have the advantage of being less susceptible to decomposition and evaporation at high temperatures. Therefore, the mask portion 5 may be a single layer film of silicon nitride or silicon oxynitride, a laminated film in which a silicon oxide film and a silicon nitride film are formed in this order, a laminated film in which a silicon nitride film and a silicon oxide film are formed in this order, or a laminated film in which a silicon nitride film, a silicon oxide film, and a silicon nitride film are formed in this order.

[0040] (template substrate) FIG. 16 is a flowchart showing a manufacturing method of the template substrate in Example 1. FIG. 17 is a cross-sectional view showing the manufacturing method of FIG. 16. In FIGS. 16 and 17, the following steps are performed: forming a seed layer SL and a sacrificial film ZF (e.g., photoresist) on a main substrate 1 in this order; patterning the seed layer SL using the patterned sacrificial film ZF as a mask pattern; etching the surface of the main substrate 1 using the sacrificial film ZF as a mask pattern to form a convex portion 1Q; forming a mask pattern 6 (using, for example, sputtering or PECVD) that covers the main substrate 1 and the sacrificial film ZF; and removing the photoresist with a remover to form an opening K and a mask portion 5 that expose the seed portion SD. In this case, the mask portion 5 is configured to cover the end face (side face) of the seed portion SD.

[0041] FIG. 18 is a flowchart showing another method for manufacturing the template substrate in Example 1. FIG. 19 is a cross-sectional view showing the manufacturing method of FIG. 18. In FIGS. 18 and 19, the following steps are performed: forming a seed layer SL and a sacrificial film ZF (silicon oxide film or resist film) in this order on a main substrate 1, which is a silicon substrate or a silicon carbide substrate; patterning the seed layer SL and the sacrificial film ZF; etching the surface of the main substrate 1 using the sacrificial film ZF as a mask pattern to form a protrusion 1Q; etching (removing) the sacrificial film ZF; and performing a substrate processing process (thermal oxidation process or nitriding process) on the surface of the main substrate 1 to form a mask portion 5 and an opening K, which are a substrate processing film (silicon thermal oxide film, silicon nitride film, or silicon oxynitride film). The substrate processing film has excellent film quality and is suitable for a selective growth mask that is subjected to high temperatures.

[0042] The thickness of the mask pattern 6 is, for example, about 100 nm to 4 μm (preferably about 150 nm to 2 μm), and the width of the openings K is about 0.1 μm to 20 μm. The smaller the width of the openings K, the fewer the number of threading dislocations propagating from each opening K to the ELO semiconductor portion 8. In addition, the area of ​​the main body portion (H1, etc.), which is a low-dislocation portion, can be increased.

[0043] (ELO semiconductor film formation) In Example 1, the ELO semiconductor portion (including 8F, 8S, and 8T) was a GaN layer, and an MOCVD (Metal Organic Chemical Vapor Deposition) apparatus was used to perform ELO film formation on the above-mentioned template substrate 7. Examples of ELO film formation conditions that can be used are: substrate temperature: 1120°C, growth pressure: 50 kPa, TMG (trimethylgallium): 22 sccm, NH3: 15 slm, and V / III=6000 (ratio of the supply amount of group V raw materials to the supply amount of group III raw materials).

[0044] In this case, the ELO semiconductor portion is selectively grown on the seed portion SD and then grows laterally above (in the air) the mask portion 5. Then, the lateral growth is stopped before the ELO semiconductor portions growing laterally above the mask portion 5 from both sides thereof meet.

[0045] The method for increasing the lateral film formation rate is as follows. First, a vertically grown layer that grows in the Z direction (c-axis direction) is formed on the seed part SD, and then a horizontally grown layer that grows in the X direction (a-axis direction) is formed. To achieve vertical growth, the growth temperature is set low, for example, to 1050°C. In this case, by setting the thickness of the vertically grown layer to 10 μm or less, preferably 5 μm or less, and more preferably 3 μm or less, the thickness of the horizontally grown layer can be kept low and the lateral film formation rate can be increased.

[0046] The film formation temperature for the ELO semiconductor portion 8 is preferably 1150° C. or lower rather than a high temperature exceeding 1200° C. The ELO semiconductor portion 8 can also be formed at a low temperature below 1000° C., which is more preferable from the viewpoint of suppressing decomposition of the mask portion 5.

[0047] It is preferable to use triethylgallium (TEG) as the gallium source gas for low-temperature film formation below 1000°C. Compared to TMG, TEG decomposes organic materials more efficiently at low temperatures, allowing for a higher lateral film formation rate.

[0048] For crystal growth in the ELO method, in addition to the above-mentioned metal organic chemical vapor deposition (MOCVD) method, hydride vapor phase epitaxy (HVPE) method, molecular beam epitaxy (MBE) method, etc. can be used.

[0049] (functional layer) The functional layer 9 located on the first and second semiconductor portions 8F-8S includes a layered device portion 9d (hereinafter simply referred to as the device layer), an insulating film 9p (passivation film) located above the device layer 9d, and first and second electrodes E1-E2 located above the insulating film 9p. The main body portion H1 and the functional layer 9 may be configured to function as semiconductor devices such as light-emitting diodes and semiconductor lasers.

[0050] The device layer 9d, the insulating film 9p, and the first and second electrodes E1 and E2 do not overlap the tether portion T1. The device layer 9d is, for example, a stack of an n-type semiconductor portion (e.g., GaN-based), an undoped semiconductor portion (e.g., GaN-based), and a p-type semiconductor portion (e.g., GaN-based), and the undoped semiconductor portion can be used as the active layer (a layer where electrons and holes recombine). The device layer 9d can be formed by any method. The insulating film 9p can be an inorganic film such as silicon oxide or silicon nitride. One of the first and second electrodes E1 and E2 can be an anode, and the other can be a cathode. The area of ​​the first electrode E1 can also be larger than the area of ​​the second electrode E2. In Example 1, the first and second electrodes E1 and E2 are provided on the device layer 9d, but this is not limiting. For example, only the first electrode E1 can be provided on the device layer 9d.

[0051] FIG. 20 is a flowchart illustrating a method for manufacturing a semiconductor substrate according to the first embodiment. FIG. 21 is a cross-sectional view illustrating the manufacturing method illustrated in FIG. 20. As illustrated in FIGS. 9, 20, and 21, the following steps are performed: forming an ELO semiconductor portion 8 on a template substrate 7; forming a device layer 9d on the ELO semiconductor portion 8; depositing an insulating film 9p on the device layer 9d by, for example, PECVD; patterning the insulating film 9p; forming first and second electrodes E1 and E2; and dry-etching (e.g., reactive ion etching: RIE) the ELO semiconductor portion 8 to form a first semiconductor portion 8F including body portions H1 and H3 and tether portions T1 and T3, and a second semiconductor portion 8S. Etching of the ELO semiconductor portion 8 can be performed using dry methods such as electron cyclotron resonance (ECR) etching and chemically assisted ion beam (CAIB) etching, as well as wet photoelectrochemical (PEC) etching.

[0052] The insulating film 9p is a passivation film (e.g., a silicon oxide film or a silicon nitride film) formed above the device layer 9d, and overlaps the main body portion H1 in a planar view but does not overlap the tether portion T1. This avoids the problem of the insulating film 9p interfering with the destruction of the tether portion T1. Furthermore, as shown in FIG. 13, a portion of the insulating film 9p (e.g., a portion covering the center of the end face of the main body portion H1 and reaching the mask portion 5 on the main substrate) functions as an anchor film 9a. This stabilizes the main body portion H1, and allows the anchor film 9a to be simultaneously destroyed when the tether portion T1 is destroyed.

[0053] When forming the ELO semiconductor portion 8, the ELO semiconductor portions growing laterally from both sides above the mask portion 5 may be caused to meet, and the meeting portion (high dislocation portion) may be removed when the ELO semiconductor portion 8 is etched.

[0054] Fig. 22 is a plan view showing another configuration of the semiconductor substrate according to the first embodiment. As shown in Fig. 22, the first floating portion P1 may include a plurality of tether portions T1-T5, and the main body portion H1 may be connected to the first base portion BF via the plurality of tether portions T1-T5. Providing a plurality of tether portions T1-T5 has the advantage of stabilizing the main body portion H1.

[0055] FIG. 23 is a plan view showing another configuration of the semiconductor substrate according to the first embodiment. As shown in FIG. 23, the tether portion T1 of the first floating portion P1 may have a notch NC. In this case, the side surface of the notch NC may be configured to form an angle of 60° with respect to the X direction. Such a notch NC can be formed, for example, by forming a semicircular notch when forming the tether portion, and then immersing the tether portion in TMAH (tetramethylammonium hydroxide) to expose the m-plane of the GaN-based semiconductor. Forming an acute-angled fracture starting point such as the notch NC makes it easier to fracture the tether portion T1.

[0056] FIG. 24 is a cross-sectional view showing another method for manufacturing the semiconductor substrate in Example 1. In FIG. 10, the main substrate 1 is provided with a protrusion 1Q, but this is not limiting. As shown in FIG. 24, a template substrate 7 including, in this order, the main substrate 1 (e.g., a silicon substrate), a planar buffer layer 2 (e.g., AlN), and a local seed portion SD (e.g., a GaN-based semiconductor) with the Y direction as its longitudinal direction, and in which the seed portion SD is exposed through an opening K in a mask pattern 6, may be used to form an ELO semiconductor portion (including a first semiconductor portion 8F) in contact with the seed portion SD and the mask portion 5, and then the mask portion 5 may be removed by etching (e.g., wet etching). This allows the first semiconductor portion 8F to be raised (with its lower surface in contact with the hollow portion VD). The mask portion 5 may also be removed before the functional layer 9 is formed.

[0057] Example 2 Fig. 25 is a plan view showing the configuration of a semiconductor substrate according to Example 2. Figs. 26 and 27 are cross-sectional views showing the configuration of a semiconductor substrate according to Example 2. In Example 1, the lateral growth of the ELO semiconductor portions growing laterally above the mask portion 5 from both sides thereof is stopped before they meet, and the first and second semiconductor portions 8F and 8S have end faces (edges) that overlap with the mask portion 5 in plan view, but this is not limiting. As shown in Figs. 25 to 27, the ELO semiconductor portions growing laterally above the mask portion 5 from both sides thereof may also meet.

[0058] 25 to 27, the first semiconductor portion 8F includes a first floating portion P1 facing the main substrate 1 across the hollow portion VD, and the second semiconductor portion 8S includes a second floating portion P2 facing the main substrate 1 across the hollow portion VD, with the first floating portion P1 and the second floating portion P2 being separated. The first semiconductor portion 8F also includes a third floating portion P3 that pairs with the first floating portion P1, with the first floating portion P1 and the third floating portion P3 aligned in a floating state in the X direction. The first semiconductor portion 8F also includes a first base portion BF located on the seed portion SD, and the first base portion BF is located between the first and third floating portions P1 and P3 and connected to them. The first floating portion P1 includes a tether portion T1 connected to the first base portion BF and a main body portion H1 connected to the tether portion T1, and the tether portion T1 has a length in the Y direction smaller than that of the main body portion H1.

[0059] The semiconductor substrate 10 has a mask pattern 6 having an opening K and a mask portion 5 (selective growth mask) above the main substrate 1, and the opening K overlaps with the seed portion SD in plan view. A hollow portion VD is located between the first semiconductor portion 8F and the mask portion 5. The mask portion 5 covers the end face of the seed portion SD. That is, the upper surface of the seed portion SD contacts the first base portion BF, the lower surface of the seed portion SD contacts the upper surface (protrusion 1Q) of the main substrate 1, and the end face (side surface) is covered by the mask portion 5. Therefore, the semiconductor portion 8F does not contact the end face of the seed portion SD.

[0060] The functional layer 9 formed on the semiconductor portion 8 includes a device layer 9d, an insulating film 9p (passivation film) located above the device layer 9d, and first and second electrodes E1 and E2 located above the insulating film 9p.

[0061] Example 3 In Examples 1 and 2, the ELO semiconductor portion is a GaN layer, but this is not limiting. In Example 3, the first and second semiconductor portions 8F and 8S (ELO semiconductor portions) can also be formed as InGaN layers, which are GaN-based semiconductor portions. The lateral deposition of the InGaN layer is performed at a low temperature, for example, below 1000°C. This is because at high temperatures, the vapor pressure of indium increases and it is not effectively incorporated into the film. The low deposition temperature has the effect of reducing the mutual reaction between the mask portion 5 and the InGaN layer. Furthermore, the InGaN layer has the effect of being less reactive with the mask portion 5 than the GaN layer. It is desirable to incorporate indium into the InGaN layer at an In composition level of 1% or more, as this further reduces the reactivity with the mask portion 5. Triethylgallium (TEG) is preferably used as the gallium source gas.

[0062] Example 4 FIG. 28 is a schematic cross-sectional view showing the configuration of Example 4. In Example 4, a semiconductor device 20 functioning as an LED (light-emitting diode) is configured by a main body portion H1 and a device layer 9d. The main body portion H1 (e.g., a GaN-based semiconductor) is, for example, an n-type doped with silicon or the like. The device layer 9d includes, from bottom to top, an active layer 34, an electron-blocking layer 35, and a GaN-based p-type semiconductor portion 36. The active layer 34 is an MQW (multi-quantum well) and includes an InGaN layer and a GaN layer. The electron-blocking layer 35 is, for example, an AlGaN layer. The GaN-based p-type semiconductor portion 36 is, for example, a GaN layer. An anode 38 (e.g., a first electrode E1) is arranged so as to be in contact with the GaN-based p-type semiconductor portion 36, and a cathode 39 (e.g., a second electrode E2) is arranged so as to be in contact with the main body portion H1.

[0063] 29 is a cross-sectional view showing an example of application of Example 4 to an electronic device. According to Example 4, a red micro LED 20R, a green micro LED 20G, and a blue micro LED 20B can be obtained, and by mounting these on a drive substrate (TFT substrate) 23, a micro LED display 30D (electronic device) can be configured. As an example, the red micro LED 20R, the green micro LED 20G, and the blue micro LED 20B are mounted on a plurality of pixel circuits 27 of the drive substrate 23 via a conductive resin 24 (e.g., anisotropic conductive resin) or the like, and then a control circuit 25, a driver circuit 29, etc. are mounted on the drive substrate 23. A part of the driver circuit 29 may be included in the drive substrate 23.

[0064] Example 5 FIG. 30 is a schematic cross-sectional view showing the configuration of Example 5. In Example 5, a semiconductor device 20 functioning as a semiconductor laser is formed by a main body H1 and a device layer 9d. The device layer 9d includes, from bottom to top, an n-type cladding layer 41, an n-type optical guide layer 42, an active layer 43, an electron blocking layer 44, a p-type optical guide layer 45, a p-type cladding layer 46, and a GaN-based p-type semiconductor portion 47. Each of the optical guide layers 42 and 45 may be an InGaN layer. Each of the cladding layers 41 and 46 may be a GaN layer or an AlGaN layer. An anode 48 is disposed in contact with the GaN-based p-type semiconductor portion 47, and the main body H1 is mounted on an n-pad 49 of a mounting substrate 53.

[0065] Example 6 FIG. 31 is a plan view showing a semiconductor substrate of Example 6. FIG. 32 is a cross-sectional view showing the semiconductor substrate of Example 6. The semiconductor substrate 10 of Example 6 includes a template substrate 7 including first and second seed regions J1 and J2 and growth-inhibiting regions (deposition-inhibiting regions) SP on its upper surface; a first semiconductor portion 8F extending from the first seed region J1 to above the growth-inhibiting regions SP and forming a hollow portion VD between the first semiconductor portion 8F and the growth-inhibiting regions SP; and a second semiconductor portion 8S extending from the second seed region J2 to above the growth-inhibiting regions SP and forming a hollow portion VD between the first semiconductor portion 8F and the second semiconductor portion 8S. The first and second semiconductor portions 8F and 8S are adjacent to each other in the first direction (Y direction) with a gap G1 between them. The Y direction may be the m-axis direction of the first and second semiconductor portions 8F and 8S containing nitride semiconductors. The first and second seed regions J1 and J2 may be located above the growth-inhibiting regions SP.

[0066] The first and second seed regions J1 and J2 may be shaped such that their longitudinal axis is in the Y direction. Both ends of each of the first and second semiconductor portions 8F and 8S may be tapered in the Y-axis direction. A fourth semiconductor portion 8U may be disposed adjacent to the first semiconductor portion 8F in the X-direction, with a gap G2 between them. The X-direction may be the a-axis direction of the first and second semiconductor portions 8F and 8U, which include nitride semiconductors. The semiconductor substrate 10 has the advantage of being less prone to warping. The first and second seed regions J1 and J2 may be regions of the top surface of the seed portion that overlap with the openings of the mask pattern, and the growth suppression region SP may be the top surface of the mask portion. [Explanation of symbols]

[0067] 1 Main board SD Seed Department 5 Mask section 6 Mask Pattern 7 Template substrate 8F 1st Semiconductor Department 8S 2nd Semiconductor Department 9 Functional Layer 9d Device Layer 10. Semiconductor substrate 20 Semiconductor Devices 30 Electronic equipment 70 Semiconductor substrate manufacturing equipment K opening VD hollow part P1 First floating section P2 Second floating part P3 3rd floating section H1 main body T1 Tether section

Claims

1. a template substrate including a mask pattern on an upper surface thereof, the mask pattern having a mask portion and an opening; a semiconductor portion having a first portion extending upward from the opening and a second portion extending from the first portion above the mask portion, The opening has a shape whose longitudinal direction is in the first direction, a hollow portion is located between the second portion and the mask portion; The second portion includes a main body portion and a tether portion that is located closer to the first portion than the main body portion and has a length in the first direction that is smaller than that of the main body portion.

2. When a direction perpendicular to the first direction is defined as a second direction, The semiconductor substrate according to claim 1 , wherein the length of the main body in the first direction is greater than the length of the main body in the second direction.

3. The semiconductor substrate according to claim 1 , wherein the length of the tether portion in the first direction is equal to or less than half the length of the main body portion in the first direction.

4. The semiconductor substrate according to claim 1 , wherein the length of the tether portion in the first direction is greater than the thickness of the tether portion.

5. the semiconductor portion includes a nitride semiconductor, The semiconductor substrate of claim 1 , wherein the first direction is a <1-100> direction of the nitride semiconductor.

6. 6. The semiconductor substrate according to claim 1, wherein the threading dislocation density of said second portion is lower than the threading dislocation density of said first portion.

7. The threading dislocation density of the second portion is 5×10 ６ [pcs / cm ２ 6. The semiconductor substrate according to claim 1, wherein the surface roughness is 0.05 or less.

8. When a direction perpendicular to the first direction is defined as a second direction, 6. The semiconductor substrate according to claim 1, wherein the length of said main body portion in said second direction is 10 μm or more.

9. 6. The semiconductor substrate according to claim 1, wherein the tether portion has a notch whose length in the first direction is smaller than that of other portions of the tether portion.

10. a step of preparing a semiconductor substrate, the semiconductor substrate comprising: a template substrate including, on an upper surface thereof, a mask pattern having a mask portion and an opening; and a semiconductor portion having a first portion extending upward from the opening and a second portion extending from the first portion above the mask portion, wherein the opening has a shape with a longitudinal direction in a first direction, a hollow portion being located between the second portion and the mask portion, and the second portion including a main portion and a tether portion being located closer to the first portion than the main portion and having a length in the first direction smaller than that of the main portion; and breaking the tether portion.

11. The method for manufacturing a semiconductor device according to claim 10 , wherein a part of the tether portion remains on a side surface of the main body portion after the breaking.

12. The method for manufacturing a semiconductor device according to claim 10 , further comprising the step of forming a functional layer on the main body portion prior to the step of breaking the tether portion.

13. The method for manufacturing a semiconductor device according to claim 12 , wherein the functional layer includes an electrode and an active layer.

14. The method for manufacturing a semiconductor device according to claim 12 , wherein in the step of breaking the tether portion, the tether portion is broken by applying pressure to the functional layer.

15. The step of preparing a semiconductor substrate includes: preparing a substrate including the template substrate and a semiconductor portion having a first portion extending upward from the opening and a second portion extending from the first portion above the mask portion; The method for manufacturing a semiconductor device according to any one of claims 10 to 12, further comprising the step of: forming the tether portion and the main body portion by etching the second portion.

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