Power conversion device

Abstract

To provide a power conversion device capable of reducing switching loss.SOLUTION: A power conversion device includes: an input terminal; a reactor provided on a path connecting the input terminal and a first node; a plurality of switching elements including first and second switching elements provided on a first path connecting the first node and a second node with a first intermediate node being interposed therebetween; a plurality of rectifier elements including first and second rectifier elements provided on a second path connecting the first node and a third node with a second intermediate node being interposed therebetween; a first capacitor having one end connected to the first intermediate node and the other end connected to the second intermediate node; an output terminal; and a control circuit capable of controlling operation of the plurality of switching elements such that a waveform of an input current becomes the same as a waveform of an input voltage. The control circuit may reduce a switching frequency below a first frequency based on the input voltage.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power conversion device that converts electric power. [Background technology]

[0002] Power conversion devices often use PFC (Power Factor Correction) converters that can improve the power factor. For example, Patent Document 1 discloses a technique related to such a PFC converter. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,536,073 Summary of the Invention [Problem to be solved by the invention]

[0004] In power conversion devices, it is desirable to reduce switching loss, and further reduction in switching loss is expected.

[0005] It is desirable to provide a power converter that can reduce switching losses. [Means for solving the problem]

[0006] A power conversion device according to one embodiment of the present invention includes an input terminal, a reactor, a plurality of switching elements, a plurality of rectifying elements, a first capacitor, an output terminal, and a control circuit. The input terminal is capable of receiving an AC voltage. The reactor is provided in a path connecting the input terminal and a first node. The plurality of switching elements include a first switching element and a second switching element provided on either side of a first intermediate node in a first path connecting the first node and a second node. The plurality of rectifying elements include a first rectifying element and a second rectifying element provided on either side of a second intermediate node in a second path connecting the first node and a third node. The first capacitor has one end connected to the first intermediate node and the other end connected to the second intermediate node. The output terminal includes a first output terminal connected to the third node and a second output terminal connected to the second node. The control circuit is capable of controlling the operation of the multiple switching elements so that the waveform of the input current flowing through the input terminal is the same as the waveform of the input voltage at the input terminal. The control circuit is capable of setting the switching frequency of the multiple switching elements to a predetermined first frequency and is capable of lowering the switching frequency below the first frequency based on the input voltage. [Effects of the Invention]

[0007] According to the power conversion device according to an embodiment of the present invention, switching loss can be reduced. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram showing an example of the configuration of a power conversion device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a block diagram illustrating an example of the configuration of the control circuit shown in FIG. [Figure 3] FIG. 3 is a timing chart illustrating an example of the operation of the power conversion device shown in FIG. [Figure 4A]FIG. 4A is a waveform diagram illustrating an example of an operation of the power conversion device shown in FIG. [Figure 4B] FIG. 4B is another waveform diagram illustrating an example of an operation of the power conversion device shown in FIG. [Figure 4C] FIG. 4C is another waveform diagram illustrating an example of an operation of the power conversion device shown in FIG. [Figure 4D] FIG. 4D is another waveform diagram illustrating an example of an operation of the power conversion device shown in FIG. [Figure 5A] FIG. 5A is an explanatory diagram illustrating one operating state of the power conversion device shown in FIG. [Figure 5B] FIG. 5B is an explanatory diagram showing another operating state of the power conversion device shown in FIG. [Figure 5C] FIG. 5C is an explanatory diagram illustrating another operating state of the power conversion device shown in FIG. [Figure 5D] FIG. 5D is an explanatory diagram showing another operating state of the power conversion device shown in FIG. [Figure 6A] FIG. 6A is an explanatory diagram illustrating another operating state of the power conversion device shown in FIG. [Figure 6B] FIG. 6B is an explanatory diagram showing another operating state of the power conversion device shown in FIG. [Figure 6C] FIG. 6C is an explanatory diagram illustrating another operating state of the power conversion device shown in FIG. [Figure 6D] FIG. 6D is an explanatory diagram showing another operating state of the power conversion device shown in FIG. [Figure 7A] FIG. 7A is an explanatory diagram showing another operating state of the power conversion device shown in FIG. [Figure 7B] FIG. 7B is an explanatory diagram showing another operating state of the power conversion device shown in FIG. [Figure 7C] FIG. 7C is an explanatory diagram illustrating another operating state of the power conversion device shown in FIG. [Figure 7D] FIG. 7D is an explanatory diagram showing another operating state of the power conversion device shown in FIG. [Figure 8A]FIG. 8A is an explanatory diagram illustrating another operating state of the power conversion device shown in FIG. [Figure 8B] FIG. 8B is an explanatory diagram showing another operating state of the power conversion device shown in FIG. [Figure 8C] FIG. 8C is an explanatory diagram illustrating another operating state of the power conversion device shown in FIG. [Figure 8D] FIG. 8D is an explanatory diagram showing another operating state of the power conversion device shown in FIG. [Figure 9] FIG. 9 is a timing waveform diagram illustrating an example of the operation of the power conversion device shown in FIG. [Figure 10] FIG. 10 is another timing waveform diagram illustrating an example of an operation of the power conversion device shown in FIG. [Figure 11] FIG. 11 is an explanatory diagram illustrating an example of setting the switching frequency in the power conversion device shown in FIG. [Figure 12] FIG. 12 is a circuit diagram illustrating an example of the configuration of a power conversion device according to a modified example. [Figure 13] FIG. 13 is a timing chart illustrating an example of the operation of the power conversion device shown in FIG. [Figure 14] FIG. 14 is a circuit diagram illustrating an example of the configuration of a power conversion device according to another modified example. [Figure 15] FIG. 15 is a circuit diagram illustrating an example of the configuration of a power conversion device according to another modified example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0010] <Embodiment> [Configuration example] 1 shows an example of the configuration of a power conversion device (power conversion device 1) according to an embodiment of the present invention. Power conversion device 1 is a PFC converter capable of correcting a power factor. Power conversion device 1 is configured to convert AC power supplied from an AC power source PAC into DC power and supply the converted DC power to a load device LD. The AC power source PAC is, for example, a system power supply. Power conversion device 1 includes input terminals T11 and T12, a voltage sensor 11, a current sensor 12, a reactor 13, transistors S1, S2, S3, and S4, a capacitor 14, diodes 15 and 16, a capacitor 17, a voltage sensor 18, a control circuit 20, and output terminals T21 and T22.

[0011] The input terminals T11 and T12 are configured to receive AC power from an AC power supply PAC.

[0012] One end of the voltage sensor 11 is connected to the input terminal T11, and the other end is connected to the input terminal T12. The voltage sensor 11 is configured to detect the voltage Vin at the input terminal T11 relative to the voltage at the input terminal T12.

[0013] The current sensor 12 is provided on a path connecting the input terminal T11 and the node N1. One end of the current sensor 12 is connected to the input terminal T11, and the other end is connected to one end of the reactor 13. The current sensor 12 is configured to detect a current Iin that flows from the input terminal T11 toward the node N1.

[0014] One end of the reactor 13 is connected to the other end of the current sensor 12, and the other end is connected to the node N1.

[0015] The transistors S1 to S4 are configured to perform switching operations. The transistors S1 to S4 are configured using, for example, N-type field effect transistors (FETs). Note that, although N-type field effect transistors are used in this example, any switching element may be used. Each of the transistors S1 to S4 has a body diode and a parasitic capacitor. For example, the anode of the body diode of the transistor S1 is connected to the source of the body of the transistor S1, and the cathode is connected to the drain of the body of the transistor S1. One end of the parasitic capacitor is connected to the drain of the body of the transistor S1, and the other end is connected to the source of the body of the transistor S1.

[0016] Transistors S1 and S3 are provided in a path connecting node N1 and reference voltage line L2. The drain of transistor S1 is connected to node N1, its gate is supplied with control signal G1, and its source is connected to the drain of transistor S3. The drain of transistor S3 is connected to the source of transistor S1, its gate is supplied with control signal G3, and its source is connected to reference voltage line L2.

[0017] Transistors S2 and S4 are provided in a path connecting node N1 and voltage line L1. The drain of transistor S2 is connected to the source of transistor S4, its gate is supplied with control signal G2, and its source is connected to node N1. The drain of transistor S4 is connected to voltage line L1, its gate is supplied with control signal G4, and its source is connected to the drain of transistor S2.

[0018] One end of the capacitor 14 is connected to the drain of the transistor S2 and the source of the transistor S4, and the other end is connected to the source of the transistor S1 and the drain of the transistor S3.

[0019] The anode of diode 15 is connected to the cathode of diode 16 and input terminal T12, and the cathode is connected to voltage line L1. The anode of diode 16 is connected to reference voltage line L2, and the cathode is connected to the anode of diode 15 and input terminal T12.

[0020] One end of the capacitor 17 is connected to the voltage line L1, and the other end is connected to the reference voltage line L2.

[0021] One end of the voltage sensor 18 is connected to the voltage line L1, and the other end is connected to the reference voltage line L2. The voltage sensor 18 is configured to detect the voltage Vout on the voltage line L1 relative to the voltage on the reference voltage line L2.

[0022] The control circuit 20 is configured to control the operation of the power conversion device 1 by generating control signals G1 to G4 based on the voltage Vin detected by the voltage sensor 11, the voltage Vout detected by the voltage sensor 18, and the current Iin detected by the current sensor 12. Specifically, the control circuit 20 controls the switching operations of the transistors S1 to S4 so that the voltage Vout is maintained at the target voltage Vref. The control circuit 20 also controls the switching operations of the transistors S1 to S4 so that the waveform of the input current (current Iin) of the power conversion device 1 becomes the same as the waveform of the input voltage (voltage Vin) of the power conversion device 1. The control circuit 20 is configured using, for example, a microcontroller or the like.

[0023] 2 shows an example of the configuration of the control circuit 20. The control circuit 20 receives the voltage Vin detected by the voltage sensor 11, the voltage Vout detected by the voltage sensor 18, and the current Iin detected by the current sensor 12. The control circuit 20 has an AD converter and converts the voltages Vin, Vout, and Iout into digital values ​​at a predetermined sampling frequency. The control circuit 20 then performs processing based on these digital values.

[0024] The control circuit 20 has a duty ratio calculation unit 21, a target voltage setting unit 22, a subtraction unit 23, a PI (Proportional-Integral) processing unit 24, an absolute value calculation unit 25, a multiplication unit 26, a filter processing unit 27, an absolute value calculation unit 28, a subtraction unit 29, a PI processing unit 31, an addition unit 32, a switching frequency setting unit 33, and a control signal generation unit 34.

[0025] The duty ratio calculation unit 21 is configured to calculate the switching duty ratio DT0 based on the value of the voltage Vin and the value of the voltage Vout. That is, the power conversion device 1 is supplied with the voltage Vin, which is an AC voltage, and the power conversion device 1 performs a switching operation to generate the voltage Vout, which is a DC voltage. Therefore, the switching duty ratio DT of the transistors S1 to S4 can change depending on the voltage Vin and the voltage Vout. The duty ratio calculation unit 21 is configured to calculate the switching duty ratio DT0 based on the value of the voltage Vin and the value of the voltage Vout.

[0026] The target voltage setting unit 22 is configured to set a target voltage Vref, which is a target value for the output voltage of the power conversion device 1. The target voltage setting unit 22 stores data of this target voltage Vref, and sets the target voltage Vref based on this stored data.

[0027] The subtraction unit 23 is configured to subtract the value of the target voltage Vref from the value of the voltage Vout. The control circuit 20 performs negative feedback control so that the output value of the subtraction unit 23 approaches zero.

[0028] The PI processing unit 24 is configured to perform proportional processing and integral processing in negative feedback control based on the output value of the subtraction unit 23.

[0029] The absolute value calculation unit 25 is configured to calculate the absolute value of the voltage Vin. That is, since the voltage Vin is an AC voltage centered around 0 V, the value of the voltage Vin can be positive or negative. Therefore, the absolute value calculation unit 25 calculates the absolute value of the voltage Vin, thereby outputting a positive value corresponding to the voltage Vin.

[0030] The multiplication unit 26 is configured to multiply the output value of the PI processing unit 24 by the output value of the absolute value calculation unit 25 .

[0031] The filter processing unit 27 is configured to perform low-pass filtering based on the value of the current Iin. That is, since the current Iin contains a ripple component as will be described later, the filter processing unit 27 performs low-pass filtering to reduce the ripple component contained in the current Iin.

[0032] The absolute value calculation section 28 is configured to calculate the absolute value of the output value of the filter processing section 27. That is, since the current Iin is an AC current centered around 0 A, the output value of the filter processing section 27 can take both positive and negative values. Therefore, the absolute value calculation section 28 calculates the absolute value of the output value of the filter processing section 27, thereby outputting a positive value corresponding to the current Iin.

[0033] The subtraction unit 29 is configured to subtract the output value of the absolute value calculation unit 28 from the output value of the multiplication unit 26. The control circuit 20 performs negative feedback control so that the output value of the subtraction unit 29 approaches zero.

[0034] The PI processing unit 31 is configured to perform proportional processing and integral processing in negative feedback control based on the output value of the subtraction unit 29, thereby calculating the switching duty ratio DT1.

[0035] The adding unit 32 is configured to add the switching duty ratio DT0 supplied from the duty ratio calculating unit 21 and the switching duty ratio DT1 supplied from the PI processing unit 31 together to generate the switching duty ratio DT of the transistors S1 to S4.

[0036] The switching frequency setting unit 33 is configured to set the switching frequency fsw of the transistors S1 to S4 based on the values ​​of the voltage Vin and the voltage Vout. The switching frequency setting unit 33 basically sets the switching frequency fsw to a predetermined frequency fo. The frequency fo is, for example, 50 kHz. The switching frequency setting unit 33 then sets a voltage range for the voltage Vin based on the values ​​of the voltage Vin and the voltage Vout, and reduces the switching frequency fsw from the frequency fo when the voltage Vin is within this voltage range.

[0037] The control signal generating unit 34 is configured to generate the control signals G1 to G4 based on the switching duty ratio DT supplied from the adding unit 32 and the switching frequency fsw supplied from the switching frequency setting unit 33.

[0038] The output terminals T21 and T22 are configured to supply the DC power generated by the power conversion device 1 to the load device LD. Within the power conversion device 1, the output terminal T21 is connected to the voltage line L1, and the output terminal T22 is connected to the reference voltage line L2.

[0039] Here, the input terminals T11 and T12 correspond to a specific example of an "input terminal" in an embodiment of the present disclosure. The reactor 13 corresponds to a specific example of a "reactor" in an embodiment of the present disclosure. The transistor S1 corresponds to a specific example of a "first switching element" in an embodiment of the present disclosure. The transistor S3 corresponds to a specific example of a "second switching element" in an embodiment of the present disclosure. The transistor S2 corresponds to a specific example of a "first rectifying element" in an embodiment of the present disclosure. The transistor S4 corresponds to a specific example of a "second rectifying element" in an embodiment of the present disclosure. The capacitor 14 corresponds to a specific example of a "first capacitor" in an embodiment of the present disclosure. The output terminals T21 and T22 correspond to a specific example of an "output terminal" in an embodiment of the present disclosure. The control circuit 20 corresponds to a specific example of a "control circuit" in an embodiment of the present disclosure. The current Iin corresponds to a specific example of an "input current" in an embodiment of the present disclosure. The voltage Vin corresponds to a specific example of an "input voltage" in an embodiment of the present disclosure. The switching frequency fsw corresponds to a specific example of a "switching frequency" in an embodiment of the present disclosure. The frequency fo corresponds to a specific example of a "first frequency" in an embodiment of the present disclosure. The diode 16 corresponds to a specific example of a "first diode" in an embodiment of the present disclosure. The diode 15 corresponds to a specific example of a "second diode" in an embodiment of the present disclosure.

[0040] [Actions and Actions] Next, the operation and function of the power conversion device 1 of this embodiment will be described.

[0041] (Overview of overall operation) First, an overview of the overall operation of the power conversion device 1 will be described with reference to Fig. 1. AC power is supplied to input terminals T11 and T12 of the power conversion device 1 from an AC power source PAC. A control circuit 20 generates control signals G1 to G4 based on voltages Vin and Vout and a current Iin. The transistors S1 to S4 perform switching operations based on the control signals G1 to G4, respectively. The control circuit 20 controls the switching operations of the transistors S1 to S4 so that the voltage Vout maintains the target voltage Vref. The control circuit 20 also controls the switching operations of the transistors S1 to S4 so that the waveform of the input current (current Iin) of the power conversion device 1 becomes the same as the waveform of the input voltage (voltage Vin) of the power conversion device 1. In this way, the power conversion device 1 converts the AC power supplied from the AC power source PAC into DC power and supplies the converted DC power to the load device LD.

[0042] (Detailed operation) FIG. 3 shows an example of operation of the power conversion device 1, where (A) shows the waveform of the voltage Vin, (B) shows the waveform of the current Iin, and (C) shows the magnitude of the ripple component of the current Iin. FIG. 3 shows the waveform for one cycle. Since the current Iin includes a ripple component, FIG. 3(B) shows the waveform of the current Iin using an envelope. As will be described later, the power conversion device 1 changes the switching frequency fsw based on the voltage Vin, but in FIG. 3, for convenience of explanation, the switching frequency fsw is fixed to a frequency fo.

[0043] As shown in Fig. 3(A), an AC voltage having a sine waveform is input to the power conversion device 1. Between times t1 and t4, the voltage Vin is a positive voltage, and between times t4 and t7, the voltage Vin is a negative voltage. In this example, the voltage Vin has an amplitude of 280 Vop (560 Vpp). In this example, the voltage Vout is 400 V.

[0044] As will be described later, the current Iin includes a ripple component. The magnitude of the ripple component varies depending on the voltage Vin, as shown in FIG. 3B. That is, the ripple component is small when the voltage Vin is 0V, when the voltage Vin is Vout / 2, and when the voltage Vin is -Vout / 2. In this example, the ripple component is small at each of the times t1 to t7. The voltage Vin can vary over four ranges RG1 to RG4. The range RG1 is greater than 0 and less than Vout / 2. The range RG2 is greater than Vout / 2 and less than Vout. The range RG3 is less than 0 and greater than -Vout / 2. The range RG4 is less than -Vout / 2 and greater than -Vout.

[0045] Figures 4A to 4D show an example of the switching operation of power conversion device 1, with Figure 4A showing the waveform when voltage Vin is within range RG1, Figure 4B showing the waveform when voltage Vin is within range RG2, Figure 4C showing the waveform when voltage Vin is within range RG3, and Figure 4D showing the waveform when voltage Vin is within range RG4. In each of Figures 4A to 4D, (A) shows the waveform of control signal G1, (B) shows the waveform of control signal G2, (C) shows the waveform of control signal G3, (D) shows the waveform of control signal G4, and (E) shows the waveform of current Iin. T is the switching period, which is the reciprocal of the switching frequency fsw.

[0046] (When voltage Vin is within range RG1) When the voltage Vin is within the range RG1, the control circuit 20 generates the control signals G1 to G4 as shown in FIG. 4A. Specifically, at timing t11, the control circuit 20 raises the control signal G1 and lowers the control signal G2. At timing t12, the control circuit 20 lowers the control signal G3 and raises the control signal G4. At timing t13, the control circuit 20 raises the control signal G3 and lowers the control signal G4. At timing t14, the control circuit 20 lowers the control signal G1 and raises the control signal G2. The time difference between timing t11 and timing t13 corresponds to half the switching period T, and the time difference between timing t13 and timing t15 corresponds to half the switching period T.

[0047] 5A to 5D show an example of the operating state of the power conversion device 1 when the voltage Vin is within the range RG1. For ease of explanation, the power conversion device 1 is depicted in a simplified manner in these FIGS. 5A to 5D. Specifically, for example, the voltage sensors 11 and 18, the current sensor 12, and the control circuit 20 are not shown. Furthermore, in FIGS. 5A to 5D, the transistors S1 to S4 are depicted as switches indicating their on / off states. When the voltage Vin is within the range RG1, the voltage Vin is a positive voltage, and the voltage at the input terminal T11 is higher than the voltage at the input terminal T12.

[0048] During the period from timing t11 to t12 (FIG. 4A), the control signals G1 and G3 are at a high level, and the control signals G2 and G4 are at a low level (FIGS. 4A(A) to 4A(D)). Therefore, as shown in FIG. 5A, the transistors S1 and S3 are in an on state, and the transistors S2 and S4 are in an off state. As a result, as shown in FIG. 5A, the current I flows through the input terminal T11, the reactor 13, the transistor S1, the transistor S3, the diode 16, and the input terminal T12 in this order. During this period, the current Iin increases, as shown in FIG. 4A(E). As a result, the reactor 13 is charged.

[0049] During the period from timing t12 to t13 (FIG. 4A), the control signals G1 and G4 are at a high level, and the control signals G2 and G3 are at a low level (FIGS. 4A(A) to 4A(D)). Therefore, as shown in FIG. 5B, the transistors S1 and S4 are in an on state, and the transistors S2 and S3 are in an off state. As a result, as shown in FIG. 5B, the current I flows through the input terminal T11, the reactor 13, the transistor S1, the capacitor 14, the transistor S4, the capacitor 17, the diode 16, and the input terminal T12 in this order. During this period, the current Iin decreases, as shown in FIG. 4A(E). As a result, the reactor 13 is discharged.

[0050] During the period from timing t13 to t14 (FIG. 4A), the control signals G1 and G3 are at a high level, and the control signals G2 and G4 are at a low level (FIGS. 4A(A) to 4A(D)). Therefore, as shown in FIG. 5C, the transistors S1 and S3 are in an on state, and the transistors S2 and S4 are in an off state. As a result, as shown in FIG. 5C, the current I flows through the input terminal T11, the reactor 13, the transistor S1, the transistor S3, the diode 16, and the input terminal T12 in this order. During this period, the current Iin increases, as shown in FIG. 4A(E). As a result, the reactor 13 is charged.

[0051] During the period from timing t14 to t15 (FIG. 4A), the control signals G2 and G3 are at a high level, and the control signals G1 and G4 are at a low level (FIGS. 4A(A) to 4A(D)). Therefore, as shown in FIG. 5D, the transistors S2 and S3 are in an on state, and the transistors S1 and S4 are in an off state. As a result, as shown in FIG. 5D, the current I flows through the input terminal T11, the reactor 13, the transistor S2, the capacitor 14, the transistor S3, the diode 16, and the input terminal T12 in this order. During this period, the current Iin decreases, as shown in FIG. 4A(E). As a result, the reactor 13 is discharged.

[0052] (When voltage Vin is within range RG2) When the voltage Vin is within the range RG2, the control circuit 20 generates the control signals G1 to G4 as shown in FIG. 4B. Specifically, at timing t21, the control circuit 20 raises the control signal G1 and lowers the control signal G2. At timing t22, the control circuit 20 lowers the control signal G1 and raises the control signal G2. At timing t23, the control circuit 20 raises the control signal G3 and lowers the control signal G4. At timing t24, the control circuit 20 lowers the control signal G3 and raises the control signal G4. The time difference between timing t21 and timing t23 corresponds to half the switching period T, and the time difference between timing t23 and timing t25 corresponds to half the switching period T.

[0053] 6A to 6D show an example of the operating state of the power conversion device 1 when the voltage Vin is within the range RG2.

[0054] During the period from timing t21 to t22 (FIG. 4B), the control signals G1 and G4 are at a high level, and the control signals G2 and G3 are at a low level (FIGS. 4B(A) to (D)). Therefore, as shown in FIG. 6A, the transistors S1 and S4 are in an on state, and the transistors S2 and S3 are in an off state. As a result, as shown in FIG. 6A, the current I flows through the input terminal T11, the reactor 13, the transistor S1, the capacitor 14, the transistor S4, the capacitor 17, the diode 16, and the input terminal T12 in this order. During this period, the current Iin increases, as shown in FIG. 4B(E). As a result, the reactor 13 is charged.

[0055] During the period from timing t22 to t23 (FIG. 4B), the control signals G2 and G4 are at a high level, and the control signals G1 and G3 are at a low level (FIGS. 4B(A) to (D)). Therefore, as shown in FIG. 6B, the transistors S2 and S4 are in an on state, and the transistors S1 and S3 are in an off state. As a result, as shown in FIG. 6B, the current I flows through the input terminal T11, the reactor 13, the transistor S2, the transistor S4, the capacitor 17, the diode 16, and the input terminal T12 in this order. During this period, the current Iin decreases, as shown in FIG. 4B(E). As a result, the reactor 13 is discharged.

[0056] During the period from timing t23 to t24 (FIG. 4B), the control signals G2 and G3 are at a high level, and the control signals G1 and G4 are at a low level (FIGS. 4B(A) to (D)). Therefore, as shown in FIG. 6C, the transistors S2 and S3 are in an on state, and the transistors S1 and S4 are in an off state. As a result, as shown in FIG. 6C, the current I flows through the input terminal T11, the reactor 13, the transistor S2, the capacitor 14, the transistor S3, the diode 16, and the input terminal T12 in this order. During this period, the current Iin increases, as shown in FIG. 4B(E). As a result, the reactor 13 is charged.

[0057] During the period from timing t24 to t25 (FIG. 4B), the control signals G2 and G4 are at a high level, and the control signals G1 and G3 are at a low level (FIGS. 4B(A) to (D)). Therefore, as shown in FIG. 6D, the transistors S2 and S4 are in an on state, and the transistors S1 and S3 are in an off state. As a result, as shown in FIG. 6D, the current I flows through the input terminal T11, the reactor 13, the transistor S2, the transistor S4, the capacitor 17, the diode 16, and the input terminal T12 in this order. During this period, the current Iin decreases, as shown in FIG. 4B(E). As a result, the reactor 13 is discharged.

[0058] (When voltage Vin is within range RG3) When the voltage Vin is within the range RG3, the control circuit 20 generates the control signals G1 to G4 as shown in FIG. 4C. Specifically, at timing t31, the control circuit 20 raises the control signal G1 and lowers the control signal G2. At timing t32, the control circuit 20 lowers the control signal G1 and raises the control signal G2. At timing t33, the control circuit 20 raises the control signal G3 and lowers the control signal G4. At timing t34, the control circuit 20 lowers the control signal G3 and raises the control signal G4. The time difference between timing t31 and timing t33 ​​corresponds to half the switching period T, and the time difference between timing t33 ​​and timing t35 corresponds to half the switching period T.

[0059] 7A to 7D show an example of the operating state of the power conversion device 1 when the voltage Vin is within the range RG3. When the voltage Vin is within the range RG3, the voltage Vin is a negative voltage, and the voltage at the input terminal T12 is higher than the voltage at the input terminal T11.

[0060] During the period from timing t31 to t32 (FIG. 4C), the control signals G1 and G4 are at a high level, and the control signals G2 and G3 are at a low level (FIGS. 4C(A) to (D)). Therefore, as shown in FIG. 7A, the transistors S1 and S4 are in an on state, and the transistors S2 and S3 are in an off state. As a result, as shown in FIG. 7A, the current I flows through the input terminal T12, the diode 15, the transistor S4, the capacitor 14, the transistor S1, the reactor 13, and the input terminal T11 in this order. During this period, the current Iin increases, as shown in FIG. 4C(E). As a result, the reactor 13 is charged.

[0061] During the period from timing t32 to t33 (FIG. 4C), the control signals G2 and G4 are at a high level, and the control signals G1 and G3 are at a low level (FIGS. 4C(A) to (D)). Therefore, as shown in FIG. 7B, the transistors S2 and S4 are in an on state, and the transistors S1 and S3 are in an off state. As a result, as shown in FIG. 7B, the current I flows through the input terminal T12, the diode 15, the transistor S4, the transistor S2, the reactor 13, and the input terminal T11 in this order. During this period, the current Iin decreases, as shown in FIG. 4C(E). As a result, the reactor 13 is discharged.

[0062] During the period from timing t33 ​​to t34 (FIG. 4C), the control signals G2 and G3 are at a high level, and the control signals G1 and G4 are at a low level (FIGS. 4C(A) to (D)). Therefore, as shown in FIG. 7C, the transistors S2 and S3 are on, and the transistors S1 and S4 are off. As a result, as shown in FIG. 7C, the current I flows through the input terminal T12, the diode 15, the capacitor 17, the transistor S3, the capacitor 14, the transistor S2, the reactor 13, and the input terminal T11 in this order. During this period, the current Iin increases, as shown in FIG. 4C(E). As a result, the reactor 13 is charged.

[0063] During the period from timing t34 to t35 (FIG. 4C), the control signals G2 and G4 are at a high level, and the control signals G1 and G3 are at a low level (FIGS. 4B(A) to (D)). Therefore, as shown in FIG. 7D, the transistors S2 and S4 are in an on state, and the transistors S1 and S3 are in an off state. As a result, as shown in FIG. 7D, the current I flows through the input terminal T12, the diode 15, the transistor S4, the transistor S2, the reactor 13, and the input terminal T11 in this order. During this period, the current Iin decreases, as shown in FIG. 4C(E). As a result, the reactor 13 is discharged.

[0064] (When voltage Vin is within range RG4) When the voltage Vin is within the range RG4, the control circuit 20 generates the control signals G1 to G4 as shown in FIG. 4D. Specifically, at timing t41, the control circuit 20 raises the control signal G1 and lowers the control signal G2. At timing t42, the control circuit 20 lowers the control signal G3 and raises the control signal G4. At timing t43, the control circuit 20 raises the control signal G3 and lowers the control signal G4. At timing t44, the control circuit 20 lowers the control signal G1 and raises the control signal G2. The time difference between timing t41 and t43 corresponds to half the switching period T, and the time difference between timing t43 and t45 corresponds to half the switching period T.

[0065] 8A to 8D show an example of the operating state of the power conversion device 1 when the voltage Vin is within the range RG4.

[0066] During the period from timing t41 to t42 (FIG. 4D), the control signals G1 and G3 are at a high level, and the control signals G2 and G4 are at a low level (FIGS. 4D(A) to (D)). Therefore, as shown in FIG. 8A, the transistors S1 and S3 are in an on state, and the transistors S2 and S4 are in an off state. As a result, as shown in FIG. 8A, the current I flows through the input terminal T12, the diode 15, the capacitor 17, the transistor S3, the transistor S1, the reactor 13, and the input terminal T11 in this order. During this period, the current Iin increases, as shown in FIG. 4D(E). As a result, the reactor 13 is charged.

[0067] During the period from timing t42 to t43 (FIG. 4D), the control signals G1 and G4 are at a high level, and the control signals G2 and G3 are at a low level (FIGS. 4D(A) to (D)). Therefore, as shown in FIG. 8B, the transistors S1 and S4 are in an on state, and the transistors S2 and S3 are in an off state. As a result, as shown in FIG. 8B, the current I flows through the input terminal T12, the diode 15, the transistor S4, the capacitor 14, the transistor S1, the reactor 13, and the input terminal T11 in this order. During this period, the current Iin decreases, as shown in FIG. 4D(E). As a result, the reactor 13 is discharged.

[0068] During the period from timing t43 to t44 (FIG. 4D), the control signals G1 and G3 are at a high level, and the control signals G2 and G4 are at a low level (FIGS. 4D(A) to (D)). Therefore, as shown in FIG. 8C, the transistors S1 and S3 are in an on state, and the transistors S2 and S4 are in an off state. As a result, as shown in FIG. 8C, the current I flows through the input terminal T12, the diode 15, the capacitor 17, the transistor S3, the transistor S1, the reactor 13, and the input terminal T11 in this order. During this period, the current Iin increases, as shown in FIG. 4D(E). As a result, the reactor 13 is charged.

[0069] During the period from timing t44 to t45 (FIG. 4D), the control signals G2 and G3 are at a high level, and the control signals G1 and G4 are at a low level (FIGS. 4D(A) to (D)). Therefore, as shown in FIG. 8D, the transistors S2 and S3 are on, and the transistors S1 and S4 are off. As a result, as shown in FIG. 8D, the current I flows through the input terminal T12, the diode 15, the capacitor 17, the transistor S3, the capacitor 14, the transistor S2, the reactor 13, and the input terminal T11 in this order. During this period, the current Iin decreases, as shown in FIG. 4D(E). As a result, the reactor 13 is discharged.

[0070] (Regarding switching frequency fsw) As shown in FIGS. 5A to 5D, 6A to 6D, 7A to 7D, and 8A to 8D, the current Iin has a ripple component. This ripple component changes depending on the voltage Vin, as shown in FIGS. 3B and 3C. That is, the ripple component is small when the voltage Vin is "0V," when the voltage Vin is "-Vout / 2," and when the voltage Vin is "Vout / 2." In this example, the ripple component is small at each of the times t1 to t7. The magnitude of the ripple component during the period from time t1 to time t4 is expressed, for example, using the following equation:

number

[0071] The magnitude of the ripple component needs to be such that it does not exceed the constraint imposed by the reactor 13. For example, in the power conversion device 1, the inductance value of the reactor 13 is designed based on the maximum value of the ripple component. For example, the ripple component is small near each of the timings t2, t3, t5, and t6, and therefore, from the viewpoint of the reactor 13, there is a margin for the ripple component.

[0072] In the example of Fig. 3, for convenience of explanation, the switching frequency fsw is kept constant. In reality, the power conversion device 1 reduces the switching frequency fsw around each of timings t2, t3, t5, and t6. Lowering the switching frequency fsw increases the ripple component, but since the ripple component is originally small around each of timings t2, t3, t5, and t6, the switching frequency fsw can be reduced. In the power conversion device 1, by reducing the switching frequency fsw in this way, it is possible to reduce switching losses.

[0073] Fig. 9 shows an example of the operation of the power conversion device 1 when the switching frequency fsw is changed, where (A) shows the waveform of the voltage Vin, (B) shows the switching frequency fsw, and (C) shows the waveform of the current Iin. Fig. 10 shows an example of a ripple component in the power conversion device 1, where (A) shows the waveform of the control signal G1, and (B) shows the waveform of the current Iin. Fig. 10(B) shows an enlarged view of a portion W2 in Fig. 9(C).

[0074] The switching frequency setting unit 33 of the control circuit 20 changes the switching frequency fsw of the transistors S1 to S4 based on the voltages Vin and Vout. Specifically, the switching frequency setting unit 33 sets a voltage range VR1 for the voltage Vin that includes "Vout / 2" and a voltage range VR2 for the voltage Vin that includes "-Vout / 2" based on the voltage Vout. Then, when the voltage Vin is within the voltage range VR1 and when the voltage Vin is within the voltage range VR2, the switching frequency setting unit 33 reduces the switching frequency fsw from a predetermined frequency fo.

[0075] In this example, the voltage Vin has an amplitude of 280 Vop (560 Vpp). The voltage Vout is 400 V in this example. The predetermined frequency fo is 50 kHz in this example. The voltage range VR1 is greater than 180 V and less than 220 V. The voltage range VR2 is less than -180 V and greater than -220 V.

[0076] 9(A) and 9(B), the switching frequency setting unit 33 reduces the switching frequency fsw from 50 kHz to 25 kHz during a period P1 when the voltage Vin first falls within the voltage range VR1. The switching frequency setting unit 33 reduces the switching frequency fsw from 50 kHz to 25 kHz during a period P2 when the voltage Vin next falls within the voltage range VR1. The switching frequency setting unit 33 reduces the switching frequency fsw from 50 kHz to 25 kHz during a period P3 when the voltage Vin falls within the voltage range VR2. The switching frequency setting unit 33 reduces the switching frequency fsw from 50 kHz to 25 kHz during a period P4 when the voltage Vin next falls within the voltage range VR2.

[0077] In each of periods P1 to P4, the switching frequency fsw is reduced, and as shown in FIG. 9C, the ripple component increases. As shown in FIG. 10, the magnitude of the ripple component when the switching frequency fsw is reduced to 25 kHz is 8.4 A, which is smaller than the maximum value of the ripple component, 9.8 A. As such, the magnitude of the ripple component when the switching frequency fsw is reduced does not exceed the maximum value of the ripple component when the switching frequency fsw is 50 kHz. Therefore, the magnitude of the ripple component when the switching frequency fsw is reduced to 25 kHz satisfies the constraint imposed by reactor 13.

[0078] As described above, the magnitude of the ripple component must not exceed the constraint imposed by the reactor 13. Furthermore, if the switching frequency fsw is reduced, the ripple component increases. Therefore, the settable switching frequency fsw has a lower limit (lower limit frequency flim), and the switching frequency fsw must be set to a frequency higher than this lower limit frequency flim.

[0079] FIG. 11 shows an example of setting the switching frequency fsw, where (A) shows the waveform of the voltage Vin, (B) shows the lower limit frequency flim of the switching frequency fsw, and (C) and (D) show examples of setting the switching frequency fsw.

[0080] 11(A), the switching frequency fsw can be lowered near each of timings t2, t3, t5, and t6. The lower limit frequency flim of this switching frequency fsw includes a curved portion W3, a curved portion W4, and a straight portion W5. The curved portion W3 can be expressed by the following equation EQ3, and the curved portion W4 can be expressed by the following equation EQ4.

number

[0081] The switching frequency fsw when reduced from the frequency fo must be set to a frequency higher than this lower limit frequency flim. The switching frequency fsw can be set, for example, as shown in Figures 11(C) and 11(D). In Figures 11(C) and 11(D), the range of the switching frequency fsw to be set is indicated by shading.

[0082] For example, in the example of FIG. 11(C), the switching frequency fsw is set to frequency f1 around each of timings t2, t3, t5, and t6. This example corresponds to the operation example shown in FIG. 9. That is, the switching frequency setting unit 33 of the control circuit 20 sets voltage ranges VR1 and VR2 based on the voltage Vout, and sets the switching frequency fsw to frequency f1 during periods P1 to P4 when the voltage Vin is within the voltage ranges VR1 and VR2. Note that in this example, the switching frequency fsw is changed from frequency fo to frequency f1 in one step, but this is not limiting and the switching frequency fsw may be changed from frequency fo to frequency f1 in multiple steps.

[0083] 11(D), the switching frequency fsw is set so as to continuously decrease from the frequency fo around each of the times t2, t3, t5, and t6. Specifically, the switching frequency setting unit 33 of the control circuit 20 sets the voltage ranges VR1 and VR2 based on the voltage Vout, and sets the switching frequency fsw so that the switching frequency fsw continuously decreases from the frequency fo during periods P1 to P4 when the voltage Vin is within the voltage ranges VR1 and VR2.

[0084] In this way, the power conversion device 1 reduces the switching frequency fsw from the frequency fo around each of the timings t2, t3, t5, and t6, thereby enabling the power conversion device 1 to reduce switching loss.

[0085] Here, the voltage ranges VR1 and VR2 correspond to a specific example of a "first voltage range" in an embodiment of the present disclosure. The voltage Vout corresponds to a specific example of an "output voltage" in an embodiment of the present disclosure. The frequency f1 corresponds to a specific example of a "second frequency" in an embodiment of the present disclosure.

[0086] In this way, the inverter circuit includes input terminals (input terminals T11, T12) to which an AC voltage can be input, reactor 13 provided in a path connecting the input terminals (input terminals T11, T12) and a first node (node ​​N1), a plurality of switching elements including a first switching element (transistor S1) and a second switching element (transistor S3) provided on either side of a first intermediate node in a first path connecting the first node and a second node (reference voltage line L2), and a first rectifying element (transistor S4) provided on either side of a second intermediate node in a second path connecting the first node (node ​​N1) and a third node (voltage line L1). The power supply includes a plurality of rectifying elements including a first rectifying element (transistor S2) and a second rectifying element (transistor S4); a first capacitor (capacitor 14) having one end connected to a first intermediate node and the other end connected to a second intermediate node; output terminals including a first output terminal (output terminal T21) connected to a third node (voltage line L1) and a second output terminal (output terminal T22) connected to a second node (reference voltage line L2); and a control circuit 20 capable of controlling the operation of the plurality of switching elements so that the waveform of an input current (current Iin) flowing through the input terminal is the same as the waveform of an input voltage (voltage Vin) at the input terminal. The control circuit 20 is capable of setting the switching frequency (switching frequency fsw) of the plurality of switching elements to a predetermined first frequency (frequency fo) and is capable of lowering the switching frequency below the first frequency (frequency fo) based on the input voltage (voltage Vin). As a result, for example, in the power conversion device 1, the switching frequency fsw can be made lower than the frequency fo during periods P1 to P5 when the voltage Vin is within the voltage ranges VR1 and VR2, as shown in Fig. 9. As a result, the power conversion device 1 can reduce switching loss.

[0087] [effect] As described above, this embodiment includes an input terminal capable of receiving an AC voltage, a reactor provided in a path connecting the input terminal and a first node, a plurality of switching elements including a first switching element and a second switching element provided on either side of a first intermediate node in a first path connecting the first node and a second node, a plurality of rectifying elements including a first rectifying element and a second rectifying element provided on either side of a second intermediate node in a second path connecting the first node and a third node, a first capacitor having one end connected to the first intermediate node and the other end connected to the second intermediate node, output terminals including a first output terminal connected to the third node and a second output terminal connected to the second node, and a control circuit capable of controlling the operation of the plurality of switching elements so that the waveform of an input current flowing through the input terminal is the same as the waveform of an input voltage at the input terminal. The control circuit is capable of setting the switching frequency of the plurality of switching elements to a predetermined first frequency and is capable of lowering the switching frequency below the first frequency based on the input voltage. This makes it possible to reduce switching losses.

[0088] [Variation 1] In the above embodiment, two transistors are provided in each of the path connecting the node N1 and the reference voltage line L2 and the path connecting the node N1 and the voltage line L1, but this is not limited to this. Alternatively, three or more transistors may be provided in each of these two paths. Below, an example in which three transistors are provided in each of these two paths will be described in detail.

[0089] 12 shows an example of the configuration of the power conversion device 2 according to this modification. The power conversion device 2 includes transistors S5 and S6, a capacitor 44, and a control circuit 50.

[0090] Transistors S5 and S6 are configured to perform switching operations similarly to transistors S1 to S4. Transistors S5 and S6 are configured using, for example, N-type field effect transistors. The drain of transistor S5 is connected to the source of transistor S3, the gate is supplied with control signal G5, and the source is connected to reference voltage line L2. The drain of transistor S6 is connected to voltage line L1, the gate is supplied with control signal G6, and the source is connected to the drain of transistor S4.

[0091] One end of the capacitor 44 is connected to the drain of the transistor S4 and the source of the transistor S6, and the other end is connected to the source of the transistor S3 and the drain of the transistor S5.

[0092] The control circuit 50 is configured to control the operation of the power conversion device 2 by generating control signals G1 to G6 based on the voltage Vin detected by the voltage sensor 11, the voltage Vout detected by the voltage sensor 18, and the current Iin detected by the current sensor 12.

[0093] Here, capacitor 44 corresponds to a specific example of a "second capacitor" in an embodiment of the present disclosure. Transistor S5 corresponds to a specific example of a "third switching element" in an embodiment of the present disclosure. Transistor S6 corresponds to a specific example of a "third rectifying element" in an embodiment of the present disclosure.

[0094] 13 shows an example of the operation of the power conversion device 2, where (A) shows the waveform of the voltage Vin and (B) shows the waveform of the current Iin. For ease of explanation, in this Fig. 13, the switching frequency fsw is fixed to the frequency fo.

[0095] As shown in Fig. 13(A), an AC voltage having a sine waveform is input to the power conversion device 2. Between timings t51 and t56, the voltage Vin is a positive voltage, and between timings t56 and t61, the voltage Vin is a negative voltage. In this example, the voltage Vin has an amplitude of 280 Vop (560 Vpp). In this example, the voltage Vout is 400 V.

[0096] The current Iin includes a ripple component. The magnitude of the ripple component changes depending on the voltage Vin, as shown in FIG. 13B. That is, the ripple component is small when the voltage Vin is "0 V," when the voltage Vin is "Vout / 3," when the voltage Vin is "2×Vout / 3," when the voltage Vin is "-Vout / 3," and when the voltage Vin is "-2×Vout / 3."

[0097] The magnitude of the ripple component in the period from timing t51 to t56 is expressed, for example, using the following equation.

number

[0098] The switching frequency setting unit 33 of the control circuit 50 sets, based on the voltage Vout, a voltage range of the voltage Vin that includes "2Vout / 3", a voltage range of the voltage Vin that includes "Vout / 3", a voltage range of the voltage Vin that includes "-Vout / 3", and a voltage range of the voltage Vin that includes "-2Vout / 3". When the voltage Vin is within these voltage ranges, the switching frequency setting unit 33 reduces the switching frequency fsw from a predetermined frequency fo.

[0099] In this way, in the power conversion device 2, similarly to the power conversion device 1 according to the above embodiment (FIGS. 3 and 11), for example, the switching frequency fsw is reduced from the frequency fo around each of the timings t52, t53, t54, t55, t57, t58, t59, and t60, thereby enabling the power conversion device 2 to reduce switching loss.

[0100] [Variation 2] In the above embodiment, the present technology is applied to the power conversion device 1 having the circuit configuration shown in Fig. 1, but the present technology is not limited to this. The present technology can be applied to power conversion devices having various circuit configurations. Some examples will be described below.

[0101] Fig. 14 shows an example of the configuration of a power conversion device 3 according to this modification. The power conversion device 3 is a multilevel boost PFC converter. The power conversion device 3 includes a rectifier circuit 61 and diodes D2 and D4. Note that Fig. 14 does not show a voltage sensor that detects voltage Vin, a current sensor that detects current Iin, a voltage sensor that detects voltage Vout, and a control circuit.

[0102] The rectifier circuit 61 is configured to rectify the AC voltage supplied from the AC power supply PAC. The rectifier circuit 61 has diodes D11 to D14. The anode of the diode D11 is connected to the cathode of the diode D12 and the input terminal T11, and the cathode is connected to one end of the reactor 13. The anode of the diode D12 is connected to the reference voltage line L2, and the cathode is connected to the anode of the diode D11 and the input terminal T11. The anode of the diode D13 is connected to the cathode of the diode D14 and the input terminal T12, and the cathode is connected to one end of the reactor 13. The anode of the diode D14 is connected to the reference voltage line L2, and the cathode is connected to the anode of the diode D13 and the input terminal T12.

[0103] Diodes D2 and D4 are provided in a path connecting node N1 and voltage line L1. The anode of diode D2 is connected to node N1, and the cathode is connected to the anode of diode D4 and one end of capacitor 14. The anode of diode D4 is connected to the cathode of diode D2 and one end of capacitor 14, and the cathode is connected to voltage line L1. Here, diode D2 corresponds to a specific example of a "first rectifying element" in an embodiment of the present disclosure. Diode D4 corresponds to a specific example of a "second rectifying element" in an embodiment of the present disclosure.

[0104] 15 shows an example of the configuration of another power conversion device 4 according to this modification. The power conversion device 4 is a multilevel semi-bridgeless PFC converter. The power conversion device 4 includes diodes D21A and D21B, reactors 13A and 13B, transistors S1A, S1B, S3A, and S3B, diodes D2A, D2B, D4A, and D4B, and capacitors 14A and 14B.

[0105] The anode of the diode D21A is connected to the reference voltage line L2, and the cathode is connected to the input terminal T11. The anode of the diode D21B is connected to the reference voltage line L2, and the cathode is connected to the input terminal T12.

[0106] One end of reactor 13A is connected to input terminal T11, and the other end is connected to node N1A. One end of reactor 13B is connected to input terminal T12, and the other end is connected to node N1B.

[0107] Transistors S1A and S3A are provided in a path connecting node N1A and reference voltage line L2. The drain of transistor S1A is connected to node N1A, its gate is supplied with control signal G1A, and its source is connected to the drain of transistor S3A. The drain of transistor S3A is connected to the source of transistor S1A, its gate is supplied with control signal G3A, and its source is connected to reference voltage line L2.

[0108] Transistors S1B and S3B are provided in a path connecting node N1B and reference voltage line L2. The drain of transistor S1B is connected to node N1B, its gate is supplied with control signal G1B, and its source is connected to the drain of transistor S3B. The drain of transistor S3B is connected to the source of transistor S1B, its gate is supplied with control signal G3B, and its source is connected to reference voltage line L2.

[0109] Diodes D2A and D4A are provided in a path connecting node N1A and voltage line L1. The anode of diode D2A is connected to node N1A, and the cathode is connected to the anode of diode D4A. The anode of diode D4A is connected to the cathode of diode D2A, and the cathode is connected to voltage line L1.

[0110] Diodes D2B and D4B are provided in a path connecting node N1B and voltage line L1. The anode of diode D2B is connected to node N1B, and the cathode is connected to the anode of diode D4B. The anode of diode D4B is connected to the cathode of diode D2B, and the cathode is connected to voltage line L1.

[0111] One end of the capacitor 14A is connected to the cathode of the diode D2A and the anode of the diode D4A, and the other end is connected to the source of the transistor S1A and the drain of the transistor S3A.

[0112] One end of the capacitor 14B is connected to the cathode of the diode D2B and the anode of the diode D4B, and the other end is connected to the source of the transistor S1B and the drain of the transistor S3B.

[0113] [Variation 3] In the above embodiment, the switching frequency setting unit 33 sets the voltage range VR1 of the voltage Vin including "Vout / 2" and the voltage range VR2 of the voltage Vin including "-Vout / 2" based on the voltage Vout, but this is not limited to this. Instead, the switching frequency setting unit 33 may set the voltage ranges VR1 and VR2 based on, for example, the target voltage Vref. That is, in the power conversion device 1, the voltage Vout is controlled by negative feedback control so that it becomes a voltage close to the target voltage Vref. Therefore, the switching frequency setting unit 33 can set the voltage ranges VR1 and VR2 based on, for example, the target voltage Vref.

[0114] [Other variations] Two or more of these variations may also be combined.

[0115] Although the present invention has been described above by way of embodiments and modifications, the present invention is not limited to these embodiments and can be modified in various ways.

[0116] For example, in the above embodiment, the present technology is applied to the circuit shown in FIG. 1, but the present technology is not limited to this, and instead, the present technology may be applied to other circuits.

[0117] The effects described in this specification are merely examples, and the effects of the present disclosure are not limited to the effects described in this specification. Therefore, other effects may be obtained with respect to the present disclosure.

[0118] Furthermore, the present disclosure may take the following aspects.

[0119] (1) an input terminal capable of inputting AC voltage; a reactor provided in a path connecting the input terminal and a first node; a plurality of switching elements including a first switching element and a second switching element provided on either side of a first intermediate node in a first path connecting the first node and a second node; a second path connecting the first node and a third node, the second path including a first rectifying element and a second rectifying element disposed on either side of a second intermediate node; a first capacitor having one end connected to the first intermediate node and the other end connected to the second intermediate node; output terminals including a first output terminal connected to the third node and a second output terminal connected to the second node; a control circuit capable of controlling the operation of the plurality of switching elements so that a waveform of an input current flowing through the input terminal becomes the same as a waveform of an input voltage at the input terminal; Equipped with The control circuit is capable of setting a switching frequency of the plurality of switching elements to a predetermined first frequency, and is capable of reducing the switching frequency below the first frequency based on the input voltage. Power conversion device. (2) The control circuit is capable of reducing the switching frequency below the first frequency when the input voltage is within a first voltage range. The power conversion device according to (1) above. (3) The control circuit is capable of setting the first voltage range based on an output voltage at the output terminal. The power conversion device according to (2) above. (4) The control circuit is capable of switching the switching frequency to a second frequency lower than the predetermined frequency when the input voltage is within the first voltage range. The power conversion device according to (2) or (3) above. (5) The control circuit is capable of continuously changing the switching frequency to a frequency lower than the predetermined frequency when the input voltage is within the first voltage range. The power conversion device according to (2) or (3) above. (6) further comprising a second capacitor; the plurality of switching elements further includes a third switching element; the first path includes the first switching element, the second switching element, and the third switching element provided in this order from the first node to the second node; the second switching element and the third switching element are provided across a third intermediate node, the plurality of rectifying elements further includes a third rectifying element; the first rectifying element, the second rectifying element, and the third rectifying element are provided in this order in the second path from the first node to the third node; the second rectifying element and the third rectifying element are provided across a fourth intermediate node, The second capacitor has one end connected to the third intermediate node and the other end connected to the fourth intermediate node. The power conversion device according to (1) above. (7) The control circuit is capable of reducing the switching frequency below the first frequency when the input voltage is within a first voltage range and when the input voltage is within a second voltage range. The power conversion device according to (6) above. (8) a first diode; The second diode and Furthermore, the input terminals include a first input terminal and a second input terminal; the first diode has an anode connected to the second node and a cathode connected to the second input terminal; the second diode has an anode connected to the second input terminal and a cathode connected to the third node; The reactor is provided in a path connecting the first input terminal and the first node. The power conversion device according to any one of (1) to (7) above. (9) Each of the plurality of rectifying elements is a diode. The power conversion device according to any one of (1) to (8) above. (10) each of the plurality of rectifying elements is a switching element; The control circuit is further capable of controlling the operation of the plurality of rectifying elements. The power conversion device according to any one of (1) to (8) above. [Explanation of symbols]

[0120] 1 to 4... power conversion device, 11... voltage sensor, 12... current sensor, 13, 13A, 13B... reactor, 14, 14A, 14B, 44... capacitor, 15, 16... diode, 17... capacitor, 18... voltage sensor, 20, 50... control circuit, 21... duty ratio calculation unit, 22... target voltage setting unit, 23... subtraction unit, 24... PI processing unit, 25... absolute value calculation unit, 26... multiplication unit, 27... filter processing unit, 28... absolute value calculation unit, 29... subtraction unit, 31... PI processing unit, 32... addition unit, 33... switching frequency setting unit, 34... control signal generation unit, 61... rectification circuit, D11 to D14... diodes, D2, D2A, D2B, D4, D4A, D4B... diodes Diode, D21A, D21B...diode, DT, DT0, DT1...switching duty ratio, G1, G1A, G1B, G2, G3, G3A, G3B, G4, G5, G6...control signal, Iin...current, Iout...voltage, L1...voltage line, L2...reference voltage line, N1, N1A, N1B...node, P1~P4...period, RG1~RG4...range, S1, S1A, S1B, S2, S3, S3A, S3B, S4, S5, S6...transistor, T...switching period, T11, T12...input terminal, T21, T22...output terminal, VR1, VR2...voltage range, Vin...voltage, Vout...voltage, Vref...target voltage, fsw...switching frequency.

Claims

1. an input terminal capable of inputting AC voltage; a reactor provided in a path connecting the input terminal and a first node; a plurality of switching elements including a first switching element and a second switching element provided on either side of a first intermediate node in a first path connecting the first node and a second node; a plurality of rectifying elements including a first rectifying element and a second rectifying element provided on either side of a second intermediate node in a second path connecting the first node and a third node; a first capacitor having one end connected to the first intermediate node and the other end connected to the second intermediate node; output terminals including a first output terminal connected to the third node and a second output terminal connected to the second node; a control circuit capable of controlling the operation of the plurality of switching elements so that a waveform of an input current flowing through the input terminal becomes the same as a waveform of an input voltage at the input terminal; Equipped with The control circuit is capable of setting a switching frequency of the plurality of switching elements to a predetermined first frequency, and is capable of reducing the switching frequency below the first frequency based on the input voltage. Power conversion device.

2. The control circuit is capable of reducing the switching frequency below the first frequency when the input voltage is within a first voltage range. The power conversion device according to claim 1 .

3. The control circuit is capable of setting the first voltage range based on an output voltage at the output terminal. The power conversion device according to claim 2 .

4. The control circuit is capable of switching the switching frequency to a second frequency lower than the predetermined frequency when the input voltage is within the first voltage range. The power conversion device according to claim 2 .

5. The control circuit is capable of continuously changing the switching frequency to a frequency lower than the predetermined frequency when the input voltage is within the first voltage range. The power conversion device according to claim 2 .

6. further comprising a second capacitor; the plurality of switching elements further includes a third switching element; the first path includes the first switching element, the second switching element, and the third switching element provided in this order from the first node to the second node; the second switching element and the third switching element are provided across a third intermediate node, the plurality of rectifying elements further includes a third rectifying element; the first rectifying element, the second rectifying element, and the third rectifying element are provided in this order in the second path from the first node to the third node; the second rectifying element and the third rectifying element are provided across a fourth intermediate node, The second capacitor has one end connected to the third intermediate node and the other end connected to the fourth intermediate node. The power conversion device according to claim 1 .

7. The control circuit is capable of reducing the switching frequency below the first frequency when the input voltage is within a first voltage range and when the input voltage is within a second voltage range. The power conversion device according to claim 6.

8. a first diode; a second diode; Furthermore, the input terminals include a first input terminal and a second input terminal; the first diode has an anode connected to the second node and a cathode connected to the second input terminal; the second diode has an anode connected to the second input terminal and a cathode connected to the third node; The reactor is provided in a path connecting the first input terminal and the first node. The power conversion device according to claim 1 .

9. Each of the plurality of rectifying elements is a diode. The power conversion device according to claim 1 .

10. each of the plurality of rectifying elements is a switching element; The control circuit is further capable of controlling the operation of the plurality of rectifying elements. The power conversion device according to claim 1 .

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