Semiconductor device and data driver

Abstract

To provide a semiconductor device capable of suppressing the number of components in a high-withstanding voltage element in a logic level shifter circuit.SOLUTION: A logic level shifter circuit includes: a first transistor and a second transistor of a first conductivity type, in each of which a first end is connected to a power source voltage supply line that supplies a second voltage, while a second end of one transistor is connected to a control end of the other, and a control end of one transistor is connected to a second end of the other; a third transistor and a fourth transistor of a second conductivity type that are connected in series between the reference voltage supply line and a first node connecting the second end of the first transistor and the control end of the second transistor, in which the third transistor receives a first input signal at the control end and the fourth transistor receives a second input signal at the control end; and a fifth transistor and a sixth transistor of the second conductivity type that are connected in parallel between the reference voltage supply line and a second node connecting the second end of the second transistor and the control end of the first transistor, in which the fifth transistor receives an inverted first input signal at the control end and the sixth transistor receives an inverted second input signal at the control end. The second node outputs an output signal.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a data driver. [Background technology]

[0002] A display device such as a liquid crystal display or organic electroluminescence (EL) display generally includes a display panel in which display cells are formed at the intersections of a plurality of gate lines and a plurality of data lines, and a data driver for driving the plurality of data lines. The data driver includes a data latch unit that sequentially captures a plurality of pixel data pieces included in a video signal, a level shifter that changes the voltage levels of the pixel data pieces captured by the data latch unit, a DA conversion unit that converts the pixel data pieces whose voltage levels have been changed by the level shifter into analog grayscale voltages, and an output amplifier unit that amplifies the grayscale voltages and outputs them to the data lines.

[0003] As a level shifter that changes the voltage level of an input signal, a configuration of a logic level shifter made up of four N-channel transistors and twelve P-channel transistors has been proposed (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-40752 Summary of the Invention [Problem to be solved by the invention]

[0005] In a logic level shifter configured as in the above-described conventional technology, the N-channel transistors can be configured with low-voltage elements, while the P-channel transistors must be configured with high-voltage elements. For this reason, when level-shifting a 4-bit input signal, for example, the configuration in Patent Document 1 requires 12 transistors made of high-voltage elements, which poses a problem of increasing the chip size.

[0006] The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device that can reduce the number of high-voltage elements in a logic level shifter circuit. [Means for solving the problem]

[0007] A semiconductor device according to the present invention includes a logic level shifter circuit that receives a first input signal and a second input signal, each of whose signal levels changes between a voltage level of a first voltage representing a first logic level and a reference voltage representing a second logic level, and generates an output signal whose signal level changes to a logic level according to a combination of the logic levels of the first input signal and the second input signal, and whose voltage level representing the first logic level is a voltage level of a second voltage different from the first voltage and whose voltage difference from the reference voltage is larger than the voltage difference between the first voltage and the reference voltage, wherein the logic level shifter circuit has a first terminal connected to a power supply voltage supply line that supplies the second voltage, and includes a first transistor and a second transistor of a first conductivity type, one of whose second terminals is connected to a control terminal on the other side, and one of whose control terminals is connected to a second terminal on the other side, and a third transistor of a second conductivity type receiving the first input signal at its control terminal and a fourth transistor of a second conductivity type receiving the second input signal at its control terminal, which are connected in series between a first node which is a node connecting the second terminal of the first transistor and the control terminal of the second transistor and a reference voltage supply line which supplies the reference voltage; a fifth transistor of a second conductivity type receiving an inverted first input signal obtained by inverting a logic level of the first input signal at its control terminal and a sixth transistor of a second conductivity type receiving an inverted second input signal obtained by inverting a logic level of the second input signal at its control terminal, which are connected in parallel between a second node which is a node connecting the second terminal of the second transistor and the control terminal of the first transistor and the reference voltage supply line, and

[0008] Further, a data driver according to the present invention is a data driver having a plurality of output channels connected to a display panel having a plurality of data lines and a plurality of gate lines, and a plurality of pixel units arranged in a matrix at each intersection of the plurality of data lines and the plurality of gate lines, and outputting a drive signal to the plurality of data lines based on a video data signal consisting of a series of pixel data pieces, the data driver including: a data latch that takes in and sequentially outputs the series of pixel data pieces; a level shifter that performs level shifting to change the signal level of the pixel data pieces output from the data latch; and an output unit that outputs the drive signal based on the pixel data pieces level-shifted by the level shifter, wherein the pixel data pieces output from the data latch are composed of a first input signal and a second input signal, each of whose signal level changes between a voltage level of a first voltage representing a first logic level and a reference voltage representing a second logic level, and the level shifter receives the first input signal and the second input signal, and shifts the signal level to a logic level corresponding to a combination of the logic levels of the first input signal and the second input signal. a logic level shifter circuit for generating an output signal whose voltage level changes in accordance with the first logic level and whose voltage level represents a first logic level is a voltage level of a second voltage which is different from the first voltage and whose voltage difference from the reference voltage is greater than the voltage difference between the first voltage and the reference voltage, the logic level shifter circuit comprising: a first transistor and a second transistor of a first conductivity type, each of whose first terminal is connected to a power supply voltage supply line which supplies the second voltage, and whose second terminal and the control terminal of one side are connected to each other, and a second terminal and a control terminal of the other side are connected to each other; a third transistor of a second conductivity type connected in series between a first node, which is a node connecting the second terminal of the second transistor and the control terminal of the first transistor, and a reference voltage supply line that supplies the reference voltage, and receiving the first input signal at its control terminal; and a fourth transistor of a second conductivity type connected in parallel between a second node, which is a node connecting the second terminal of the second transistor and the control terminal of the first transistor, and the reference voltage supply line, and receiving an inverted first input signal, which is an inverted logic level of the first input signal, at its control terminal;and a sixth transistor of a second conductivity type that receives at its control end an inverted second input signal obtained by inverting the logic level of the second input signal, and outputs the output signal from the second node. [Effects of the Invention]

[0009] According to the semiconductor device of the present invention, it is possible to reduce the number of high-voltage elements in the logic level shifter circuit. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a configuration of a display device according to an embodiment of the present invention; [Figure 2] 1 is a block diagram showing a configuration of a data driver according to an embodiment of the present invention; [Figure 3] FIG. 2 is a diagram illustrating an example of a minimum configuration of a logic level shifter circuit according to the first embodiment. [Figure 4] 4 is a diagram showing signal levels of input and output signals of the logic level shifter circuit of FIG. 3. [Figure 5] 4 is an input / output table showing combinations of signal levels of input / output signals in FIG. 3; [Figure 6] FIG. 1 is a diagram illustrating a configuration example of a practical logic level shifter circuit. [Figure 7] 4 is a diagram showing an example of the configuration of a four-output logic level shifter circuit that is a combination of the logic level shifter circuits of FIG. 3; FIG. [Figure 8] 8 is a table showing an input / output table of the logic level shifter circuit of FIG. 7; [Figure 9] FIG. 10 is a diagram illustrating a modified example of the configuration of the logic level shifter circuit according to the first embodiment. [Figure 10] 10 is a table showing an input / output table of the logic level shifter circuit of FIG. 9; [Figure 11] FIG. 10 is a diagram illustrating a configuration example of a logic level shifter circuit according to a second embodiment. [Figure 12] FIG. 10 is a diagram illustrating signal levels of input and output signals of the logic level shifter circuit of the second embodiment. [Figure 13]12 is a table showing an input / output table of the logic level shifter circuit of FIG. 11. DETAILED DESCRIPTION OF THE INVENTION

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail. In the following description of each embodiment and in the accompanying drawings, the same reference numerals are used to designate substantially the same or equivalent parts. [Example]

[0012] 1 is a block diagram showing the configuration of a display device 100 according to a first embodiment of the present invention. The display device 100 is an active matrix liquid crystal display device. The display device 100 includes a display panel 11, a display controller 12, a gate driver 13, and a data driver 14.

[0013] The display panel 11 is composed of a semiconductor substrate on which a plurality of pixel units P11 to Pnm and pixel switches M11 to Mnm (n is an integer of 2 or greater, and m is an integer of 2 or greater and a multiple of 3) are arranged in a matrix of n rows and m columns. The display panel 11 has n gate lines GL1 to GLn which are horizontal scanning lines, and m data lines DL1 to DLm which are arranged orthogonally to intersect the gate lines GL1 to GLn. The pixel units P11 to Pnm and pixel switches M11 to Mnm are provided at the intersections of the gate lines GL1 to GLn and the data lines DL1 to DLm, and are arranged in a matrix.

[0014] The pixel switches M11 to Mnm are controlled to be on or off in response to gate signals Vg1 to Vgn supplied from the gate driver 13. The pixel units P11 to Pnm are supplied with pixel drive voltage signals G1 to Gm corresponding to video data from the data driver 14. When the pixel switches M11 to Mnm are respectively on, the pixel drive voltage signals G1 to Gm are applied to the pixel electrodes of the pixel units P11 to Pnm, and each pixel electrode is charged. The brightness of the pixel units P11 to Pnm is controlled in response to the pixel drive voltage signals G1 to Gm at the pixel electrodes of the pixel units P11 to Pnm, and display is performed.

[0015] The display controller 12 receives the video data and generates a video data signal VDS including a series of pixel data fragments PD that represent the brightness level of each pixel in, for example, 256 8-bit brightness gradations. The video data signal VDS is configured as a video data signal serialized according to the number of transmission paths for each predetermined number of source lines.

[0016] In this embodiment, one frame of video data signal VDS is formed by serially connecting n pixel data fragment groups, each consisting of m pixel data fragments PD. Each of the n pixel data fragment groups is a pixel data fragment group consisting of pixel data fragments corresponding to the gradation voltages to be supplied to pixels on one horizontal scanning line (i.e., each of gate lines GL1 to GLn). The operation of the data driver 14 generates a video data signal VDS for n×m pixel sections (i.e., pixel section P) based on the m×n pixel data fragments PD. 11 ~P nm ) are generated, and pixel drive voltage signals G1 to Gm corresponding to these voltages are applied via data lines DL1 to DLm.

[0017] Furthermore, the display controller 12 supplies the gate driver 13 with a gate timing signal that indicates the timing at which the gate lines GL1 to GLn are selected in order.

[0018] The gate driver 13 receives a gate timing signal from the display controller 12, and sequentially supplies gate signals Vg1 to Vgn to the gate lines GL1 to GLn based on the clock timing included in the gate timing signal.

[0019] The data driver 14 converts each of the multiple pixel data fragments PD included in the video data signal VDS supplied from the display controller 12 into an analog voltage having a magnitude corresponding to the brightness level indicated by that pixel data fragment PD. The data driver 14 outputs the voltages obtained by converting each of the multiple pixel data fragments into analog voltages as pixel drive voltage signals G1 to Gm and supplies them to the data lines DL1 to DLm of the display panel 11. Note that "m" corresponds to the number of channels of the output of the data driver 14; for example, if the output of the data driver 14 is 960 channels, then m=960.

[0020] 2 is a block diagram showing the configuration of the data driver 14. In this embodiment, the data driver 14 is formed on a single semiconductor IC (Integrated Circuit) chip.

[0021] The data driver 14 includes an interface (I / F) 21, a reference voltage generating circuit 22, a logic circuit 23, a shift register 24, a data latch 25, a level shifter 26, a DA (digital-to-analog) conversion circuit 27, and an output amplifier circuit .

[0022] The interface 21 is an interface circuit unit that receives the video data signal VDS supplied from the display controller 12. The interface 21 extracts a reference timing signal included in the video data signal VDS and supplies it to a logic circuit 23. The interface 21 also extracts a horizontal synchronization signal from the video data signal VDS, generates a start pulse signal synchronized with this horizontal synchronization signal, and supplies it to a shift register 24. The interface 21 also extracts a series of pixel data pieces included in the video data signal VDS and supplies it to a data latch 25.

[0023] The reference voltage generating circuit 22 receives a voltage supply from the display controller 12, and based on this, generates reference voltages indicating different voltage values ​​that represent the range of brightness levels that can be expressed by the video signal in multiple stages (e.g., 1024), and supplies these to the DA conversion circuit 27.

[0024] The logic circuit 23 generates a reference clock signal CLK based on the reference timing signal supplied from the interface 21 and supplies it to a shift register 24 .

[0025] The shift register 24 generates latch timing signals t1 to tm having different timings by shifting the start pulse signal supplied from the interface 21 based on the reference clock signal CLK. The shift register 24 supplies the latch timing signals t1 to tm to the data latch 25.

[0026] The data latch 25 includes a plurality of latch circuits, receives a sequence of pixel data fragments included in the video data signal VDS, and captures each pixel data fragment at the timing of latch timing signals t1 to tm. The data latch 25 sequentially outputs the captured pixel data fragments as pixel data P1 to Pm.

[0027] The level shifter 26 performs level shift processing on the pixel data P1 to Pm output from the data latch 25 to increase the voltage level (i.e., the amplitude of the signal), and supplies the pixel data signals D1 to Dm to the DA conversion circuit 27. The level shifter 26 is made up of a plurality of logical level shifter circuits.

[0028] Based on the reference voltage supplied from the reference voltage generating circuit 22, the DA conversion circuit 27 converts the pixel data signals D1 to Dm into analog pixel drive voltages A1 to Am corresponding to the luminance levels thereof and supplies them to the output amplifier circuit .

[0029] The output amplifier circuit 28 amplifies the pixel drive voltages A1 to Am and outputs them to the data lines DL1 to DLm as pixel drive voltage signals G1 to Gm.

[0030] 3 is a diagram showing the minimum configuration of a logical level shifter circuit 30 provided in the level shifter 26. Here, pixel data P1 to Pm are signals corresponding to input signals in1 and Iin2, and pixel data signals D1 to Dm are signals corresponding to output signal out.

[0031] The logic level shifter circuit 30 is composed of a first circuit block 31 consisting of cross-connected P-channel transistors, a second circuit block 32 consisting of series-connected N-channel transistors, and a third circuit block 33 consisting of parallel-connected N-channel transistors.

[0032] The first circuit block 31 is composed of a transistor PM1 and a transistor PM2. The transistors PM1 and PM2 are each composed of a P-channel MOSFET of a first conductivity type, and each of the sources is connected to a voltage supply line L1 of the high power supply voltage Vdd.

[0033] The drain of the transistor PM1 is connected to the node n1. The gate of the transistor PM1 is connected to the node n2. The node n2 is an output node that outputs the output signal out of the logic level shifter circuit 30. The drain of the transistor PM2 is connected to the node n2. The gate of the transistor PM2 is connected to the node n1.

[0034] The transistors PM1 and PM2 are arranged in a state where one gate is connected to the other drain, and one drain is connected to the other gate, that is, in a so-called cross-connected state.

[0035] The second circuit block 32 is composed of a transistor NM1 and a transistor NM2. The transistors NM1 and NM2 are each composed of an N-channel MOSFET, which is a second conductivity type opposite to the first conductivity type.

[0036] The drain of transistor NM1 is connected to node n1. The source of transistor NM2 is connected to voltage supply line L2 of ground potential VSS, which is the reference potential. By connecting the source of transistor NM1 and the drain of transistor NM2, transistors NM1 and NM2 are connected in series between node n1 and voltage supply line L2 of ground potential VSS.

[0037] An input signal in1 is supplied to the gate of the transistor NM1, and an input signal in2 is supplied to the gate of the transistor NM2.

[0038] The third circuit block 33 is composed of a transistor NM3 and a transistor NM4. The transistors NM3 and NM4 are each composed of an N-channel MOSFET.

[0039] The drains of the transistors NM3 and NM4 are connected to each other and to the node n2. The sources of the transistors NM3 and NM4 are connected to each other and to the voltage supply line L2 of the ground potential VSS. The drains of the transistors NM3 and NM4 are connected to each other and the sources of the transistors NM3 and NM4 are connected to each other, so that the transistors NM3 and NM4 are connected in parallel between the node n2 and the voltage supply line L2 of the ground potential VSS.

[0040] An inverted input signal xin1, which is the inverted signal level of the input signal in1, is supplied to the gate of the transistor NM3. An inverted input signal xin2, which is the inverted signal level of the input signal in2, is supplied to the gate of the transistor NM4.

[0041] 4 is a diagram showing the signal levels of the input signals in1 and in2, the inverted input signals xin1 and xin2, and the output signal out. Note that the low power supply voltage vcc and the high power supply voltage vdd are both positive power supply voltages, and the high power supply voltage vdd has a larger voltage difference from the ground potential vss than the low power supply voltage vcc.

[0042] The input signals in1, in2 and the inverted input signals xin1, xin2 are all signals whose signal levels change between logic level 1 (H level) and logic level 0 (L level), with logic level 1 representing the low power supply voltage vcc and logic level 0 representing the ground potential vss.

[0043] The signal level of the output signal out changes between logic level 1 and logic level 0, with logic level 1 corresponding to the high power supply voltage vdd and logic level 0 corresponding to the ground potential vss.

[0044] FIG. 5 is an input / output table showing the signal levels of the output signal out according to combinations of the signal levels of the input signals in1 and in2.

[0045] When the input signals in1 and in2 are both at the signal level of the ground potential vss (L level), the output signal out also has the signal level of the ground potential vss (L level).

[0046] When the input signal in1 is at the ground potential vss (L level) and the input signal in2 is at the low power supply voltage vcc (H level), the output signal out has the signal level of the ground potential vss (L level).

[0047] When the input signal in1 is at the low power supply voltage vcc (H level) and the input signal in2 is at the ground potential vss (L level), the output signal out has the signal level of the ground potential vss (L level).

[0048] When the input signals in1 and in2 are both at the signal level of the low power supply voltage vcc (H level), the output signal out becomes the signal level of the high power supply voltage vdd (H level).

[0049] In this way, in the logic level shifter circuit 30 of this embodiment, when the signal levels of the input signals in1 and in2 are a specific combination, the signal level of the output signal out becomes the vdd level.

[0050] According to this configuration, it is possible to perform a level shift from the voltage level of the low power supply voltage vcc to the voltage level of the high power supply voltage Vdd while reducing the number of P-channel MOS transistors that need to be configured using high-voltage elements.

[0051] Furthermore, since the number of transistors connected in series is two, the transition of the input signal is faster than in a logic level shifter circuit configured with three or more stages of transistors connected in series. Therefore, the configuration of the logic level shifter circuit 30 of this embodiment makes it possible to quickly perform level shifting of the signal.

[0052] Here, we have explained an example in which the signal level of the output signal out becomes the vdd level when the input signals in1 and in2 are both at the signal level of the low power supply voltage vcc. However, by switching the input signals supplied to the gates of each transistor, it is possible to configure the output signal out to become the vdd level when the signal levels of the input signals in1 and in2 are other specific combinations.

[0053] FIG. 6 is a diagram showing an example of the configuration of a practical logic level shifter circuit 40 in which a pair of voltage clamping transistors is provided in the logic level shifter circuit 30 of FIG.

[0054] The logic level shifter circuit 40 has a voltage clamping transistor pair 41. The voltage clamping transistor pair 41 is made up of a transistor NM5 and a transistor NM6. The transistors NM5 and NM6 are each made up of an N-channel MOSFET.

[0055] The transistor NM5 is inserted between the drain of the transistor PM1 and the drain of the transistor NM1, that is, the drain of the transistor NM5 is connected to the node n1, and the source is connected to the drain of the transistor NM1.

[0056] The transistor NM6 is inserted between the drain of the transistor PM2 and the drain of the transistor NM3. That is, the drain of the transistor NM6 is connected to the node n2, and the source of the transistor NM6 is connected to the drains of the transistors NM3 and NM4. The gates of the transistors NM5 and NM6 are connected to each other and receive the bias voltage vbias.

[0057] With this configuration, the drain-source voltage Vds of the transistors NM1, NM2, NM3, and NM4 is equal to or less than the bias voltage vbias. Therefore, by making vbias≈vcc, the N-channel MOS transistors NM1 to NM6 can be configured with low-breakdown-voltage elements.

[0058] FIG. 7 is a circuit diagram showing the configuration of a four-output logic level shifter circuit 50 configured by providing a plurality of components similar to the logic level shifter circuit of the minimum configuration shown in FIG.

[0059] The logic level shifter circuit 50 is made up of a first circuit section 51, a second circuit section 52, a third circuit section 53, and a fourth circuit section 54, each of which has the same configuration as the logic level shifter circuit 30 of FIG.

[0060] The first circuit section 51 includes transistors PM11 and PM12 which are cross-connected P-channel MOS transistors, transistors NM11 and NM12 which are series-connected N-channel MOS transistors, and transistors NM13 and NM14 which are parallel-connected N-channel MOS transistors.

[0061] The gate of transistor NM11 is supplied with an inverted input signal xin1, the gate of transistor NM12 is supplied with an inverted input signal xin2, the gate of transistor NM13 is supplied with an input signal in1, and the gate of transistor NM14 is supplied with an input signal in2.

[0062] An output signal out0 is output from a node n12, which is a node connecting the gate of the transistor PM11, the drain of the transistor PM12, and the drains of the transistors NM13 and NM14.

[0063] The second circuit section 52 includes transistors PM21 and PM22 which are cross-connected P-channel MOS transistors, transistors NM21 and NM22 which are series-connected N-channel MOS transistors, and transistors NM23 and NM24 which are parallel-connected N-channel MOS transistors.

[0064] The gate of transistor NM21 is supplied with an inverted input signal xin1, the gate of transistor NM22 is supplied with an input signal in2, the gate of transistor NM23 is supplied with the input signal in1, and the gate of transistor NM24 is supplied with an inverted input signal xin2.

[0065] An output signal out1 is output from a node n22 that is a node connecting the gate of the transistor PM21, the drain of the transistor PM22, and the drains of the transistors NM23 and NM24.

[0066] The third circuit section 53 includes transistors PM31 and PM32 which are cross-connected P-channel MOS transistors, transistors NM31 and NM32 which are series-connected N-channel MOS transistors, and transistors NM33 and NM34 which are parallel-connected N-channel MOS transistors.

[0067] The gate of transistor NM31 is supplied with input signal in1, the gate of transistor NM32 is supplied with inverted input signal xin2, the gate of transistor NM33 is supplied with inverted input signal xin1, and the gate of transistor NM34 is supplied with input signal in2.

[0068] An output signal out2 is output from a node n32, which is a node connecting the gate of the transistor PM31, the drain of the transistor PM32, and the drains of the transistors NM33 and NM34.

[0069] The fourth circuit section 54 includes transistors PM41 and PM42 which are cross-connected P-channel MOS transistors, transistors NM41 and NM42 which are series-connected N-channel MOS transistors, and transistors NM43 and NM44 which are parallel-connected N-channel MOS transistors.

[0070] The gate of transistor NM41 is supplied with an input signal in1, the gate of transistor NM42 is supplied with an input signal in2, the gate of transistor NM43 is supplied with an inverted input signal xin1, and the gate of transistor NM44 is supplied with an inverted input signal xin2.

[0071] An output signal out3 is output from a node n42, which is a node connecting the gate of the transistor PM41, the drain of the transistor PM42, and the drains of the transistors NM43 and NM44.

[0072] FIG. 8 is an input / output table showing the signal levels of the output signals out0, out1, out2, and out3 according to combinations of the signal levels of the input signals in1 and in2.

[0073] When the input signals in1 and in2 are both at the signal level of the ground potential vss (L level), the output signal out0 is at the high power supply voltage vdd (H level), and the output signals out1 to out3 are at the signal level of the ground potential vss (L level).

[0074] When the input signal in1 is at the ground potential vss (L level) and the input signal in2 is at the signal level of the low power supply voltage vcc (H level), the output signal out1 is at the high power supply voltage vdd (H level), and the output signals out0, out2, and out3 are at the signal level of the ground potential vss (L level).

[0075] When the input signal in1 is at the low power supply voltage vcc (H level) and the input signal in2 is at the ground potential vss (L level), the output signal out2 is at the high power supply voltage vdd (H level), and the output signals out0, out1, and out3 are at the ground potential vss (L level).

[0076] When the input signals in1 and in2 are both at the signal level of the low power supply voltage vcc (H level), the output signal out3 is at the signal level of the high power supply voltage vdd (H level), and the output signals out0 to out2 are at the signal level of the ground potential vss (L level).

[0077] In this way, in the logic level shifter circuit 50, when the signal levels of the input signals are in a specific combination, any one of the output signals out0 to out3 becomes the vdd level.

[0078] With this configuration, a four-output logic level shifter circuit can be configured using eight P-channel MOS transistors, making it possible to reduce the number of high-voltage elements and perform signal level shifting while preventing an increase in chip size.

[0079] FIG. 9 is a circuit diagram showing the configuration of a logic level shifter circuit 60 having three input signals (that is, three inputs), as a modification of the logic level shifter circuit of this embodiment.

[0080] The logic level shifter circuit 60 is composed of a first circuit block 61 consisting of cross-connected P-channel transistors, a second circuit block 62 consisting of three series-connected N-channel transistors, and a third circuit block 63 consisting of three parallel-connected N-channel transistors.

[0081] The first circuit block 61 has a configuration similar to that of the first circuit block 31 shown in FIG. 3, and therefore a description thereof will be omitted here.

[0082] The second circuit block 62 is composed of transistors NM51, NM52, and NM53. The transistors NM51, NM52, and NM53 are composed of N-channel MOSFETs, and are connected in series between node n1 and the voltage supply line L2 of the ground potential VSS by connecting the source of transistor NM51 to the drain of transistor NM52, and the source of transistor NM52 to the drain of transistor NM53, respectively.

[0083] An input signal in1 is supplied to the gate of the transistor NM51, an input signal in2 is supplied to the gate of the transistor NM52, and an input signal in3 is supplied to the gate of the transistor NM53.

[0084] The third circuit block 63 is composed of a transistor NM54, a transistor NM55, and a transistor NM56. The transistors NM53, NM54, and NM55 are composed of N-channel MOSFETs, and are connected in parallel between the node n2 and the voltage supply line L2 of the ground potential VSS by connecting their drains to each other and their sources to each other.

[0085] The gate of transistor NM54 is supplied with an inverted input signal xin1, which is the inverted version of the input signal in1. The gate of transistor NM55 is supplied with an inverted input signal xin2, which is the inverted version of the input signal in2. The gate of transistor NM56 is supplied with an inverted input signal xin3, which is the inverted version of the input signal in3.

[0086] FIG. 10 is an input / output table showing the signal levels of the output signal out according to combinations of the signal levels of the input signals in1, in2, and in3.

[0087] When the input signals in1, in2, and in3 are all at the signal level of the ground potential vss (L level), the output signal out also has the signal level of the ground potential vss (L level).

[0088] When the input signals in1 and in2 are at the ground potential vss (L level) and the input signal in3 is at the low power supply voltage vcc (H level), the output signal out has the signal level of the ground potential vss (L level).

[0089] When the input signals in1 and in3 are at the ground potential vss (L level) and the input signal in2 is at the low power supply voltage vcc (H level), the output signal out has the signal level of the ground potential vss (L level).

[0090] When the input signal in1 is at the ground potential vss (L level) and the input signals in2 and in3 are at the signal level of the low power supply voltage vcc (H level), the output signal out has the signal level of the ground potential vss (L level).

[0091] When the input signal in1 is at the low power supply voltage vcc (H level) and the input signals in2 and in3 are at the ground potential vss (L level), the output signal out has the signal level of the ground potential vss (L level).

[0092] When the input signals in1 and in3 are at the low power supply voltage vcc (H level) and the input signal in2 is at the ground potential vss (L level), the output signal out has the signal level of the ground potential vss (L level).

[0093] When the input signals in1 and in2 are at the low power supply voltage vcc (H level) and the input signal in3 is at the ground potential vss (L level), the output signal out has the signal level of the ground potential vss (L level).

[0094] When the input signals in1, in2, and in3 are all at the signal level of the low power supply voltage vcc (H level), the output signal out becomes the signal level of the high power supply voltage vdd (H level).

[0095] As described above, the configuration of the logic level shifter circuit 30 of this embodiment shown in Fig. 3 can be easily expanded by changing the number of N-channel MOS transistors connected in series or in parallel. That is, even in the case of a logic level shifter circuit 60 shown in Fig. 9, in which the number of N-channel MOS transistors connected in series and the number of N-channel MOS transistors connected in parallel are three, the signal level of the output signal out can be set to the vdd level when the signal levels of multiple input signals are in a specific combination, just like the logic level shifter circuit 30. Note that by switching the input signals, the combination of input signals that results in the output signal out being the vdd level can be arbitrarily changed. [Example]

[0096] Next, a second embodiment of the present invention will be described.

[0097] Second Embodiment FIG. 11 is a circuit diagram showing a configuration of a logic level shifter circuit 70 according to a second embodiment of the present invention.

[0098] The logic level shifter circuit 60 is composed of a first circuit block 71 consisting of cross-connected N-channel transistors, a second circuit block 72 consisting of series-connected P-channel transistors, and a third circuit block 73 consisting of parallel-connected P-channel transistors.

[0099] The first circuit block 71 is composed of a transistor NM61 and a transistor NM62. The transistors NM61 and NM62 are each composed of an N-channel MOSFET, and each of the sources is connected to a voltage supply line L4 of the negative high power supply voltage vmd.

[0100] The drain of transistor NM61 is connected to node n3. The gate of transistor NM61 is connected to node n4. Node n4 is an output node that outputs the output signal out of the logic level shifter circuit 60. The drain of transistor NM62 is connected to node n4. The gate of transistor NM62 is connected to node n3.

[0101] The transistors NM61 and NM62 are connected to each other in a so-called cross-connected state, with one gate connected to the drain of the other and one drain connected to the gate of the other.

[0102] The second circuit block 72 is made up of a transistor PM61 and a transistor PM62. The transistors PM61 and PM62 are each made up of a P-channel MOSFET.

[0103] The source of the transistor PM61 is connected to the voltage supply line L3 of the ground potential VSS. The drain of the transistor PM62 is connected to the node n3. The drain of the transistor PM61 and the source of the transistor PM62 are connected in series between the voltage supply line L3 of the ground potential VSS and the node n3.

[0104] The gate of the transistor PM61 is supplied with an input signal in1, and the gate of the transistor PM62 is supplied with an input signal in2.

[0105] The third circuit block 73 is made up of a transistor PM63 and a transistor PM64. The transistors PM63 and PM64 are each made up of a P-channel MOSFET.

[0106] The drains of the transistors PM63 and PM64 are connected to each other and to a node n4. The sources of the transistors PM63 and PM64 are connected to each other and to a voltage supply line L3 of the ground potential VSS. The drains and sources of the transistors PM63 and PM64 are connected to each other, so that the transistors PM63 and PM64 are connected in parallel between the voltage supply line L3 of the ground potential VSS and the node n4.

[0107] An inverted input signal xin1, which is the inverted signal level of the input signal in1, is supplied to the gate of the transistor PM63. An inverted input signal xin2, which is the inverted signal level of the input signal in2, is supplied to the gate of the transistor PM64.

[0108] 12 is a diagram showing the signal levels of the input signals in1 and in2, the inverted input signals xin1 and xin2, and the output signal out. Note that the low power supply voltage vmc and the high power supply voltage vmd are both negative power supply voltages, and the high power supply voltage vmd has a larger voltage difference from the ground potential vss than the low power supply voltage vmc.

[0109] The input signals in1, in2 and the inverted input signals xin1, xin2 are all signals whose signal levels change between logic level 0 (H level) and logic level 1 (L level), with logic level 0 representing the ground potential vss and logic level 1 representing the negative low power supply voltage vmc.

[0110] The signal level of the output signal out changes between logic level 0 and logic level 1, with logic level 0 being the ground potential vss and logic level 1 being the signal level of the negative high power supply voltage vmd.

[0111] FIG. 13 is an input / output table showing the signal levels of the output signal out according to combinations of the signal levels of the input signals in1 and in2.

[0112] When the input signals in1 and in2 are both at the signal level of the ground potential vss (H level), the output signal out also has the signal level of the ground potential vss (H level).

[0113] When the input signal in1 is at the ground potential vss (H level) and the input signal in2 is at the signal level of the low power supply voltage vmc (L level), the output signal out has the signal level of the ground potential vss (H level).

[0114] When the input signal in1 is at the low power supply voltage vmc (L level) and the input signal in2 is at the ground potential vss (H level), the output signal out has the signal level of the ground potential vss (H level).

[0115] When the input signals in1 and in2 are both at the signal level of the low power supply voltage vmc (L level), the output signal out becomes the signal level of the high power supply voltage vmd (L level).

[0116] As described above, the configuration of the logic level shifter circuit 70 of this embodiment makes it possible to reduce the number of high-voltage elements in the logic level shifter circuit even when the power supply voltage is a negative power supply voltage.

[0117] It should be noted that the present invention is not limited to the above-described embodiments. For example, the above-described embodiments have been described with reference to a configuration in which the data driver 14 includes the logic level shifter circuit 30. However, the configurations of the logic level shifter circuits 30 to 70 described above can be applied to various other semiconductor devices. [Explanation of symbols]

[0118] 100 display device 11 Display panel 12 Display Controller 13 Gate Driver 14 Data Driver 21 Interface 22 Reference voltage generation circuit 23 Logic Circuits 24 Shift Register 25 Data Latch 26 Level Shifter 27 DA conversion circuit 28 Output amplifier circuit 30, 40, 50, 60, 70 Logic level shifter circuit 31, 61, 71 First circuit block 32, 62, 72 Second circuit block 33,63,73 Third circuit block 41 Voltage clamp transistor pair 51 1st circuit section 52 2nd circuit section 53 Third circuit section 54 4th circuit section

Claims

1. a logic level shifter circuit that receives a first input signal and a second input signal, each of whose signal levels changes between a voltage level of a first voltage representing a first logic level and a reference voltage representing a second logic level, and generates an output signal whose signal level changes to a logic level according to a combination of the logic levels of the first input signal and the second input signal, and whose voltage level representing the first logic level is a voltage level of a second voltage that is different from the first voltage and whose voltage difference from the reference voltage is larger than the voltage difference between the first voltage and the reference voltage, The logic level shifter circuit comprises: a first transistor and a second transistor of a first conductivity type, each having a first end connected to a power supply voltage supply line that supplies the second voltage, and one second end and the other control end, and one control end and the other second end, connected to each other; a third transistor of a second conductivity type, the control terminal of which receives the first input signal, and a fourth transistor of a second conductivity type, the control terminal of which receives the second input signal, connected in series between a first node, which is a node connecting the second terminal of the first transistor and the control terminal of the second transistor, and a reference voltage supply line that supplies the reference voltage; a fifth transistor of a second conductivity type, the fifth transistor receiving at its control end an inverted first input signal obtained by inverting a logic level of the first input signal, and a sixth transistor of a second conductivity type, the fifth transistor and the sixth transistor being connected in parallel between the reference voltage supply line and a second node, the fifth transistor receiving at its control end an inverted second input signal obtained by inverting a logic level of the second input signal; and The semiconductor device outputs the output signal from the second node.

2. The logic level shifter circuit comprises: a first clamp transistor having a first terminal connected to the second terminal of the third transistor, a second terminal connected to the first node, and a control terminal receiving a bias voltage; a second clamp transistor having a first terminal connected to the second terminals of the fifth transistor and the sixth transistor, a second terminal connected to the second node, and a control terminal connected to the control terminal of the first clamp transistor and receiving the bias voltage; 2. The semiconductor device according to claim 1, further comprising a voltage clamp transistor pair comprising:

3. the third transistor receives the first input signal at its gate; the fourth transistor receives the second input signal at its gate; the fifth transistor receives the inverted first input signal at its gate; the sixth transistor receives the inverted second input signal at its gate; 3. The semiconductor device according to claim 1, wherein when the first input signal and the second input signal are both at logic level 1, the semiconductor device outputs the output signal at logic level 1.

4. the first transistor and the second transistor are P-channel MOS transistors, each having a source connected to the power supply voltage supply line, and one gate and the other drain, and one drain and the other gate, connected to each other; the third transistor and the fourth transistor are configured as N-channel MOS transistors, and are connected in series with each other between the first node and the reference voltage supply line by connecting a source of the third transistor and a drain of the fourth transistor; the fifth transistor and the sixth transistor are configured by N-channel MOS transistors, and are connected in parallel to each other between the second node and the reference voltage supply line by having their drains connected to each other and their sources connected to each other; 3. The semiconductor device according to claim 1, wherein the first insulating film is a semiconductor material.

5. the first transistor and the second transistor are configured as N-channel MOS transistors, each having a source connected to the power supply voltage supply line, and one gate and the other drain, and one drain and the other gate, connected to each other; the third transistor and the fourth transistor are P-channel MOS transistors, and are connected in series between the first node and the reference voltage supply line by connecting a drain of the third transistor and a source of the fourth transistor; the fifth transistor and the sixth transistor are configured as P-channel MOS transistors, and are connected in parallel to each other between the second node and the reference voltage supply line by having their drains connected to each other and their sources connected to each other; 3. The semiconductor device according to claim 1, wherein the first insulating film is a semiconductor material.

6. A data driver is connected to a display panel having a plurality of data lines and a plurality of gate lines, and a plurality of pixel units arranged in a matrix at each intersection of the plurality of data lines and the plurality of gate lines, the data driver having a plurality of output channels for outputting drive signals to the plurality of data lines based on a video data signal consisting of a series of pixel data pieces, a data latch for capturing and sequentially outputting the series of pixel data pieces; a level shifter that performs a level shift to change the signal level of the pixel data piece output from the data latch; an output unit that outputs the driving signal based on the pixel data piece level-shifted by the level shifter; Including, The pixel data pieces output from the data latch are composed of a first input signal and a second input signal, each of whose signal levels changes between a voltage level of a first voltage representing a first logic level and a reference voltage representing a second logic level; the level shifter comprises a logic level shifter circuit that receives the first input signal and the second input signal, and generates an output signal whose signal level changes to a logic level according to a combination of the logic levels of the first input signal and the second input signal, and whose voltage level representing the first logic level is a voltage level of a second voltage that is different from the first voltage and whose voltage difference from the reference voltage is larger than the voltage difference between the first voltage and the reference voltage; The logic level shifter circuit comprises: a first transistor and a second transistor of a first conductivity type, each having a first end connected to a power supply voltage supply line that supplies the second voltage, and one second end and the other control end, and one control end and the other second end, connected to each other; a third transistor of a second conductivity type, the control terminal of which receives the first input signal, and a fourth transistor of a second conductivity type, the control terminal of which receives the second input signal, connected in series between a first node, which is a node connecting the second terminal of the first transistor and the control terminal of the second transistor, and a reference voltage supply line that supplies the reference voltage; a fifth transistor of a second conductivity type, the fifth transistor receiving at its control end an inverted first input signal obtained by inverting a logic level of the first input signal, and a sixth transistor of a second conductivity type, the fifth transistor and the sixth transistor being connected in parallel between the reference voltage supply line and a second node, the fifth transistor receiving at its control end an inverted second input signal obtained by inverting a logic level of the second input signal; and outputting the output signal from the second node.

1. A data driver comprising:

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