Semiconductor device

Abstract

To provide a semiconductor device whose tolerance can be improved.SOLUTION: A semiconductor device in an embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a first conductor part, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a second electrode. The first semiconductor region includes a first part and a second part that exists around the first part. The second semiconductor region is provided on the first part. The first conductor part faces the second semiconductor region through a first insulating layer. The fourth semiconductor region is provided on the second part. A second conductor part faces the fourth semiconductor region through a second insulating layer in a second direction. A lower end of the second conductor part exists lower than a lower end of the first conductor part. The fifth semiconductor region is provided between the second part and the lower end of the second conductor part. The fifth semiconductor region has higher impurity concentration of the first conductivity type than the second part.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used for power conversion, etc. It is desirable for semiconductor devices to have high withstand voltages. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-168659 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor device capable of improving the withstand voltage. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a first conductive portion, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a second electrode. The first semiconductor region is provided on the first electrode. The first semiconductor region includes a first portion and a second portion located around the first portion along a first plane perpendicular to a first direction from the first electrode toward the first semiconductor region. The second semiconductor region is provided on the first portion. The third semiconductor region is provided on the second semiconductor region. The first conductive portion faces the second semiconductor region via a first insulating layer in a second direction perpendicular to the first direction. The fourth semiconductor region is provided on the second portion. The second conductive portion faces the fourth semiconductor region in the second direction via a second insulating layer. A lower end of the second conductive portion is located lower than a lower end of the first conductive portion. The fifth semiconductor region is provided between the second portion and the lower end of the second conductive portion. The fifth semiconductor region has a higher impurity concentration of the first conductivity type than the second portion. The second electrode is provided on the second semiconductor region, the third semiconductor region, and the fourth semiconductor region. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is an enlarged perspective cross-sectional view of a portion II of FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. [Figure 4] 4A and 4B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the embodiment. [Figure 5] 5A and 5B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the embodiment. [Figure 6] 6A to 6C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the embodiment. [Figure 7]FIG. 7 is an enlarged cross-sectional view of a part of FIG. [Figure 8] FIG. 8 is a cross-sectional view showing a part of a semiconductor device according to a modified example of the embodiment. [Figure 9] FIG. 9 is an enlarged cross-sectional view of a part of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and each drawing, elements similar to those already described are designated by the same reference numerals, and detailed description will be omitted as appropriate. In the following description and drawings, n + , n, n - and p + , p - The notation indicates the relative level of each impurity concentration. That is, a notation with a "+" indicates a relatively higher impurity concentration than a notation with neither a "+" nor a "-" and a notation with a "-" indicates a relatively lower impurity concentration than a notation with neither. When both p-type and n-type impurities are contained in each region, these notations indicate the relative level of the net impurity concentration after the impurities compensate for each other. In each of the embodiments described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0008] Fig. 1 is a plan view showing a semiconductor device according to an embodiment, Fig. 2 is an enlarged perspective cross-sectional view of a portion II in Fig. 1, and Fig. 3 is a cross-sectional view taken along the line III-III in Fig. 1. The semiconductor device 100 according to the embodiment is a MOSFET. As shown in FIGS. - type (first conductivity type) drift region 1 (first semiconductor region), p -type (second conductivity type) base region 2 (second semiconductor region), n + source region 3 (third semiconductor region), p - n-type semiconductor region 4 (fourth semiconductor region), n-type semiconductor region 5 (fifth semiconductor region), n + shaped drain region 6, p - The semiconductor region 7 includes a first conductive portion 11, a first insulating layer 11a, a second conductive portion 12, a second insulating layer 12a, a drain electrode 21 (first electrode), a source electrode 22 (second electrode), and a gate pad 23. In FIG. 2, the source electrode 22 is indicated by a dashed line.

[0009] In the description of the embodiment, an XYZ orthogonal coordinate system is used. - The direction toward the drift region 1 is defined as the Z direction (first direction). Two directions that are perpendicular to the Z direction and orthogonal to each other are defined as the X direction (second direction) and the Y direction (third direction). - The direction toward the n-type drift region 1 is called "up" and the opposite direction is called "down." These directions are - The shape is based on the relative position to the drift region 1 and is independent of the direction of gravity.

[0010] 1, a source electrode 22 and a gate pad 23 are provided on the upper surface of the semiconductor device 100. The source electrode 22 and the gate pad 23 are spaced apart from each other and electrically isolated from each other.

[0011] As shown in FIG. 2, a drain electrode 21 is provided on the bottom surface of the semiconductor device 100. + The drain region 6 is provided on the drain electrode 21 and is electrically connected to the drain electrode 21. - The drift region 1 is n + The n-type drain region 6 is provided on the n-type drain region 6. - The drift region 1 is n + The n-type drain region 6 is electrically connected to the drain electrode 21. - The n-type impurity concentration in the n-type drift region 1 is +The n-type impurity concentration in the n-type drain region 6 is lower than that in the n-type drain region 6 .

[0012] n - As shown in FIGS. 1 to 3, the drift region 1 includes a first portion 1a and a second portion 1b. The second portion 1b is located around the first portion 1a in the XY plane (first plane). The first portion 1a is located in the cell region. The cell region is a region through which current mainly flows when the semiconductor device 100 is in operation. The second portion 1b is located in the termination region. The termination region is a region in which a depletion layer extends toward the periphery of the semiconductor device 100 when the semiconductor device 100 is at its breakdown voltage.

[0013] As shown in Figures 2 and 3, - The base region 2 is provided on the first portion 1a. + The source region 3 is p - The first conductive portion 11 is provided on the first portion 1a via a first insulating layer 11a. The first conductive portion 11 is connected to the p - It faces the shape base area 2.

[0014] As shown in Figure 3, p - The semiconductor region 4 is provided on the second portion 1b. The second conductive portion 12 is provided on the second portion 1b via a second insulating layer 12a. The second conductive portion 12 is connected to the p - The second conductive portion 12 faces the shaped semiconductor region 4. The lower end of the second conductive portion 12 is located lower than the lower end of the first conductive portion 11.

[0015] p - On top of the semiconductor region 4, + There is no n-type semiconductor region such as the p-type source region 3. - In the upper part of the semiconductor region 4, n + No n-type semiconductor region is provided in the position adjacent to the n-type source region 3, and - A part of the semiconductor region 4 is present.

[0016] The n-type semiconductor region 5 is provided between the second portion 1b and the lower end of the second conductive portion 12. The n-type impurity concentration in the n-type semiconductor region 5 is higher than the n-type impurity concentration in the second portion 1b. - It is preferable that the semiconductor region 4 is away from the substrate.

[0017] p - The semiconductor region 7 is provided on the second portion 1b as shown in FIG. - The semiconductor region 4 has a p - Shape base region 2 and p - The second conductive portion 12 is located between the first conductive portion 12 and the second conductive portion 7. - Semiconductor region 4 and p - It is located between the semiconductor region 7. - The length of the semiconductor region 7 in the X direction is p - The length of the semiconductor region 4 in the X direction is longer than the length of the semiconductor region 4 in the X direction.

[0018] The source electrode 22 is p - Shape base area 2, n + Shape source region 3, p - shaped semiconductor region 4, and p - The source electrode 22 is provided on the p-type semiconductor region 7. - Shape base area 2, n + Shape source region 3, p - shaped semiconductor region 4, and p - The semiconductor region 7 is electrically connected to the semiconductor region 7 .

[0019] The first conductive portion 11 and the source electrode 22 are electrically isolated from each other by an insulating layer 11b. The second conductive portion 12 and the source electrode 22 are electrically isolated from each other by an insulating layer 12b. The first conductive portion 11 and the second conductive portion 12 are electrically connected to a gate pad 23.

[0020] As shown in Figures 2 and 3, - Shape base area 2, n + A plurality of the source regions 3 and a plurality of the first conductive portions 11 are provided on the first portion 1a in the X direction.- Shape base region 2, p - The semiconductor region 4, the first conductive portion 11, and the second conductive portion 12 extend in the Y direction. - The base regions 2 and the plurality of first conductive portions 11 are arranged alternately.

[0021] 3 shows the structure of one end side in the X direction of the semiconductor device 100. The structure of the other end side in the X direction of the semiconductor device 100 is substantially symmetrical to the structure shown in FIG. 3. That is, one second conductive part 12 is provided at one end side in the X direction of the semiconductor device 100, and another second conductive part 12 is provided at the other end side in the X direction of the semiconductor device 100. - Shape base region 2, multiple n + The source region 3 and the plurality of first conductive portions 11 are located between a pair of second conductive portions 12 spaced apart from each other in the X direction.

[0022] As shown in Figure 2, p - The base region 2 may include a contact region 2a with a high p-type impurity concentration. - The p-type semiconductor region 4 may include a contact region 4a having a high p-type impurity concentration. - The p-type semiconductor region 7 may include a contact region 7a having a high concentration of p-type impurities. The contact region 2a, the contact region 4a, and the contact region 7a are in contact with the source electrode 22.

[0023] As shown in Figure 2, one p - On the base region 2, a plurality of contact regions 2a and a plurality of n + The source regions 3 are arranged alternately in the Y direction. + The length Ls of the source region 3 in the Y direction is longer than the length Lb of the contact region 2a in the Y direction. + This corresponds to the distance between the source regions 3.

[0024] The operation of the semiconductor device 100 will be described. In a state where a positive voltage is applied to the drain electrode 21 with respect to the source electrode 22, a voltage equal to or higher than the threshold is applied to the first conductive section 11. As a result, p - A channel (inversion layer) is formed in the base region 2. Electrons pass through the channel and travel from the source electrode 22 to the n - Then, when the voltage applied to the first conductive portion 11 becomes lower than the threshold, the p - The channel in the base region 2 disappears, and the semiconductor device 100 enters an off state. The first conductive portion 11 functions as a gate electrode for controlling the flow of current in the semiconductor device 100.

[0025] p - On the n-type semiconductor region 4, there is no n-type semiconductor region electrically connected to the source electrode 22. Therefore, even when a voltage equal to or higher than the threshold is applied to the second conductive portion 12, the p - No current flows through the inversion layer of the semiconductor region 4.

[0026] An example of the material for each component is explained below. - Shape drift region 1, p - Shape base area 2, n + Shape source region 3, p - n-type semiconductor region 4, n-type semiconductor region 5, n + shaped drain region 6, and p - The semiconductor region 7 includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity. The first conductive portion 11 and the second conductive portion 12 include a conductive material such as polysilicon. The first insulating layer 11a, the insulating layer 11b, the second insulating layer 12a, and the insulating layer 12b include an insulating material such as silicon oxide. The drain electrode 21, the source electrode 22, and the gate pad 23 include a metal such as titanium, gold, or aluminum.

[0027] The preferred ranges of impurity concentrations in each semiconductor region are as follows:- The n-type impurity concentration in the drift region 1 is 1.0×10 16 atom / cm 3 Over 1.0 x 10 18 atom / cm 3 The following is true: - Shape base region 2, p - shaped semiconductor region 4, and p - The n-type impurity concentration in the n-type semiconductor region 7 is 1.0×10 17 atom / cm 3 Over 1.0 x 10 19 atom / cm 3 The following is true: n + The n-type impurity concentration in the source region 3 is 5.0×10 18 atom / cm 3 Over 5.0 x 10 20 atom / cm 3 The n-type impurity concentration in the contact region 2a, the contact region 4a, and the contact region 7a is 5.0×10 18 atom / cm 3 Over 5.0 x 10 20 atom / cm 3 The following is true: n + The n-type impurity concentration in the n-type drain region 6 is 1.0×10 19 atom / cm 3 Over 1.0 x 10 21 atom / cm 3 The following is the result.

[0028] 4(a), 4(b), 5(a), 5(b), and 6 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the embodiment. An example of a manufacturing method for the semiconductor device 100 will be described. - Shape drift region 1 and n + A semiconductor substrate Sub including a drain region 6 is prepared. As shown in FIG. - A plurality of openings OP1 are formed in the upper surface of the drift region 1. The plurality of openings OP1 are aligned in the X direction, and each opening OP1 extends in the Y direction. -An opening OP2 is formed in the upper surface of the semiconductor drift region 1. The opening OP2 is formed deeper than the openings OP1. The opening OP2 is located outside the region in which the semiconductor device 100 is formed, relative to the multiple openings OP1.

[0029] The semiconductor substrate Sub is thermally oxidized. As a result, the inner surface of the opening OP1, the inner surface of the opening OP2, and the n - An insulating layer 10a is formed on the upper surface of the n-type drift region 1. As shown in FIG. 4(b), n-type impurities are ion-implanted into the bottom of the opening OP2 to form an n-type semiconductor region 5.

[0030] A polysilicon layer is formed by chemical vapor deposition (CVD) to fill the openings OP1 and OP2. The upper surface of the polysilicon layer is recessed by etching. As a result, as shown in FIG. 5(a), a first conductive portion 11 is formed inside the opening OP1, and a second conductive portion 12 is formed inside the opening OP2.

[0031] P-type impurity and n-type impurity ions are implanted sequentially, and n - At the top of the drift region 1, p - Shape base area 2, n + Shape source region 3, p - shaped semiconductor region 4, and p - 5B, an n-type semiconductor region 7 is formed. An insulating layer 10b is formed by CVD to cover the semiconductor region. + Shape source region 3, p - shaped semiconductor region 4, and p - The insulating layer 10b and the insulating layer 10a are etched so that the upper surface of the semiconductor region 7 is exposed.

[0032] A metal layer is formed by CVD, sputtering, etc. The metal layer is patterned to form a source electrode 22 and a gate pad 23 (not shown). + The n-type drain region 6 is then grown to a predetermined thickness. + The bottom surface of the shaped drain region 6 is ground. +A drain electrode 21 is formed by sputtering on the lower surface of the drain region 6. In this way, the semiconductor device 100 according to the embodiment is manufactured.

[0033] The advantages of the embodiment will be described. The semiconductor device 100 is - Shape drift region 1, p - Shape base region 2, and n + The semiconductor device 100 includes a parasitic transistor consisting of a source region 3. When the semiconductor device 100 is turned off, impact ionization (avalanche breakdown) occurs inside the semiconductor device 100. A large amount of carriers (electrons and holes) are generated by the impact ionization. The electrons are - The holes pass through the p-type drift region 1 and are discharged to the drain electrode 21. - The electrons pass through the base region 2 and are discharged to the source electrode 22. At this time, the electrons are discharged to the p - If the potential of the base region 2 rises, a parasitic transistor may operate. If a large current flows through the semiconductor device 100 due to the operation of the parasitic transistor, the semiconductor device 100 may be destroyed. For this reason, it is desirable that the parasitic transistor is unlikely to operate.

[0034] The semiconductor device 100 includes a first conductive portion 11 and a second conductive portion 12. When the semiconductor device 100 is turned off, n - The potential difference between the drift region 1 and the first conductive portion 11, and n - Due to the potential difference between the drift region 1 and the second conductive portion 12, impact ionization occurs near the lower end of the first conductive portion 11, near the lower end of the second conductive portion 12, etc. In particular, in the semiconductor device 100, the lower end of the second conductive portion 12 is located lower than the lower end of the first conductive portion 11. Therefore, when the semiconductor device 100 is turned off, impact ionization occurs mainly near the lower end of the second conductive portion 12.

[0035] When impact ionization occurs near the bottom end of the second conductive portion 12, holes are mainly transported through p - Semiconductor region 4 and p - flow into the semiconductor region 7. - Semiconductor region 4 and p -On the semiconductor region 7, n + There is no n-type semiconductor region such as the n-type source region 3. + At the height (position in the Z direction) where the source region 3 is provided, - A part of the semiconductor region 4 and p - There is a part of the semiconductor region 7. - Semiconductor region 4 and p - No parasitic transistor exists in the region where the semiconductor region 7 is provided. By providing the second conductive portion 12, the occurrence of parasitic transistors in the semiconductor device 100 can be suppressed, and the avalanche resistance of the semiconductor device 100 can be improved.

[0036] On the other hand, when the lower end of the second conductive portion 12 is located lower than the lower end of the first conductive portion 11, the second conductive portion 12 and n + The distance between the first conductive portion 11 and the n-type drain region 6 is + The distance between the second conductive portion 12 and the drain region 6 is shorter than the distance between the second conductive portion 12 and the drain region 6. + As a result, the breakdown voltage of the semiconductor device 100 decreases.

[0037] To address this issue, in the embodiment, an n-type semiconductor region 5 is provided between the second portion 1b and the second conductive portion 12. The n-type impurity concentration in the n-type semiconductor region 5 is higher than the n-type impurity concentration in the second portion 1b. By providing the n-type semiconductor region 5, the expansion of a depletion layer in the region below the second conductive portion 12 is suppressed. This makes it possible to suppress a decrease in the breakdown voltage of the semiconductor device 100.

[0038] According to the embodiment, the avalanche resistance of the semiconductor device 100 can be improved while suppressing a decrease in the breakdown voltage of the semiconductor device 100.

[0039] FIG. 7 is an enlarged cross-sectional view of a part of FIG. The width W2 of the second conductive portion 12 may be the same as the width W1 of the first conductive portion 11. Alternatively, as shown in FIG. 7, the width W2 of the second conductive portion 12 may be wider than the width W1 of the first conductive portion 11. The width is the length in the X direction. When the width W2 is wider than the width W1, impact ionization occurs more easily near the lower end of the second conductive portion 12. This can further improve the avalanche resistance of the semiconductor device 100. For example, the width W2 is preferably 1.01 to 3 times the width W1, and more preferably 1.02 to 2 times the width W1. Note that when the width of the first conductive portion 11 or the second conductive portion 12 varies in the Z direction, n - Shape drift region 1 and p - The width W1 or width W2 is measured at a height where a pn junction exists between the base region 2 and the semiconductor substrate.

[0040] As described above, the lower end of the second conductive portion 12 is located lower than the lower end of the first conductive portion 11. For example, the depth D2 of the second conductive portion 12 is longer than the depth D1 of the first conductive portion 11. The depth D1 is n + The depth D2 corresponds to the distance in the Z direction from the top surface of the source region 3 to the bottom end of the first conductive portion 11. - Depth D2 corresponds to the distance in the Z direction from the upper surface of n-type semiconductor region 4 to the lower end of second conductive portion 12. As depth D2 is longer, impact ionization occurs more easily near the lower end of second conductive portion 12. On the other hand, if depth D2 is excessively long, the breakdown voltage of semiconductor device 100 may decrease even when n-type semiconductor region 5 is provided. For example, depth D2 is preferably 1.01 to 1.3 times, and more preferably 1.02 to 1.2 times, of depth D1.

[0041] The distance d2 may be the same as the distance d1, or may be longer than the distance d1. The distance d1 is the distance between the first conductive portions 11 adjacent to each other in the X direction. The distance d2 is the distance in the X direction between the second conductive portion 12 and the first conductive portion 11 adjacent to the second conductive portion 12. The distance d2 may be different from the distance d1, or may be the same as the distance d1. It is preferable that the difference between the distance d1 and the distance d2 is small. If the distance d2 is excessively shorter than the distance d1, p -The width of the semiconductor region 4 is reduced, and - Holes are less likely to be discharged from the semiconductor region 4. If the distance d2 is excessively longer than the distance d1 and the second conductive portion 12 is farther away from the first conductive portion 11, impact ionization is more likely to occur near the lower end of the first conductive portion 11. For example, the distance d2 is preferably 0.78 to 1.5 times the distance d1, and more preferably 0.85 to 1.2 times the distance d1. Most preferably, the distance d1 and the distance d2 are the same. Note that if the distance d1 or the distance d2 changes in the Z direction, n - Shape drift region 1 and p - The distance d1 or the distance d2 is measured at the height where the pn junction between the base region 2 and the semiconductor substrate 1 exists.

[0042] The higher the n-type impurity concentration in the n-type semiconductor region 5, the more the depletion layer can be suppressed from spreading in the region below the second conductive portion 12. On the other hand, if the n-type impurity concentration in the n-type semiconductor region 5 is excessively high, an electric field will concentrate near the n-type semiconductor region 5, which may reduce the breakdown voltage of the semiconductor device 100. For this reason, the n-type impurity concentration in the n-type semiconductor region 5 is set to n - The concentration of n-type impurities in the n-type drift region 1 is preferably 8 times or more and 300 times or less, and more preferably 10 times or more and 100 times or less.

[0043] (Variation) FIG. 8 is a cross-sectional view showing a part of a semiconductor device according to a modified example of the embodiment. The semiconductor device 110 shown in FIG. 8 further includes a third conductive portion 13 in comparison with the semiconductor device 100. The third conductive portion 13 is provided on the second portion 1b. The third conductive portion 13 is located between the first conductive portion 11 and the second conductive portion 12 in the X direction. Between the first conductive portion 11 and the third conductive portion 13, p - A p-type semiconductor region 4 is provided between the second conductive portion 12 and the third conductive portion 13. - The third conductive portion 13 is provided with a p-type semiconductor region 4. The third conductive portion 13 is connected to each of the p-type semiconductor regions 4 in the X direction via the third insulating layer 13a. -The third conductive portion 13 faces the semiconductor region 4. The third conductive portion 13 and the source electrode 22 are electrically isolated from each other by an insulating layer 13b. The third conductive portion 13 is electrically connected to a gate pad 23.

[0044] FIG. 9 is an enlarged cross-sectional view of a part of FIG. As shown in FIG. 9, the lower end of the third conductive portion 13 is located higher than the lower end of the second conductive portion 12. The lower end of the third conductive portion 13 may be located higher than the lower end of the first conductive portion 11. By positioning the lower end of the third conductive portion 13 higher than the lower end of the second conductive portion 12, impact ionization is less likely to occur near the lower end of the third conductive portion 13. The third conductive portion 13 has a higher n + The third conductive portion 13 is close to the source region 3. That is, the distance between the third conductive portion 13 and the parasitic transistor is shorter than the distance between the second conductive portion 12 and the parasitic transistor. By suppressing impact ionization near the bottom end of the third conductive portion 13, holes generated by impact ionization are prevented from flowing into the p - This can prevent the current from flowing into the base region 2. This can improve the avalanche resistance of the semiconductor device 110.

[0045] The depth D3 of the third conductive portion 13 is shorter than the depth D1 and shorter than the depth D2. + It corresponds to the distance in the Z direction from the upper surface of the source region 3 to the lower end of the third conductive portion 13. For example, the depth D3 is preferably 0.85 to 0.99 times the depth D1, and more preferably 0.95 to 0.99 times the depth D1.

[0046] The width W3 of the third conductive portion 13 is narrower than the width W2. The width W3 may be the same as the width W1, or may be narrower than the width W1 as shown in the figure. When the width W3 is narrower than the width W2, impact ionization is less likely to occur near the lower end of the third conductive portion 13. This further improves the avalanche resistance of the semiconductor device 110. For example, the width W3 is preferably 0.75 to 0.98 times the width W2, and more preferably 0.85 to 0.95 times the width W2.

[0047] The distance d3 may be the same as the distance d1, or may be different from the distance d1. The distance d3 is the distance in the X direction between the third conductive portion 13 and the first conductive portion 11 adjacent to the third conductive portion 13. It is preferable that the difference between the distance d1 and the distance d3 is small. If the distance d3 is excessively shorter than the distance d1, p - The width of the semiconductor region 4 is reduced, and - Holes are less likely to be discharged from the semiconductor region 4. If the distance d3 is excessively longer than the distance d1, impact ionization is more likely to occur near the lower end of the first conductive portion 11. For example, the distance d3 is preferably 0.85 to 1.15 times the distance d1, and more preferably 0.95 to 1.05 times the distance d1. Most preferably, the distance d1 and the distance d3 are the same.

[0048] The distance d4 may be the same as the distance d1, or may be longer than the distance d1 as shown in FIG. 9. In the semiconductor device 110, the lower end of the third conductive portion 13 is located higher than the lower ends of the first conductive portion 11 and the second conductive portion 12. Therefore, impact ionization is more likely to occur near the lower end of the second conductive portion 12 adjacent to the third conductive portion 13 than in the semiconductor device 100. When the distance d4 is long and p - The wide width of the semiconductor region 4 allows a large number of holes generated by impact ionization to be efficiently discharged. For example, the distance d4 is preferably greater than 1.0 times and less than or equal to 1.5 times the distance d1, and more preferably greater than or equal to 1.02 times and less than or equal to 1.2 times the distance d1.

[0049] Embodiments of the invention include the following features. (Feature 1) A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode, the first semiconductor region including a first portion and a second portion located around the first portion along a first plane perpendicular to a first direction from the first electrode toward the first semiconductor region; a second semiconductor region of a second conductivity type provided on the first portion; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a first conductive portion facing the second semiconductor region via a first insulating layer in a second direction perpendicular to the first direction; a fourth semiconductor region of the second conductivity type provided on the second portion; a second conductive portion that faces the fourth semiconductor region in the second direction via a second insulating layer and has a lower end located lower than a lower end of the first conductive portion; a fifth semiconductor region of the first conductivity type provided between the second portion and the lower end of the second conductive part and having a higher impurity concentration of the first conductivity type than the second portion; a second electrode provided on the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; A semiconductor device comprising: (Feature 2) 2. The semiconductor device according to feature 1, wherein the length of the second conductive portion in the second direction is longer than the length of the first conductive portion in the second direction. (Feature 3) further comprising a third conductive portion located between the first conductive portion and the second conductive portion in the second direction; 3. The semiconductor device according to feature 1 or 2, wherein the third conductive portion faces the fourth semiconductor region in the second direction via a third insulating layer. (Feature 4) 4. The semiconductor device according to feature 3, wherein the lower end of the second conductive portion is located lower than the lower end of the third conductive portion. (Feature 5) 5. The semiconductor device according to feature 4, wherein the lower end of the third conductive portion is located higher than the lower end of the first conductive portion. (Feature 6) A semiconductor device described in any one of features 3 to 5, wherein the length of the third conductive portion in the second direction is shorter than the length of the first conductive portion in the second direction and shorter than the length of the second conductive portion in the second direction. (Feature 7) A semiconductor device described in any one of features 3 to 6, wherein the distance in the second direction between the second conductive portion and the third conductive portion is longer than the distance in the second direction between the first conductive portion and the third conductive portion. (Feature 8) a pair of the second conductive portions spaced apart from each other in the second direction is provided, The semiconductor device according to any one of features 1 to 7, wherein a plurality of the second semiconductor regions and a plurality of the first conductive portions are alternately arranged in the second direction and are located between the pair of second conductive portions.

[0050] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed using SCM. Furthermore, the impurity concentration in each semiconductor region can be measured using, for example, secondary ion mass spectrometry (SIMS).

[0051] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0052] 1:n - Shape drift region, 1a: first part, 1b: second part, 2:p - shaped base region, 2a:contact region, 3:n + Shape source area, 4:p - n-type semiconductor region, 4a: contact region, 5: n-type semiconductor region, 6: n + Shape drain region, 7:p -semiconductor region, 7a: contact region, 10a, 10b: insulating layer, 11: first conductive portion, 11a: first insulating layer, 11b: insulating layer, 12: second conductive portion, 12a: second insulating layer, 12b: insulating layer, 13: third conductive portion, 13a: third insulating layer, 21: drain electrode, 22: source electrode, 23: gate pad, 100, 110: semiconductor device, d1 to d4: distance, D1 to D3: depth, OP1, OP2: opening, Sub: semiconductor substrate, W1 to W3: width

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode, the first semiconductor region including a first portion and a second portion located around the first portion along a first plane perpendicular to a first direction from the first electrode toward the first semiconductor region; a second semiconductor region of a second conductivity type provided on the first portion; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a first conductive portion facing the second semiconductor region via a first insulating layer in a second direction perpendicular to the first direction; a fourth semiconductor region of the second conductivity type provided on the second portion; a second conductive portion that faces the fourth semiconductor region in the second direction via a second insulating layer and has a lower end located lower than a lower end of the first conductive portion; a fifth semiconductor region of the first conductivity type provided between the second portion and the lower end of the second conductive part and having a higher impurity concentration of the first conductivity type than the second portion; a second electrode provided on the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the length of said second conductive portion in said second direction is longer than the length of said first conductive portion in said second direction.

3. a third conductive portion located between the first conductive portion and the second conductive portion in the second direction, The semiconductor device according to claim 1 , wherein said third conductive portion faces said fourth semiconductor region in said second direction with a third insulating layer interposed therebetween.

4. The semiconductor device according to claim 3 , wherein the lower end of the second conductive portion is located lower than the lower end of the third conductive portion.

5. The semiconductor device according to claim 4 , wherein the lower end of the third conductive portion is located higher than the lower end of the first conductive portion.

6. 4. The semiconductor device according to claim 3, wherein a length of the third conductive portion in the second direction is shorter than a length of the first conductive portion in the second direction and shorter than a length of the second conductive portion in the second direction.

7. 4. The semiconductor device according to claim 3, wherein a distance in the second direction between the second conductive portion and the third conductive portion is longer than a distance in the second direction between the first conductive portion and the third conductive portion.

8. a pair of the second conductive portions spaced apart from each other in the second direction; 8. The semiconductor device according to claim 1, wherein a plurality of the second semiconductor regions and a plurality of the first conductive portions are alternately arranged in the second direction and are located between the pair of second conductive portions.

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