Surface processing method for chuck for wafer test device and chuck for wafer test device

Abstract

To provide a surface processing method for a chuck for a wafer test device capable of suppressing a chip crack when performing dicing processing upon the wafer, suppressing a failure that a chuck top face and a wafer bottom face fall into a fixed state, and bringing the chuck top face and the wafer bottom face into a stable adhered state with small contact resistance by reducing a height of burrs on the chuck top face equal to or less than a predetermined dimension or removing the burrs, and a chuck for a wafer test device.SOLUTION: Disclosed is a surface processing method for a disk-shaped chuck which is provided in a wafer test device and holds a wafer by vacuum adsorption. The chuck comprises a top face on which a wafer is mounted, a hole which is recessed from the top face, and a recess consisting of a groove or a step. The surface processing method for the chuck includes successively: a blast polishing step S1 of applying blast polishing to an outer peripheral part of the top face; an electrolytic polishing step S3 of applying electrolytic polishing to the chuck; and a chemical polishing step S4 of applying chemical polishing to the chuck.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a surface treatment method for a chuck of a wafer testing device and a chuck of the wafer testing device. [Background technology]

[0002] BACKGROUND ART Conventionally, wafer testing devices that perform functional tests on semiconductor chips mounted on semiconductor wafers (hereinafter sometimes referred to as wafers) such as silicon wafers are known (for example, Patent Document 1).

[0003] The wafer inspection device (wafer testing device) described in Patent Document 1 includes a vacuum chuck (chuck) on which a wafer is placed and which vacuum-sucks the wafer. The upper surface of the vacuum chuck has a large number of holes and grooves (recesses) formed therein to stably suck and hold the wafer.

[0004] A probe card corresponding to the semiconductor chip to be inspected formed on the wafer is attached to the upper side of the vacuum chuck, and the probe card is provided with a plurality of probes that come into contact with the semiconductor chip.

[0005] The probe card then simultaneously contacts multiple probes on the wafer with the pads of the semiconductor chips formed on the wafer to perform an electrical test. The electrical test also checks the operating status under various temperature conditions. The vacuum chuck is connected to a temperature control system, which can control the temperature of the wafer placed on the vacuum chuck. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2022-113293 Summary of the Invention [Problem to be solved by the invention]

[0007] The chuck of this type of wafer testing device has the following problems. When manufacturing a chuck, minute burrs of several tens of micrometers may occur in recesses formed by holes, grooves, or steps recessed from the top surface of the chuck, or on the outer periphery of the top surface. The inventors of the present invention have found that the influence of these burrs can cause various problems.

[0008] Specifically, the first defect is as follows: The metal film deposited on the underside of the wafer is damaged by contact with burrs due to the suction pressure when the wafer is vacuum-sucked onto the upper surface of the chuck, or due to the contact pressure when multiple probes contact the wafer. This damage prevents a complete seal from being created between the underside of the wafer and the frame tape when the tape is attached to the underside of the wafer in a process downstream of the wafer testing equipment. This causes air bubbles to form between the underside of the wafer and the frame tape, and when the wafer is diced into semiconductor chips, chip cracks may occur, originating near these air bubbles.

[0009] The second problem is as follows: When a wafer is placed on the top surface of a heated chuck, the wafer undergoes thermal expansion changes as it is attracted to the chuck. Specifically, the wafer is subjected to both an attracting force on the underside of the wafer and an expansion force toward the outside of the wafer's diameter. However, contact with the burrs prevents the wafer from thermally expanding, causing the metal film on the underside of the wafer to peel off and resulting in a stuck state between the underside of the wafer and the suction holes (recesses). This stuck state makes it difficult to remove the wafer from the top surface of the chuck when returning it to a cassette after a functional test.

[0010] The third problem is as follows: To obtain accurate test results by passing electricity through a wafer using a wafer testing device, it is ideal to bring the contact resistance between the wafer and the chuck close to the limit of 0.000 Ω. However, when burrs of several tens of microns are present on the top surface of the chuck, the top surface of the chuck and the bottom surface of the wafer do not come into contact with each other over the entire surface, making it difficult to approach the ideal state.

[0011] The above-mentioned problems are particularly likely to become more pronounced in power devices that use a metal film on the underside of the wafer as an electrode. As wafers have become thinner in recent years, it is expected that the metal film on the underside of the wafer will also become thinner. Furthermore, it is expected that wafer diameters will shift from the conventional 8 inches to 12 inches, which will lead to larger chuck diameters. It is also expected that wafer testing temperatures will shift from the conventional room temperature to higher temperatures.

[0012] The present invention aims to provide a surface treatment method for a chuck of a wafer testing device, and a chuck for a wafer testing device, which can reduce the height of burrs on the upper surface of the chuck to a predetermined dimension or less, or can remove the burrs, thereby suppressing chip cracks when the wafer is diced, preventing problems such as the upper surface of the chuck and the lower surface of the wafer becoming stuck together, and achieving a stable, tight contact state with low contact resistance between the upper surface of the chuck and the lower surface of the wafer. [Means for solving the problem]

[0013] In order to solve the above problems, the present invention provides the following means.

[0014] [Aspect 1 of the present invention] A surface treatment method for a disk-shaped chuck that is provided in a wafer testing device and holds a wafer by vacuum suction, the chuck having an upper surface on which the wafer is placed and a recess formed by a hole, groove, or step recessed from the upper surface, the surface treatment method for the chuck comprising, in this order, a blast polishing step for blast polishing the outer periphery of the upper surface, an electrolytic polishing step for electrolytic polishing the chuck, and a chemical polishing step for chemical polishing the chuck.

[0015] Unlike the present invention, physical polishing, such as grinding or lapping, to remove burrs from the top surface of the chuck has limitations, making it impossible to remove burrs with heights of 20 μm to several tens of μm. Furthermore, the external dimensions of the chuck are large, with a diameter of approximately 205 mm (periphery length of approximately 644 mm) for 8-inch wafers and a diameter of approximately 305 mm (periphery length of approximately 958 mm) for 12-inch wafers. For this reason, physical polishing is prone to variations, bias, and unevenness, making it difficult to achieve uniform polishing across the entire top surface of the chuck.

[0016] On the other hand, the surface treatment method for a chuck of a wafer testing device of the present invention includes a blast polishing step, an electrolytic polishing step, and a chemical polishing step in this order, thereby achieving the following excellent effects.

[0017] When manufacturing a chuck, burrs with a large protruding height (burrs with a height of several tens of μm) exist on the top surface of the chuck, especially on the outer periphery. In the present invention, a blast polishing process is first carried out to remove such high burrs on the outer periphery of the chuck. This process breaks down the high burrs and reduces the burr height to a certain level or less (below the target value for blast polishing).

[0018] Thereafter, an electrolytic polishing step and a chemical polishing step are carried out in this order to reduce or remove burrs remaining on the upper surface of the chuck by dissolving them. Specifically, electrolytic polishing has a strong dissolving power and has the property of easily dissolving sharp objects. By utilizing this property, the height of high burrs (sharp burrs) can be further reduced by electrolytic polishing.

[0019] Although chemical polishing has weaker dissolving power than electrolytic polishing, it has excellent uniformity. By utilizing this property, chemical polishing can be used to perform uniform polishing without variation, bias, or unevenness over the entire area, including recesses such as the suction holes of the chuck, thereby reducing the overall height of burrs on the top surface of the chuck.

[0020] In the present invention, by going through the above steps, the height of burrs protruding from the upper surface of the chuck can be reduced to a predetermined size of, for example, 15 μm or less, or the burrs can be removed.

[0021] Therefore, according to the present invention, it is possible to prevent problems such as damage to a metal film formed on the underside of a wafer due to contact with burrs caused by the suction pressure when the wafer is vacuum-sucked to the upper surface of the chuck or the contact pressure when multiple probes contact the wafer. Therefore, when a frame tape is attached to the underside of the wafer in a process subsequent to the wafer testing device, a completely sealed state can be achieved between the underside and the tape. Since it is possible to prevent air bubbles from forming between the underside of the wafer and the frame tape, it is possible to prevent chip cracks from occurring near the air bubbles when the wafer is diced into individual semiconductor chips.

[0022] Furthermore, when a wafer is placed on the upper surface of the heated chuck, even if a thermal expansion change occurs in the wafer at the same time as the wafer is attracted to the chuck, the thermal expansion (radial expansion) of the wafer is prevented from being hindered by contact with the burrs. This prevents the metal film on the lower surface of the wafer from peeling off, and also prevents the lower surface of the wafer from becoming stuck in recesses such as suction holes. Therefore, when the wafer is returned to the cassette after the functional test, the wafer can be stably peeled off from the upper surface of the chuck.

[0023] Furthermore, because the height of the burrs is sufficiently reduced, the underside of the wafer and the upper surface of the chuck are in intimate contact over the entire surface. This allows the contact resistance between the wafer and the chuck to approach the limit of 0.000 Ω, enabling accurate test results to be obtained by passing current through the wafer using a wafer testing device. The above-described effects are particularly pronounced when the present invention is applied to power devices that use a metal film on the underside of the wafer as an electrode.

[0024] As described above, according to the present invention, the height of the burrs on the upper surface of the chuck can be reduced to a predetermined value or less, or the burrs can be removed, thereby suppressing chip cracks during the dicing process of the wafer, preventing the upper surface of the chuck and the lower surface of the wafer from adhering to each other, and achieving a stable, tight contact state with low contact resistance between the upper surface of the chuck and the lower surface of the wafer, thereby enabling the stable production of high-quality wafers and semiconductor chips.

[0025] [Aspect 2 of the present invention] The surface treatment method for a chuck of a wafer test apparatus according to aspect 1, further comprising a lapping step of lapping the upper surface between the blast polishing step and the electrolytic polishing step.

[0026] In this case, the surface of the chuck roughened by blast polishing can be restored to a flat surface by the lapping process. Although new burrs may be generated on the upper surface of the chuck by the lapping process, according to the present invention, the height of the new burrs can be sufficiently reduced by the electrolytic polishing process and chemical polishing process after the lapping process.

[0027] Here, the new burrs will be explained in detail. In the blast polishing process before the lapping process, the collision of media with the upper surface of the chuck creates a fine uneven shape, and also creates a gentle downward slope (incline) along the blast irradiation angle. When this upper surface of the chuck is subjected to lapping in the lapping process, the uneven shape is removed and a flat surface is recreated, and a boundary line is formed on the upper surface of the chuck between the gentle downward slope and the flat surface. New burrs (low-height convex burrs) may be generated along this boundary line. In the present invention, it is possible to reduce the height of such new burrs to a predetermined size of, for example, 15 μm or less, or to remove them altogether.

[0028] In order to reduce the disadvantage of new burrs being generated on the upper surface of the chuck due to the lapping process, it is preferable to keep the lapping time as short as possible. In order to keep the lapping time to the minimum necessary, it is preferable to cover the upper surface of the chuck except for the outer periphery with masking tape or the like in advance in the blast polishing process before the lapping process, and to keep the processing area to be subjected to blast polishing to the minimum necessary. By shortening the lapping time in this way, it is possible to prevent new burrs from being generated along the boundary line.

[0029] [Embodiment 3 of the present invention] 3. The surface treatment method for a chuck of a wafer testing apparatus according to claim 1, wherein the diameter of the chuck is 8 inches or more, and in the electrolytic polishing step, three or more electrode wirings are connected to the outer periphery of the chuck at intervals in the circumferential direction of the chuck.

[0030] In this case, the size of the chuck is for an 8-inch wafer or a larger 12-inch wafer. When electrolytic polishing is performed on such a large object, the dissolution effect tends to be weaker at points farther away from the electrode.

[0031] Therefore, in the above-described configuration of the present invention, three or more electrode wirings are connected to the outer periphery of the chuck at intervals in the circumferential direction of the chuck, and then the chuck is subjected to an electrolytic polishing process. This makes it less likely that areas of the outer periphery of the chuck will be far from the electrodes, and makes it easier to obtain a uniform dissolution effect throughout the entire outer periphery of the chuck. Therefore, the height of any sharp burrs present on the outer periphery of the chuck can be uniformly reduced by the electrolytic polishing process.

[0032] [Aspect 4 of the present invention] A disk-shaped chuck that is provided in a wafer testing device and holds a wafer by vacuum suction, the chuck having an upper surface on which the wafer is placed and a recess formed by a hole, groove, or step recessed from the upper surface, and the height dimension of any burrs protruding from the upper surface or the recess is 15 μm or less.

[0033] The chuck for a wafer testing device of the present invention is obtained by the above-described surface treatment method for a chuck for a wafer testing device, and with this chuck for a wafer testing device, the height of burrs protruding from the upper surface or recess of the chuck is kept low to 15 μm or less, so that the above-described excellent effects are stably achieved.

[0034] [Embodiment 5 of the present invention] 5. The chuck of claim 4, wherein the upper surface has a vertical height that decreases toward the recess.

[0035] The chuck of the wafer testing device of the present invention undergoes the above-mentioned electrolytic polishing and chemical polishing processes, so that the height dimension of the chuck upper surface around the recessed portion becomes lower as it approaches the recessed portion (a downward gradient is imparted by dissolution). Therefore, even when a wafer is held by suction on the upper surface of the chuck heated to a high temperature, it is possible to more reliably prevent the lower surface of the wafer from becoming stuck between the recessed portion and the chuck. [Effects of the Invention]

[0036] According to the surface treatment method for a chuck of a wafer testing apparatus and the chuck of the wafer testing apparatus of the above aspects of the present invention, the height of burrs on the upper surface of the chuck can be reduced to a predetermined dimension or less, or the burrs can be removed, thereby suppressing chip cracks when the wafer is diced, preventing problems such as the upper surface of the chuck and the lower surface of the wafer becoming stuck together, and achieving a stable, tight contact state with low contact resistance between the upper surface of the chuck and the lower surface of the wafer. [Brief explanation of the drawings]

[0037] [Figure 1] FIG. 1 is a side view (side cross-sectional view) that schematically shows the wafer testing device of this embodiment. [Figure 2] FIG. 2 is a flowchart illustrating a surface treatment method for a chuck of a wafer testing apparatus according to this embodiment. [Figure 3] FIG. 3 is a diagram schematically showing an electrolytic polishing step included in the surface treatment method for a chuck of a wafer test apparatus according to this embodiment. [Figure 4] FIG. 4 is an image showing suction holes (recesses) recessed from the top surface of the chuck, and shows the state before the surface treatment method for the chuck of the wafer testing device of this embodiment is carried out. [Figure 5] FIG. 5 is a cross-sectional view showing the VV cross section of FIG. [Figure 6] FIG. 6 is an image showing suction holes (recesses) recessed from the top surface of the chuck, and shows the state after the surface treatment method for the chuck of the wafer testing device of this embodiment has been carried out. [Figure 7] FIG. 7 is a cross-sectional view showing a cross section taken along line VII-VII in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0038] A wafer testing apparatus 1, a chuck 10 of the wafer testing apparatus 1, and a surface treatment method for the chuck 10 of the wafer testing apparatus 1 according to one embodiment of the present invention will be described with reference to the drawings. The wafer testing apparatus 1 of this embodiment is an apparatus that performs a functional test (electrical test) of semiconductor chips mounted on a semiconductor wafer (wafer) W such as a silicon wafer, and is also called a prober.

[0039] As shown in FIG. 1, the wafer testing device 1 includes a disk-shaped chuck 10 for holding a wafer W, an XY-axis moving means 2, a Z-axis moving means 3, a drain cable 4, a probe card 5, a probe card fixing mechanism 6, a contact spring pin mechanism 7, and an electrical test measuring instrument 8.

[0040] The central axis C of the chuck 10 provided in the wafer testing apparatus 1 extends in the vertical direction. That is, in this embodiment, the direction in which the central axis C of the chuck 10 extends (axial direction) corresponds to the vertical direction. Of a pair of plate surfaces of the chuck 10 facing in the vertical direction, one plate surface facing upward (one axial side) is the upper surface 10a, and the other plate surface facing downward (the other axial side) is the lower surface 10b.

[0041] In this embodiment, the direction perpendicular to the central axis C is called the radial direction. Of the radial directions, the direction approaching the central axis C is called the radially inner direction, and the direction away from the central axis C is called the radially outer direction. The direction going around the central axis C is called the circumferential direction.

[0042] The chuck 10 has a diameter (outer diameter) larger than that of the disk-shaped wafer W. In this embodiment, the diameter of the chuck 10 is 8 inches or larger. That is, the chuck 10 is for an 8-inch wafer or a larger diameter, such as a 12-inch wafer.

[0043] The chuck 10 has a temperature control means (not shown). The temperature control means has at least a heating means. The temperature control means may also have a cooling means. The temperature control means heats (or cools) the chuck 10 to a predetermined temperature and maintains it at the predetermined temperature.

[0044] The chuck 10 also has an upper surface 10a on which the wafer W is placed, and a recess 11 formed by a hole, a groove, or a step recessed from the upper surface 10a.

[0045] 4 and 6, in this embodiment, the recesses 11 are suction holes that open to the upper surface 10a. The suction holes are, for example, circular holes. Although not shown, air suction means such as a vacuum pump is connected to the suction holes (recesses 11) via a flow path in the chuck, piping, etc.

[0046] 1, the wafer W placed on the upper surface 10a of the chuck 10 is sucked and held on the upper surface 10a by air suction (vacuum suction) by air suction means through a recess 11 (not shown in FIG. 1). That is, the chuck 10 holds the wafer W by vacuum suction. The other configurations of the chuck 10 will be described separately later.

[0047] The XY-axis moving means 2 moves the chuck 10 and the wafer W held by the chuck 10 in the plane direction of the XY axes, i.e., in the horizontal plane direction (the direction in which a horizontal plane perpendicular to the up-down direction extends). The Z-axis moving means 3 moves the chuck 10 and the wafer W held by the chuck 10 in the up-down direction. The drain cable 4 is connected to the chuck 10.

[0048] The probe card 5 is placed directly above the wafer W held by the chuck 10. The probe card 5 has a plurality of probes (contact needles) 5a protruding downward from the probe card 5. The plurality of probes 5a are placed facing from above minute terminals of a semiconductor chip provided on the wafer W.

[0049] The probe card fixing mechanism 6 supports the probe card 5 in a fixed state. The probe card 5 is detachably attached to the probe card fixing mechanism 6. A probe card 5 corresponding to a semiconductor chip to be inspected provided on the wafer W is appropriately selected and attached to the probe card fixing mechanism 6.

[0050] The contact spring pin mechanism 7 is disposed above the probe card 5, facing the probe card 5. The contact spring pin mechanism 7 is capable of contacting the probe card 5 from above. This allows the contact spring pin mechanism 7 to be electrically connected to each probe 5a of the probe card 5.

[0051] The electrical test meter 8 is disposed above the contact spring pin mechanism 7. The electrical test meter 8 measures information about the semiconductor chip detected by the probe 5a via the contact spring pin mechanism 7. The electrical test meter 8 has a test head 8a and a performance board 8b provided on the underside of the test head 8a.

[0052] Next, a method for treating the surface of the chuck 10 of the wafer testing device 1 will be described. During the manufacture of the chuck 10, sharp burrs (tall burrs) several tens of micrometers in height are generated on the outer periphery of the upper surface 10a of the chuck 10, which has been machined by cutting, grinding, or the like, and on recesses 11 formed by holes, grooves, or steps recessed from the upper surface 10a. Specifically, burrs B protruding to a height of several tens of micrometers from the upper surface 10a are formed on the opening edges of the suction holes (recesses 11) shown in FIGS. 4 and 5, for example. In the example shown in FIG. 5, the protruding height of the burrs B is approximately 40 to 50 micrometers. In the surface treatment method for the chuck 10 of the wafer testing apparatus 1 of this embodiment, the height of such burrs B is reduced to a predetermined dimension or less, or the burrs B are removed.

[0053] 2, the surface treatment method for the chuck 10 of the wafer testing apparatus 1 (hereinafter sometimes simply referred to as the surface treatment method) includes, in this order, a blast polishing step S1 for blast polishing the outer periphery of the upper surface 10a of the chuck 10, an electrolytic polishing step S3 for electrolytic polishing the chuck 10, and a chemical polishing step S4 for chemical polishing the chuck 10. Furthermore, the surface treatment method of this embodiment includes a lapping step S2 for lapping the upper surface 10a of the chuck 10 between the blast polishing step S1 and the electrolytic polishing step S3.

[0054] In the blast polishing step S1, for example, a blast nozzle inclined at a predetermined angle with respect to the central axis C is arranged opposite to the outer periphery of the upper surface 10a of the chuck 10, and a media having an average particle size of 100 to 1000 μm and made of a metal or plastic sphere or the like is sprayed at a pressure of 6 kgf / cm. 2 The blast polishing treatment is carried out at a spray flow rate of 4000 L / min.

[0055] In the blast polishing step S1, it is preferable to cover the upper surface 10a of the chuck 10 except for the outer periphery with masking tape or the like before spraying the media onto the outer periphery of the upper surface 10a.

[0056] The lapping process S2 is performed, for example, by placing the chuck 10 on a lapping machine having a larger diameter than the chuck 10, pouring an abrasive (lapping agent) containing abrasive grains onto the upper surface 10a, and applying pressure from above and below with a weight of approximately 7 kgf to perform the lapping process.

[0057] As shown in FIG. 3, the electrolytic polishing step S3 is performed by immersing the chuck 10 in a tank containing an electrolytic polishing liquid such as an acidic liquid, connecting an anode to the outer periphery of the chuck 10 using a bolt or the like, connecting a cathode to the tank, and applying a current value of 0.15 A to perform the electrolytic polishing process.

[0058] Specifically, in this embodiment, in the electrolytic polishing step S3, three or more anode cables (electrode wiring) are connected to the outer periphery of the chuck 10 at intervals in the circumferential direction of the chuck 10. In the illustrated example, four anode cables (electrode wiring) are connected to the outer periphery of the chuck 10 at equal intervals in the circumferential direction of the chuck 10.

[0059] The chemical polishing step S4 is performed by, for example, immersing the chuck 10 in a tank containing a chemical polishing liquid such as an acidic liquid, heating the liquid to a temperature of 15 to 25°C, and performing the chemical polishing process for a predetermined processing time while stirring the liquid or oscillating the chuck 10 in the liquid.

[0060] 4 and 5 show an image and a cross-sectional view of the vicinity of the suction holes (recesses 11) on the upper surface 10a of the chuck 10 before the above-described surface treatment method is performed, and Fig. 6 and 7 show an image and a cross-sectional view of the vicinity of the suction holes (recesses 11) on the upper surface 10a of the chuck 10 after the above-described surface treatment method is performed. Note that in the cross-sectional views of Fig. 5 and Fig. 7, the cross-sectional shape inside the suction holes (recesses 11) appears wavy because the depth dimension of the suction holes is large and therefore the cross-sectional shape could not be measured accurately.

[0061] As shown in Figures 4 and 5, before the surface treatment method of this embodiment was carried out, burrs B of several tens of micrometers in height were present on the opening edges of the suction holes. In Figure 4, the particularly dark parts of the opening edges of the suction holes correspond to burrs B. In contrast, as shown in Figures 6 and 7, after the surface treatment method of this embodiment was carried out, burrs B of several tens of micrometers in height were no longer present on the opening edges of the suction holes.

[0062] Specifically, in the chuck 10 of the wafer testing apparatus 1 on which the surface treatment method of this embodiment is performed, the height dimension of burrs protruding from the upper surface 10a or the recessed portion 11 is set to 15 μm or less. Furthermore, by performing the above-described surface treatment method (particularly the electrolytic polishing step S3 and the chemical polishing step S4), the height of the upper surface 10a of the chuck 10 decreases in the vertical direction as it approaches the recessed portion 11, as shown in FIG.

[0063] The surface treatment method for the chuck 10 of the wafer testing apparatus 1 and the chuck 10 of the wafer testing apparatus 1 according to the present embodiment described above provide the following advantageous effects.

[0064] Unlike the present embodiment, physical polishing, such as grinding or lapping, to remove burrs from the chuck upper surface 10a has limitations, making it impossible to remove burrs with heights of 20 μm to several tens of μm. Furthermore, the external dimensions of the chuck 10 are large, with a diameter of approximately 205 mm (periphery length of approximately 644 mm) for an 8-inch wafer and a diameter of approximately 305 mm (periphery length of approximately 958 mm) for a 12-inch wafer. For this reason, physical polishing is prone to variations, bias, and unevenness, making it difficult to achieve uniform polishing across the entire chuck upper surface 10a.

[0065] On the other hand, the surface treatment method for the chuck 10 of the wafer test apparatus 1 of this embodiment includes a blast polishing step S1, an electrolytic polishing step S3, and a chemical polishing step S4 in this order, which provides the following excellent effects.

[0066] When manufacturing the chuck 10, burrs with a large protruding height (burrs with a height of several tens of μm) exist on the chuck upper surface 10a, particularly on the outer periphery. In this embodiment, a blast polishing step S1 is first performed to address such high burrs on the outer periphery of the chuck. This breaks down the high burrs and reduces the burr height to a certain level or less (a target value or less for blast polishing).

[0067] Thereafter, an electrolytic polishing step S3 and a chemical polishing step S4 are carried out in this order, whereby burrs remaining on the chuck upper surface 10a are reduced or removed by dissolution. Specifically, electrolytic polishing has a strong dissolving power and has the property of easily dissolving sharp objects. By utilizing this property, the height of high burrs (sharp burrs) can be further reduced by electrolytic polishing.

[0068] Although chemical polishing has weaker dissolving power than electrolytic polishing, it has excellent uniformity. By utilizing this property, chemical polishing can be performed to uniformly polish the entire area of ​​the chuck 10, including the recesses 11 such as the suction holes, without any variations, bias, or unevenness, thereby reducing the overall height of the burrs on the chuck upper surface 10a.

[0069] In this embodiment, by going through the above steps, the height of the burrs protruding from the chuck upper surface 10a can be reduced to a predetermined height of, for example, 15 μm or less, or the burrs can be removed.

[0070] Therefore, according to this embodiment, it is possible to prevent problems such as damage to the metal film formed on the underside of the wafer W due to contact with burrs caused by the suction pressure when the wafer W is vacuum-sucked to the upper surface 10a of the chuck 10 or the contact pressure when the multiple probes 5a contact the wafer W. As a result, when a frame tape is attached to the underside of the wafer W in a process subsequent to the wafer testing apparatus 1, a completely sealed state can be created between the underside and the tape. Since it is possible to prevent air bubbles from being generated between the underside of the wafer W and the frame tape, it is possible to prevent chip cracks from occurring near the air bubbles when the wafer W is diced into individual semiconductor chips.

[0071] Furthermore, when the wafer W is placed on the upper surface 10a of the chuck 10 heated to a high temperature by the heating means, even if a thermal expansion change occurs in the wafer W at the same time as the wafer W is attracted to the chuck 10, the thermal expansion (radial expansion) of the wafer W is prevented from being hindered by contact with the burrs. This prevents the metal film on the lower surface of the wafer W from peeling off, and also prevents the lower surface of the wafer W from becoming stuck in the recesses 11 such as the suction holes. Therefore, when the wafer W is recovered into a cassette after a functional test, the wafer W can be stably peeled off from the upper surface 10a of the chuck.

[0072] Furthermore, because the height of the burrs is sufficiently reduced, the lower surface of the wafer W and the upper surface 10a of the chuck are in intimate contact over the entire surface. This allows the contact resistance between the wafer W and the chuck 10 to approach the limit of 0.000 Ω, enabling accurate test results to be obtained by passing current through the wafer W using the wafer testing device 1. In particular, when this embodiment is applied to a power device that uses a metal film on the lower surface of the wafer W as an electrode, the above-mentioned effects become even more pronounced.

[0073] As described above, according to this embodiment, the height of the burrs on the chuck upper surface 10a can be reduced to a predetermined dimension or less, or the burrs can be removed, thereby suppressing chip cracks when dicing the wafer W, preventing the chuck upper surface 10a and the lower surface of the wafer W from adhering to each other, and achieving a stable, tight contact state with low contact resistance between the chuck upper surface 10a and the lower surface of the wafer W. This allows for the stable production of high-quality wafers W and semiconductor chips.

[0074] The surface treatment method of this embodiment further includes a lapping step S2 for lapping the chuck upper surface 10a between the blast polishing step S1 and the electrolytic polishing step S3. In this case, the surface of the chuck 10 that has become rough due to the blast polishing can be restored to a flat surface by the lapping step S2. Note that, although new burrs may be generated on the chuck upper surface 10a by the lapping step S2, according to this embodiment, the height dimension of the new burrs can also be sufficiently reduced by the electrolytic polishing step S3 and the chemical polishing step S4 that follow the lapping step S2.

[0075] Here, the new burrs will be explained in detail. In the blast polishing step S1 before the lapping step S2, the collision of media with the chuck upper surface 10a creates a fine uneven shape, and also creates a gentle downward slope (incline) along the blast irradiation angle. When this chuck upper surface 10a is subjected to lapping in the lapping step S2, the uneven shape is removed and a flat surface is recreated, and a boundary line is formed on the chuck upper surface 10a between the gentle downward slope and the flat surface. New burrs (low-height convex burrs) may be generated along this boundary line. In this embodiment, it is possible to reduce the height of such new burrs to a predetermined dimension of, for example, 15 μm or less, or to remove them.

[0076] In order to reduce the disadvantage of new burrs being generated on the chuck upper surface 10a by the lapping step S2, it is preferable to keep the lapping time as short as possible. To keep the lapping time to the minimum necessary, it is preferable to cover the chuck upper surface 10a except for the outer periphery with masking tape or the like in advance in the blast polishing step S1 before the lapping step S2, thereby minimizing the area to be blast polished. By shortening the lapping time in this way, it is possible to prevent new burrs from being generated along the boundary line.

[0077] In this embodiment, the diameter of the chuck 10 is 8 inches or more, and in the electrolytic polishing step S3, three or more electrode wirings are connected to the outer periphery of the chuck 10 at intervals in the circumferential direction of the chuck 10. More preferably, three or more (four in this embodiment) electrode wirings are connected to the outer periphery of the chuck 10 at equal intervals in the circumferential direction of the chuck 10.

[0078] In this case, the size of the chuck 10 is for an 8-inch wafer or a larger 12-inch wafer. When electrolytic polishing is performed on such a large object, the dissolution effect tends to be weaker at locations farther away from the electrode.

[0079] Therefore, in the above configuration of this embodiment, three or more electrode wirings are connected to the outer periphery of the chuck 10 at intervals in the circumferential direction of the chuck 10, and then the electrolytic polishing process is performed on the chuck 10. This makes it less likely that any areas on the outer periphery of the chuck 10 will be far from the electrodes, and also makes it easier to obtain a uniform dissolution effect over the entire outer periphery of the chuck 10. Therefore, the height dimension of any sharp burrs present on the outer periphery of the chuck 10 can be uniformly reduced by the electrolytic polishing step S3.

[0080] In addition, this embodiment is a disk-shaped chuck 10 that is provided in a wafer testing device 1 and holds a wafer W by vacuum suction. The chuck 10 has an upper surface 10a on which the wafer W is placed and a recess 11 formed by a hole, groove, or step recessed from the upper surface 10a, and the height dimension of burrs protruding from the upper surface 10a or the recess 11 is 15 μm or less.

[0081] The chuck 10 of the wafer testing apparatus 1 of this embodiment is obtained by the above-described surface treatment method for the chuck 10 of the wafer testing apparatus 1. According to this chuck 10 of the wafer testing apparatus 1, the height dimension of burrs protruding from the chuck upper surface 10a or the recessed portion 11 is kept low to 15 μm or less, and therefore the above-described excellent effects are stably achieved.

[0082] In this embodiment, the closer the chuck upper surface 10a is to the recess 11, the lower its height in the vertical direction. The chuck 10 of the wafer testing apparatus 1 of this embodiment undergoes the electrolytic polishing step S3 and chemical polishing step S4 described above, so that the height dimension of the chuck upper surface 10a around the recess 11 becomes lower as it approaches the recess 11 (a downward gradient is provided by dissolution). Therefore, even when the wafer W is held by suction on the upper surface 10a of the chuck 10, which has been heated to a high temperature, it is possible to more reliably prevent the lower surface of the wafer W from becoming stuck to the recess 11 (the opening edge of the recess 11).

[0083] The present invention is not limited to the above-described embodiment, and the configuration can be changed within the scope of the present invention, as will be described below.

[0084] In the above-described embodiment, the recesses 11 recessed from the upper surface 10a of the chuck 10 are suction holes (holes), but the present invention is not limited to this. The recesses 11 may be, for example, suction grooves (grooves) recessed from the chuck upper surface 10a. Alternatively, when a TAIKO (registered trademark) wafer is used as the wafer W, a step recessed from the remaining portion of the chuck upper surface 10a may be formed in the outer periphery of the chuck in correspondence with the thick outer periphery of the TAIKO (registered trademark) wafer, and this step may be used as the recess 11.

[0085] The present invention may be combined with the various configurations described in the above-described embodiments and modifications, and may also include additions, omissions, substitutions, and other modifications of the configurations, without departing from the spirit of the present invention. Furthermore, the present invention is not limited to the above-described embodiments, but is limited only by the claims. [Industrial Applicability]

[0086] The surface treatment method for a chuck for a wafer testing device and the chuck for the wafer testing device of the present invention can reduce the height of burrs on the upper surface of the chuck to a predetermined dimension or less, or can remove the burrs, thereby suppressing chip cracks during wafer dicing, preventing adhesion between the upper surface of the chuck and the lower surface of the wafer, and achieving a stable, tight contact state with low contact resistance between the upper surface of the chuck and the lower surface of the wafer. This allows for the stable production of high-quality wafers and semiconductor chips. Therefore, the present invention has industrial applicability. [Explanation of symbols]

[0087] 1...wafer testing device, 10...chuck, 10a...upper surface, 11...recess, B...burr, S1...blast polishing process, S2...lapping process, S3...electrolytic polishing process, S4...chemical polishing process, W...wafer

Claims

1. A surface treatment method for a disk-shaped chuck that is provided in a wafer testing device and holds a wafer by vacuum suction, comprising: The chuck is an upper surface on which the wafer is placed; a recess formed by a hole, a groove, or a step recessed from the upper surface, The surface treatment method for the chuck comprises: a blast polishing step of blast polishing an outer periphery of the upper surface; an electrolytic polishing step of electrolytically polishing the chuck; and a chemical polishing step of chemically polishing the chuck, in this order. A method for treating the surface of a chuck of a wafer test device.

2. A lapping step of lapping the upper surface is further provided between the blast polishing step and the electrolytic polishing step.

2. The method for treating the surface of a chuck of a wafer testing device according to claim 1.

3. The chuck has a diameter of 8 inches or more, In the electrolytic polishing step, three or more electrode wirings are connected to the outer periphery of the chuck at intervals in the circumferential direction of the chuck.

3. A surface treatment method for a chuck of a wafer testing device according to claim 1.

4. A disk-shaped chuck that is provided in a wafer testing device and holds a wafer by vacuum suction, The chuck is an upper surface on which the wafer is placed; a recess formed by a hole, a groove, or a step recessed from the upper surface, The height dimension of a burr protruding from the upper surface or the recess is 15 μm or less. Wafer test equipment chuck.

5. The upper surface has a height in the vertical direction that decreases as it approaches the recessed portion.

5. The chuck of claim 4 for a wafer testing apparatus.

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