Compound oxide semiconductor

Abstract

To improve the field effect mobility and the reliability in a transistor having an oxide semiconductor film.SOLUTION: The following oxide semiconductor is used for a semiconductor layer of a transistor. The oxide semiconductor is a compound oxide semiconductor in which a first region and a second region are mixed. The first region has a plurality of first clusters mainly containing one or more selected from indium, zinc, and oxygen. The second region includes a plurality of second clusters mainly containing one or more selected from indium, an element M (M is Al, Ga, Y, or Sn), zinc, and oxygen. The first region has a part where the plurality of first clusters are connected together and the second region has a part where the plurality of second clusters are connected together.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device. Regarding the device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention relates to semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, and the like. The present invention relates to a driving method for the above-mentioned or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] A transistor (field-effect transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology that makes up the field-effect transistor (FET) or thin-film transistor (TFT) is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in electronic devices. Silicon is a semiconductor thin film that can be used in transistors. Semiconductor materials, such as silicon, are widely known, but oxide semiconductors are also attracting attention. It is being watched.

[0005] In addition, a plurality of oxide semiconductor layers are stacked, and a channel and a gate electrode are formed in the plurality of oxide semiconductor layers. The oxide semiconductor layer contains indium and gallium, and the ratio of indium is adjusted to gallium. By increasing the ratio of A semiconductor device that has improved the performance (see Patent Document 1) has been disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-7399 Summary of the Invention [Problem to be solved by the invention]

[0007] As a transistor using an oxide semiconductor film for the channel region, it has high field-effect mobility. However, increasing the field effect mobility of a transistor However, there is a problem that the characteristics of the transistor tend to become normally-on. This means that a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode. It is a state in which one becomes disoriented.

[0008] In addition, in a transistor using an oxide semiconductor film for a channel region, The oxygen vacancies formed in the semiconductor layer are problematic because they affect transistor characteristics. When oxygen vacancies are formed in the oxide semiconductor film, hydrogen bonds to the oxygen vacancies to supply carriers. When a carrier supply source is generated in the oxide semiconductor film, This causes a change in the electrical characteristics of the transistor, typically a shift in the threshold voltage.

[0009] For example, if there are too many oxygen vacancies in the oxide semiconductor film, the threshold voltage of the transistor may be increased. Therefore, the oxide semiconductor film is shifted to the negative side, resulting in a normally-on characteristic. In particular, in the channel region, there is little oxygen vacancy or the device has normally-on characteristics. It is preferable that the amount of oxygen deficiency is such that it does not cause any damage.

[0010] In view of the above problems, one embodiment of the present invention provides a transistor including an oxide semiconductor film, One of the objectives is to improve the field effect mobility and the reliability. One embodiment of the present invention is to prevent fluctuations in electrical characteristics of a transistor including an oxide semiconductor film. Another object of the present invention is to suppress the occurrence of such a problem and to improve reliability. Another object of the present invention is to provide a semiconductor device with reduced power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device. An object of one embodiment is to provide a novel display device.

[0011] The above description of the problem does not preclude the existence of other problems. The embodiment does not necessarily have to solve all of these problems. Problems other than those mentioned above can be solved by the specification. It is clear from the description of the specification, etc. that the problems other than those mentioned above cannot be extracted from the description of the specification, etc. It is possible to issue it. [Means for solving the problem]

[0012] One embodiment of the present invention is a composite oxide semiconductor in which a first region and a second region are mixed. The first region is selected from the group consisting of indium (In), zinc (Zn), and oxygen (O). The second region has a plurality of first clusters each having one or more of the above as a main component. is selected from indium, element M (where M is Al, Ga, Y, or Sn), zinc, and oxygen. The first cluster has a plurality of second clusters each having one or more of the selected components as a principal component. The region has a portion where a plurality of first clusters are connected to each other, and the second region has a portion where a plurality of second clusters are connected to each other. The clusters are characterized by having portions that are connected to each other.

[0013] In the above, the first region is preferably surrounded by the second region. It's nice.

[0014] In the above, the first cluster has higher conductivity than the second cluster, and the second The clusters are preferably more semiconducting than the first clusters.

[0015] In addition, the size of the first cluster in the complex oxide semiconductor is 0.5 nm or more and 1.5 nm or less. It is preferred to have a portion that is m or less.

[0016] In the above, the atomic ratio of In, element M, and Zn is In:M:Zn=4:2. : When In is 4, the element M is 1.5 or more and 2.5 or less, and Zn is 2 It is preferable that the number is 4 or less.

[0017] Alternatively, in the above, the atomic ratio of In, element M, and Zn is In:M:Zn=5: When In is 5, the element M is 0.5 or more and 1.5 or less, and Zn is It is preferable that the number is 5 or more and 7 or less.

[0018] Another embodiment of the present invention is a semiconductor device including a semiconductor layer, a gate, and a gate insulating layer. The semiconductor layer comprises any one of the composite oxide semiconductors described above. At this time, the gate voltage is greater than 0V and less than 10V, and the drain voltage is greater than 0V and less than 10V. In the range of 20 V or less, the maximum field-effect mobility is 100 cm 2 / Vs or more 200c m 2 It is preferable that the value is equal to or less than / Vs.

[0019] Another embodiment of the present invention is a method for manufacturing a complex oxide semiconductor, the method including: placing a substrate in a deposition chamber; a first step of introducing either argon gas or oxygen gas or both into the film-forming chamber; a second step of introducing indium, an element M (where M is Al, Ga, Y, or Sn), zinc, and a third step of applying a voltage to the target having oxygen. and a fourth step of depositing a compound oxide semiconductor. The first step involves preferential sputtering of elements M and zinc from the target, and the second step involves sputtering of indium. After the indium becomes clustered, the clustered indium is sputtered from the target. and a second step of:

[0020] Another embodiment of the present invention is a method for manufacturing a complex oxide semiconductor, the method including: a first step of disposing a film forming chamber in a deposition gas atmosphere containing argon gas and not containing oxygen gas; a second step of introducing indium, an element M (where M is Al, Ga, Y, or Sn), and zinc; a third step of applying a voltage to a target having lead and oxygen; and and a fourth step of depositing a complex oxide semiconductor on the substrate. The first step involves preferential sputtering of the elements M and zinc from the target; After the indium becomes clustered, the clustered indium is sputtered from the target. and a second step in which the second step is performed.

[0021] In the above-described manufacturing method, it is preferable that the substrate is not intentionally heated. stomach.

[0022] Another embodiment of the present invention is a display device including any of the above semiconductor devices and a display element. Another embodiment of the present invention is a display module including the display device and a touch sensor. Another aspect of the present invention is a semiconductor device according to any one of the above aspects. a display device or a display module, and an operation key or a battery. It is an electronic device. [Effects of the Invention]

[0023] According to one embodiment of the present invention, a field-effect transfer The accuracy and reliability can be improved. In a transistor including an oxide semiconductor film, fluctuation in electrical characteristics can be suppressed and signal quality can be improved. Further, according to one embodiment of the present invention, power consumption can be reduced. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a novel display device can be provided. This can be done.

[0024] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. can be extracted from descriptions in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0025] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a complex oxide semiconductor. [Figure 2] 1A and 1B are diagrams illustrating atomic ratios of oxide semiconductors. [Figure 3] 1A and 1B are a top view and a cross-sectional view illustrating a complex oxide semiconductor. [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating a complex oxide semiconductor. [Figure 5] 1A and 1B are a top view and a cross-sectional view illustrating a complex oxide semiconductor. [Figure 6] 1A and 1B are a top view and a cross-sectional view illustrating a complex oxide semiconductor. [Figure 7] FIG. 1 is a diagram illustrating a sputtering apparatus. [Figure 8] FIG. 1 is a process flow diagram illustrating a method for manufacturing a complex oxide semiconductor. [Figure 9] FIG. 2 is a diagram illustrating a cross section near a target. [Figure 10] FIG. 1 is a diagram illustrating an analysis method. [Figure 11] 1A and 1B are diagrams illustrating SEM observation results and EDX mapping. [Figure 12] 1A and 1B are diagrams illustrating SEM observation results and EDX mapping. [Figure 13] FIG. 1 is a diagram illustrating the composition of a sample. [Figure 14] FIG. 1 is a diagram illustrating the composition of a sample. [Figure 15] 1A and 1B are diagrams illustrating SEM observation results and EDX mapping. [Figure 16] 1A and 1B are diagrams illustrating SEM observation results and EDX mapping. [Figure 17] 1A and 1B are diagrams illustrating SEM observation results and EDX mapping. [Figure 18] 1A and 1B are diagrams illustrating SEM observation results and EDX mapping. [Figure 19] 1A and 1B are diagrams illustrating SEM observation results and EDX mapping. [Figure 20] 1A and 1B are diagrams illustrating SEM observation results and EDX mapping. [Figure 21] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 22] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 23] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 24] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 25] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 26] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 27] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 28] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 29] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 30] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 31] FIG. 1 is a diagram illustrating a band structure. [Figure 32] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 33] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 34] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 35] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 36] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 37] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 38] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 39] FIG. 1 is a top view illustrating one embodiment of a display device. [Figure 40] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 41] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 42] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 43] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 44] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 45] 1A to 1C are cross-sectional views illustrating a method for forming an EL layer. [Figure 46] FIG. 1 is a conceptual diagram illustrating a droplet ejection device. [Figure 47] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Figure 48] FIG. 2 is a diagram illustrating a display module. [Figure 49] 1A to 1C illustrate electronic devices. [Figure 50] 1A to 1C illustrate electronic devices. [Figure 51] FIG. 1 is a perspective view illustrating a display device. [Figure 52] Planar HAADF-STEM image and EDX mapping. [Figure 53] Cross-sectional HAADF-STEM image and EDX mapping. [Figure 54] XRD analysis results. [Figure 55] FIG. 10 is a graph showing Id-Vg characteristics of a transistor. [Figure 56] FIG. 10 is a graph showing Id-Vg characteristics of a transistor. [Figure 57] 1A and 1B illustrate cross-sectional STEM images of a transistor. DETAILED DESCRIPTION OF THE INVENTION

[0026] Hereinafter, embodiments will be described with reference to the drawings. It is understood that the present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily apparent to those skilled in the art that various modifications may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0027] Also, in the drawings, the size, thickness of layers, or areas are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown. The drawings are merely schematic illustrations and are not limited to the shapes or values ​​shown in the drawings.

[0028] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the number of components. It should be noted that this is added to avoid confusion and is not intended to limit the number.

[0029] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used to indicate the position of components. The positional relationship is used for convenience in describing the structure with reference to the drawings. The relationship between the two components changes depending on the direction in which each component is depicted. The terms are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0030] In this specification, a transistor includes a gate, a drain, and a source. It is an element having at least three terminals including a drain (drain terminal, drain Between the drain electrode and the source terminal It has a channel region in the middle, and current flows between the source and drain through the channel region. In this specification and the like, the channel region is a region through which a current mainly flows. This refers to the area where the fluid flows.

[0031] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. do.

[0032] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "of" is not subject to any particular restrictions as long as it allows the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. It has various functions such as switching elements, resistors, inductors, capacitors, etc. This includes elements such as:

[0033] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes cases where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0034] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer" It may be possible to change the term to

[0035] Unless otherwise specified, in this specification and the like, the off-state current refers to the current that flows when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also known as a cut-off state). Unless otherwise specified, for an n-channel transistor, the voltage V between the gate and source When gs is lower than the threshold voltage Vth, the gate and This refers to the state in which the voltage Vgs between the n-channel and n-channel transistors is higher than the threshold voltage Vth. The off-state current of a transistor is the voltage between the gate and source, Vgs, that is, the threshold voltage, Vt It may refer to the drain current when it is lower than h.

[0036] The off-state current of a transistor may depend on Vgs. The off-state current is I or less if there is a Vgs value at which the off-state current of the transistor is I or less. The off-state current of a transistor is the current that flows through it in the off state at a given Vgs. , an off-state at Vgs within a predetermined range or a sufficiently reduced off-current is obtained. It may refer to the off-state current at Vgs.

[0037] As an example, when the threshold voltage Vth is 0.5V and Vgs is 0.5V, The on-current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 -1 3 A, and the drain current at Vgs = -0.5 V is 1 × 10 -19 A and Vg The drain current at s = -0.8V is 1×10 -22 A n-channel transistor The drain current of the transistor is as follows when Vgs is -0.5V: , or 1×10 when Vgs is in the range of -0.5V to -0.8V -19 A or below Therefore, the off-state current of the transistor is 1×10 -19 It may be said that it is below A. The drain current of the transistor is 1×10 -22 A or less Vgs exists. Therefore, the off-state current of the transistor is 1×10 -22 It may be said that it is below A.

[0038] In this specification and the like, the off-state current of a transistor having a channel width W is calculated based on the It is sometimes expressed as the current value that flows per watt. In the latter case, the unit of the off-state current is current / length. It may be expressed in units with an element (e.g., A / μm).

[0039] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the values ​​are measured at room temperature, 60°C, 85°C, 95°C, or 125°C. It may also represent the current that is generated when the reliability of a semiconductor device that includes the transistor is guaranteed. or the temperature at which a semiconductor device containing the transistor is used (e.g. For example, the off-state current at any temperature between 5°C and 35°C. The off-state current of the transistor is I or less at room temperature, 60°C, 85°C, 95°C, 125°C, The temperature at which the reliability of a semiconductor device including the transistor is guaranteed, or The temperature at which the semiconductor device containing the transistor is used (for example, between 5°C and 35°C) There exists a value of Vgs at which the off-state current of the transistor is I or less at It may refer to:

[0040] The off-state current of a transistor can depend on the voltage Vds between the drain and source In this specification, unless otherwise specified, the off-state current is measured when Vds is 0.1 V, 0.8 V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or In some cases, the value represents the off-state current at 20 V. Alternatively, the value represents the off-state current of the semiconductor containing the transistor. Vds that guarantees the reliability of semiconductor devices, or semiconductor devices that include the transistor The off-state current of a transistor at Vds is sometimes used in The current is I or less when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, transistors included Vds that guarantees the reliability of the semiconductor device, etc. that contains the transistor, or The off-state current of a transistor at Vds used in semiconductor devices is I or less. It may refer to the existence of a Vgs value.

[0041] In the above description of the off-state current, the drain may be read as the source. Current may also refer to the current through the source when the transistor is in the off state.

[0042] In this specification and the like, the term "leak current" may be used to mean the same thing as "off-state current." In this specification, the off-state current is, for example, the current when a transistor is in an off state. , may refer to the current flowing between the source and drain.

[0043] In this specification, the threshold voltage of a transistor is the voltage at which a channel is formed in the transistor. This refers to the gate voltage (Vg) when a gate electrode is formed. Specifically, it refers to the threshold voltage of a transistor. The voltage is plotted by plotting the gate voltage (Vg) on ​​the horizontal axis and the square root of the drain current (Id) on the vertical axis. In the simulated curve (Vg-√Id characteristics), the tangent line with the maximum slope is extrapolated to form a straight line. , the gate voltage (Vg Alternatively, the threshold voltage of a transistor can be expressed as the channel length L and the The channel width is W, and the value of Id[A]×L[μm] / W[μm] is 1×10 -9 [A] It may also refer to the gate voltage (Vg) applied to the device.

[0044] In addition, even when the term "semiconductor" is used in this specification, for example, a material having electrical conductivity is also included. If the dielectric constant is low enough, it may have the properties of an "insulator." The boundary between "insulator" and "insulator" is vague and it may not be possible to strictly distinguish them. The term "semiconductor" in the above may be replaced with "insulator." The term "insulator" in the specification etc. may be replaced with "semiconductor." In some cases, the term "insulator" used in this specification can be rephrased as "semi-insulator." .

[0045] In addition, even when the term "semiconductor" is used in this specification, for example, a material having electrical conductivity is also included. If the electrical conductivity is sufficiently high, it may have the properties of a "conductor." The boundary between "conductor" and "electroconductor" is vague and it may not be possible to strictly distinguish them. The term "semiconductor" in the above may be replaced with "conductor." The term "conductor" in the specification etc. may be replaced with "semiconductor" in some cases.

[0046] In this specification, impurities in semiconductors refer to substances other than the main components that make up the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent are impurities. The formation of DOS (Density of States) in semiconductors and the The semiconductor may have poor mobility or poor crystallinity. In the case of a nitride semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements. These include elements of Group 2, Group 14, Group 15, and transition metals other than the main component. , hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen In the case of oxide semiconductors, oxygen vacancies can be created by the inclusion of impurities such as hydrogen. In addition, when the semiconductor contains silicon, the properties of the semiconductor are changed. The impurities include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements, etc.

[0047] (Embodiment 1) In this embodiment, an oxide semiconductor including a complex oxide semiconductor according to one embodiment of the present invention is used. A film and a semiconductor device using the film will be described.

[0048] <1-1. Oxide semiconductor film>

[0049] The oxide semiconductor film preferably contains at least indium. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. It is preferable that the material contains boron, silicon, titanium, or the like. , iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium One selected from zinc, hafnium, tantalum, tungsten, or magnesium Or, multiple types may be included.

[0050] Here, the case where the oxide semiconductor film contains indium, the element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, etc. Applicable elements for element M include boron, silicon, titanium, iron, nickel, and germanium. Smoke, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum However, the element M can be any of the above elements. Note that indium, the element M, and nitrogen contained in the oxide semiconductor film can be combined. The respective terms of the atomic ratio of lead are [In], [M], and [Zn].

[0051] <1-2. Structure of oxide semiconductor film> FIG. 1 shows a conceptual diagram of an oxide semiconductor film including a complex oxide semiconductor according to one embodiment of the present invention. .

[0052] FIG. 1A is a conceptual diagram of a top surface (here, referred to as the ab-plane direction) of an oxide semiconductor film. FIG. 1B shows a cross section (here, the c-axis direction) of an oxide semiconductor film formed on a substrate Sub. This is a conceptual diagram of the direction of rotation.

[0053] Although FIG. 1 illustrates a case where an oxide semiconductor film is formed on a substrate, , but is not limited to, an insulating film such as an underlayer film or an interlayer film between the substrate and the oxide semiconductor film; Alternatively, other semiconductor films such as an oxide semiconductor film may be formed.

[0054] As shown in FIGS. 1A and 1B, the oxide semiconductor film of one embodiment of the present invention has a region A1 and region B1 are mixed to form a composite oxide semiconductor. In the following description, the oxide semiconductor film may be referred to as a composite oxide semiconductor. .

[0055] The region A1 shown in Figure 1(A)(B) is [In]:[M]:[Zn]=x:y:z (x> 0, y ≥ 0, z ≥ 0). On the other hand, region B1 is a region where [In]:[M This is the region where there is little In such that ]:[Zn]=a:b:c (a>0, b>0, c>0).

[0056] In this specification, the atomic ratio of In to element M in region A1 is The atomic ratio of In to M in region A1 is larger than that in region B1. Therefore, in this specification, the region A1 is referred to as an in-rich region. The area B1 is also called an in-poor area.

[0057] For example, the concentration of In in the region A1 is 1.1 times or more, preferably 2 times or more, than that in the region B1. The region A1 is preferably an oxide containing at least In. However, the elements M and Zn do not necessarily have to be included.

[0058] Here, the atomic ratio of elements contained in the complex oxide semiconductor of one embodiment of the present invention will be described. .

[0059] In the composite oxide semiconductor, for example, the region A1 has In, the element M, and Zn. In this case, the atomic ratio of each element can be shown using the phase diagram shown in Figure 2. The atomic ratio of Zn and Zn is expressed as x:y:z, where x, y, and z are the atomic numbers. The ratio can be expressed in the diagram as coordinates (x:y:z). The ratio is not stated.

[0060] In Figure 2, the dashed line indicates the relationship between [In]:[M]:[Zn]=(1+α):(1-α):1. The line where the atomic ratio (-1≦α≦1) is [In]:[M]:[Zn]=(1+α):( The line where the atomic ratio is 1-α):2, [In]:[M]:[Zn]=(1+α):(1 -α):3 atomic ratio line, [In]:[M]:[Zn]=(1+α):(1- α):4 atomic ratio line, and [In]:[M]:[Zn]=(1+α):( This represents the line where the atomic ratio is 1-α):5.

[0061] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=1:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=1:2:β, the line where [In ]:[M]:[Zn]=1:3:β, the atomic ratio is [In]:[M]:[Zn ]=1:4:β, and the atomic ratio of [In]:[M]:[Zn]=1:7:β. The line where the atomic ratio is [In]:[M]:[Zn]=2:1:β , and the line where the atomic ratio is [In]:[M]:[Zn]=5:1:β.

[0062] In addition, as shown in FIG. 2, the atomic ratio of [In]:[M]:[Zn]=0:2:1 or close to it Oxide semiconductors tend to have a spinel-type crystal structure.

[0063] The region A2 shown in FIG. 2 is a region having a ratio of the number of atoms of indium, element M, and zinc in the region A1. The figure shows an example of a preferred range. Note that the region A2 is [In]:[M]:[Zn ]=(1+γ):0:(1-γ) atomic ratio (-1≦γ≦1) Let's say.

[0064] The region B2 shown in FIG. 2 is a region where the atomic ratio of indium, element M, and zinc contained in the region B1 is This shows an example of a preferred range. ]=4:2:3 to 4.1 and its neighboring values. The neighboring values ​​include, for example, the atomic ratio [In]:[M]:[Zn]=5:3:4. Region B2 contains [In]:[ M]:[Zn]=5:1:6 and its neighboring values.

[0065] Since the concentration of In is high in the region A2, the conductivity is higher than that in the region B2. It has the function of increasing the carrier mobility (or the field-effect mobility of the transistor). Therefore, the on-state current and the carry current of the transistor including the oxide semiconductor film having the region A1 are The carrier mobility can be increased.

[0066] On the other hand, the region B2 has a lower In concentration and is therefore less conductive than the region A2. Therefore, the region B1 has a function of reducing the leakage current of the film or transistor. The off-state current of a transistor including such an oxide semiconductor film can be reduced.

[0067] In the oxide semiconductor film of one embodiment of the present invention, the region A1 and the region B1 form a complex. In other words, in region A1, carrier movement is likely to occur, and in region B1, carrier Therefore, the oxide semiconductor of one embodiment of the present invention has high carrier mobility. Moreover, it can be used as a material with high switching characteristics and excellent semiconductor characteristics.

[0068] In other words, the region A1 is a region that is less semiconductive and more conductive than the region B1. On the other hand, the region B1 has a higher semiconductivity than the region A1 and is also conductive. Here, the high semiconductivity means that the band gap This can be rephrased as having a wide band, good switching characteristics, and being similar to an i-type semiconductor.

[0069] As an example, as shown in FIGS. 1A and 1B, the region A1 is oriented in the ab plane direction and In the c-axis direction, multiple granular clusters exist. The clusters may be distributed evenly in a regular pattern. In addition, multiple clusters may be overlapped or connected. For example, one cluster may overlap with another cluster, The area A1 may be observed to spread out like a cloud.

[0070] In other words, the clusters in area A1 are half as dense as the clusters in area B1. It can be said that the conductor is low and the conductivity is high. The clusters in region A1 are regions that are more semiconductive and less conductive than the clusters in region A1. It can also be said that...

[0071] In other words, the complex oxide semiconductor of one embodiment of the present invention has a first region having a high concentration of In and a second region having a high concentration of I n has a second region where the concentration is low, and the first region and the second region are connected in a cloud-like shape. Alternatively, in the complex oxide semiconductor according to one embodiment of the present invention, In is distributed at a high concentration. The semiconductor device has a first region and a second region in which In is not distributed at a high concentration. The two areas are connected in a cloud-like fashion.

[0072] As shown in Figures 1(A) and 1(B), the regions A1 are connected to each other in the ab-plane direction, forming a region The region A1 can be a current path, which can increase the conductivity of the oxide semiconductor film. This can increase the field effect mobility of a transistor using this.

[0073] Moreover, it can be said that the regions B1 shown in FIGS. 1(A) and 1(B) are scattered within the region A1. Therefore, the region B1 can exist in a state where it is sandwiched between the regions A1. , the region B1 can exist in a state surrounded by the region A1. This is the structure contained in 1.

[0074] Moreover, the region B1 has a cluster different from the cluster (also called the first cluster) that the region A1 has. This can also be seen as a configuration with a raster (also called a second cluster). The region B1 has a plurality of second clusters, and the plurality of second clusters are connected to each other. In other words, the first cluster in the region A1 has a portion that is different from other first clusters. The second cluster in the area B1 is connected to the other second clusters. It has clusters of these and parts that are connected to each other in a cloud-like manner.

[0075] The proportion of the scattered regions A1 varies depending on the manufacturing conditions or composition of the composite oxide semiconductor. For example, a composite oxide semiconductor having a small proportion of the region A1, or A complex oxide semiconductor having a high proportion of the region A1 can be formed. In a composite oxide semiconductor, the ratio of region A1 to region B1 is not necessarily small. In the case of a complex oxide semiconductor in which the ratio of In addition, for example, the size of the granular area formed by the area A1 may be can be appropriately adjusted by the preparation conditions or composition of the composite oxide semiconductor.

[0076] In Figures 3(A)(B), the proportion of area A1 is smaller than that in Figures 1(A)(B), and the proportion of area B is This indicates a complex oxide semiconductor with a high proportion of 1.

[0077] In addition, in Fig. 4(A)(B), the proportion of area A1 is smaller than that in Fig. 3(A)(B), and the proportion of area A2 is smaller than that in Fig. 3(A)(B). The composite oxide semiconductor shown in Figure 4 has a high proportion of B1. As shown, there may be included first clusters that are interspersed without overlapping.

[0078] Depending on the manufacturing conditions or composition of the composite oxide semiconductor, the region A is more favorable than the region B shown in Fig. 1(A)(B). It is also possible to form a composite oxide semiconductor in which the proportion of region 1 is high and the proportion of region B1 is low.

[0079] Here, when all the regions A1 are connected in the ab plane direction, the switching of the transistor The characteristics may deteriorate. For example, the off-state current of the transistor may increase. Therefore, as shown in Figures 3(A)(B) and 4(A)(B), the area A1 is the area B1 Therefore, the area A1 is sandwiched between the areas B1. In other words, the region A1 can exist in a state where it is surrounded by the region B1. In other words, the region A1 is contained in the region B1. This improves the switching characteristics of the transistor, particularly reducing the off-state current.

[0080] In addition, there are cases where a clear boundary between area A1 and area B1 cannot be observed. The sizes of the regions 1 and B1 were measured by energy dispersive X-ray spectroscopy (EDX). EDX mapping using spersive X-ray spectroscopy For example, the cluster in area A1 can be evaluated by a cross-sectional photograph or a planar photograph. In true EDX mapping, cluster diameters between 0.1 nm and 2.5 nm were observed. Preferably, the diameter of the cluster is 0.5 nm or more and 1.5 nm or less. do.

[0081] In this manner, the oxide semiconductor of one embodiment of the present invention has a mixed structure of the region A1 and the region B1. a composite oxide semiconductor, and the functions of the region A1 and the region B1 are different from each other; The region A1 and the region B1 function complementary to each other. For example, in the In-Ga In the case of IGZO, the oxide semiconductor of one embodiment of the present invention is It can be called complementary IGZO (abbreviated as C / IGZO).

[0082] On the other hand, for example, in the case where the region A1 and the region B1 are laminated in layers, Since there is no interaction or interaction is unlikely to occur between A1 and B1, the function of A1 is The functions of area A1 and area B1 may function independently. Even if the carrier mobility can be increased, the off-state current of the transistor will be high. Therefore, by using the above-mentioned composite oxide semiconductor or C / IGZO, It has both high carrier mobility and good switching characteristics. This is an excellent effect obtained from the complex oxide semiconductor of one embodiment of the present invention. be.

[0083] When an oxide semiconductor is deposited using a sputtering device, the atomic ratio of the target In particular, depending on the substrate temperature during film formation, the ratio of the number of atoms in [Zn] may be different. In some cases, the atomic ratio of the film may be smaller than the atomic ratio of the target.

[0084] Furthermore, the characteristics of the complex oxide semiconductor of one embodiment of the present invention are uniquely defined by the atomic ratio. Therefore, the illustrated region is a region A1 and a region B This is a region showing a preferable atomic ratio of 1, and the boundaries are not strict.

[0085] Here, the region B1 may be a region having crystallinity. More preferably, the region B1 may be a region having crystallinity. AAC-OS(c-axis aligned crystalline oxide The CAAC-OS may have a c-axis orientation. The nanocrystals are connected in the ab-plane direction, and have a distorted crystal structure. The distortion is caused by the fact that the CAAC-OS has regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement. This refers to the area where the orientation of the lattice array changes between the area and the area.

[0086] In FIG. 5(A), a plurality of nanocrystals contained in region B1 are shown schematically by dashed lines. Nanocrystals are basically hexagonal, but they are not limited to regular hexagonal shapes and may be non-regular hexagonal. In addition, in the strained portion, there are cases where polygonal nanocrystals such as pentagons and heptagons are present. There is a match.

[0087] In addition, in CAAC-OS, clear grain boundaries were confirmed even near the strained portion. In other words, the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because the oxygen atoms in the CAAC-OS are densely arranged in the ab-plane direction. The lack of density and the change in bond distance between atoms due to the substitution of metal elements This is thought to be because the distortion can be tolerated.

[0088] In addition, Figure 5(B) shows that the nanocrystals have a c-axis orientation, forming a film with a CAAC-OS c-axis. The direction of the slit is generally perpendicular to the surface on which the slit is formed (also called the surface on which the slit is formed) or the upper surface. CAAC-OS has a layered crystal structure (also called a layered structure) with a c-axis orientation. A layer containing indium and oxygen (hereinafter referred to as the In layer) and a layer containing elements M, zinc, and The (M,Zn) layer has a laminated structure in which a layer containing M and an oxygen-containing layer (hereinafter referred to as an (M,Zn) layer) is stacked.

[0089] Indium and element M may be substituted for each other. Therefore, the (M, Zn) layer A part of the element M is replaced with indium, and it can also be expressed as an (In, M, Zn) layer. In this case, a layered structure is formed in which an In layer and an (In, M, Zn) layer are stacked.

[0090] In addition, in Figures 6(A) and (B), the proportion of area A1 is smaller than in Figures 5(A) and (B). 10 shows an example in which the proportion of the area B1 is large.

[0091] Oxide semiconductors have various structures and each structure has various characteristics. The oxide semiconductors are classified into amorphous oxide semiconductors, polycrystalline oxide semiconductors, and a-like oxide semiconductors, which will be described later. Composite oxides containing two or more of OS, nc-OS (described later), and CAAC-OS (described later). The region A1 and the region B1 may have different crystallinity. good.

[0092] For example, it is preferable that the region A1 is non-single crystalline. In this case, when the region A1 is indium, it tends to be tetragonal. In the case of indium oxide ([In]:[M]:[Zn]=x:0:0(x>0)), The region A1 tends to have a rxbyite-type crystal structure. In the case of [n]:[M]:[Zn]=x:0:z (x>0, z>0), a layered crystal structure There is a tendency for this to happen.

[0093] For example, the region B1 is preferably non-single crystal. However, the region B1 does not necessarily have to consist of only the CAAC-OS. In addition, the insulating film may have regions of a polycrystalline oxide semiconductor, an nc-OS, or the like.

[0094] CAAC-OS is an oxide semiconductor with high crystallinity. Since it is not possible to confirm the grain boundaries, the decrease in electron mobility caused by the grain boundaries occurs. In addition, the crystallinity of oxide semiconductors can be affected by impurities and defects. Therefore, CAAC-OS is an oxidized material with few impurities and defects (such as oxygen vacancies). Therefore, the presence of CAAC-OS allows it to function as a composite oxide semiconductor. To provide a composite oxide semiconductor that is heat-resistant and highly reliable because the physical properties of can be done.

[0095] <1-3. Transistor having an oxide semiconductor film> Next, the case where the above oxide semiconductor film is used for a transistor will be described.

[0096] By using the above complex oxide semiconductor in a transistor, the carrier mobility is high, Furthermore, a transistor with high switching characteristics can be realized. Therefore, a low-power transistor can be realized.

[0097] In addition, an oxide semiconductor film with low carrier density is preferably used for the transistor. For example, an oxide semiconductor film has a carrier density of 8×10 11 / cm 3 Less than 1 x10 11 / cm3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all there is to it.

[0098] In the case of reducing the carrier density of the oxide semiconductor film, impurities in the oxide semiconductor film In this specification and the like, the impurity concentration is low, and the defect level density is low. A low density of defect states is called high purity intrinsic or substantially high purity intrinsic. Since a highly purified or substantially intrinsic oxide semiconductor film has few carrier generation sources, In addition, the oxide can be made of high-purity intrinsic or substantially high-purity intrinsic material. Since the defect state density of a compound semiconductor film is low, the trap state density may also be low.

[0099] In addition, the time required for the charges trapped in the trap states of the oxide semiconductor film to disappear is Therefore, the trap level density Transistors in which the channel region is formed in a high-temperature oxide semiconductor have unstable electrical characteristics. There are cases where this happens.

[0100] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor film is In addition, in order to reduce the impurity concentration in the oxide semiconductor film, It is preferable to reduce the impurity concentration in the adjacent film. , alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0101] Here, the influence of each impurity in the oxide semiconductor film will be described.

[0102] When silicon or carbon, which is one of the group 14 elements, is contained in an oxide semiconductor film, Defect levels are formed in the oxide semiconductor. The carbon concentration and the silicon and carbon concentrations near the interface with the oxide semiconductor (Secondary Ion Mass Spectroscopy) Secondary Ion Mass Spectrometry (SIMS) The concentration obtained by 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0103] Furthermore, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor film, a defect level Therefore, alkali metal or alkaline earth metal A transistor using an oxide semiconductor film containing metals tends to be normally on. Therefore, it is necessary to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film. Specifically, it is preferable to use an alkali metal in the oxide semiconductor film obtained by SIMS. The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 The following applies.

[0104] Furthermore, when nitrogen is contained in the oxide semiconductor film, electrons that serve as carriers are generated, and As a result, oxide semiconductors containing nitrogen are easily converted into n-type semiconductors. Therefore, the transistors used in the oxide semiconductor are likely to be normally on. In the present invention, it is preferable that the nitrogen content is reduced as much as possible. For example, the nitrogen content in the oxide semiconductor is The element concentration is 5×10 19 atoms / cm 3 Less than 5x1 0 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 below, More preferably, 5 × 10 17 atoms / cm 3 The following applies.

[0105] In addition, hydrogen contained in the oxide semiconductor film reacts with oxygen that bonds to metal atoms to form water. Therefore, oxygen deficiency (V o ) may be formed. o ) by adding hydrogen In some cases, electrons, which act as carriers, are generated. In addition, some of the hydrogen atoms bond with metal atoms. It can combine with oxygen to generate electrons, which are carriers. A transistor using an oxide semiconductor having such a structure tends to be normally on. It is preferable that the amount of hydrogen in the oxide semiconductor is reduced as much as possible. The hydrogen concentration obtained by SIMS in the conductor is 1×10 20 atoms / cm 3 Not yet less than 1×10 19 atoms / cm 3 less than 5 × 10 18 at oms / cm 3 less than 1×10 18 atoms / cm 3 Less than.

[0106] In addition, oxygen vacancies (V o ) is a method for introducing oxygen into an oxide semiconductor film. In other words, oxygen vacancies (V o ) is supplemented with oxygen By filling, oxygen vacancies (V o ) disappears. Therefore, oxygen is diffused into the oxide semiconductor film. By dispersing the oxygen vacancies (V o ) and improve reliability. can.

[0107] Note that oxygen can be introduced into the oxide semiconductor film by, for example, It is possible to provide an oxide containing more oxygen than the oxygen required for the stoichiometric composition. In oxides, there is a region where oxygen exists in excess of the stoichiometric composition (hereinafter referred to as the excess oxygen region). In particular, when an oxide semiconductor film is used for a transistor, In this case, oxides with excess oxygen regions are used in the underlayer film near the transistor or in the interlayer film. By providing the insulating film, oxygen vacancies in the transistor can be reduced, and the reliability can be improved.

[0108] An oxide semiconductor film in which impurities are sufficiently reduced is used for a channel formation region of a transistor. This allows stable electrical properties to be imparted.

[0109] One embodiment of the present invention is a semiconductor device including a transistor, the transistor comprising: a gate electrode, a first insulating film on the first gate electrode, and an oxide semiconductor on the first insulating film; a second insulating film on the oxide semiconductor film; a second gate electrode on the second insulating film; a third insulating film on the second gate electrode, and the oxide semiconductor film is a channel region overlapping with the first or second gate electrode, and a source region in contact with the third insulating film; a drain region in contact with the third insulating film, and a first gate electrode and a second gate electrode are electrically connected to each other.

[0110] In addition, the electrical characteristics of the transistor are such that the gate voltage of the transistor is 0V The maximum field-effect mobility in the range of 10 V or less is 10 cm 2 / Vs or more 200 cm 2 / Vs, and a second region where the threshold voltage is between -1V and 1V. a third region where the S value is less than 0.3 V / decade and the off-state current is 1×10 - 12 A / cm 2 and a fourth region having a thickness less than 100 nm. The maximum mobility is expressed as μFE(max), and the field effect When the effective mobility value is expressed as μFE (Vg=2V), μFE(max) / μFE(V g=2V) is greater than or equal to 1 and less than 10.

[0111] More preferably, the electrical characteristics of the transistor are such that the gate voltage of the transistor is The maximum value of the field-effect mobility in the voltage range of 0 V to 10 V is 60 cm 2 / Vs or later Upper 200cm 2 / Vs, and a second region where the threshold voltage is between -1V and 1V. a second region where the S value is less than 0.3 V / decade; a third region where the off-state current is 1 x10 -12 A / cm 2 and a fourth region that is less than the first region. The maximum value of the field effect mobility is expressed as μFE(max) and is calculated when the gate voltage of the transistor is 2V. When the field effect mobility value is expressed as μFE (Vg=2V), μFE(max) / μ FE (Vg=2V) is 1 or more and less than 2.

[0112] In other words, the semiconductor device of one embodiment of the present invention has an oxide semiconductor layer in a channel region. A transistor having a thin film, the field effect mobility, the threshold voltage of the transistor This is a transistor with excellent off-state current and S value. For example, the transistors in the pixels of liquid crystal displays and organic EL displays, It can be suitably used for transistors in drive circuits of LCDs and organic EL displays. .

[0113] <1-4. Method for producing composite oxide semiconductor> Here, an example of a method for manufacturing the complex oxide semiconductor shown in FIGS. 1A and 1B will be described. The complex oxide semiconductor of one embodiment of the present invention can be formed using a sputtering apparatus. can.

[0114] [Sputtering equipment] FIG. 7(A) is a cross-sectional view illustrating a film formation chamber 2501 of the sputtering apparatus. FIG. 7(B) shows the magnet unit 2530a and the magnet FIG. 25 is a plan view of the cot unit 2530b.

[0115] The film forming chamber 2501 shown in FIG. 7(A) includes a target holder 2520a and a target holder da 2520b, backing plate 2510a, backing plate 2510b, Target 2502a, target 2502b, member 2542, and substrate holder 257 0. The target 2502a is disposed on a backing plate 2510a. The backing plate 2510a is placed on the target holder 2520a. The magnet unit 2530a is placed on the backing plate 2510a. The target 2502b is placed under the backing. The backing plate 2510b is placed on the target The magnet unit 2530b is disposed on the backing holder 2520b. The target 2502b is placed under the target 2502b via a guide plate 2510b.

[0116] As shown in FIG. 7(A) and FIG. 7(B), the magnet unit 2530a is a magnet. Net 2530N1, Magnet 2530N2, Magnet 2530S, Magnet In the magnet unit 2530a, the magnet Magnet 2530N1, Magnet 2530N2 and Magnet 2530S are magnet holders. The magnets 2530N1 and 2530N The magnet unit 25 is disposed at a distance from the magnet 2530S. The film forming chamber 2501 has the same structure as the magnet unit 2530a. When the substrate 2560 is loaded into the substrate holder 2570, the substrate 2560 is placed in contact with the substrate holder 2570. .

[0117] Target 2502a, backing plate 2510a, and target holder 2520 a, a target 2502b, a backing plate 2510b, and a target holder 25 20b are separated by a member 2542. The member 2542 is an insulator. However, the member 2542 may be a conductor or a semiconductor. The member 2542 may be a conductor or semiconductor whose surface is covered with an insulator. .

[0118] The target holder 2520a and the backing plate 2510a are connected by screws (bolts, etc. ) and are fixed to the same potential. It has a function of supporting the target 2502a via the king plate 2510a. The target holder 2520b and the backing plate 2510b are connected by screws (bolts, etc.) ) and are fixed to the same potential. It has the function of supporting the target 2502b via the king plate 2510b.

[0119] The backing plate 2510a has a function of fixing the target 2502a. Additionally, the backing plate 2510b has the function of fixing the target 2502b.

[0120] In addition, in FIG. 7(A), the magnetic field lines 25 formed by the magnet unit 2530a are 80a, 2580b are explicitly stated.

[0121] As shown in FIG. 7(B), the magnet unit 2530a has a rectangular or substantially long a square magnet 2530N1, a rectangular or approximately rectangular magnet 2530N2, A rectangular or approximately rectangular magnet 2530S is fixed to a magnet holder 2532. The magnet unit 2530a is arranged in the direction indicated by the arrows in FIG. For example, the magnet unit 2530a can be swung left and right as shown in the figure. It is sufficient to oscillate at a beat of 0.1 Hz to 1 kHz.

[0122] The magnetic field on the target 2502a changes with the oscillation of the magnet unit 2530a. The area with a strong magnetic field becomes a high-density plasma area, and the target 2 Sputtering phenomenon of 502a is likely to occur. This is because the magnet unit 2530b The same is true for .

[0123] <1-5. Complex oxide semiconductor manufacturing flow> FIG. 8 is a process flow diagram illustrating a method for manufacturing a complex oxide semiconductor.

[0124] The composite oxide semiconductor shown in FIGS. 1(A) and 1(B) comprises at least the first to fourth processes shown in FIG. It is produced through a process.

[0125] [First step: placing the substrate in the film formation chamber] The first step includes placing a substrate in a film formation chamber (see step S101 in FIG. 8).

[0126] In the first step, for example, the substrate holder 2570 of the film formation chamber 2501 shown in FIG. The substrate 2560 is placed on the substrate 2560.

[0127] The temperature of the substrate 2560 during film formation affects the electrical properties of the composite oxide semiconductor. The higher the concentration, the higher the crystallinity of the complex oxide semiconductor and the higher the reliability. The lower the substrate temperature, the lower the crystallinity of the composite oxide semiconductor and the higher the carrier mobility. In particular, the lower the substrate temperature during film formation, the easier it is to form a transistor having a complex oxide semiconductor. In this case, the field-effect mobility at low gate voltages (e.g., greater than 0 V and less than 2 V) The improvement is noticeable.

[0128] The temperature of the substrate 2560 is from room temperature (25° C.) to 200° C., preferably from room temperature to The substrate temperature may be set to 170° C. or less, more preferably, room temperature or more and 130° C. or less. By doing so, it is possible to manufacture a large-area glass substrate (for example, an 8th or 10th generation glass substrate described later). In particular, it is suitable for the case where the substrate temperature during film formation of the composite oxide semiconductor is low. By keeping the temperature at room temperature, in other words, in a state where it is not intentionally heated, the bending or distortion of the substrate can be prevented. This is preferable because it can suppress the

[0129] In addition, a cooling mechanism or the like may be provided in the substrate holder 2570 to cool the substrate 2560. good.

[0130] In addition, by setting the temperature of the substrate 2560 to 100°C or higher and 130°C or lower, the composite oxide By removing the water impurity in this way, the electric The reliability can be improved while improving the field effect mobility.

[0131] In addition, by setting the temperature of the substrate 2560 to 100°C or more and 130°C or less, sputtering This prevents distortion of the semiconductor device due to excessive heat. This allows for improved productivity of the equipment, and therefore, it is suitable for large-scale production equipment. Since the device is easy to introduce, it is possible to easily manufacture large display devices using large-area substrates. Cut.

[0132] In addition, by increasing the temperature of the substrate 2560, the water in the composite oxide semiconductor can be more effectively Not only can it be removed, but it can also improve the crystallinity of the composite oxide semiconductor. For example, the temperature of the substrate 2560 is set to 80° C. or more and 200° C. or less, preferably 100° C. or more and 170° C. or less. By setting the temperature at 0°C or less, a highly crystalline composite oxide semiconductor film can be formed.

[0133] [Second step: Step of introducing gas into the film formation chamber] The second step includes a step of introducing gas into the film formation chamber (see step S201 in FIG. 8).

[0134] In the second step, for example, a gas is introduced into the film formation chamber 2501 shown in FIG. As the gas supply, either argon gas or oxygen gas or both may be introduced. Instead of argon gas, an inert gas such as helium, xenon, or krypton may be used. .

[0135] When forming a composite oxide semiconductor film using oxygen gas, the ratio of oxygen to the entire film formation gas is Therefore, it is sometimes referred to as the "oxygen flow ratio."

[0136] The higher the oxygen flow rate ratio, the higher the crystallinity of the composite oxide semiconductor and the higher its reliability. On the other hand, the smaller the oxygen flow ratio, the lower the crystallinity of the composite oxide semiconductor, and the more difficult it is to transfer carriers. In particular, the smaller the oxygen flow rate ratio, the more the mobility of the composite oxide semiconductor can be increased. In transistors, at low gate voltages (for example, in the range greater than 0 V and less than 2 V), The improvement in field effect mobility is remarkable.

[0137] The oxygen flow rate ratio is set to 0% or more in order to obtain the desired characteristics for the composite oxide semiconductor depending on its application. It can be set appropriately within the range of 100% or less.

[0138] For example, when used in the semiconductor layer of a transistor with high field effect mobility, a composite oxide The oxygen flow rate during semiconductor film formation is greater than 0% and less than 30%, preferably 5% or more and 30% or less, and more preferably 7% or more and 15% or less. When forming a film, it is possible to form the film without using oxygen gas. In this case, the oxygen flow rate is set to 0%. be.

[0139] Furthermore, a transistor having both relatively high field-effect mobility and relatively high reliability can be obtained. To achieve this, the oxygen flow rate during film formation of the composite oxide semiconductor should be set to between 30% and 70%. Preferably, the ratio is greater than 30% and less than 50%. The oxygen flow rate ratio in the gas is set to 10% or more and 50% or less, preferably 30% or more and 50% or less.

[0140] In addition, in order to obtain a highly reliable transistor, it is necessary to The oxygen flow rate ratio is set to 70% or more and 100% or less.

[0141] In this way, by controlling the substrate temperature and oxygen flow rate during film formation, it is possible to obtain the desired electrical properties. For example, lowering the substrate temperature (raising it) ) and decreasing (increasing) the oxygen flow rate contribute to the field-effect mobility, respectively. Therefore, for example, due to equipment restrictions, the substrate temperature may not be raised sufficiently. Even if it is not possible to form a film by increasing the oxygen flow rate, the substrate temperature can be increased. It is also possible to realize a transistor having a field effect mobility equivalent to that obtained when the SiO 2 layer is used.

[0142] In addition, by controlling the substrate temperature and oxygen flow rate during film formation, it is possible to obtain complex films with increased carrier mobility. Even when a composite oxide semiconductor is used, oxygen vacancies and impurities can be reduced by the method described below. By doing so, a highly reliable transistor can be realized.

[0143] In addition, the gases mentioned above must also be highly purified. The dew point of the gas is -40°C or less, preferably -80°C or less, more preferably -100°C or less. By using gas that has been highly purified to temperatures below -120°C, or more preferably below -120°C, It is possible to prevent moisture and the like from being absorbed into the conductor as much as possible.

[0144] In addition, the film-forming chamber 2501 is designed to remove as much water as possible, which is an impurity for the composite oxide semiconductor. To remove the gas, a high vacuum (5×10) was created using an adsorption type vacuum pump such as a cryopump. - 7 Pa to 1 x 10 -4 It is preferable to exhaust the gas to a pressure of about 100 Pa. When the deposition device is in standby, gas molecules (m / z=1 8) is the partial pressure of 1 x 10 -4 Pa or less, preferably 5 x 10 -5 Pa or less It is preferable to set the following.

[0145] [Third step: Step of applying voltage to the target] The third step includes applying a voltage to the target (see step S301 in FIG. 8). ).

[0146] In the third step, for example, the target holder 2520a and the target shown in FIG. A voltage is applied to the holder 2520b. A potential is applied to a terminal V1 connected to the substrate holder 2570. The potential is set to be lower than the potential of the target holder 2520b. The potential applied is set to be lower than the potential of terminal V2 connected to substrate holder 2570. The potential applied to the terminal V2 connected to the substrate holder 2570 is set to the ground potential. The potential applied to terminal V3 connected to magnet holder 2532 is set to the ground potential.

[0147] The potentials applied to terminals V1, V2, V3, and V4 are the same as those mentioned above. Also, the target holder 2520, the substrate holder 2570, the magnet holder It is not necessary to apply a potential to all of the substrates 2532. For example, if the substrate holder 2570 is The voltage applied to terminal V1 can be controlled. A power source capable of being electrically connected is assumed. The power source may be a DC power source, an AC power source, or An RF power source can be used.

[0148] The target 2502a and the target 2502b are made of indium, an element When a target having M (where M is Al, Ga, Y, or Sn), zinc, and oxygen is used, An example of the target 2502a and the target 2502b is In-G a-Zn metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]), I n-Ga-Zn metal oxide target (In:Ga:Zn=5:1:7 [atomic ratio]) In the following, an In-Ga-Zn metal oxide target (In:G The case where a Zn atom ratio of 4:2:4.1 is used will be described.

[0149] [Fourth step: Depositing a composite oxide semiconductor on a substrate] In the fourth step, sputtering particles are ejected from the target and deposited on the substrate as a composite oxide semiconductor. (see step S401 in FIG. 8).

[0150] In the fourth step, for example, argon gas or oxygen is used in the film-forming chamber 2501 shown in FIG. The elementary gas is ionized and split into positive ions and electrons to form plasma. The positive ions are transported to the target holders 2520a and 2520b by the potential applied to the target holders 2520a and 2520b. The positive ions are accelerated toward the targets 2502a and 2502b. By colliding with the oxide target, sputter particles are generated and sputtered onto the substrate 2560. The particles accumulate.

[0151] The targets 2502a and 2502b were made of In:Ga:Zn with an atomic ratio of 4: 2:4.1 or In-Ga-Zn metal oxide with an atomic ratio of In:Ga:Zn=5:1:7 When using a solid target, there are cases where the target contains multiple crystal grains with different compositions. For example, the diameter of the plurality of crystal grains is often 10 μm or less. When the In-Ga-Zn metal oxide target contains crystal grains with a high In content, There are cases where the proportion of the region A1 described above that is formed increases.

[0152] <1-6. Film formation model> Next, in the fourth step, the film formation model shown in Figure 9(A), (B), and (C) can be considered. can.

[0153] 9(A), (B), and (C) are cross-sectional schematic diagrams of the vicinity of the target 2502a shown in FIG. 9(A) shows the state of the target before use, and FIG. 9(B) shows the state of the target before film formation. 9(A) shows the state of the target during film formation, and FIG. 9(C) shows the state of the target during film formation. B) (C) shows the target 2502a, plasma 2190, positive ions 2192, and sputtering. Particles 2504a, 2506a, etc. are clearly shown.

[0154] In FIG. 9(A), the surface of the target 2502a is relatively flat and has a composition ( For example, the composition of In, Ga, and Zn is uniform. By performing a sputtering process or the like, unevenness is formed on the surface of the target 2502a, The unevenness and segregation are caused by sputtering performed beforehand. This can be caused by plasma (e.g., Ar plasma) used in the coating process. shows a segregation region 2504 and a segregation region 2506. 4 is the region containing a large amount of Ga and Zn (Ga, Zn-rich region), and the segregation region 2506 The region containing a large amount of In (In-Rich region) is defined as the segregation region containing a large amount of Ga. The reason why the region 2504 is formed is that Ga is a material with a lower melting point than In, and therefore The heat received by the target 2502a during the plasma treatment causes some of the target to melt and agglomerate. This is thought to be because the segregation region 2504 is formed as a result of the above.

[0155] [First Step] In Figure 9(C), argon gas or oxygen gas is ionized to produce positive ions 2192 and electrons (Figure (not shown) and form plasma 2190. After that, the positive Ions 2192 are directed toward target 2502a (here, an In-Ga-Zn oxide target ) and positive ions 2192 collide with the In-Ga-Zn oxide target. As a result, sputtered particles 2504a and 2506a are generated, and the In-Ga-Zn oxide substrate Sputtered particles 2504a and 2506a are ejected from the get. 2504a is expelled from the segregation region 2504, and is therefore a Ga, Zn-rich class. In addition, the sputtered particles 2506a may form a gap between the segregation region 2506 and the sputtered particles 2506a. Because they are pushed out, they may form in-rich clusters.

[0156] In the case of the In-Ga-Zn oxide target, the segregation region 2504 is first separated into two regions. It is believed that the sputter particles 2504a are preferentially sputtered. When 2192 is bombarded with an In-Ga-Zn oxide target, the relative atomic mass is Since Ga and Zn are lighter than In-Ga-Zn oxide, they are preferentially ejected from the target. The ejected sputtered particles 2504a are deposited on the substrate. 1(A)(B) and the like is formed.

[0157] [Second step] Subsequently, as shown in FIG. 9(C), sputtered particles 2506a are sputtered from the segregation region 2506. The sputtered particles 2506a collide with the area B1 on the substrate where the film was previously formed. As a result, the area A1 shown in FIGS. 1(A) and 1(B) is formed.

[0158] As shown in FIG. 9(C), the target 2502a continues to be sputtered during film formation. Therefore, the generation and disappearance of the segregation region 2504 occur intermittently. .

[0159] By repeating the film formation model of the first step and the second step, the film formation shown in Figure 1(A) can be obtained. A complex oxide semiconductor according to one embodiment of the present invention, such as that shown in (B), can be obtained.

[0160] That is, the in-rich segregation region 2506 and the Ga, Zn-rich segregation region 2507 are Sputtered particles (2504a and 2506a) are ejected individually from 504. On the substrate, the In-Rich regions are connected to each other in a cloud-like formation. A complex oxide semiconductor according to one embodiment of the present invention can be formed as shown in FIGS. In the oxide semiconductor film, the in-rich regions are connected to each other in a cloud-like manner, Transistors using composite oxide semiconductors have high on-current (Ion) and high field effect. It has a mobility (μFE).

[0161] In this way, transistors that satisfy high on-current (Ion) and high field-effect mobility (μFE) are In transistors, In is important, and other metals (e.g., Ga) are not necessarily Not necessary.

[0162] In the above, argon gas is used to form the composite oxide semiconductor of the present invention. In this case, the complex oxide semiconductor contains many oxygen vacancies. When a complex oxide semiconductor contains many oxygen vacancies, shallow defects appear in the complex oxide semiconductor. In complex oxide semiconductors, sDOS can be formed. When formed, the sDOS becomes a carrier trap, and the on-current and field-effect mobility decrease. It will decrease.

[0163] Therefore, when a composite oxide semiconductor is formed using argon gas, After the oxide semiconductor is formed, oxygen is supplied to the composite oxide semiconductor, and the composite oxide It is preferable to compensate for oxygen vacancies in the semiconductor to reduce sDOS.

[0164] As a method for supplying oxygen, for example, after forming the composite oxide semiconductor, an oxygen-containing atmosphere is Examples of such methods include a method of performing heat treatment in an atmosphere containing oxygen, and a method of performing plasma treatment in an atmosphere containing oxygen. Alternatively, an insulating film or a composite oxide film in contact with the composite oxide semiconductor of one embodiment of the present invention may be formed. The insulating film may have excess oxygen in the vicinity of the oxide semiconductor. The configuration will be described in detail in the second embodiment.

[0165] Although the sputtering method has been described here, the present invention is not limited to this. Pulsed laser deposition (PLD), plasma enhanced chemical vapor deposition (PECVD), and thermal CV D (Chemical Vapor Deposition) method, ALD (Atomic Alternatively, a thermal CVD method, a vacuum deposition method, or the like may be used. Examples of this include MOCVD (Metal Organic Chemical Vapor Deposition) r Deposition) method.

[0166] <1-7. Verification of the film formation model> Next, in order to verify the above film formation model, the shape and composition of the sputtering target surface were The composition of the material was investigated. The target change was investigated.

[0167] FIG. 10 is a diagram illustrating the sample preparation and analysis method.

[0168] The sample used was a part cut out from a metal oxide target. A metal oxide target with an atomic ratio of In:Ga:Zn=4:2:3, In:Ga: Metal oxide target with Zn=1:1:1, gold with In:Ga:Zn=5:1:6 Four types of metal oxide targets: In:Ga:Zn=5:1:8 A similar type was used.

[0169] The surface of the sample was then polished. Observation by SEM-EDX ( Energy Dispersive X-ray spectroscopy Composition analysis was performed. SEM image observation and EDX measurement were performed using the EX-370 manufactured by Horiba Ltd. The acceleration voltage was set to 15 kV.

[0170] Next, the sample surface was subjected to a sputtering process. Argon gas was used as the gas, and the treatment was carried out for 1 hour under the conditions of a pressure of 0.4 Pa and a DC power of 200 W. The theory was carried out.

[0171] After that, the sputtered surface was observed by SEM as above, and The composition was analyzed by M-EDX.

[0172] In EDX analysis, electron beams are irradiated onto each point in the analysis area of ​​the sample, and the resulting The energy and frequency of the characteristic X-rays of the sample are measured, and the EDX spectrum corresponding to each point is obtained. Here, the peaks in the EDX spectrum at each point are determined as electron transitions to the L shell of the In atom, Ga electron transitions to the L shell of an atom, electron transitions to the L shell of a Zn atom, and electron transitions to the K shell of an O atom The ratio of each atom at each point was calculated. By performing the same analysis, EDX mapping can be obtained, showing the distribution of the ratio of each atom. Cut.

[0173] First, S measured for a metal oxide target with In:Ga:Zn=4:2:3 The EM image and EDX mapping are shown in Figures 11 and 12. Figure 11 shows the results before sputtering. Fig. 12 shows the SEM image and EDX mapping of the sample surface after sputtering. SEM images and EDX mapping of the sample surface. In each figure, the same position as the SEM image is 1 shows EDX mapping of O, Zn, Ga, and In atoms in the sample.

[0174] As shown in Figure 11, although voids (holes) can be seen in the SEM image, the sample surface is relatively clean. In addition, multiple grains are observed in the SEM image, and the sample is polycrystalline. In addition, EDX mapping confirmed that some Zn-rich regions were present. However, it was confirmed that each element was distributed uniformly.

[0175] On the other hand, as shown in Figure 12, when sputtering is performed, an uneven shape is formed on the sample surface. More specifically, it was confirmed that particles with a diameter of approximately 0.1 μm to 5 μm were formed on the surface of the sample. In the EDX mapping shown in Figure 12, granular precipitates of the following size were confirmed. There are some points where EDX spectra could not be obtained due to the influence of surface irregularities.

[0176] Also, looking at the EDX mapping in Figure 12, O atoms, Zn atoms, and Ga atoms The distribution reflects the shape of the sample surface, and the abundance ratio varies greatly depending on the location. It can also be seen that the precipitate surface tends to have a high composition of Ga and Zn atoms. On the other hand, the shape of the sample surface is not reflected in the In atoms, and they are It can be seen that the distribution is uniform.

[0177] Figure 13 shows a pie chart of the abundance ratios of In, Ga, and Zn at several positions. FIG. 14 is a bar graph showing the results shown in FIG. 13. As shown in Fig. 14, the composition is roughly uniform before the sputtering process, and the composition of the target The composition after sputtering varies depending on the position. In particular, the precipitates observed after sputtering treatment contained a small amount of In. It was confirmed that there were regions where Ga and Zn were segregated.

[0178] 15 and 16 show the results of the measurement using a metal oxide target with In:Ga:Zn=1:1:1. The SEM image and EDX mapping of the In: SEM image and EDX measurement of a metal oxide target with Ga:Zn=5:1:6 19 and 20 show the mapping of In:Ga:Zn=5:1:8. The SEM image and EDX mapping of the metal oxide target are shown.

[0179] Thus, for metal oxide targets of different compositions, sputtering After the treatment, precipitates with a low In content and a high Ga and Zn content were present on the surface. It was also confirmed that In was distributed more uniformly than O, Ga, and Zn. was confirmed.

[0180] From the above results, it is clear that the sputtering treatment produces Ga on the surface of the metal oxide target. It can be seen that segregation regions containing a large amount of In and Zn are formed. Therefore, the film formation model explained above is quite valid. It can be seen that...

[0181] <1-8. Classification of oxide semiconductors> Next, classification of oxide semiconductors will be described.

[0182] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned d crystalline oxide semiconductor), polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous- like oxide semiconductor), and amorphous oxide semiconductor, etc. be.

[0183] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxides. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC -OS, polycrystalline oxide semiconductor, and nc-OS.

[0184] Amorphous structures are generally isotropic and have no heterogeneous structure, and are characterized by the arrangement of atoms in a metastable state. The position is not fixed, the bond angle is flexible, and there is short-range order but no long-range order. It is said that there is no such thing.

[0185] That is, a stable oxide semiconductor is transformed into a completely amorphous In addition, it is not isotropic (for example, in a microscopic region, An oxide semiconductor having a periodic structure cannot be called a completely amorphous oxide semiconductor. -like OS is not isotropic but has an unstable structure with voids. In terms of instability, a-like OS is physically an amorphous oxide semiconductor. Close to.

[0186] [CAAC-OS] First, let me explain about CAAC-OS.

[0187] CAAC-OS is an oxide having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0188] CAAC-OS is an oxide semiconductor with high crystallinity. CAAC-OS is designed to be free from impurities and defects. It can also be said to be an oxide semiconductor with few defects (such as oxygen vacancies).

[0189] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon are more oxidative than metal elements that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0190] [nc-OS] Next, we will explain nc-OS.

[0191] We will explain the analysis of nc-OS by XRD. However, when structural analysis was performed using the out-of-plane method, no peaks indicating orientation appeared. That is, the crystals of the nc-OS do not have any orientation.

[0192] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, in nc-OS, there is no regularity in the crystal orientation between different pellets. Therefore, the nc-OS may have a higher density of defect states than the CAAC-OS.

[0193] [a-like OS] The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a semiconductor.

[0194] A-like OS has porosity or low density areas. Therefore, it is an unstable structure.

[0195] In addition, a-like OS has porosity, so compared to nc-OS and CAAC-OS, Specifically, the density of a-like OS is lower than that of a single crystal with the same composition. The density of nc-OS and CAAC- The density of OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a density of less than 78%.

[0196] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The densities of nc-OS and CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0197] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By combining these, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density corresponding to a single crystal of a desired composition is calculated based on the ratio of the single crystals of different compositions combined. However, the density can be estimated by using as few types of single crystals as possible. It is preferable to estimate them together.

[0198] As described above, oxide semiconductors have various structures, each of which has various characteristics. Note that the oxide semiconductor film of one embodiment of the present invention can be formed using an amorphous oxide semiconductor, an a-like OS, Two or more of the nc-OS and CAAC-OS may be mixed.

[0199] The region A1 described above is preferably non-single crystal. It is preferable that the region A1 and the region B1 have different crystal structures. That's fine.

[0200] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0201] (Embodiment 2) In this embodiment, a transistor different from that described in Embodiment 1 is used. The data will be described with reference to FIGS. 21 to 38.

[0202] <2-1. Transistor configuration examples> The structure of a transistor according to one embodiment of the present invention will be described.

[0203] [Transistor configuration example 1] 21(A) is a top view of the transistor 100A, and FIG. 21(B) is a top view of the transistor 100A. 21(C) is a cross-sectional view taken along the dashed line Y1-X2 in FIG. 21A is a cross-sectional view of the section Y2. For clarity, in FIG. 21A, the insulating film 110 and other components are not shown. In the top view of the transistor, the components are omitted. 21(A), some of the components may be omitted. The dashed line X1-X2 direction is the channel length (L) direction, and the dashed line Y1-Y2 direction is the channel width It is sometimes called the (W) direction.

[0204] The transistor 100A shown in FIGS. 21(A), 21(B), and 21(C) includes a conductive film 10 on a substrate 102. 6, the insulating film 104 on the conductive film 106, the oxide semiconductor film 108 on the insulating film 104, and An insulating film 110 on the nitride semiconductor film 108, a conductive film 112 on the insulating film 110, and 4, the oxide semiconductor film 108, and the insulating film 116 over the conductive film 112. The compound semiconductor film 108 includes a channel region 108i overlapping with the conductive film 112, an insulating film 116, and a a source region 108s in contact with the insulating film 116 and a drain region 108d in contact with the insulating film 116; .

[0205] The insulating film 116 contains nitrogen or hydrogen. s and the drain region 108d, the nitrogen or hydrogen in the insulating film 116 is sorbed. The source region 108s and the drain region 108d are doped with Zn. The carrier density of the rain region 108d increases when nitrogen or hydrogen is added.

[0206] The transistor 100A also includes an insulating film 118 on the insulating film 116, and a A conductor electrically connected to the source region 108s is formed through an opening 141a formed in the semiconductor substrate 18. The drain electrode 120a is connected to the drain electrode 120b via the opening 141b formed in the insulating films 116 and 118. The insulating film 120b may be electrically connected to the region 108d. An insulating film 122 may be provided over the film 118, the conductive film 120a, and the conductive film 120b. In addition, in FIGS. 21B and 21C, the insulating film 122 is provided as an example. There is no limitation, and the insulating film 122 may not be provided.

[0207] In this specification and the like, the insulating film 104 is referred to as a first insulating film, and the insulating film 110 is referred to as a second insulating film. the insulating film, the insulating film 116 as the third insulating film, the insulating film 118 as the fourth insulating film, and the insulating film 122 The insulating film 104 is sometimes referred to as the first gate insulating film. The insulating film 110 functions as a second gate insulating film. The insulating films 116 and 118 function as protective insulating films, and the insulating film 122 serves as a planarizing film. It functions as an insulating film.

[0208] The insulating film 110 has an excess oxygen region. As a result, excess oxygen is supplied to the channel region 108i of the oxide semiconductor film 108. Therefore, oxygen vacancies that may be formed in the channel region 108i can be compensated for by the excess oxygen. Since the semiconductor device can be filled with the conductive material, a highly reliable semiconductor device can be provided.

[0209] In order to supply excess oxygen into the oxide semiconductor film 108, Excess oxygen may be supplied to the insulating film 104 formed below the insulating film 10. The excess oxygen contained in the oxide semiconductor film 108 is used to form the source region 108s and the drain region 108s of the oxide semiconductor film 108. The source region 108s and the drain region 108d may also be supplied with When excess oxygen is supplied to the source region 108s and the drain region 108d, the resistance It may be higher.

[0210] On the other hand, in the structure in which the insulating film 110 formed above the oxide semiconductor film 108 contains excess oxygen, By forming the film, it is possible to selectively supply excess oxygen only to the channel region 108i. Alternatively, the channel region 108i, the source region 108s, and the drain region 10 After supplying excess oxygen to the source region 108s and the drain region 108d, By selectively increasing the region density, the resistance of the source region 108s and the drain region 108d can be reduced. Therefore, it is possible to suppress an increase in resistance.

[0211] The source region 108s and the drain region 108d of the oxide semiconductor film 108 are and each preferably has an element that forms an oxygen vacancy or an element that bonds to an oxygen vacancy. Representative elements that form oxygen vacancies or elements that bond with oxygen vacancies include: Examples include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Representative examples of rare gas elements include helium, neon, argon, krypton, and The insulating film 116 contains one or more of the above elements that form oxygen vacancies. When the insulating film 116 is included, the source region 108s and the drain region 108d are diffused. The element that forms the oxygen vacancy is added to the source region 108s and the drain region 108s by an impurity addition process. It may be added in the rain region 108d.

[0212] When an impurity element is added to an oxide semiconductor film, a bond between a metal element and oxygen in the oxide semiconductor film forms. Alternatively, an impurity element is added to the oxide semiconductor film, and oxygen vacancies are formed. When this occurs, oxygen that has been bonded to a metal element in the oxide semiconductor film is bonded to an impurity element, and the metal element As a result, oxygen is released from the oxide semiconductor film, and oxygen vacancies are formed. The carrier density increases and the conductivity increases.

[0213] FIG. 22 is an enlarged view of the oxide semiconductor film 108 and its vicinity in FIG. In this way, the channel region 108i contains oxygen released from the insulating film 110 by heat treatment or the like. (O) is supplied, and oxygen vacancies are reduced. This makes the channel region 108i i-type. On the other hand, the source region 108s and the drain region 108d can be doped with hydrogen (H ) is supplied, and the hydrogen and oxygen vacancies are bonded. The drain region 108d can be made n-type. Hydrogen contained in the film-forming gas during film formation, or hydrogen released from the insulating film 116 by heat treatment or the like etc.

[0214] The conductive film 106 shown in FIGS. 21(B) and 21(C) functions as a first gate electrode. The conductive film 112 functions as a second gate electrode, and the conductive film 120a functions as a source The conductive film 120b functions as a drain electrode.

[0215] As shown in FIG. 21(C), an opening 143 is provided in the insulating films 104 and 110. The conductive film 106 is electrically connected to the conductive film 112 through the opening 143. Therefore, the same potential is applied to the conductive film 106 and the conductive film 112. 43 may not be provided, and different potentials may be applied to the conductive film 106 and the conductive film 112. Alternatively, the conductive film 106 may be used as a light-shielding film without providing the opening 143. By forming the film 106 from a light-shielding material, the downward light irradiated onto the channel region 108i is It is possible to suppress light from

[0216] As shown in FIGS. 21B and 21C, the oxide semiconductor film 108 is the conductive film 106 functioning as a first gate electrode and the conductive film 112 functioning as a second gate electrode. It is positioned opposite to the gate electrode and is sandwiched between two conductive films that function as gate electrodes.

[0217] The length of the conductive film 112 in the channel width direction is equal to that of the oxide semiconductor film 108. The length of the oxide semiconductor film 108 in the channel width direction is longer than the length of the insulating film 110. The conductive film 112 and the conductive film 106 are sandwiched between the insulating film 112 and the conductive film 106. 104 and the insulating film 110 are connected through an opening 143. One of the side surfaces of the conductive film 108 in the channel width direction is connected to a conductive film 112 with an insulating film 110 sandwiched therebetween. and is opposed to it.

[0218] In other words, in the channel width direction of the transistor 100A, the conductive film 106 and the conductive film 108 are The film 112 is connected to the insulating film 104 and the insulating film 110 at an opening 143 provided therein. The oxide semiconductor film 108 is surrounded by the insulating film 104 and the insulating film 110. It is a structure that includes:

[0219] With this configuration, the oxide semiconductor film 10 included in the transistor 100A 8 is a conductive film 106 functioning as a first gate electrode and a conductive film 108 functioning as a second gate electrode. The transistor 100A can be electrically surrounded by the electric field of the conductive film 112. As described above, a channel region is formed by the electric fields of the first gate electrode and the second gate electrode. The device structure of the transistor that electrically surrounds the oxide semiconductor film 108 is called Surro. This can be called an unded channel (S-channel) structure. The transistor 100A can also be called a Dual Gate structure based on the number of gate electrodes. .

[0220] Since the transistor 100A has an S-channel structure, the conductive film 106 or The conductive film 112 effectively applies an electric field for inducing a channel to the oxide semiconductor film 108. This improves the current driving capability of the transistor 100A, resulting in a high on-state current. It is also possible to increase the on-current, which allows The transistor 100A can be miniaturized. The semiconductor film 108 is surrounded by the conductive film 106 and the conductive film 112. Therefore, the mechanical strength of the transistor 100A can be increased.

[0221] Note that the opening in the oxide semiconductor film 108 in the channel width direction of the transistor 100A An opening different from opening 143 may be formed on the side where portion 143 is not formed.

[0222] Note that the transistor 100A is positioned such that the conductive film 112 is positioned relative to the oxide semiconductor film 108, Alternatively, the conductive film 112 may be formed by a method such as TGSA (Top Gate Self Alignment). However, the semiconductor device of one embodiment of the present invention is not limited to this. It is not used as a BGTC (Bottom Gate Top Contact) type FET. That's fine.

[0223] <2-2. Components of a transistor> Next, the components of the transistors shown in FIGS. 21(A), (B), and (C) will be described in detail. do.

[0224] [substrate] The substrate 102 is made of a material that has heat resistance enough to withstand the heat treatment during the manufacturing process. It is possible.

[0225] Specifically, non-alkali glass, soda-lime glass, alkali glass, crystal glass The insulating film may be made of glass, quartz, sapphire, etc. Alternatively, an inorganic insulating film may be used. Examples of the inorganic insulating film include a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Examples of the film include an aluminum oxide film.

[0226] The alkali-free glass may have a thickness of 0.2 mm or more and 0.7 mm or less. Alternatively, the above thickness may be achieved by polishing the alkali-free glass.

[0227] In addition, alkali-free glass is available in 6th generation (1500mm x 1850mm) and 7th generation. (1870mm x 2200mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 2800mm), 10th generation (2950mm x 3400mm) etc. This allows the use of a large glass substrate, making it possible to manufacture a large display device. can be done.

[0228] The substrate 102 may be a single crystal semiconductor substrate made of silicon or silicon carbide, or a polycrystalline A semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like may also be used. .

[0229] Alternatively, an inorganic material such as a metal may be used as the substrate 102. Examples of the material include stainless steel and aluminum.

[0230] The substrate 102 is made of an organic material such as resin, resin film, or plastic. The resin film may be polyester, polyolefin, polyamide (nano), or the like. Iron, aramid, etc.), polyimide, polycarbonate, polyurethane, acrylic resin, Epoxy resin, polyethylene terephthalate (PET), polyethylene naphthalate (P Examples include polyethersulfone (PES), polyethersulfone (PEN), and resins with siloxane bonds. It can be obtained.

[0231] Alternatively, the substrate 102 may be made of a composite material that combines an inorganic material and an organic material. The composite material is a material made by bonding a metal plate or a thin glass plate to a resin film. composite materials, fibrous metal, particulate metal, fibrous glass, or particulate glass. Materials dispersed in an oil film, or fibrous resin or particulate resin dispersed in inorganic materials Materials, etc.

[0232] The substrate 102 is at least capable of supporting a film or layer formed thereon or therebelow. Any suitable film may be used, and the film may be one or more of an insulating film, a semiconductor film, and a conductive film. stomach.

[0233] [First insulating film] The insulating film 104 can be formed by sputtering, CVD, evaporation, pulsed laser deposition ( The insulating film 104 can be formed by appropriately using a photo-induced laser deposition (PLD) method, a printing method, a coating method, or the like. For example, an oxide insulating film or a nitride insulating film may be formed as a single layer or a stacked layer. Note that in order to improve the interface characteristics with the oxide semiconductor film 108, In this case, at least a region in contact with the oxide semiconductor film 108 is preferably formed using an oxide insulating film. It is also preferable to use an oxide insulating film that releases oxygen by heating as the insulating film 104. Then, oxygen contained in the insulating film 104 is transferred to the oxide semiconductor film 108 by heat treatment. It is possible.

[0234] The thickness of the insulating film 104 is 50 nm or more, or 100 nm or more and 3000 nm or less, or The thickness of the insulating film 104 can be set to 200 nm or more and 1000 nm or less. This can increase the amount of oxygen released from the insulating film 104 and also increase the The interface state at the interface with the conductor film 108 and the channel region 1 of the oxide semiconductor film 108 It is possible to reduce the oxygen vacancies contained in 08i.

[0235] The insulating film 104 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. silicon oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide The insulating film may be formed as a single layer or a stacked layer. The layer structure 104 is a stack of a silicon nitride film and a silicon oxynitride film. The insulating film 104 has a laminated structure, with a silicon nitride film on the lower layer side and an oxynitride film on the upper layer side. By using a silicon film, oxygen can be efficiently introduced into the oxide semiconductor film 108. Cut.

[0236] [Oxide semiconductor film] The oxide semiconductor film 108 is made of the composite oxide semiconductor described above or C / IGZO. It is preferable to use the following.

[0237] [Second insulating film] The insulating film 110 supplies oxygen to the oxide semiconductor film 108, particularly to the channel region 108i. For example, the insulating film 110 may be a single layer of an oxide insulating film or a nitride insulating film. Alternatively, the oxide semiconductor film 108 may be formed by stacking the oxide semiconductor film 108 and the oxide semiconductor film 109. In order to achieve this, the insulating film 110 has a region in contact with the oxide semiconductor film 108. The insulating film 110 is preferably formed using an oxide insulating film. Silicon oxide, silicon nitride, silicon nitride oxide, silicon nitride, or the like may be used.

[0238] The thickness of the insulating film 110 is 5 nm or more and 400 nm or less, or 5 nm or more and 300 nm or less. The thickness can be 10 nm or less, or 10 nm or more and 250 nm or less.

[0239] Furthermore, it is preferable that the insulating film 110 has few defects. The signal observed by ESR (Electron Spin Resonance) For example, the signal above is observed at a g value of 2.001. The E' center is an electron-doped ion that occurs in the dangling bond of silicon. The insulating film 110 has a spin density due to the E' center of 3×10 17 spi ns / cm 3 Less than or equal to 5 x 10 16 spins / cm 3 Silicon oxide is less than A silicon oxynitride film or a silicon nitride film may be used.

[0240] In addition to the above signals, the insulating film 110 also contains signals due to nitrogen dioxide (NO2). The signal is divided into three signals depending on the nuclear spin of N. The g value of each is between 2.037 and 2.039 (first signal). , g value is 2.001 or more and 2.003 or less (second signal), and g value is 1.96 It is observed between 4 and 1.966 (referred to as the third signal).

[0241] For example, the insulating film 110 may have a spin density of 1×10 1 7 spins / cm 3 More than 1×10 18 spins / cm 3 When an insulating film having a thickness of less than It is suitable.

[0242] In addition, nitrogen oxides (NO x ) creates a level in the insulating film 110 The level is located within the energy gap of the oxide semiconductor film 108. Therefore, nitrogen oxides (NOx) diffuse to the interface between the insulating film 110 and the oxide semiconductor film 108. When this happens, the level may trap electrons on the insulating film 110 side. The trapped electrons remain near the interface between the insulating film 110 and the oxide semiconductor film 108. Therefore, the insulating film 11 When a film containing a small amount of nitrogen oxide is used, the threshold voltage of the transistor is The shift can be reduced.

[0243] Nitrogen oxides (NO x ) is released in a small amount, for example, a silicon oxynitride film. The silicon oxynitride film can be analyzed by thermal desorption spectroscopy (TDS). Thermal Desorption Spectroscopy (DSS) revealed that nitrogen oxides (NO x ) is a membrane that releases more ammonia than water, and typically Output is 1 x 10 18 / cm 3 5x10 or more 19 / cm 3 The above is the ammo The amount of Ni release is higher when the temperature of the heat treatment in TDS is 50°C or higher and 650°C or lower, or when the temperature is 50 The total amount is in the range of ℃ to 550℃.

[0244] Nitrogen oxides (NO x ) reacts with ammonia and oxygen during heat treatment, By using an insulating film that releases a large amount of monoxide, x ) is reduced.

[0245] When the insulating film 110 was analyzed by SIMS, the nitrogen concentration in the film was 6×10 20 ato ms / cm 3 It is preferable that the following is true:

[0246] The insulating film 110 is made of hafnium silicate (HfSiO x ), nitrogen is added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate (HfAl x O y N z ), high-k materials such as hafnium oxide may also be used. The use of this high-k material can reduce gate leakage of transistors.

[0247] [Third insulating film] The insulating film 116 contains nitrogen or hydrogen. The insulating film 116 also contains fluorine. The insulating film 116 may be, for example, a nitride insulating film. Examples include silicon nitride, silicon nitride oxide, silicon oxynitride, silicon nitride fluoride, The insulating film 116 can be formed using silicon fluoride nitride or the like. is 1 x 10 22 atoms / cm 3 The insulating film 116 is preferably formed of an acid. The source region 108s and the drain region 108d of the nitride semiconductor film 108 are in contact with each other. Therefore, the impurities in the source region 108s and the drain region 108d that are in contact with the insulating film 116 The (nitrogen or hydrogen) concentration increases, and the source region 108s and the drain region 108d The carrier density can be increased.

[0248] [Fourth insulating film] The insulating film 118 can be an oxide insulating film. For example, a stacked film of an oxide insulating film and a nitride insulating film can be used. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, Hafnium oxide, gallium oxide, Ga-Zn oxide, or the like may be used.

[0249] The insulating film 118 functions as a barrier film against hydrogen, water, and the like from the outside. It is preferable that

[0250] The thickness of the insulating film 118 is 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less. m or less.

[0251] [Fifth insulating film] The insulating film 122 may be formed using an inorganic or organic material as long as it has insulating properties. The inorganic material may be a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. , silicon nitride film, aluminum oxide film, aluminum nitride film, etc. Examples of the material include photosensitive resin materials such as acrylic resin and polyimide resin. can be done.

[0252] [Conductive film] The conductive films 106, 112, 120a, and 120b are formed by sputtering or vacuum deposition. It can be formed by using a pulsed laser deposition (PLD) method, a thermal CVD method, etc. The conductive films 106, 112, 120a, and 120b are made of conductive metal films, visible light If a conductive film having a function of reflecting visible light or a conductive film having a function of transmitting visible light is used, good.

[0253] Conductive metal films include aluminum, gold, platinum, silver, copper, chromium, tantalum, Titanium, molybdenum, tungsten, nickel, iron, cobalt, palladium or manganese Alternatively, a material containing the above-mentioned metal element can be used. An alloy containing the metal may also be used.

[0254] Specifically, the conductive metal film may be a two-layer structure in which a copper film is laminated on a titanium film. Two-layer structure with copper film laminated on titanium nitride film, two-layer structure with copper film laminated on tantalum nitride film A three-layer structure is used, in which a copper film is laminated on a titanium film, and a titanium film is formed on top of that. In particular, by using a conductive film containing copper, the resistance can be reduced. Furthermore, the conductive film containing copper element is preferably an alloy film containing copper and manganese. The alloy film is suitable because it can be processed using a wet etching method. .

[0255] The conductive films 106, 112, 120a, and 120b are made of tantalum nitride films. The tantalum nitride film is preferably conductive and has high resistance to copper or hydrogen. Furthermore, tantalum nitride film has excellent barrier properties because it releases less hydrogen from itself. Therefore, a metal film in contact with the oxide semiconductor film 108 or a metal film near the oxide semiconductor film 108 It can be most suitably used as such.

[0256] In addition, instead of the above-mentioned conductive metal film, a conductive macromolecule or a conductive polymer may be used. It's fine.

[0257] The conductive film having the above-mentioned function of reflecting visible light may be made of gold, silver, copper, or para- In particular, conductive materials containing silver can be used. The use of a film is preferable because it can increase the reflectance in visible light.

[0258] The conductive film having the above-mentioned function of transmitting visible light may be formed of indium, tin, zinc, A material containing an element selected from gallium or silicon can be used. are In oxide, Zn oxide, In-Sn oxide (also called ITO), In-Sn-Si oxide (also called ITSO), In-Zn oxide, In-Ga-Zn oxide, etc. do.

[0259] The conductive film having the above-mentioned function of transmitting visible light may be made of graphene or graphene. A film containing graphene oxide may be used as the film containing graphene. and reducing the graphene oxide-containing film to form a graphene-containing film. The reduction method can be achieved by applying heat or by using a reducing agent. can be done.

[0260] The conductive films 112, 120a, and 120b can be formed by electroless plating. Materials that can be formed by the electroless plating method include, for example, Cu, Ni, Al, One or more selected from Au, Sn, Co, Ag, and Pd may be used. In particular, when Cu or Ag is used, the resistance of the conductive film can be reduced. Therefore, it is preferable.

[0261] Furthermore, when a conductive film is formed by electroless plating, the constituent elements of the conductive film tend to diffuse outward. In order to prevent the diffusion of the conductive film, a diffusion prevention film may be formed under the conductive film. A seed layer may be formed between the film and the conductive film on which the conductive film can be grown. The diffusion prevention film can be formed by, for example, sputtering. The diffusion prevention film may be, for example, a tantalum nitride film or a titanium nitride film. The seed layer can be formed by electroless plating. The seed layer may be made of a conductive film material that can be formed by electroless plating. Materials similar to those used for the stencil printing can be used.

[0262] The conductive film 112 is formed using an oxide semiconductor such as In-Ga-Zn oxide. When nitrogen or hydrogen is supplied from the insulating film 116, the oxide semiconductor In other words, the oxide semiconductor has a high carrier density. Therefore, oxide semiconductors function as gate electrodes. It can be used as such.

[0263] For example, the conductive film 112 may have a single layer structure of an oxide conductor (OC) or a single layer structure of a metal film. Alternatively, a laminated structure of an oxide conductor (OC) and a metal film may be used.

[0264] The conductive film 112 may have a single-layer structure of a metal film having a light-shielding property or an oxide conductor ( When a laminated structure of an OC and a metal film having a light-shielding property is used, a layer formed below the conductive film 112 This is preferable because the channel region 108i that is to be covered by the conductive film 11 can be shielded from light. 2. A laminate of an oxide semiconductor or oxide conductor (OC) and a metal film having a light-shielding property. When using this structure, a metal film (e.g., a thin film of a metal oxide) is formed on an oxide semiconductor or an oxide conductor (OC). By forming a metal film, the constituent elements in the metal film can be converted into an oxide semiconductor. or diffusion into the oxide conductor (OC) side, resulting in low resistance, or damage during the deposition of the metal film (for example, The resistance is reduced due to the presence of oxide semiconductor in the metal film. Alternatively, oxygen in the oxide conductor (OC) diffuses, forming oxygen vacancies and resulting in low resistance. do.

[0265] The thickness of the conductive films 106, 112, 120a, and 120b is 30 nm or more and 500 nm or less. or less, or from 100 nm to 400 nm.

[0266] <2-3. Transistor configuration example 2> 23(A) and 23(B) are cross-sectional views of the transistor 100B, and FIGS. 24(A) and 24(B) are cross-sectional views of the transistor 100B. 25(A) and 25(B) are cross-sectional views of the transistor 100D. 10B, 10C, and 10D. The top view of the transistor 100D is the same as that of the transistor 100A shown in FIG. Therefore, the explanation here will be omitted.

[0267] The transistor 100B shown in FIGS. 23A and 23B has a stacked structure of a conductive film 112, a conductive film The shape of the insulating film 110 and the shape of the insulating film 112 are different from those of the transistor 100A.

[0268] The conductive film 112 of the transistor 100B is a conductive film 112_1 on the insulating film 110 and a conductive film 112_2 on the insulating film 110. For example, the conductive film 112_1 may be made of an acid. By using a nitride conductive film, excess oxygen can be added to the insulating film 110. The oxide conductive film is formed by sputtering in an atmosphere containing oxygen gas. The oxide conductive film may be, for example, an oxide film containing indium and tin. oxides containing tungsten and indium; oxides containing tungsten, indium, and zinc oxides containing titanium and indium; oxides containing titanium, indium, and tin oxides containing indium and zinc; oxides containing silicon, indium, and tin; Examples of suitable oxides include oxides containing indium, gallium, and zinc.

[0269] 23(B), in the opening 143, the conductive film 112_2 and the conductive When the opening 143 is formed, the conductive film 112_1 is connected to the conductive film 106. After forming the hole, an opening 143 is formed, thereby forming the shape shown in FIG. 23(B). When an oxide conductive film is used for the conductive film 112_1, the conductive film 112_2 and the conductive film 112_3 can be formed. By using a structure in which the conductive film 112 and the conductive film 106 are connected, the contact resistance between the conductive film 112 and the conductive film 106 can be reduced. It is possible.

[0270] The conductive film 112 and the insulating film 110 of the transistor 100B have a tapered shape. More specifically, the lower end of the conductive film 112 is formed outside the upper end of the conductive film 112. The lower end of the insulating film 110 is formed outside the upper end of the insulating film 110. The lower end of the conductive film 112 is formed at approximately the same position as the upper end of the insulating film 110 .

[0271] The conductive film 112 and the insulating film 110 of the transistor 100B are tapered, Compared with the case where the conductive film 112 and the insulating film 110 of the transistor 100A are rectangular, This is preferable because it can improve the coverage of 16.

[0272] The other configurations of the transistor 100B are the same as those of the transistor 100A shown above. and has the same effect.

[0273] The transistor 100C shown in FIGS. 24A and 24B has a stacked structure of a conductive film 112, a conductive film The shape of the insulating film 110 and the shape of the insulating film 112 are different from those of the transistor 100A.

[0274] The conductive film 112 of the transistor 100C is a conductive film 112_1 on the insulating film 110 and a conductive film 112_2 on the insulating film 110. The conductive film 112_2 is formed on the conductive film 112_1. For example, the conductive film 112_1 and the conductive film 112_2 are formed on the outer side of the upper end of the conductive film 112_1. The film 112_2 and the insulating film 110 are processed using the same mask, and the conductive film 112_2 is wet The conductive film 112_1 and the insulating film 110 are dry-etched by etching. By processing, the above structure can be obtained.

[0275] In addition, by using the structure of the transistor 100C, the region 1 The region 108f may be formed between the channel region 108i and the source region 108i. 108s and between the channel region 108i and the drain region 108d.

[0276] The region 108f functions as either a high resistance region or a low resistance region. The resistance region has a resistance equivalent to that of the channel region 108i and is a conductive region that functions as a gate electrode. This is the region where the film 112 does not overlap. When the region 108f is a high resistance region, the region 108f is This functions as a so-called offset region. When the region 108f functions as an offset region, In order to suppress the decrease in the on-current of the transistor 100C, the channel length (L ) direction, the region 108f may be set to 1 μm or less.

[0277] The low resistance region is a region having a resistance lower than that of the channel region 108i and a resistance lower than that of the source region 10 The region 108f is a low-resistance region. In this case, the region 108f is a so-called LDD (Lightly Doped Drain) region. When the region 108f functions as an LDD region, the drain This allows for the relaxation of the electric field in the drain region, thereby reducing the threshold voltage of the transistor due to the electric field in the drain region. This can reduce fluctuations in the value voltage.

[0278] When the region 108f is used as an LDD region, for example, the insulating film 116 is 8f is supplied with one or more of nitrogen, hydrogen, and fluorine, or the insulating film 110 and the conductive film 11 By adding an impurity element from above the conductive film 112_1 using the conductive film 112_1 as a mask, The impurities pass through the conductive film 112_1 and the insulating film 110 and are added to the oxide semiconductor film 108. It can be formed by

[0279] 24(B), in the opening 143, the conductive film 112_2 and the conductive The membrane 106 is connected.

[0280] The other configurations of the transistor 100C are the same as those of the transistor 100A shown above. and has the same effect.

[0281] The transistor 100D shown in FIGS. 25A and 25B has a stacked structure of a conductive film 112, a conductive film The shape of the insulating film 110 and the shape of the insulating film 112 are different from those of the transistor 100A.

[0282] The conductive film 112 of the transistor 100D is a conductive film 112_1 on the insulating film 110 and a conductive film 112_2 on the insulating film 110. The conductive film 112_2 is formed on the conductive film 112_1. The insulating film 110 is formed on the outer side of the lower end of the conductive film 112_2. For example, the conductive film 112_1 and the conductive film 112_2 are formed on the outer side of the lower end of the conductive film 112_1. The conductive film 112_2 and the insulating film 110 are processed using the same mask. 12_1 is processed by wet etching, and the insulating film 110 is processed by dry etching. By performing this process, the above structure can be achieved.

[0283] In addition, like the transistor 100C, the transistor 100D has an oxide semiconductor film 1 A region 108f may be formed in the SiO2 layer. The region 108f may be a channel region 108i. and the source region 108s, and between the channel region 108i and the drain region 108d. is formed.

[0284] 25(B), in the opening 143, the conductive film 112_2 and the conductive The membrane 106 is connected.

[0285] The other configurations of the transistor 100D are the same as those of the transistor 100A shown above. and has the same effect.

[0286] <2-4. Transistor configuration example 3>

[0287] 26(A) and 26(B) are cross-sectional views of the transistor 100E, and FIGS. 27(A) and 27(B) are cross-sectional views of the transistor 100E. 28(A) and 28(B) are cross-sectional views of the transistor 100G. 29(A) and (B) are cross-sectional views of a transistor 100H, and FIG. 30 1A and 1B are cross-sectional views of a transistor 100J. Transistor 100F, transistor 100G, transistor 100H, and transistor The top view of the transistor 100J is the same as that of the transistor 100A shown in FIG. Therefore, the explanation here will be omitted.

[0288] Transistor 100E, transistor 100F, transistor 100G, transistor The transistor 100H and the transistor 100J are the same as the transistor 100A shown above, except that they are oxide semiconductor The structure of the film 108 is different. Other configurations are the same as the transistor 100A shown above. It has the same configuration and produces the same effects.

[0289] The oxide semiconductor film 108 included in the transistor 100E shown in FIGS. The oxide semiconductor film 108_1 on the insulating film 104 and the oxide semiconductor film 108_1 on the oxide semiconductor film 108_1 an oxide semiconductor film 108_2 and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2; The channel region 108i, the source region 108s, and the drain region 108d are The oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3 are respectively It has a three-layer laminated structure of 108_3.

[0290] The oxide semiconductor film 108 included in the transistor 100F illustrated in FIGS. The oxide semiconductor film 108_2 on the insulating film 104 and the oxide semiconductor film 108_2 The semiconductor layer 108_3 includes a channel region 108i, a source region 108s, and The drain region 108d is formed by the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. It has a two-layer laminated structure of 08_3.

[0291] The oxide semiconductor film 108 included in the transistor 100G illustrated in FIGS. The oxide semiconductor film 108_1 on the insulating film 104 and the oxide semiconductor film 108_1 on the oxide semiconductor film 108_1 The semiconductor layer 108_2 also includes a channel region 108i, a source region 108s, and The drain region 108d is formed by the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2. It has a two-layer laminated structure of 08_2.

[0292] The oxide semiconductor film 108 included in the transistor 100H shown in FIGS. The oxide semiconductor film 108_1 on the insulating film 104 and the oxide semiconductor film 108_1 on the oxide semiconductor film 108_1 an oxide semiconductor film 108_2 and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2; The channel region 108i is formed by the oxide semiconductor film 108_1 and the oxide semiconductor film 108 The source region 108s and the oxide semiconductor film 108_2 are stacked. The drain region 108d is formed of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2, respectively. The transistor 100H has a two-layer stack structure of 108_2. In the cross section in the direction perpendicular to the plane, the oxide semiconductor film 108_3 is It covers the side surface of the semiconductor film 108_2.

[0293] The oxide semiconductor film 108 included in the transistor 100J illustrated in FIGS. The oxide semiconductor film 108_2 on the insulating film 104 and the oxide semiconductor film 108_2 The channel region 108i includes the oxide semiconductor film 108_3. 2 and an oxide semiconductor film 108_3, and The drain region 108d has a single-layer structure of the oxide semiconductor film 108_2. In the cross section of the transistor 100J in the channel width (W) direction, the oxide semiconductor film 108 The oxide semiconductor film 108_3 covers the side surface of the oxide semiconductor film 108_2.

[0294] The side surface or the vicinity of the channel region 108i in the channel width (W) direction is processed. Damage in the Therefore, even if the channel region 108i is substantially intrinsic, When stress such as an electric field is applied, the channel width ( The side surface or its vicinity in the W direction is activated and tends to become a low-resistance (n-type) region. When the side surface of the channel region 108i in the channel width (W) direction or its vicinity is an n-type region, Since the n-type region serves as a path for carriers, a parasitic channel may be formed.

[0295] Therefore, in the transistor 100H and the transistor 100J, the channel region The channel region 108i has a stacked structure, and the side surface of the channel region 108i in the channel width (W) direction is By using this structure, the side surface of the channel region 108i is covered with one of the layers. or suppressing defects on or near the side of the channel region 108i. This makes it possible to reduce the adhesion of impurities to the substrate.

[0296] [Band structure] Here, the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 104 The band structure of the insulating film 110, the insulating film 104, the oxide semiconductor films 108_2 and 108_3, and The band structure of the insulating film 110, the insulating film 104, the oxide semiconductor films 108_1 and 108_2, and the The band structure of the insulating layer 110 will be described with reference to FIGS. 31(A), 31(B), and 31(C). 31(A), (B), and (C) show the band structure in the channel region 108i. do.

[0297] FIG. 31(A) shows the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3. 3 is an example of a band structure in the thickness direction of a laminated structure having the insulating film 110. 1(B) shows the insulating film 104, the oxide semiconductor films 108_2 and 108_3, and the insulating film 110. FIG. 31(C) shows an example of a band structure in the film thickness direction of a laminated structure having an insulating film. 104, a stacked structure including oxide semiconductor films 108_1 and 108_2, and an insulating film 110. This is an example of a band structure in the film thickness direction. For ease of understanding, the band structure is shown as an insulating film. 104, the oxide semiconductor films 108_1, 108_2, 108_3, and the insulating film 110 The energy level (Ec) at the lower band edge is shown.

[0298] 31(A) shows a case where silicon oxide films are used as the insulating films 104 and 110, and an oxide semiconductor film is used as the insulating film. The metal oxide film 108_1 has an atomic ratio of In:Ga:Zn=1:3:2. An oxide semiconductor film formed using a metal target was used as the oxide semiconductor film 108_2. A metal oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1 was used. The oxide semiconductor film 108_3 is formed by using an oxide semiconductor film formed by adding an atom of a metal element. Oxide formed using a metal oxide target with a numerical ratio of In:Ga:Zn=1:3:2 FIG. 1 is a band diagram of a configuration using a semiconductor film.

[0299] 31(B) shows a case where silicon oxide films are used as the insulating films 104 and 110, and an oxide semiconductor film is used as the insulating film. The conductor film 108_2 is made of a metal having an atomic ratio of In:Ga:Zn=4:2:4.1. The oxide semiconductor film 108_3 is formed using an oxide semiconductor film formed using an oxide target. A metal oxide target with an atomic ratio of metal elements of In:Ga:Zn=1:3:2 was used. FIG. 10 is a band diagram of a structure using an oxide semiconductor film formed by

[0300] 31(C) shows a case where silicon oxide films are used as the insulating films 104 and 110, and an oxide semiconductor film is used as the insulating film. The metal oxide film 108_1 has an atomic ratio of In:Ga:Zn=1:3:2. An oxide semiconductor film formed using a metal target was used as the oxide semiconductor film 108_2. A metal oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1 was used. FIG. 10 is a band diagram of a structure using an oxide semiconductor film formed by

[0301] As shown in FIG. 31A, in the oxide semiconductor films 108_1, 108_2, and 108_3, In addition, as shown in Figure 31(B), the energy level at the bottom of the conduction band changes gradually. As shown, the energy level of the conduction band minimum in the oxide semiconductor films 108_2 and 108_3 is As shown in FIG. 31C, the oxide semiconductor films 108_1 and 1 In O8_2, the energy level at the bottom of the conduction band changes smoothly. It can be said that the band structure changes continuously or is a continuous junction. For this purpose, the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or the oxide At the interface between the semiconductor film 108_2 and the oxide semiconductor film 108_3, trap centers and recombination Assume that there are no impurities that form defect levels such as coalescence centers.

[0302] In order to form a continuous junction in the oxide semiconductor films 108_1, 108_2, and 108_3, A multi-chamber deposition system (sputtering system) equipped with a load lock chamber was used. It is necessary to laminate each film successively without exposing it to the atmosphere.

[0303] By using the structure shown in FIGS. 31A, 31B, and 31C, the oxide semiconductor film 108_2 is formed in a well. In a transistor using the above stacked structure, the channel region becomes an oxide semiconductor (well). It can be seen that it is formed on the conductive film 108_2.

[0304] Note that by providing the oxide semiconductor films 108_1 and 108_3, defect states can be reduced by It can be placed farther away from the semiconductor film 108_2.

[0305] In addition, the defect level is at the bottom of the conduction band of the oxide semiconductor film 108_2 which functions as a channel region. The energy level (Ec) can be farther from the vacuum level, and electrons accumulate in the defect level. When electrons accumulate in the defect level, they become a fixed negative charge. Therefore, the threshold voltage of the transistor is shifted in the positive direction. is closer to the vacuum level than the energy level (Ec) of the conduction band minimum of the oxide semiconductor film 108_2. By doing so, electrons are less likely to accumulate in the defect level. This increases the on-state current of the transistor and also increases the field-effect mobility. can be increased.

[0306] The oxide semiconductor films 108_1 and 108_3 are more conductive than the oxide semiconductor film 108_2. The energy level of the bottom of the conduction band is close to the vacuum level. The energy levels of the conduction band minimums of the oxide semiconductor films 108_1 and 108_3 are The difference between the energy levels is 0.15 eV or more, or 0.5 eV or more and 2 eV or less, That is, the electron affinity of the oxide semiconductor films 108_1 and 108_3 is The electron affinity of the oxide semiconductor film 108_2 is larger than that of the oxide semiconductor film 108_1. The electron affinity of the oxide semiconductor film 108_3 and the electron affinity of the oxide semiconductor film 108_2 are The difference is 0.15 eV or more, or 0.5 eV or more and 2 eV or less, or 1 eV or more Below.

[0307] With such a structure, the oxide semiconductor film 108_2 serves as a main current path. That is, the oxide semiconductor film 108_2 functions as a channel region. The films 108_1 and 108_3 function as oxide insulating films. The films 108_1 and 108_3 constitute the oxide semiconductor film 108_2 in which a channel region is formed. It is preferable to use an oxide semiconductor film formed of one or more metal elements. By using such a structure, the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2, Alternatively, the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3 may be diffused at the interface between them. Therefore, the movement of carriers is not hindered at the interface, and therefore, The field effect mobility of the transistor increases.

[0308] The oxide semiconductor films 108_1 and 108_3 function as part of a channel region. To prevent this, a material with sufficiently low electrical conductivity must be used. The conductive films 108_1 and 108_3 are each made of oxide insulating material in view of their physical properties and / or functions. Alternatively, the oxide semiconductor films 108_1 and 108_3 may be formed by using a material having a high electron affinity (vacuum the energy level difference between the conduction band minimum and the conduction band minimum) is smaller than that of the oxide semiconductor film 108_2, The energy level of the conduction band minimum is the same as that of the oxide semiconductor film 108_2. The material with a difference (band offset) is used. In order to suppress the difference in threshold voltage depending on the thickness of the oxide semiconductor film 108, The energy levels of the conduction band minimums of the oxide semiconductor film 108_1 and 108_3 are higher than the conduction band minimum of the oxide semiconductor film 108_2. It is preferable to use a material whose energy level is closer to the vacuum level than the lower energy level. For example, oxide The energy level of the conduction band minimum of the semiconductor film 108_2 and the oxide semiconductor films 108_1 and 108_2 are The difference in energy level between the conduction band minimum of 8_3 and the It is preferable that the above is set.

[0309] The oxide semiconductor films 108_1 and 108_3 each contain a spinel crystal structure. It is preferable that the oxide semiconductor films 108_1 and 108_3 do not contain spinel-type crystals. When the spinel type crystal structure is included, the conductive film 120 The constituent elements of the oxide semiconductor film 108_2 may diffuse into the oxide semiconductor film 108_2. When the oxide semiconductor films 108_1 and 108_3 are CAAC-OS films, which will be described later, This is preferable because it increases the blocking properties of the constituent elements of 120a and 120b, such as copper.

[0310] In this embodiment, the oxide semiconductor films 108_1 and 108_3 are made of a metal The atomic ratio of the elements was In:Ga:Zn=1:3:2. However, the present invention is not limited to this. The compound semiconductor films 108_1 and 108_3 are made of In:Ga:Zn=1:1:1 [atomic ratio] ], In:Ga:Zn=1:1:1.2[atomic ratio], In:Ga:Zn=1:3:4[ Atomic ratio], In:Ga:Zn=1:3:6 [Atomic ratio], In:Ga:Zn=1:4: 5 [atomic ratio], In:Ga:Zn=1:5:6 [atomic ratio], or In:Ga:Zn Oxide semiconductor film formed using a metal oxide target with an atomic ratio of 1:10:1 Alternatively, the oxide semiconductor films 108_1 and 108_3 may be formed using a metal element. Oxide semiconductors formed using a metal oxide target with an atomic ratio of Ga:Zn=10:1 In this case, the oxide semiconductor film 108_2 may have an atomic ratio of metal elements of Oxide semiconductor formed using a metal oxide target with an In:Ga:Zn=1:1:1 ratio The oxide semiconductor films 108_1 and 108_3 are formed by using a Ga:Z When an oxide semiconductor film formed using a metal oxide target of n=10:1 is used, The energy level of the bottom of the conduction band of the oxide semiconductor film 108_2 and the energy level of the oxide semiconductor film 108_1, The difference in energy level between the conduction band minimum of 108_3 and that of 108_3 can be made 0.6 eV or more. This is therefore preferable.

[0311] Note that the oxide semiconductor films 108_1 and 108_3 are made of In:Ga:Zn=1:1:1 When a metal oxide target having an atomic ratio of 108 is used, the oxide semiconductor films 108_1 and 108 _3 is the case where In:Ga:Zn=1:β1(0<β1≦2):β2(0<β2≦2) In addition, the oxide semiconductor films 108_1 and 108_3 may be formed of In:Ga:Zn=1 When a metal oxide target having an atomic ratio of 1:3:4 is used, the oxide semiconductor film 108_1 , 108_3 is In:Ga:Zn=1:β3(1≦β3≦5):β4(2≦β4≦6) In addition, the oxide semiconductor films 108_1 and 108_3 may be formed of In:Ga: When a metal oxide target with an atomic ratio of Zn=1:3:6 is used, the oxide semiconductor film 1 08_1 and 108_3 are In:Ga:Zn=1:β5(1≦β5≦5):β6(4≦β 6≦8).

[0312] <2-5. Transistor configuration example 4> 32(A) is a top view of the transistor 300A, and FIG. 32(B) is a top view of the transistor 300A. 32(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 32(C). 2(A) along the dashed line Y1-Y2 in FIG. In (A), in order to avoid complication, some of the components of the transistor 300A are The insulating film (which functions as a gate insulating film, etc.) is omitted in the illustration. When the -X2 direction is called the channel length direction and the dashed dotted line Y1-Y2 direction is called the channel width direction Note that the top views of the transistors in the following drawings are the same as those in FIG. Similarly, some of the components may be omitted in the drawings.

[0313] The transistor 300A shown in FIG. 32 includes a conductive film 304 on a substrate 302 and a and an insulating film 306 on the conductive film 304, an insulating film 307 on the insulating film 306, and an insulating film 307 on the insulating film 307. the oxide semiconductor film 308, the conductive film 312a over the oxide semiconductor film 308, and the oxide semiconductor and a conductive film 312b on the film 308. Insulating films 314 and 316 are formed over the conductive films 312a and 312b and the oxide semiconductor film 308. An insulating film 318 is provided.

[0314] In the transistor 300A, the insulating films 306 and 307 are A, and the insulating films 314, 316, and 318 function as the gate insulating films of the transistor The insulating film functions as a protective insulating film for the transistor 300A. The conductive film 304 functions as a gate electrode, and the conductive film 312a functions as a source electrode. The conductive film 312b functions as a drain electrode.

[0315] In this specification and the like, the insulating films 306 and 307 are referred to as the first insulating film, and the insulating film 314, The insulating film 316 may be referred to as a second insulating film, and the insulating film 318 may be referred to as a third insulating film. .

[0316] The transistor 300A shown in FIG. 32 has a channel-etched transistor structure. The oxide semiconductor film of one embodiment of the present invention can be suitably used for a channel-etch transistor. This can be done.

[0317] <2-6. Transistor configuration example 5> 33(A) is a top view of the transistor 300B, and FIG. 33(B) is a top view of the transistor 300B. 33(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 33(C). 3(A) along the dashed line Y1-Y2.

[0318] The transistor 300B shown in FIG. 33 includes a conductive film 304 on a substrate 302 and a and an insulating film 306 on the conductive film 304, an insulating film 307 on the insulating film 306, and an insulating film 307 on the insulating film 307. the oxide semiconductor film 308, the insulating film 314 over the oxide semiconductor film 308, and the insulating film 314 through the insulating film 316 and the opening 341a provided in the insulating film 314 and the insulating film 316. The conductive film 312a electrically connected to the oxide semiconductor film 308, the insulating film 314, and the insulating film The insulating film 316 is electrically connected to the oxide semiconductor film 308 through an opening 341b. The conductive film 312b is formed on the transistor 300B, more specifically, on the conductive film 31 An insulating film 318 is provided on the layers 2 a and 312 b and the insulating film 316 .

[0319] In the transistor 300B, the insulating films 306 and 307 are B, and the insulating films 314 and 316 function as gate insulating films for the oxide semiconductor film 308 The insulating film 318 functions as a protective insulating film for the transistor 300B. In the transistor 300B, the conductive film 304 functions as a gate The conductive film 312a functions as a source electrode, and the conductive film 3 12b functions as a drain electrode.

[0320] The transistor 300A shown in FIG. 32 has a channel-etched structure. On the other hand, the transistor 300B shown in FIGS. 33(A), (B), and (C) has a channel protection structure. The oxide semiconductor film of one embodiment of the present invention is also suitable for a channel protective transistor. It can be used.

[0321] <2-7. Transistor configuration example 6> 34(A) is a top view of the transistor 300C, and FIG. 34(B) is a top view of the transistor 300C. 34(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 34(C). 4(A) along the dashed line Y1-Y2.

[0322] The transistor 300C shown in FIG. 34 is the same as the transistors shown in FIGS. 33(A), 33(B), and 33(C). The shape of the insulating films 314 and 316 differs from that of the transistor 300B. The insulating films 314 and 316 are provided in an island shape on the channel region of the oxide semiconductor film 308. The other configurations are the same as those of the transistor 300B.

[0323] <2-8. Transistor configuration example 7> FIG. 35(A) is a top view of the transistor 300D, and FIG. 35(B) is a top view of the transistor 300D. 35(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 35(C). 5(A) along the dashed line Y1-Y2.

[0324] The transistor 300D shown in FIG. 35 includes a conductive film 304 on a substrate 302 and a and an insulating film 306 on the conductive film 304, an insulating film 307 on the insulating film 306, and an insulating film 307 on the insulating film 307. the oxide semiconductor film 308, the conductive film 312a over the oxide semiconductor film 308, and the oxide semiconductor The conductive film 312b over the oxide semiconductor film 308, the conductive films 312a and 312b, and the oxide semiconductor film 308 an insulating film 314 on the insulating film 314, an insulating film 316 on the insulating film 314, and an insulating film 318 on the insulating film 316; and conductive films 320a and 320b on the insulating film 318.

[0325] In the transistor 300D, the insulating films 306 and 307 are The insulating films 314, 316, and 318 function as the first gate insulating film of the transistor D. The second gate insulating film of the transistor 300D also functions as a second gate insulating film. In D, the conductive film 304 functions as a first gate electrode, and the conductive film 320a functions as a second gate electrode. The conductive film 320b functions as a pixel electrode used in a display device. The conductive film 312a also functions as a source electrode. The film 312b functions as a drain electrode.

[0326] As shown in FIG. 35(C), the conductive film 320a is formed on the insulating films 306, 307, 314, In the openings 342b and 342c formed in the conductive film 316 and 318, Therefore, the conductive film 320a and the conductive film 304 are applied with the same potential.

[0327] In the transistor 300D, openings 342b and 342c are provided, and the conductive film 3 Although the configuration in which 20a and the conductive film 304 are connected has been exemplified, the present invention is not limited to this. , only one of the openings 342b and 342c is formed, and the conductive film 3 20a and the conductive film 304 are connected, or openings 342b and 342c are provided. In this case, the conductive film 320a and the conductive film 304 may not be connected to each other. In the case where the conductive film 320a and the conductive film 304 are not connected, the conductive film 320a and the conductive film 304 are Each of the electrodes can be given a different potential.

[0328] The conductive film 320b is formed through the openings 342a provided in the insulating films 314, 316, and 318. , and is connected to the conductive film 312b via the conductive film 312c.

[0329] The transistor 300D has the S-channel structure described above.

[0330] <2-9. Transistor configuration example 8> In addition, the oxide semiconductor film included in the transistor 300A shown in FIGS. 308 may have a multi-layer structure. An example of this case is shown in FIGS. 36(A) and 36(B) and 37. Shown in (A) and (B).

[0331] 36(A) and 36(B) are cross-sectional views of the transistor 300E, and FIGS. 37(A) and 37(B) are cross-sectional views of the transistor 300E. 1 and 2 are cross-sectional views of the transistor 300F. The diagram is similar to the transistor 300A shown in FIG.

[0332] The oxide semiconductor film 308 included in the transistor 300E illustrated in FIGS. 36A and 36B is an oxide semiconductor film. an oxide semiconductor film 308_1, an oxide semiconductor film 308_2, and an oxide semiconductor film 308_3 37(A) and 37(B) include an oxide semiconductor. The oxide semiconductor film 308 includes an oxide semiconductor film 308_2 and an oxide semiconductor film 308_3.

[0333] Note that the conductive film 304, the insulating film 306, the insulating film 307, the oxide semiconductor film 308, and the oxide semiconductor film 309 are Conductor film 308_1, oxide semiconductor film 308_2, oxide semiconductor film 308_3, conductive film 31 2a, 312b, insulating films 314, 316, 318, and conductive films 320a, 3 20b are the conductive film 106, the insulating film 116, and the oxide semiconductor film 10 8, oxide semiconductor film 108_1, oxide semiconductor film 108_2, oxide semiconductor film 108_3 , conductive films 120a and 120b, insulating films 104, insulating films 118, insulating films 116, and conductive films The same material as 112 can be used.

[0334] <2-10. Transistor configuration example 9> 38(A) is a top view of the transistor 300G, and FIG. 38(B) is a top view of the transistor 300G. 38(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 38(C). 8(A) along the dashed line Y1-Y2.

[0335] The transistor 300G shown in FIG. 38 includes a conductive film 304 on a substrate 302 and a and an insulating film 306 on the conductive film 304, an insulating film 307 on the insulating film 306, and an insulating film 307 on the insulating film 307. the oxide semiconductor film 308, the conductive film 312a over the oxide semiconductor film 308, and the oxide semiconductor The conductive film 312b over the oxide semiconductor film 308, the conductive film 312a, and the conductive film 312b are An insulating film 314 on the insulating film 314, an insulating film 316 on the insulating film 314, and a conductive film on the insulating film 316. 320a and a conductive film 320b on the insulating film 316.

[0336] The insulating film 306 and the insulating film 307 have an opening 351. On the film 307, a conductive film 312 electrically connected to the conductive film 304 through the opening 351 is formed. The insulating film 314 and the insulating film 316 have an opening that reaches the conductive film 312b. The conductive film 312c has a portion 352a and an opening 352b that reaches the conductive film 312c.

[0337] The oxide semiconductor film 308 is formed by stacking an oxide semiconductor film 308_2 on the conductive film 304 side and an oxide semiconductor film 308_3 on the conductive film 304 side. and an oxide semiconductor film 308_3 on the oxide semiconductor film 308_2.

[0338] An insulating film 318 is provided on the transistor 300G. The insulating film 316 is formed to cover the conductive film 320a and the conductive film 320b.

[0339] In the transistor 300G, the insulating films 306 and 307 are G, and the insulating films 314 and 316 function as the first gate insulating film of the transistor 3 The insulating film 318 functions as a second gate insulating film of the transistor 300. In the transistor 300G, the conductive film 3 The conductive film 320a functions as a first gate electrode, and the conductive film 320b functions as a second gate electrode. The conductive film 320b functions as a pixel electrode used in a display device. In the transistor 300G, the conductive film 312a functions as a source electrode. The conductive film 312b functions as a drain electrode. In 0G, the conductive film 312c functions as a connection electrode.

[0340] The transistor 300G has the S-channel structure described above.

[0341] In addition, the structures of the transistors 300A to 300G can be freely combined. They may also be used in combination.

[0342] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0343] (Embodiment 3) In this embodiment, one of the display devices including the semiconductor device exemplified in the previous embodiment will be described. An example will be described below with reference to FIGS.

[0344] 39 is a top view showing an example of a display device. The display device 700 shown in FIG. A pixel portion 702 is provided on the first substrate 701, and a source driver 703 is provided on the second substrate 701. The pixel section 702, the source driver circuit section 704, the gate driver circuit section 706, a sealant 712 disposed to surround the path portion 704 and the gate driver circuit portion 706; and a second substrate 705 provided so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are The first substrate 701, the sealant 712, and the second substrate 705 seal the entire structure. Although not shown in FIG. 39, a display element is provided between the first substrate 701 and the second substrate 705. It can be done.

[0345] The display device 700 is surrounded by a sealant 712 on the first substrate 701. The pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are arranged in a region different from the region. and a flexible printed circuit (FPC) terminal 708 (FPC: Flex Also, an FPC terminal portion 708 An FPC 716 is connected to the pixel section 702 and the source driver circuit. Various signals are supplied to the path section 704 and the gate driver circuit section 706. 702, a source driver circuit section 704, a gate driver circuit section 706, and an FPC terminal section Signal lines 710 are connected to the respective terminals 708. Various signals are supplied by an FPC 716. Signals are transmitted through signal lines 710 to the pixel section 702, the source driver circuit section 704, the gate driver The driver circuit portion 706 and the FPC terminal portion 708 are connected to the wiring board 704 .

[0346] Furthermore, the display device 700 may be provided with a plurality of gate driver circuits 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example in which the pixel portion 702 is formed on the same first substrate 701 is shown, the present invention is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit etc. is formed (for example, A driving circuit board formed of a monocrystalline semiconductor film or a polycrystalline semiconductor film is formed on a first substrate 701. The method of connecting the separately formed drive circuit board is not particularly limited. Instead of COG (Chip On Glass) method, wire bonding method, etc. can be used.

[0347] The display device 700 also includes a pixel section 702, a source driver circuit section 704, and a gate The driver circuit section 706 includes a plurality of transistors.

[0348] The display device 700 can also include various elements, such as: For example, electroluminescence (EL) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements, LEDs, etc.), light-emitting transistor elements (which emit light according to the current) transistors), electron emission elements, liquid crystal elements, electronic ink elements, electrophoretic elements, Low-wetting element, plasma display panel (PDP), MEMS (micro- Electro-mechanical systems) displays (e.g., grating light bulbs) GLV (Glass Laser Diode), Digital Micromirror Device (DMD), Digital Microshaft Distributed Membrane Switching (DMS) element, Interferometric Modulation (IMOD) element ), piezoelectric ceramic displays, etc.

[0349] An example of a display device using an EL element is an EL display. An example of a display device using emission elements is a field emission display (FE D) or SED type flat panel display (SED: Surface-conductive n Electron-emitter Display) etc. An example of such a display device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). Displays, reflective LCD displays, direct-view LCD displays, projection LCD displays Examples of display devices using electronic ink elements or electrophoretic elements include: There are also semi-transmissive LCD displays and reflective LCD displays. In this case, a part or all of the pixel electrode should function as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum, silver, etc. In this case, a memory circuit such as an SRAM may be provided under the reflective electrode. This can further reduce power consumption.

[0350] The display method of the display device 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying colors include R It is not limited to the three colors GB (R stands for red, G stands for green, B stands for blue). For example, It may be composed of four pixels: a pixel, a B pixel, and a W (white) pixel. As in the column, two colors of RGB make up one color element, and different two You can also select a color and configure it by adding one or more colors such as yellow, cyan, magenta, etc. to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, but also to monochrome display devices. It can also be applied to a display device.

[0351] Also, white light is emitted from the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) In order to display full color using (W), a colored layer (also called a color filter) is used. The colored layer may be, for example, red (R), green (G), blue (B), or the like. ), yellow (Y), etc. can be used in combination as appropriate. In this case, the color reproducibility can be improved compared to when no color layer is used. By disposing a region having a colored layer and a region not having a colored layer, The white light in the region may be directly used for display. By placing the color layer in the display, the decrease in brightness caused by the color layer can be reduced during bright display, and power consumption can be reduced by 2. However, it may be possible to reduce the emission by approximately 100% to 30%. When using optical elements to display full color, R, G, B, Y, and W are emitted by each color. By using a self-luminous element, it is possible to make the light emitted from a colored layer. In some cases, power consumption can be further reduced.

[0352] In addition, as a colorization method, a part of the light emitted from the above-mentioned white light is passed through a color filter. In addition to the color filter method, which converts red, green, and blue by filtering, A method that uses each color of light (three-color method), or a method that uses part of the light emitted from the blue light to emit red or A method of converting to green (color conversion method, quantum dot method) may also be applied.

[0353] In this embodiment, a liquid crystal element and an EL element are used as display elements. 40 to 42. Note that FIGS. 40 and 41 are diagrams showing the chained dotted line shown in FIG. This is a cross-sectional view taken along line QR, and shows a configuration in which a liquid crystal element is used as a display element. 42 is a cross-sectional view taken along the dashed line QR in FIG. 39, and shows a display device using an EL element as a display element. This is the configuration used.

[0354] First, the common parts shown in Figures 40 to 42 will be explained, and then the different parts will be explained. This will be explained below.

[0355] <3-1. Explanation of common parts of display devices> The display device 700 shown in FIGS. 40 to 42 includes a wiring portion 711, a pixel portion 702, and a , a source driver circuit section 704, and an FPC terminal section 708. The line portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and The source driver circuit portion 704 includes a transistor 752. Has.

[0356] Transistor 750 and transistor 752 are similar to transistor 100A shown above. The transistors 750 and 752 have the following configurations. Other transistors shown in the embodiment may also be used.

[0357] The transistor used in this embodiment is made of a highly purified oxide in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. This allows for longer retention times for electrical signals such as signals, and the write interval can also be extended when the power is on. Therefore, the frequency of refresh operations can be reduced, resulting in reduced power consumption. It has the effect of suppressing force.

[0358] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed driving can be used in a liquid crystal display. By using this in a display device, the switching transistor in the pixel section and the driver circuit section can be In other words, the driver transistor can be formed on the same substrate as a separate driver circuit. Therefore, it is not necessary to use a semiconductor device formed from a silicon wafer or the like. The number of components can be reduced. By using a register, high quality images can be provided.

[0359] The capacitor 790 has a conductive film that functions as a first gate electrode of the transistor 750. The lower electrode is formed through a process of processing the same conductive film as the film, and the transistor 750 is A conductive film serving as a source electrode and a drain electrode, or a second gate electrode and an upper electrode formed through a process of processing the same conductive film as the functional conductive film. In addition, a first gate insulating film of the transistor 750 is provided between the lower electrode and the upper electrode. an insulating film formed through a process of forming the same insulating film as the insulating film that functions as the transistor; The insulating film that functions as the protective insulating film on the transistor 750 is formed through a process. That is, the capacitor 790 has a dielectric film formed between a pair of electrodes. It has a laminated structure in which an insulating film that functions as a film is sandwiched.

[0360] 40 to 42, a transistor 750, a transistor 752, and a capacitor A planarization insulating film 770 is provided on the capacitor 790 .

[0361] 40 to 42, the transistor 750 and the The transistor 752 in the source driver circuit portion 704 has the same structure as the transistor 752 in the source driver circuit portion 704. However, the present invention is not limited to this. For example, the pixel section 702 and the source A transistor different from that of the driver circuit section 704 may be used. A top-gate transistor is used for the source driver circuit section 702, and a bottom-gate transistor is used for the source driver circuit section 704. Alternatively, a bottom-gate transistor may be used in the pixel portion 702. and a top-gate transistor is used in the source driver circuit section 704. The source driver circuit section 704 may be referred to as a gate driver circuit section. It may be read differently.

[0362] The signal line 710 is connected to the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed through the same process as the conductive film that functions as the signal line 710. When materials containing ZnO are used, signal delays caused by wiring resistance are minimal, making it possible to display on a large screen. It becomes Noh.

[0363] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 71. 6. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed through the same process as the conductive film that functions as the drain electrode. , and is electrically connected to a terminal of the FPC 716 via an anisotropic conductive film 780 .

[0364] The first substrate 701 and the second substrate 705 may be made of, for example, glass. In addition, the first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. do.

[0365] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film. The distance (cell gap) between the first substrate 701 and the second substrate 705 is controlled. It should be noted that the structures 778 may be spherical spacers.

[0366] On the second substrate 705 side, there is a light-shielding film 738 that functions as a black matrix, A colored film 736 that functions as a color filter, a light-shielding film 738, and a film that contacts the colored film 736 An insulating film 734 is provided.

[0367] <3-2. Configuration example of a display device using a liquid crystal element> The display device 700 shown in FIG. 40 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film The conductive film 774 is formed on the second substrate 705. The display device 700 shown in FIG. The alignment state of the liquid crystal layer 776 changes depending on the voltage applied to the conductive film 772 and the conductive film 774. This controls whether light is transmitted or not, allowing images to be displayed.

[0368] The conductive film 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed over the planarization insulating film 770. The pixel electrode functions as one electrode of the display element.

[0369] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a light-transmitting property in visible light can be used. For example, a material containing one of the elements selected from indium (In), zinc (Zn), and tin (Sn) As a conductive film that is reflective in visible light, for example, aluminum Alternatively, a material containing silver may be used.

[0370] When a conductive film that is reflective to visible light is used as the conductive film 772, the display device 700 The liquid crystal display device is a reflective type. When using the above, the display device 700 becomes a transmissive liquid crystal display device.

[0371] In addition, by changing the structure on the conductive film 772, the driving method of the liquid crystal element can be changed. An example of this case is shown in FIG. 41. The display device 700 shown in FIG. This is an example of a configuration using a horizontal electric field method (e.g., FFS mode) as the driving method. In the structure shown in FIG. 1, an insulating film 773 is provided over a conductive film 772, and a conductive film 773 is provided over the insulating film 773. In this case, the conductive film 774 is used as a common electrode. The insulating film 773 functions as a conductive film. The orientation state of the liquid crystal layer 776 can be controlled by the field.

[0372] Although not shown in FIGS. 40 and 41, either the conductive film 772 or the conductive film 774 An alignment film is provided on either one or both of the surfaces of the substrate 771 and the liquid crystal layer 776. 40 and 41, a polarizing member, a phase difference member, a reflecting member, etc. may be used. Optical members (optical substrates) such as a polarizing substrate and a positioning member may be provided as appropriate. Circularly polarized light produced by a retardation substrate may also be used. Either may be used.

[0373] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, The liquid crystals that can be used include polymer dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, the liquid crystal material can be in a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0374] In addition, when the in-plane switching method is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. Therefore, in order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. Since the liquid crystal display has a short rotational speed and is optically isotropic, no alignment treatment is required. Since the rubbing process is unnecessary, electrostatic damage caused by the rubbing process is prevented. This can prevent defects and damage to the liquid crystal display device during the manufacturing process. Furthermore, liquid crystal materials exhibiting a blue phase have little viewing angle dependency.

[0375] When a liquid crystal element is used as a display element, a TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero) lectric Liquid Crystal) mode, AFLC (AntiFerr It can be used in dielectric liquid crystal mode. .

[0376] Furthermore, normally black type liquid crystal display devices, such as those employing vertical alignment (VA) mode, The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode Mode, ASV mode, etc. can be used.

[0377] <3-3. Display devices using light-emitting elements> The display device 700 shown in FIG. 42 includes a light-emitting element 782. The light-emitting element 782 includes a conductive film The display device 700 shown in FIG. The EL layer 786 of the light element 782 emits light, thereby displaying an image. The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0378] Materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. In addition, materials that can be used for quantum dots include colloidal quantum dots. materials, alloy-type quantum dot materials, core-shell-type quantum dot materials, core-type quantum dot materials, Also, the elements of the 12th and 16th families, the 13th and 15th families, or the 14th and 16th families Materials containing the element group may also be used. Alternatively, cadmium (Cd), selenium (Se), Zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (P b) Quantum atoms with elements such as gallium (Ga), arsenic (As), and aluminum (Al). Dot material may also be used.

[0379] The organic compounds and inorganic compounds described above can be prepared by, for example, deposition methods (including vacuum deposition methods). The method used is a droplet ejection method (also called an inkjet method), a coating method, a gravure printing method, etc. The EL layer 786 can be formed using a low molecular weight material, a medium molecular weight material (o The polymer may comprise a polymeric material, such as a polymeric polymer (including a polymeric polymer, a dendrimer, or a polymer).

[0380] Here, a method for forming the EL layer 786 by droplet discharge will be described with reference to FIG. 45(A) to 45(D) are cross-sectional views illustrating a method for manufacturing the EL layer 786. be.

[0381] First, a conductive film 772 is formed over a planarization insulating film 770. The insulating film 730 is formed as shown in FIG. 45(A).

[0382] Next, a droplet is discharged from a droplet discharge device 783 to an exposed portion of the conductive film 772, which is an opening in the insulating film 730. Droplets 784 are ejected to form a layer 785 containing the composition. The droplets 784 contain the composition including the solvent. and is attached onto the conductive film 772 (see FIG. 45B).

[0383] The step of discharging the droplets 784 may be performed under reduced pressure.

[0384] Next, the solvent is removed from the layer 785 containing the composition, and the layer is solidified to form an EL layer 786. (See Figure 45(C)).

[0385] The solvent may be removed by a drying step or a heating step.

[0386] Next, a conductive film 788 is formed on the EL layer 786 to form a light emitting element 782 (FIG. 45( See D).

[0387] In this way, when the EL layer 786 is formed by the droplet discharge method, the composition can be selectively discharged. This reduces material waste. Since no additional steps are required, the process can be simplified and costs can be reduced.

[0388] The droplet discharge method described above is a method of discharging a composition using a nozzle having a discharge port, or one or more is a general term for anything that has a means for ejecting droplets, such as a head having multiple nozzles.

[0389] Next, a droplet discharge device used in the droplet discharge method will be described with reference to FIG. 14 is a conceptual diagram illustrating a droplet ejection device 1400. FIG.

[0390] The droplet discharge device 1400 has a droplet discharge means 1403. 3 has a head 1405 and a head 1412.

[0391] The head 1405 and the head 1412 are connected to a control means 1407, which controls the computer. By controlling the image forming apparatus 1410, it is possible to draw a pattern in a pre-programmed manner. can.

[0392] The timing of drawing may be, for example, the timing of the marker 1 formed on the substrate 1402. Alternatively, the reference point may be determined based on the outer edge of the substrate 1402. Here, the marker 1411 is detected by the imaging means 1404, and the image processing means 1 The signal converted into a digital signal by 409 is recognized by a computer 1410 and a control signal is generated. The generated signal is sent to the control means 1407.

[0393] The imaging means 1404 may be a charge coupled device (CCD) or a complementary metal oxide semiconductor ( An image sensor using a CMOS (Complementary Metal Oxide Semiconductor) can be used. The information of the pattern to be formed is stored in the storage medium 1408. Based on this, a control signal is sent to the control means 1407, and the individual heads 1 of the droplet discharging means 1403 are controlled. The material to be discharged is supplied from the material supply source 1. 413, a material supply source 1414 is connected to the head 1405 and the head 1412 through piping. and supplied.

[0394] The inside of the head 1405 is a space for filling the liquid material as shown by the dotted line 1406, and a space for discharging the material. Although not shown, head 1412 is also a head 1. The head 1405 and the head 1412 have the same internal structure. By providing a head with a different size, different materials can be printed at different widths simultaneously. It is possible to discharge and draw multiple types of luminescent materials, etc., and when drawing over a wide area, In order to improve throughput, the same material is ejected from multiple nozzles simultaneously to create a pattern. When a large substrate is used, the head 1405 and the head 1412 move over the substrate as shown in FIG. 6. Freely scan in the X, Y, and Z directions shown in the figure to freely set the area to be drawn. This allows the same pattern to be drawn multiple times on a single substrate.

[0395] The step of discharging the composition may be carried out under reduced pressure. After the composition is discharged, one or both of the steps of drying and baking are carried out. Both processes involve heat treatment, but the purpose, temperature and time are different. The drying and firing processes are carried out under normal or reduced pressure by laser light irradiation, instantaneous thermal annealing, or heating. The timing and number of times of this heat treatment are not particularly limited. In order to perform the drying and baking processes well, the temperature at that time should be adjusted depending on the material and composition of the substrate. It depends on the nature of the composition.

[0396] As described above, the EL layer 786 can be manufactured using a droplet discharge apparatus.

[0397] Returning to the description of the display device 700 shown in FIG.

[0398] In the display device 700 shown in FIG. 42, an insulating film 770 is formed on the planarizing insulating film 770 and the conductive film 772. The insulating film 730 covers part of the conductive film 772. Therefore, the conductive film 788 has a light-transmitting property, and the EL layer 7 In this embodiment, the top emission structure For example, a bottom that emits light to the conductive film 772 side is shown. A dual emission structure in which light is emitted to both the conductive film 772 and the conductive film 788 is also used. It can also be applied to mission structures.

[0399] A colored film 736 is provided at a position overlapping the light-emitting element 782, and a colored film 736 is provided at a position overlapping the insulating film 730. A light-shielding film 738 is provided in the position where the light-shielding film 738 is to be drawn, the wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 1, a configuration in which a colored film 736 is provided is exemplified. For example, when the EL layer 786 is formed by coloring, The film 736 may not be provided.

[0400] <3-4. Example of a configuration in which an input / output device is provided in a display device> Furthermore, the display device 700 shown in FIGS. 41 and 42 may be provided with an input / output device. An example of the force device is a touch panel.

[0401] 43 and 42 show a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. 41. FIG. 44 shows a configuration in which a touch panel 791 is provided on a display device 700.

[0402] FIG. 43 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. 44 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. be.

[0403] First, the touch panel 791 shown in FIGS. 43 and 44 will be described below.

[0404] The touch panel 791 shown in FIGS. 43 and 44 is made of a second substrate 705 and a colored film 736. The touch panel 791 is a so-called in-cell type touch panel that is provided between the colored film. It may be formed on the second substrate 705 side before forming 736 .

[0405] The touch panel 791 includes a light-shielding film 738, an insulating film 792, an electrode 793, and an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797. When a detection object such as a stylus approaches, a change in capacitance between electrode 793 and electrode 794 occurs. It is possible to detect the change.

[0406] 43 and 44, an electrode 793 and The electrode 796 is formed through an opening in the insulating film 795. 43. The electrode 794 is electrically connected to the two electrodes 793 that sandwich the electrode 794 via the 44 illustrates a configuration in which the region where the electrode 796 is provided is provided in the pixel portion 702. However, the present invention is not limited to this, and may be formed in the source driver circuit section 704, for example.

[0407] The electrodes 793 and 794 are provided in a region overlapping with the light-shielding film 738. As shown in FIG. 1, the electrode 793 is preferably provided so as not to overlap with the light-emitting element 782. As shown in FIG. 44, the electrode 793 is provided so as not to overlap with the liquid crystal element 775. In other words, the electrode 793 overlaps with the light-emitting element 782 and the liquid crystal element 775. In other words, the electrode 793 has a mesh shape. By configuring the electrode 793 in this manner, the electrode 793 does not block the light emitted from the light emitting element 782. Alternatively, the electrode 793 may have a structure that does not block light that passes through the liquid crystal element 775. Therefore, the reduction in brightness due to the placement of the touch panel 791 is extremely small. Since the number of pixels is small, a display device with high visibility and reduced power consumption can be realized. The pole 794 may have a similar configuration.

[0408] In addition, since the electrodes 793 and 794 do not overlap with the light-emitting element 782, The electrode 794 can be made of a metal material with low transmittance for visible light. Since the electrodes 793 and 794 do not overlap with the liquid crystal element 775, For example, a metal material having low transmittance of visible light can be used.

[0409] Therefore, compared with electrodes using oxide materials with high visible light transmittance, The resistance of the electrode 794 can be reduced, improving the sensor sensitivity of the touch panel. It is possible.

[0410] For example, the electrodes 793, 794, and 796 may be made of conductive nanowires. The nanowires have an average diameter of 1 nm to 100 nm, preferably 5 nm to 50 nm. The size of the nanoparticles may be 5 nm or less, more preferably 5 nm or more and 25 nm or less. The wires may be metal nanowires such as Ag nanowires, Cu nanowires, or Al nanowires. For example, the electrodes 793 and 794 may be made of wires or carbon nanotubes. When Ag nanowires are used for either 94 or 796, or both, the The light transmittance is 89% or more, and the sheet resistance is 40Ω / □ or more and 100Ω / □ or less. can.

[0411] 43 and 44 illustrate the configuration of an in-cell type touch panel. For example, a so-called on-cell type transistor formed on the display device 700 may be used. a touch panel or a so-called out-cell type touch panel that is attached to the display device 700 It may also be possible to use the following.

[0412] In this way, the display device of one embodiment of the present invention can be used in combination with various types of touch panels. It can be used.

[0413] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0414] (Fourth embodiment) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0415] <4. Circuit configuration of display device> The display device shown in FIG. 47(A) has a region having pixels of a display element (hereinafter referred to as a pixel portion 502). ) and a circuit section ( hereinafter referred to as a drive circuit section 504), and a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 50 6) and a terminal portion 507. Note that the protection circuit 506 is not provided. That's fine.

[0416] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When a part or all of the pixel portion 502 is not formed on the same substrate, the driving circuit A part or the whole of the path portion 504 is COG or TAB (Tape Automated Bearing). It can be implemented by

[0417] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device has a circuit for driving a plurality of display elements (hereinafter referred to as pixel circuit 501), The path section 504 is a circuit (hereinafter referred to as a gate driver) that outputs a signal (scanning signal) for selecting a pixel. 504a), for supplying signals (data signals) for driving the display elements of the pixels. The source driver 504b includes a driving circuit such as the circuit (hereinafter referred to as a source driver 504b).

[0418] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is inputted through the terminal section 507, and a signal for outputting the shift register is outputted. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc. The gate driver 504a receives a scanning signal and outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 504a are provided, and the plurality of gate drivers 504a drive the scanning lines GL_1 to Alternatively, the gate driver 504a may control the GL_X by dividing it into the initialization signal However, the gate driver 50 has a function of supplying 4a may also provide other signals.

[0419] The source driver 504b includes a shift register and the like. Through the terminal section 507, signals for driving the shift register as well as the source of the data signal are transmitted. The source driver 504b receives a signal (image signal) that is to be output from the pixel circuit The source driver 504b has a function of generating a data signal to be written to the source driver 501. A data signal is generated in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of a data signal. The data lines DL_1 to DL_Y are connected to the data lines DL_2 through DL_Y. Alternatively, the source driver 504b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b may also supply other signals. It is possible.

[0420] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a plurality of analog switches, The image signal can be time-divided and output as a data signal. The source driver 504b may be configured using the same.

[0421] Each of the plurality of pixel circuits 501 is connected to one of the plurality of scanning lines GL to which a scanning signal is applied. A pulse signal is input via the data line DL, and a data signal is given via one of the data lines DL. Each of the pixel circuits 501 is connected to a gate driver 504a controls writing and holding of data of the data signal. The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or less than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via the input terminal 504a (n is a natural number equal to or less than Y).

[0422] The protection circuit 506 shown in FIG. 47(A) is, for example, a gate driver 504a and a pixel circuit 5 01. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The data line DL is connected between the driver 504b and the pixel circuit 501. The protection circuit 506 can be connected to the wiring between the gate driver 504a and the terminal section 507. Alternatively, the protection circuit 506 may be formed by wiring between the source driver 504b and the terminal section 507. The terminal section 507 can be connected to a power supply and a line from an external circuit to the display device. This refers to the part where terminals for inputting control signals and image signals are provided.

[0423] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit 506 This is a circuit that brings one wire into electrical continuity with another wire.

[0424] As shown in FIG. 47A, a pixel section 502 and a driver circuit section 504 are provided with a protection circuit 50. 6, ESD (Electro Static Discharge: This can improve the resistance of the display device to overcurrents caused by electrostatic discharges and the like. However, the configuration of the protection circuit 506 is not limited to this. For example, A configuration in which a protection circuit 506 is connected, or a configuration in which the protection circuit 506 is connected to the source driver 504b Alternatively, a configuration in which a protection circuit 506 is connected to the terminal portion 507 may be used. It can also be done as follows.

[0425] In FIG. 47(A), the gate driver 504a and the source driver 504b Therefore, although an example in which the driver circuit portion 504 is formed is shown, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a separately prepared source driver circuit is formed. A substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is implemented. It may also be configured to be equipped with

[0426] Furthermore, the plurality of pixel circuits 501 shown in FIG. 47(A) may be, for example, a configuration shown in FIG. 47(B). It can be said that:

[0427] The pixel circuit 501 shown in FIG. 47B includes a liquid crystal element 570, a transistor 550, and a capacitor. The transistor 550 may be any of the transistors described in the previous embodiments. can be applied.

[0428] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 included in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. One of the electrodes may be given a different potential.

[0429] For example, the display device including the liquid crystal element 570 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned Mode) Micro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid Crystal id Crystal) mode, AFLC (AntiFerroelectric Li Quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode may also be used. In addition to the above-mentioned driving method, the display device can also be driven by an ECB (Electric Carrier Board) or the like. Ally Controlled Birefringence mode, PDLC (P Polymer Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest However, there are various types of liquid crystal elements and their driving methods, and they are not limited to these. A variety of materials can be used.

[0430] In the pixel circuit 501 in the mth row and the nth column, the source electrode or the drain electrode of the transistor 550 One of the electrodes is electrically connected to the data line DL_n, and the other is connected to a pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the other of the electrodes of the scan line G. L_m. The transistor 550 can be turned on or off. This provides a function of controlling the writing of data signals.

[0431] One of the pair of electrodes of the capacitor 560 is connected to a wiring to which a potential is supplied (hereinafter, a potential supply line VL ) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

[0432] For example, in a display device having the pixel circuit 501 of FIG. 47(B), The pixel circuits 501 in each row are sequentially selected by the gate driver 504a shown in FIG. 550 is turned on and data of the data signal is written.

[0433] The pixel circuit 501 in which data has been written is turned off by turning off the transistor 550. By repeating this process for each row, an image can be displayed.

[0434] Furthermore, the plurality of pixel circuits 501 shown in FIG. 47(A) may be, for example, a configuration shown in FIG. 47(C). It can be said that:

[0435] The pixel circuit 501 shown in FIG. 47C includes transistors 552 and 554 and a capacitor. The transistor 552 and the transistor 554 The transistor described in the above embodiment can be used for either one or both of the above. .

[0436] One of the source and drain electrodes of the transistor 552 is supplied with a data signal. The transistor is electrically connected to a wiring (hereinafter referred to as a data line DL_n). The gate electrode 552 is connected to the wiring to which the gate signal is given (hereinafter referred to as the scanning line GL_m). are electrically connected.

[0437] Transistor 552 is turned on or off to transfer the data of the data signal. It has the function of controlling the writing of data.

[0438] One of the pair of electrodes of the capacitor 562 is connected to a wiring to which a potential is applied (hereinafter, a potential supply line VL _a), and the other is electrically connected to the source electrode and drain electrode of the transistor 552. The second electrode is electrically connected to the other of the first and second electrodes.

[0439] The capacitor 562 functions as a storage capacitor for holding written data.

[0440] One of the source electrode and the drain electrode of the transistor 554 is connected to the potential supply line VL_a. Furthermore, the gate electrode of transistor 554 is electrically connected to the It is electrically connected to the other of the source electrode and the drain electrode.

[0441] One of the anode and cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b. The other is electrically connected to the other of the source electrode and drain electrode of the transistor 554. will be done.

[0442] The light emitting element 572 may be, for example, an organic electroluminescence element (also known as an organic EL element). However, the light emitting element 572 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0443] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0444] In a display device having the pixel circuit 501 of FIG. 47(C), for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written by turning it on.

[0445] The pixel circuit 501 to which the data has been written is turned off by turning off the transistor 552. Furthermore, the transistor 554 is held in a holding state in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 The light is emitted at a brightness that corresponds to the flow rate. By repeating this process row by row, an image can be displayed.

[0446] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0447] (Embodiment 5) In this embodiment, a display module and an electronic device including a semiconductor device according to one embodiment of the present invention will be described. This will be explained using FIGS. 48 to 51.

[0448] <5-1. Display module> The display module 7000 shown in FIG. 48 includes an upper cover 7001 and a lower cover 7002. Between them, touch panel 7004 connected to FPC7003 and A display panel 7006, a backlight 7007, a frame 7009, a printed circuit board 701 0, has battery 7011.

[0449] The semiconductor device of one embodiment of the present invention can be used for the display panel 7006, for example.

[0450] The upper cover 7001 and the lower cover 7002 are connected to the touch panel 7004 and the display panel The shape and dimensions can be changed as needed to fit the size of the 7006.

[0451] The touch panel 7004 is a resistive or capacitive touch panel. The display panel 7006 can be used by overlapping it with the opposing substrate (sealing substrate) of the display panel 7006. It is also possible to provide the display panel 7 with a touch panel function. It is also possible to provide an optical sensor in each pixel of 006 to make it an optical touch panel.

[0452] The backlight 7007 has a light source 7008. In FIG. Although the configuration in which the light source 7008 is disposed on the base 7007 has been described as an example, the present invention is not limited to this. For example, a light source 7008 is arranged at the end of a backlight 7007, and a light diffusion plate is further used. In addition, when a self-luminous light emitting element such as an organic EL element is used, or when a reflective In the case of a flat panel or the like, the backlight 7007 may not be provided.

[0453] The frame 7009 not only protects the display panel 7006 but also prevents the movement of the printed circuit board 7010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the The frame 7009 may also function as a heat sink.

[0454] The printed circuit board 7010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 7011 provided separately. This can be omitted if a commercial power source is used.

[0455] The display module 7000 also includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may also be provided in addition.

[0456] <5-2.Electronic equipment 1> Next, examples of electronic devices are shown in FIGS. 49(A) to 49(E).

[0457] FIG. 49(A) shows the appearance of the camera 8000 with the viewfinder 8100 attached. This is a diagram.

[0458] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, and a shutter. The camera 8000 has a button 8004 and the like. The camera 8000 also has a detachable lens 8006. It is attached.

[0459] Here, the camera 8000 is assumed to have a lens 8006 that is detached from the housing 8001 and replaced. However, the lens 8006 and the housing may be integrated.

[0460] The camera 8000 can capture an image by pressing the shutter button 8004. The display unit 8002 also functions as a touch panel. It is also possible to take an image by

[0461] The housing 8001 of the camera 8000 has a mount with electrodes, and a finder 810 In addition to the 0, strobe devices etc. can also be connected.

[0462] The finder 8100 includes a housing 8101, a display unit 8102, buttons 8103, etc. .

[0463] The housing 8101 has a mount that engages with the mount of the camera 8000, The mount can be attached to the camera 8000. The image received from the camera 8000 through the electrode is displayed on the display unit 8102. It can be done.

[0464] The button 8103 functions as a power button. The 8102 display can be switched on and off.

[0465] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are The display device according to one embodiment of the present invention can be applied.

[0466] In FIG. 49(A), the camera 8000 and the finder 8100 are separate electronic devices. These are configured to be detachable, but the housing 8001 of the camera 8000 is equipped with a display device. The camera may have a built-in viewfinder.

[0467] FIG. 49(B) is a diagram showing the appearance of the head mounted display 8200.

[0468] The head-mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 82 8203, a display unit 8204, a cable 8205, etc. It has a built-in 8206 battery.

[0469] A cable 8205 supplies power from a battery 8206 to the main body 8203. 03 is equipped with a wireless receiver and the like, and image information such as received image data is displayed on a display unit 8204. In addition, the camera installed in the main body 8203 can record the movements of the user's eyeballs and eyelids. By capturing the user's viewpoint and calculating the coordinates of the user's viewpoint based on that information, It can be used as an input means.

[0470] Furthermore, the wearing unit 8201 may be provided with a plurality of electrodes at positions that come into contact with the user. The main body 8203 detects the current flowing through the electrodes in accordance with the movement of the user's eyeballs, The device may have a function to recognize the user's point of view. By doing so, the attachment unit 820 may have a function of monitoring the pulse of the user. The sensor 1 may have various sensors such as a temperature sensor, a pressure sensor, an acceleration sensor, etc. The device may have a function to display the user's biological information on the display unit 8204. The image displayed on the display unit 8204 is changed according to the movement of the part. Good too.

[0471] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0472] 49(C), (D), and (E) are diagrams showing the appearance of the head-mounted display 8300. The head mounted display 8300 includes a housing 8301, a display portion 8302, and a backlight. The lens 8302 has a braided fixture 8304 and a pair of lenses 8305 .

[0473] A user can view the display on the display unit 8302 through the lens 8305 . It is preferable to arrange the display portion 8302 in a curved state. By doing so, the user can feel a high sense of realism. Although the configuration in which one display unit 8302 is provided has been illustrated, the present invention is not limited to this. For example, In this case, one display is provided for each eye of the user. If the configuration is such that the display section is arranged, it will be possible to perform 3D display using parallax. .

[0474] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of this invention has extremely high definition. Even if the image is enlarged using the lens 8305, the pixels are not visible to the user, and the image is displayed more clearly. This makes it possible to display images with a higher sense of reality.

[0475] <5-3.Electronic equipment 2> Next, an example of an electronic device different from the electronic devices shown in FIGS. 49(A) to 49(E) is shown in FIG. 0(A) to 50(G).

[0476] The electronic device shown in FIGS. 50A to 50G includes a housing 9000, a display portion 9001, a screen Speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminal Child 9006, sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, number of rotations, distance, Light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions to measure flow rate, humidity, gradient, vibration, odor or infrared rays), It has 9008, etc.

[0477] The electronic devices shown in Figures 50(A) to 50(G) have various functions. Function to display various information (still images, videos, text images, etc.) on the display, touch panel function , calendar, date or time display functions, various software (programs) a function for controlling processing by wireless communication, a function for controlling various computers by wireless communication, Functions for connecting to a network and transmitting or receiving various data using wireless communication functions The function of reading out the program or data recorded on the recording medium and displaying it on the display unit. The electronic devices shown in FIGS. The functions that can be possessed by the device are not limited to these, and the device can have a variety of functions. Although not shown in FIGS. 50(A) to 50(G), the electronic device may have a plurality of display units. The electronic device may be provided with a camera or the like to take still images. , the function to shoot videos, and save the captured images to a recording medium (external or built-in to the camera) The image capturing device may have a function of capturing an image, a function of displaying a captured image on a display unit, and the like.

[0478] The electronic devices shown in FIGS. 50(A) to 50(G) will be described in detail below.

[0479] FIG. 50(A) is a perspective view showing a television device 9100. 100 is a display unit 9001 with a large screen of, for example, 50 inches or more or 100 inches or more. It is possible to incorporate.

[0480] 50(B) is a perspective view showing a portable information terminal 9101. For example, the device has one or more functions selected from a telephone, a notebook, an information viewing device, etc. Specifically, it can be used as a smartphone. A speaker, a connection terminal, a sensor, and the like may be provided. Image information can be displayed on multiple sides of the screen. For example, three operation buttons 9050 ( Operation icons (also referred to as "icons") can be displayed on one side of the display unit 9001. Also, information 9051 shown in a dashed rectangle can be displayed on the other side of the display unit 9001. Examples of information 9051 include emails and social networking sites (SNS). Display to notify you of incoming calls, e-mails, SNS, etc. Subject, sender name of email or SNS, date and time, time, remaining battery level, antenna reception Or, instead of the information 9051, Alternatively, operation buttons 9050 and the like may be displayed.

[0481] 50(C) is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 is , and has the function of displaying information on three or more surfaces of the display unit 9001. An example is shown in which information 9053 and information 9054 are displayed on different sides. The user of the portable information terminal 9102 stores the portable information terminal 9102 in the breast pocket of his / her clothes. In this state, the display (information 9053 in this case) can be confirmed. The telephone number or name of the caller is displayed in a position that can be observed from above the mobile information terminal 9102. The user can view the display without taking the mobile information terminal 9102 out of his pocket. You can check the call and decide whether to accept it or not.

[0482] 50(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The 9200 is suitable for mobile phone calls, e-mail, document browsing and writing, music playback, and internet communications. It is possible to run various applications such as computer games. The display surface of the display unit 9001 is curved, and the display is performed along the curved display surface. In addition, the portable information terminal 9200 can perform short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, handset The mobile information terminal 9200 also has a connection terminal 9006. It has a connector and can directly exchange data with other information terminals. Charging can also be performed via the connection terminal 9006. It may also be possible to supply power wirelessly without going through 6.

[0483] 50(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. FIG. 50(E) is a perspective view of the mobile information terminal 9201 in an unfolded state, and FIG. (F) shows the mobile information terminal 9201 being changed from one of the unfolded state and the folded state to the other. 50(G) is a perspective view of the portable information terminal 9201 in a folded state. The portable information terminal 9201 is highly portable when folded, and is easily portable when unfolded. When the display is turned on, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 01 is made up of three housings 9000 connected by hinges 9055. The two housings 9000 are supported by the hinge 9055. This allows the portable information terminal 9201 to be reversibly transformed from an unfolded state to a folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. It can be done.

[0484] Next, the electronic devices shown in FIGS. 49(A) to 49(E) and the electronic devices shown in FIGS. 50(A) to 50(E) An example of an electronic device different from the electronic device shown in (G) is shown in Figures 51(A) and (B). (B) is a perspective view of a display device having a plurality of display panels. 51(A) is a perspective view of a state in which a plurality of display panels are rolled up, and FIG. 51(B) is a perspective view of a state in which a plurality of display panels are rolled up. FIG. 1 is a perspective view of the roll in an unfolded state.

[0485] The display device 9500 shown in FIGS. 51(A) and 51(B) includes a plurality of display panels 9501 and a shaft portion 9 511 and a bearing portion 9512. The plurality of display panels 9501 have a display area 9502 and a light-transmitting region 9503.

[0486] The display panels 9501 are flexible. The filters 9501 are arranged so that they partially overlap each other. The light-transmitting region 9503 of the display panel 9501 can be overlapped. By using the display panel 9501, a large screen display device can be provided. The display panel 9501 can be rolled up depending on the situation, making it a versatile display. It can be a display device.

[0487] 51(A) and 51(B), the display area 9502 is located on the adjacent display panel 950. 1 shows a state in which the display panels are spaced apart, but this is not limited to this. For example, the display panels 9 By overlapping the display areas 9502 of the 501 without any gaps, a continuous display area 9502 is created. You may do so.

[0488] The electronic device described in this embodiment has a display unit for displaying some information. However, the semiconductor device of one embodiment of the present invention is an electronic device that does not have a display portion. It can also be applied to vessels.

[0489] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. [Example]

[0490] In this example, an In-Ga-Zn oxide film was formed using the method shown in the above embodiment. (hereinafter referred to as IGZO film) and the results of elemental analysis are described below.

[0491] In the sample according to this embodiment, In-Ga-Zn oxide (atomic ratio In:Ga:Zn=5: 1:7) target was used for sputtering, aiming for a film thickness of 100 nm on a glass substrate. An IGZO film was formed on the substrate. The IGZO film was formed using a gas atmosphere containing 200 sccm of argon gas. The atmospheric pressure was controlled to 0.6 Pa, the substrate temperature was set to room temperature, and 2.5 kW of AC power was applied. And so he went.

[0492] The IGZO film of the prepared sample was observed using HAADF-STEM images and EDX. The HAADF-STEM images and EDX measurements were performed using a JEOL Ltd. A molecular resolution analytical electron microscope JEM-ARM200F was used, and the accelerating voltage was 200 kV and the beam The electron beam was irradiated with a diameter of approximately 0.1 nm.

[0493] In addition, for EDX measurements, the energy dispersive X-ray analyzer JED-2 was used as the elemental analyzer. A Si drift detector was used to detect the X-rays emitted from the sample. Ta.

[0494] In EDX measurement, each point in the analysis area of ​​the sample is irradiated with an electron beam, and the resulting The energy and frequency of the characteristic X-rays of the sample are measured, and the EDX spectrum corresponding to each point is obtained. In this example, the peaks in the EDX spectrum at each point are determined as electron transitions to the L shell of the In atom, Electron transition to the K shell of Ga atom, electron transition to the K shell of Zn atom, and electron transition to the K shell of O atom The ratio of each atom at each point was calculated. By performing EDX analysis on the region, it is possible to obtain EDX mapping that shows the distribution of the ratio of each atom. can be done.

[0495] The HAADF-STEM image and EDX mapping of the sample IGZO film are shown in Figure 52 and The results are shown in Figure 53. Figure 52 shows the HAADF-STEM image and EDX map of the IGZO film. Figure 53 shows the HAADF-STEM image and EDX mapping of the cross section of the IGZO film. Figure 52(A) and Figure 53(A) are HAADF-STEM images of the sample. In addition, Fig. 52(B) and Fig. 53(B) are EDX mappings of O atoms, and Fig. 52(C) and and Fig. 53(C) are EDX mappings of Zn atoms, and Fig. 52(D) and Fig. 53(D) are This is EDX mapping of Ga atoms, and Figure 52(E) and Figure 53(E) are EDX mapping of In atoms. The HAADF-STEM images and EDX mapping in Figures 52 and 53 are The magnification is 7.2 million times.

[0496] 52(B) to 52(E) and 53(B) to 53(E). The bar above the X-mapping indicates the ratio of each atom at each point in the IGZO film [atom mic%].

[0497] In the EDX mapping shown in Figures 52 and 53, a distribution of relative brightness can be seen in the image. It can be seen that each atom exists with a certain distribution in the IGZO film. 2(B) to 52(E), and the frame 1A and frame 1B shown in Figs. 53(B) to 53(E). Pay attention to boxes 2A and 2B shown.

[0498] In Figure 52(E) and Figure 53(E), frames 1A and 2A contain many relatively bright areas. In other words, the frames 1A and 2A are made of In elements. Box 1B and box 2B are regions with relatively few In atoms. In FIG. 52(E) and FIG. 53(E), the relatively bright area is area A shown in the above embodiment. The relatively dark area corresponds to area B1 shown in the above embodiment.

[0499] In contrast to FIGS. 52(E) and 53(E), in FIGS. 52(D) and 53(D), frame 1 A and frame 2A contain many relatively dark areas, while frame 1B and frame 2B contain relatively bright areas. In other words, the regions in boxes 1A and 2A contain relatively few Ga atoms, while the regions in boxes 1B and Frame 2B is a region where Ga atoms are relatively abundant. In the region where there are relatively few Ga atoms, and in the region where there are relatively few In atoms, there are relatively many Ga atoms. Therefore, the relatively bright areas in Figure 52(D) and Figure 53(D) are The relatively dark area roughly corresponds to the area B1 shown in the above embodiment. It roughly corresponds to area A1.

[0500] In Figures 52(C) and 53(C), the frames 1B and 2B contain many relatively bright areas. Frames 1A and 2A contain bright areas, though not as bright as frames 1B and 2B. Frames 1B and 2B are regions with relatively many Zn atoms, and frames 1A and 2A are regions with relatively many Zn atoms. This is a region that contains Zn atoms, although not as many as in frame 2B.

[0501] Similarly, looking at FIG. 52(B) and FIG. 53(B), frame 1A, frame 1B, frame 2A It can be seen that the area in frame 2B is a region with a relatively large number of oxygen atoms.

[0502] Thus, the region A1 of the IGZO film contains many In atoms and O atoms, and the region B1 Therefore, the region A1 is a region containing Zn atoms, for example, indium It is suggested that the region contains a large amount of indium oxide, In-Zn oxide, etc. A1 acts as a region that is more conductive than region B1, and therefore This contributes to an increase in mobility and on-current.

[0503] Here, the area corresponding to the area A1 shown in FIG. 52(E) and FIG. 53(E) (for example, frame 1A If you look at the area A1 and frame 2A, you can see multiple granular parts. The diameter of the particles is observed to be between 0.5 nm and 1.5 nm. The granular parts of the image appear to be connected to each other. A1 is formed in a cloud-like shape. The granular parts included in the region A1 are the above-mentioned This corresponds to the cluster in the area A1 shown in the embodiment.

[0504] The region B1 of the IGZO film contains a large amount of Ga atoms, Zn atoms, and O atoms, and the region A Although not as many as in region B1, it is a region that contains In atoms. It is suggested that region B1 contains a large amount of n-Ga-Zn oxide. It functions as a region with higher semiconductivity, contributing to the switching characteristics of the transistor. do.

[0505] Here, the area corresponding to the area B1 shown in FIG. 52(D) and FIG. 53(D) (for example, frame 1B If we look at the area B1 and frame 2B, we can see multiple granular parts in the area B1. The granular parts of the image appear to be connected to each other. B1 is also formed in a cloud-like shape. The granular parts included in the region B1 are This corresponds to the cluster in the area B1 shown in the embodiment.

[0506] As described above, the IGZO film sample fabricated in this example has an In-rich region A1 and an I The n-poor region B1 is formed in the complex oxide semiconductor. The region B1 contributes to the on-state current and field-effect mobility of the transistor, and the region B2 contributes to the switching characteristics of the transistor. Therefore, by using this complex oxide semiconductor, it is possible to achieve a large on-current and high mobility. Therefore, it is possible to fabricate a transistor having a small S value and electrical characteristics.

[0507] This example may be any of the embodiments, at least some of which are described herein, or other implementations. The present invention can be implemented in combination with the examples as appropriate. [Example]

[0508] In this example, a composite oxide semiconductor film was formed and its crystallinity was examined by XRD. and explain.

[0509] [Sample preparation] In this example, the oxygen flow rate ratio and the substrate temperature during film formation were varied to form oxide semiconductor A sample with a membrane was prepared.

[0510] Each sample was prepared by depositing an oxide semiconductor film on a 600 mm × 720 mm glass substrate. I got more.

[0511] The oxide semiconductor film was formed by sputtering with a deposition gas flow rate of 200 sccm. The pressure was set to 0.6 Pa and the indium, gallium, and zinc A metal oxide target (In:Ga:Zn=5:1:7 [atomic ratio]) having It was formed by applying 0.5kW of AC power.

[0512] Here, three substrate temperature conditions and six oxygen flow rate conditions were used to prepare a total of 18 types of samples. The substrate temperature during film formation was set at three conditions: room temperature, 130°C, and 170°C. The oxygen flow rate was 0%. The deposition gas was oxygen. The ratio of the gas flow rate and the argon gas flow rate is set to 200 sccm. Varying conditions were used.

[0513] [XRD analysis results] XRD analysis is a type of out-of-plane method, known as the powder method (theta-2-theta method). The θ-2θ method was carried out by changing the incident angle of the X-ray and This method measures X-ray diffraction intensity by setting the angle of the detector installed at the same angle as the incident angle. The X-rays were incident from an angle of approximately 0.40° from the film surface, and the angle of the detector was changed to measure the X-ray intensity. GIXRD (Grazin Intensity Diffraction) is a type of out-of-plane method for measuring diffraction intensity. g-Incidence XRD) method (thin film method or Seemann-Bohlin method) ) may also be used.

[0514] Figure 54 shows the results of XRD measurement for each sample. The horizontal axis in Figure 54 represents the angle 2θ, and the vertical axis indicates the diffraction intensity in arbitrary units. The diffraction profiles are shown for three different locations. The upper side is the center of the board (A), the lower side is the outer periphery of the board (C), and the middle is the measurement result between A and C. The result is...

[0515] The diffraction angle at which the diffraction intensity peaked (around 2θ = 31°) was the same as that of single-crystal InGaZnO4 This corresponds to the diffraction angle of the (009) plane in the structural model. In the samples where cracks were confirmed, the c-axis was oriented in the film thickness direction (hereinafter referred to as oriented crystals). It can be seen that the .

[0516] As shown in Figure 54, a clear peak was observed when film formation was performed at room temperature and the oxygen flow rate ratio was 0%. This suggests that the proportion of oriented crystals in the film is extremely low. are.

[0517] On the other hand, even under room temperature film formation conditions, a clear peak can be obtained by adding oxygen to the film formation gas. It has been confirmed that, under film formation conditions at room temperature, when the oxygen flow rate ratio is set to 70% or more, the peak intensity There is also a downward trend.

[0518] Furthermore, when the substrate temperature is increased, a clear peak is observed even when the oxygen flow rate is 0%. In addition, when the substrate temperature was 130°C and 170°C, the deposition gas contained oxygen. As with the room temperature film formation conditions, a clearer peak is obtained when the oxygen flow rate ratio is high. Under low (70% or higher) conditions, the peak intensity tends to decrease.

[0519] From the above, the crystallinity of the oxide semiconductor film to be formed depends on the oxygen flow rate during film formation and the substrate It was confirmed that the temperature can be controlled by two conditions. However, it was found that the crystallinity could be improved by increasing the substrate temperature. In addition, even when the substrate temperature is room temperature, the crystallinity can be improved by increasing the oxygen flow rate. I found that it is possible.

[0520] This example may be any of the embodiments or other examples described at least in part herein. can be implemented in appropriate combination. [Example]

[0521] In this example, a transistor corresponding to the transistor 100A described in Embodiment 2 was fabricated. In this example, the following sample S was prepared and the electrical characteristics of the transistor were evaluated. Sample S1 was fabricated. The channel length L was 3 μm and the channel width W was 50 μm. This is a sample on which a transistor is formed.

[0522] [Preparation method of sample S1] First, a titanium film having a thickness of 10 nm and a copper film having a thickness of 100 nm were sputtered on a glass substrate. The conductive film was then processed by photolithography. Ta.

[0523] Next, four insulating layers were formed on the substrate and the conductive film. The insulating film was formed in a vacuum using a phase-enhanced chemical vapor deposition (PECVD) system. 50nm thick silicon nitride film, 300nm thick silicon nitride film, 50nm thick silicon nitride film A silicon nitride film with a thickness of 50 nm and a silicon oxynitride film with a thickness of 50 nm were used.

[0524] Next, an oxide semiconductor film is formed over the insulating film and processed into an island shape. The oxide semiconductor film 108 was formed by depositing an oxide semiconductor film having a thickness of 40 nm. The oxide semiconductor film was formed using the composite oxide semiconductor described above or C / It is IGZO.

[0525] The oxide semiconductor film was formed under the following conditions: the substrate temperature was set to room temperature (25°C), and the flow rate was set to 200 s Argon gas was introduced into the chamber of the sputtering device at a pressure of 0.6 Pa. A metal oxide target containing indium, gallium, and zinc (In:Ga: The film was formed by applying 2.5 kW of AC power to a ZnO film (Zn=5:1:7 [atomic ratio]). In this example, the oxygen flow rate ratio during the formation of the oxide semiconductor film is 0%.

[0526] Next, an insulating film having a thickness of 150 nm was formed on the insulating film and the semiconductor layer. The silicon oxynitride film was formed using a PECVD apparatus.

[0527] Next, a heat treatment was carried out. The heat treatment was carried out in a mixed gas atmosphere of nitrogen and oxygen for 3 hours. The heat treatment was carried out at 50°C for 1 hour.

[0528] Next, openings were formed in desired areas of the insulating film. The etching method was used.

[0529] Next, a conductive film was formed on the insulating film so as to cover the opening, and the conductive film was processed into an island shape. In addition, after forming the conductive film, the insulating film in contact with the lower side of the conductive film is processed. was formed.

[0530] The conductive film is a 10-nm-thick oxide semiconductor film, a 50-nm-thick titanium nitride film, and A copper film having a thickness of 100 nm was formed in this order. The plate temperature was set to 170°C, and oxygen gas with a flow rate of 200 sccm was introduced into the chamber of the sputtering equipment. The pressure was 0.6 Pa, and a gold alloy containing indium, gallium, and zinc was introduced into the bar. Metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) with 2.5kW The titanium nitride film and the copper film were formed by applying an AC power of 1000 W. It was formed using a ring apparatus.

[0531] Next, plasma treatment was performed on the semiconductor layer, the insulating film, and the conductive film. A PECVD apparatus was used, the substrate temperature was set to 220°C, and argon gas and nitrogen gas were used. The reaction was carried out under a mixed gas atmosphere.

[0532] Next, an insulating film was formed on the semiconductor layer, the insulating film, and the conductive film. A silicon nitride film with a thickness of 300 nm and a silicon oxynitride film with a thickness of 300 nm were deposited using a PECVD device. The film was formed by laminating using

[0533] Next, a mask is formed on the formed insulating film, and an opening is formed in the insulating film using the mask. did.

[0534] Next, a conductive film is formed so as to fill the opening, and the conductive film is processed into an island shape. A conductive film having a thickness of 100 μm was formed on the surface of the semiconductor substrate to become the source electrode and the drain electrode. A titanium film with a thickness of 100 nm and a copper film with a thickness of 100 nm were deposited using a sputtering device. Formed.

[0535] Next, an insulating film was formed on the insulating film and the conductive film. An acrylic photosensitive resin was used.

[0536] In this manner, sample S1 was prepared.

[0537] [Transistor Id-Vg characteristics] Next, the Id-Vg characteristics of the transistor of the sample S1 fabricated as described above were measured. The measurement conditions for the Id-Vg characteristics of the transistor are as follows: The voltage applied to the gate electrode (hereinafter also referred to as gate voltage (Vg)) and the gate electrode functioning as the second gate electrode The voltage applied to the conductive film (hereinafter referred to as back gate voltage (Vbg)) is set to -10 A voltage was applied from V to +10 V in 0.25 V steps. The voltage applied to the conductive film (hereinafter also referred to as source voltage (Vs)) is set to 0 V (comm), The voltage applied to the conductive film that functions as the drain electrode (hereinafter referred to as the drain voltage (Vd)) (c) was set to 0.1V and 20V.

[0538] FIG. 55 shows the Id-Vg characteristics of sample S1. In FIG. 55, the first vertical axis represents Id [A], the second vertical axis is the field effect mobility (μFE [cm 2 / Vs]) and the horizontal axis is Vg[ V]. The field effect mobility is measured at Vd = 20V. value.

[0539] In Figure 55, the upper limit of Id during measurement is set to 1 mA. Under the condition of Vd=20V, Id exceeds this upper limit when Vg=7.5V. Therefore, in Figure 55, the field effect mobility estimated from the Id-Vg characteristics is , the range of Vg=7.5V or less is clearly indicated.

[0540] As shown in FIG. 55, a transistor that is a semiconductor device of one embodiment of the present invention has good electrical conductivity. The characteristics of the transistor shown in FIG. 55 are shown in Table 1.

[0541] [Table 1]

[0542] As described above, the field-effect mobility of the transistor that is the semiconductor device of one embodiment of the present invention is 1 00cm 2 / Vs, which is comparable to that of low-temperature polysilicon transistors. This is a very high value, which is an astonishing characteristic for a transistor using an oxide semiconductor. It can be said that.

[0543] As shown in Table 1, sample S1 is a transistor whose gate voltage is greater than 0 V and less than 10 V. The maximum field-effect mobility in the lower range is 60 cm 2 / Vs or more 150cm 2 / Vs less a first region where the threshold voltage is -1 V or more and 1 V or less; a second region where the S value is , a third region where the off-current is less than 0.3 V / decade, and -12 Air conditioning m 2 and a fourth region where the maximum field effect mobility of the transistor is less than μFE. (max), and the field-effect mobility at a gate voltage of 2 V is expressed as μFE (Vg=2V), μFE(max) / μFE(Vg=2V) is 1 or more, 2 or less. It will be less than.

[0544] The characteristics of the above transistors are as follows: This can be achieved by using a composite oxide semiconductor, or C / IGZO, as the transistor semiconductor. By using it in the conductor layer, it has the function of high carrier mobility and good switching characteristics. It is possible to achieve both Noh and other things at the same time.

[0545] This example may be any of the embodiments, at least some of which are described herein, or other implementations. The present invention can be implemented in combination with the examples as appropriate. [Example]

[0546] In this example, a transistor corresponding to the transistor 100A described in Embodiment 2 was fabricated. The electrical characteristics and cross-sectional shape of the transistor were evaluated. In this example, the following sample S2 was fabricated. The sample S2 had a channel length L of 2 μm. The sample had a transistor with a channel width W of 3 μm.

[0547] [Preparation method of sample S2] First, a titanium film having a thickness of 10 nm and a copper film having a thickness of 100 nm were sputtered on a glass substrate. The conductive film was then processed by photolithography. Ta.

[0548] Next, four insulating layers were formed on the substrate and the conductive film. The insulating film was formed in a vacuum using a phase-enhanced chemical vapor deposition (PECVD) system. 50nm thick silicon nitride film, 100nm thick silicon nitride film, 50nm thick silicon nitride film A silicon nitride film with a thickness of 50 nm and a silicon oxynitride film with a thickness of 50 nm were used.

[0549] Next, an oxide semiconductor film is formed over the insulating film and processed into an island shape. The oxide semiconductor film 108 was formed by depositing an oxide semiconductor film having a thickness of 40 nm. The oxide semiconductor film was formed using the composite oxide semiconductor described above or C / It is IGZO.

[0550] The oxide semiconductor film was formed under the conditions of a substrate temperature of 70° C. and a flow rate of 180 sccm. Argon gas and oxygen gas at a flow rate of 20 sccm were introduced into the chamber of the sputtering device. The pressure was set to 0.6 Pa, and a metal oxide having indium, gallium, and zinc was introduced into the reactor. The target (In:Ga:Zn=4:2:4.1 [atomic ratio]) was subjected to 2.5 kW AC power. In this example, the oxide semiconductor film was formed by applying electric power. The ratio is 10%.

[0551] Next, an insulating film having a thickness of 150 nm was formed on the insulating film and the semiconductor layer. The silicon oxynitride film was formed using a PECVD apparatus.

[0552] Next, a heat treatment was carried out. The heat treatment was carried out in a mixed gas atmosphere of nitrogen and oxygen for 3 hours. The heat treatment was carried out at 50°C for 1 hour.

[0553] Next, openings were formed in desired areas of the insulating film. The etching method was used.

[0554] Next, a conductive film was formed on the insulating film so as to cover the opening, and the conductive film was processed into an island shape. In addition, after forming the conductive film, the insulating film in contact with the lower side of the conductive film is processed. was formed.

[0555] The conductive film is a first oxide semiconductor film having a thickness of 10 nm and a second oxide semiconductor film having a thickness of 90 nm. The first oxide semiconductor film was formed in this order. The temperature was set to 170°C, and oxygen gas with a flow rate of 200 sccm was introduced into the chamber of the sputtering equipment. The pressure was set to 0.6 Pa, and a metal oxide containing indium, gallium, and zinc was introduced into the The ion beam was applied to a 2.5kW ion source for a ZnO target (In:Ga:Zn=4:2:4.1 [atomic ratio]). The second oxide semiconductor film was formed by applying a current to the substrate. The temperature was set to 170°C, and the flow rate of argon gas was 180 sccm and the flow rate of oxygen was 20 sccm. The gas was introduced into the chamber of the sputtering device, the pressure was set to 0.6 Pa, and the A metal oxide target containing In, Ga, and Zn (In:Ga:Zn=4:2 The film was formed by applying 2.5 kW of AC power to a film (atomic ratio: 4.1).

[0556] Next, plasma treatment was performed on the semiconductor layer, the insulating film, and the conductive film. A PECVD apparatus was used, the substrate temperature was set to 220°C, and argon gas and nitrogen gas were used. The reaction was carried out under a mixed gas atmosphere.

[0557] Next, an insulating film was formed on the semiconductor layer, the insulating film, and the conductive film. A silicon nitride film with a thickness of 300 nm and a silicon oxynitride film with a thickness of 300 nm were deposited using a PECVD device. The film was formed by laminating using

[0558] Next, a mask is formed on the formed insulating film, and an opening is formed in the insulating film using the mask. did.

[0559] Next, a conductive film is formed so as to fill the opening, and the conductive film is processed into an island shape. A conductive film having a thickness of 50 mm was formed to become the source electrode and the drain electrode. nm thick titanium film, 400 nm thick aluminum film, and 100 nm thick titanium film , and were formed in this order using a sputtering apparatus.

[0560] Next, an insulating film was formed on the insulating film and the conductive film. An acrylic photosensitive resin was used.

[0561] In this manner, sample S2 was prepared.

[0562] [Transistor Id-Vg characteristics] Next, the Id-Vg characteristics of the transistor of the sample S2 fabricated as described above were measured. The conditions for measuring the Id-Vg characteristics of the transistor were the same as those in Example 3 described above.

[0563] FIG. 56 shows the Id-Vg characteristics of sample S2.

[0564] As shown in FIG. 56, a transistor that is a semiconductor device of one embodiment of the present invention has good electrical conductivity. The characteristics of the transistor shown in FIG. 56 are shown in Table 2.

[0565] [Table 2]

[0566] As shown in Table 2, sample S2 is a transistor whose gate voltage is greater than 0 V and less than 10 V. The maximum field-effect mobility in the lower range is 60 cm 2 / Vs or more 150cm 2 / Vs less a first region where the threshold voltage is -1 V or more and 1 V or less; a second region where the S value is , a third region where the off-current is less than 0.3 V / decade, and -12 Air conditioning m 2 and a fourth region where the maximum field effect mobility of the transistor is less than μFE. (max), and the field-effect mobility at a gate voltage of 2 V is expressed as μFE (Vg=2V), μFE(max) / μFE(Vg=2V) is 1 or more, 2 or less. It will be less than.

[0567] The characteristics of the above transistors are as follows: This can be achieved by using a composite oxide semiconductor, or C / IGZO, as the transistor semiconductor. By using it in the conductor layer, it has the function of high carrier mobility and good switching characteristics. It is possible to achieve both Noh and other things at the same time.

[0568] [Transistor cross-sectional shape] Next, the cross-sectional shape of the transistor of the sample S2 fabricated as described above was evaluated. To evaluate the cross-sectional shape of the transistor, cross-sectional STEM observation was performed. A cross-sectional STEM image of the sta

[0569] As shown in FIG. 57, it was confirmed that the sample S2 prepared in this example had a good cross-sectional shape. The channel length L was designed to be 2 μm, but the final dimension was 1.78 μm. It was confirmed that the particle size was μm.

[0570] This example may be any of the embodiments, at least some of which are described herein, or other implementations. The present invention can be implemented in combination with the examples as appropriate. [Explanation of symbols]

[0571] A1 area A2 area B1 area B2 area 100A transistor 100B transistor 100C transistor 100D transistor 100E transistor 100F transistor 100G transistor 100H transistor 100J transistor 102 Circuit Board 104 insulating film 106 Conductive film 108 Oxide semiconductor film 108_1 Oxide semiconductor film 108_2 Oxide semiconductor film 108_3 Oxide semiconductor film 108d Drain region 108f area 108i Channel Area 108s Source Area 110 insulating film 112 Conductive film 112_1 Conductive film 112_2 Conductive film 116 Insulating film 118 insulating film 120a Conductive film 120b Conductive film 122 insulating film 141a opening 141b opening 143 Opening 300A transistor 300B transistor 300C transistor 300D transistor 300E transistor 300F transistor 300G transistor 302 Substrate 304 Conductive film 306 Insulating film 307 Insulating Film 308 Oxide semiconductor film 308_1 Oxide semiconductor film 308_2 Oxide semiconductor film 308_3 Oxide semiconductor film 312a Conductive film 312b Conductive film 312c conductive film 314 Insulating film 316 Insulating Film 318 Insulating Film 320a Conductive film 320b Conductive film 341a opening 341b opening 342a opening 342b opening 342c opening 351 Opening 352a opening 352b opening 501 pixel circuit 502 pixel section 504 Drive circuit section 504a Gate Driver 504b source driver 506 Protection circuit 507 Terminal section 550 transistors 552 transistor 554 Transistor 560 Capacitor 562 Capacitor 570 Liquid Crystal Devices 572 Light-emitting element 700 Display device 701 PCB 702 pixel section 704 Source driver circuit section 705 PCB 706 Gate driver circuit section 708 FPC terminal section 710 Signal Line 711 Wiring section 712 Sealing material 716 FPC 730 insulating film 732 Sealing film 734 Insulating Film 736 Colored film 738 Light-shielding film 750 transistors 752 transistors 760 connecting electrode 770 Planarization insulating film 772 Conductive film 773 insulating film 774 Conductive film 775 Liquid Crystal Elements 776 Liquid Crystal Layer 778 Structure 780 Anisotropic Conductive Film 782 Light-emitting element 783 Droplet discharge device 784 Droplet 785 layers 786 EL layer 788 Conductive Film 790 Capacitor 791 Touch Panel 792 insulating film 793 Electrode 794 Electrode 795 insulating film 796 Electrode 797 Insulating Film 1400 Droplet discharge device 1402 PCB 1403 Droplet discharge means 1404 Imaging means 1405 Head 1406 dotted line 1407 Control means 1408 Storage medium 1409 Image processing means 1410 Computer 1411 Marker 1412 head 1413 Material Source 1414 Material Source 2190 Plasma 2192 cations 2501 Deposition chamber 2502a Target 2502b Target 2504a Sputtered particles 2504 Segregation region 2506a Sputtered particles 2506 Segregation area 2510a Backing Plate 2510b Backing Plate 2520 Target Holder 2520a Target Holder 2520b target holder 2530a Magnet Unit 2530b Magnet Unit 2530N1 Magnet 2530N2 Magnet 2530S Magnet 2532 Magnet holder 2542 parts 2560 board 2570 PCB holder 2580a magnetic field lines 2580b magnetic field lines 7000 Display Module 7001 Top cover 7002 Lower cover 7003 FPC 7004 Touch Panel 7005 FPC 7006 Display Panel 7007 Backlight 7008 Light source 7009 Frame 7010 Printed Circuit Board 7011 Battery 8000 Camera 8001 Case 8002 Display section 8003 Operation button 8004 Shutter button 8006 Lens 8100 Finder 8101 Housing 8102 Display section 8103 Button 8200 Head Mounted Display 8201 Mounting part 8202 Lens 8203 Main unit 8204 Display section 8205 Cable 8206 Battery 8300 Head Mounted Display 8301 Housing 8302 Display section 8304 Fixtures 8305 Lens 9000 chassis 9001 Display section 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Television equipment 9101 Mobile Information Terminal 9102 Mobile Information Terminal 9200 Mobile Information Terminal 9201 Mobile Information Terminal 9500 display device 9501 Display Panel 9502 Display area 9503 area 9511 Shaft 9512 Bearing section

Claims

[Claim 1] A composite oxide semiconductor in which a first region and a second region are mixed, the first region has a plurality of first clusters containing one or more elements selected from In, Zn, and O as a main component; the second region has a plurality of second clusters containing one or more elements selected from In, an element M (M is Al, Ga, Y, or Sn), Zn, and O as a main component; the first region has a portion where the plurality of first clusters are connected to each other, the second region has a portion where the plurality of second clusters are connected to each other.

Images