Semiconductor device and method of manufacturing semiconductor device

Abstract

To provide a semiconductor device which prevents influences upon embedding of a gate electrode by making possible electric field relaxation of a trench three-dimensional corner and preventing an opening width in a trench width direction from becoming narrow, and a method of manufacturing a semiconductor device.SOLUTION: A semiconductor device 100 comprises a gate insulator film 16 disposed inside of a trench 2, a gate electrode 7 including a region at least partially disposed inside of the trench 2, a JFET region 8 of a first conductivity type disposed below a channel region 5, and a body region 9 of a second conductivity type disposed on the side of the JFET region 8. In the gate insulator film 16, an oxide film 16a on a substrate surface in a trench width direction is wider than an oxide film 16b in contact with the channel region 5 in the trench width direction.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Semiconductor power elements require not only high breakdown voltage, but also low on-resistance and low switching loss, but silicon (Si) power elements, which are currently the mainstream, are approaching their theoretical performance limits. Silicon carbide (SiC) has a dielectric breakdown field strength approximately one order of magnitude greater than Si, so by making the drift layer that maintains the breakdown voltage approximately one-tenth thinner and increasing the impurity concentration by approximately 100 times, it is theoretically possible to reduce element resistance by more than three orders of magnitude. In addition, because its band gap is approximately three times larger than Si, it is also capable of high-temperature operation, and SiC semiconductor elements are expected to exceed the performance of Si semiconductor elements, and development of SiC power devices is underway.

[0003] A SiC trench-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) has a trench formed in a silicon carbide (SiC) substrate, with a gate insulating film and gate electrode inside the trench. Compared to Si power devices, it has a high breakdown voltage and low on-resistance. However, unlike Si, when using wide bandgap materials, the trench corners have a wide gap, making the breakdown voltage design of the SiO2 important. In particular, when a SiC trench-type MISFET (hereinafter referred to as "trench-type MIS") is applied, the electric field concentrates at the trench corners, generating leakage current and easily degrading the insulating film.

[0004] Generally, the maximum electric field in semiconductor devices is 4MV / cm 2 However, in trench-type MIS, the electric field concentrates at the corners of the trench, resulting in a low breakdown voltage. Examples of structures that alleviate the electric field concentration at the corners of the trench include the technologies described in Patent Documents 1 to 3.

[0005] Patent Document 1 describes a semiconductor device having a silicon carbide substrate, a drift layer formed on the upper part of the silicon carbide substrate, a body layer formed on the drift layer, a source region formed on the body layer, a first trench formed in the drift layer, the first trench having a first side surface in contact with the source region and the body layer, a first thermal oxide film formed at an intersection between the first side surface and a surface of the source region, a gate insulating film formed on an inner wall of the first trench, and a gate electrode filling the first trench.

[0006] Patent Document 2 describes a semiconductor device including: a semiconductor layer of a first conductivity type in which a gate trench is formed; a gate insulating film formed on the side and bottom surfaces of the gate trench, the gate insulating film integrally including a side insulating film on the side surfaces and a bottom insulating film on the bottom surface; and a gate electrode embedded in the gate trench, the gate electrode selectively having an overlapping portion that overlaps the surface of the semiconductor layer at an upper edge formed at an opening end of the gate trench, the side insulating film including an overhang portion at the upper edge that is selectively thicker than other portions of the side insulating film so as to protrude inward into the gate trench.

[0007] Patent Document 3 describes a buried gate type semiconductor device comprising: a plurality of buried gates that are buried in a semiconductor substrate so as to penetrate a channel semiconductor region, have long sides and short sides intersecting the long sides in a plane parallel to the substrate surface, and are repeatedly arranged at least in the length direction of the short sides; a second one-conductivity type semiconductor region formed on the surface side of the channel semiconductor region; a second other-conductivity type semiconductor region that has a bottom deeper than the bottom surface of the buried gate and is formed at least on the side of the short side of the buried gate; and a wiring layer, wherein a contact portion where the second one-conductivity type semiconductor region comes into contact with the wiring layer is located on the short side of the buried gate.

[0008] A trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a vertical channel fin structure has been proposed as a type of trench MOSFET. Fig. 15 is a perspective view schematically illustrating the structure of a trench MOSFET with a vertical channel fin structure disclosed in Patent Document 3. Fig. 16 is a cross-sectional view taken along X2-X2' in Fig. 15, and Fig. 17 is a cross-sectional view taken along Y1-Y1' in Fig. 15. Note that Fig. 15 does not illustrate the gate electrode 7, gate insulating film 6, interlayer insulating film 14, source electrode 12, and drain electrode 13. Fig. 18 is a diagram showing the positional relationship between the gate electrode, trench, and gate oxide film in the semiconductor device of Fig. 15 when viewed from the substrate surface side.

[0009] 15 has a plurality of trenches 2 arranged in a plane, with the longitudinal direction in a first direction and the lateral direction in a second direction. The trenches 2 shown by dotted lines in the cross section at the front of FIG. 15 are hypothetical positions corresponding to the trenches 2 in order to explain the positional relationship between the other components and the trenches 2. The first conductivity type source region has a fin structure in which a portion is separated by a plurality of trenches 2. For convenience of explanation, in FIG. 15 , the unseparated portion is referred to as the first source region 3, and the separated portion (divided by trenches 2) is referred to as the second source region 4.

[0010] A second conductivity type channel region 5 having a fin structure separated by a plurality of trenches 2 is formed on the underside of the second source region 4 and in contact with the second source region 4. A first conductivity type JFET (Junction Field Effect Transistor) region 8 is formed below the channel region 5, and a second conductivity type body region 9 is formed on the side of the JFET region 8. A first conductivity type drift region 10 is formed below the JFET region 8, and a first conductivity type drain region 11 is formed below the drift region 10.

[0011] 15 has a channel structure in which a gate electrode is embedded inside the trench 2 via a gate insulating film formed on the side surface of the trench 2, and a current flows in the depth direction along the side surface of the trench 2. The gate electrodes embedded inside the trench 2 are connected to each other outside the trench 2. With this structure, the trench pitch can be reduced to increase the channel density, thereby reducing the on-resistance.

[0012] As shown in FIG. 16, the semiconductor device 1 has a gate insulating film 6 disposed inside the trench 2 and a gate electrode 7 including a region at least partially disposed inside the trench 2. As shown in FIG. 17, the gate electrodes 7 disposed inside the trench 2 are connected to each other outside the trench 2. An interlayer insulating film 14 is formed between the connected portions of the gate electrodes 7 and the second source region 4. This interlayer insulating film 14 is formed so as to cover the top and side portions of the connected portions of the gate electrodes 7. The gate electrode 7 can be formed of, for example, polysilicon. [Prior art documents] [Patent documents]

[0013] [Patent Document 1] Japanese Patent Application Publication No. 2019-195030 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-232533 [Patent Document 3] Japanese Patent Application Laid-Open No. 2004-207289 Summary of the Invention [Problem to be solved by the invention]

[0014] The semiconductor device described in Patent Document 1 forms a thermal oxide film at the intersection between the side surface of the trench and the surface of the source region, thereby thickening the gate insulating film at the upper corners of the trench and alleviating the electric field at the corners. However, in Patent Document 1, the oxide film is formed in the area that normally functions as the channel, and the presence of the oxide film makes the channel width narrower than conventional ones.

[0015] Patent Document 2 is an example of a structure that alleviates the electric field at the upper corners of a trench. The semiconductor device structure described in Patent Document 2 selectively thickens the oxide film at the upper edge of the trench using a CVD method and forms overhanging oxide film portions at the trench corners, thereby alleviating the electric field in the contact trench and active region. However, in the structure described in Patent Document 2, the oxide film is thick at all edges of the trench, narrowing the trench opening width and resulting in poor gate electrode embedding. Furthermore, if the oxide film in contact with the active region's channel region is not uniform, it can lead to variations in characteristics and failure to achieve the expected threshold voltage and on-resistance. Therefore, when thickening the oxide film at the trench edge, care must be taken not to alter the oxide film in the channel region, resulting in poor controllability. Furthermore, the process described in Patent Document 2 makes it difficult to selectively thicken the oxide film in only a portion of the trench.

[0016] In the semiconductor device described in Patent Document 3 (semiconductor device 1 in Figure 15), the three-dimensional corners of the trench, where electric fields are most likely to concentrate and cause gate insulating film breakdown, are located within the second-conductivity body region, resulting in a high electric field relaxation effect when high voltages are applied. However, while a narrower trench pitch allows for a smaller cell pitch and reduced on-resistance, the trench must be large enough to accommodate the electrode. Therefore, a structure that can relax the electric field at the three-dimensional corners of the trench without affecting the electrode burying along the short side of the trench and without changing the oxide film thickness on the trench sidewalls used as the channel is essential. The three-dimensional corners are the intersections (vertices) of the XY, XZ, and YZ planes.

[0017] The present invention has been made in consideration of the above circumstances, and aims to provide a semiconductor device and a method for manufacturing the semiconductor device that enable the electric field relaxation of the three-dimensional corners of the trench while preventing the opening width in the short direction of the trench from becoming narrower, thereby not affecting the embedding of the gate electrode. [Means for solving the problem]

[0018] In order to achieve the above object, a semiconductor device of the present invention comprises: a plurality of trenches having a longitudinal direction in a first direction and a lateral direction in a second direction in a plan view, the plurality of trenches being arranged in the second direction; a first source region of a first conductivity type disposed outside the trenches in the first direction; a second source region of the first conductivity type including a region having a fin structure at least a portion of which is separated by the plurality of trenches; a channel region of a second conductivity type in contact with a lower surface of the second source region and having a fin structure separated by the plurality of trenches; a gate insulating film disposed inside the trench; a gate electrode including a region at least a portion of which is disposed inside the trench; a JFET region of the first conductivity type disposed below the channel region; and a body region of a second conductivity type disposed to a side of the JFET region, wherein the gate insulating film is characterized in that an oxide film on a substrate surface in the lateral direction of the trench is wider than an oxide film in contact with the channel region in the lateral direction of the trench. [Effects of the Invention]

[0019] According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing a semiconductor device that enable electric field relaxation in the three-dimensional corners of the trench while preventing the opening width in the short direction of the trench from narrowing, thereby not affecting the embedding of the gate electrode. [Brief explanation of the drawings]

[0020] [Figure 1] 1 is a perspective view of a semiconductor device according to a first embodiment of the present invention; [Figure 2] 2 is a cross-sectional view (X1-X1') taken in the longitudinal direction of a trench in the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 3] 2 is a cross-sectional view (X2-X2') in the longitudinal direction of a trench in the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 4A] 2 is a cross-sectional view (Y1-Y1') of the semiconductor device according to the first embodiment of the present invention, taken along the short side direction of the trench. FIG. [Figure 4B] 3 is a cross-sectional view (Y2-Y2') in the short side direction of a trench in the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 5] 2 is a diagram showing the positional relationship between a gate electrode, a trench, and a gate oxide film when viewed from the substrate surface side in the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 6] FIG. 10 is a cross-sectional view of a trench in a short side direction in a semiconductor device according to a second embodiment of the present invention. [Figure 7] FIG. 10 is a diagram showing the positional relationship between a gate electrode, a trench, and a gate oxide film when viewed from the substrate surface side in a semiconductor device according to a second embodiment of the present invention. [Figure 8A] 5A to 5C are diagrams illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 8B] 5A to 5C are diagrams illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 8C] 5A to 5C are diagrams illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 8D] 5A to 5C are diagrams illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 8E] 5A to 5C are diagrams illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 8F] 5A to 5C are diagrams illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 8G] 5A to 5C are diagrams illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 9] FIG. 10 is a diagram showing the positional relationship between a gate electrode, a trench, and a gate oxide film when viewed from the substrate surface side in a semiconductor device according to a third embodiment of the present invention. [Figure 10] FIG. 10 is a cross-sectional view taken along the longitudinal direction of a trench in a semiconductor device according to a third embodiment of the present invention. [Figure 11A]10A to 10C are diagrams illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention. [Figure 11B] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention. [Figure 11C] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention. [Figure 11D] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention. [Figure 11E] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention. [Figure 12] FIG. 10 is a diagram showing the positional relationship between a gate electrode, a trench, and a gate oxide film when viewed from the substrate surface side in a semiconductor device according to a fourth embodiment of the present invention. [Figure 13] FIG. 13 is a diagram showing the positional relationship between a gate electrode, a trench, and a gate oxide film when viewed from the substrate surface side in a semiconductor device according to Modification 1 of the fourth embodiment of the present invention. [Figure 14] FIG. 13 is a diagram showing the positional relationship between a gate electrode, a trench, and a gate oxide film when viewed from the substrate surface side in a semiconductor device according to Modification 2 of the fourth embodiment of the present invention. [Figure 15] FIG. 10 is a perspective view illustrating a structure of a trench MOSFET with a vertical channel fin structure disclosed in Patent Document 3. [Figure 16] 16 is a cross-sectional view taken along the line X2-X2′ of FIG. 15. [Figure 17] 16 is a cross-sectional view taken along the line Y1-Y1' in FIG. 15. [Figure 18] 16 is a diagram showing the positional relationship between the gate electrode, trench, and gate oxide film when viewed from the substrate surface side in the semiconductor device of FIG. 15. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. (First embodiment) A semiconductor device 100 according to a first embodiment of the present invention will be described below. The semiconductor device 100 according to this embodiment is an example applied to a trench MOS with a vertical channel FIN structure in which a channel current flows in the vertical direction.

[0022] FIG. 1 is a perspective view of a semiconductor device 100 according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of the semiconductor device 100 of FIG. 1 taken parallel to the trench longitudinal direction (X1-X1'), and FIG. 3 is a cross-sectional view including the trench longitudinal direction (X2-X2') of the semiconductor device 100 of FIG. 1. FIG. 4A is a cross-sectional view of the semiconductor device 100 of FIG. 1 taken in the trench lateral direction (Y1-Y1'), and FIG. 4B is a cross-sectional view of the semiconductor device 100 of FIG. 1 taken in the trench lateral direction (Y2-Y2'). Components identical to those in FIG. 15 are denoted by the same reference numerals. Note that the interlayer insulating film 14, source electrode 12, and drain electrode 13 are not shown in the figures. FIG. 5 is a diagram showing the positional relationship between the gate electrode, trench, and gate oxide film when viewed from the substrate surface side in the semiconductor device 100 of FIG. As shown in FIG. 5, the trench 2 of the semiconductor device 100 has a rectangular shape when viewed from above, and has a trench short side in the lateral direction of the trench and a trench long side perpendicular to the trench short side.

[0023] The semiconductor device 100 is a trench MOS with a vertical channel FIN structure in which a channel current flows in the vertical direction. As shown in FIG. 1, the semiconductor device 100 has a longitudinal direction in a first direction when viewed from above, a lateral direction in a second direction, and a plurality of trenches 2 arranged in the second direction; a first source region 3 of a first conductivity type arranged outside the trenches 2 in the first direction; a second source region 4 of the first conductivity type including a region at least partially forming a fin structure separated by the plurality of trenches 2; and a second conductivity type channel region 5 of a fin structure separated by the plurality of trenches 2 and in contact with a lower surface of the second source region 4. The gate insulating film 16 includes a gate electrode 7 having a region at least a portion of which is disposed inside the trench 2, a JFET region 8 of a first conductivity type disposed below the channel region 5, and a body region 9 (P body layer) of a second conductivity type disposed to the side of the JFET region 8, and the gate insulating film 16 has an oxide film 16a (FIG. 3) on the substrate surface in the short-side direction of the trench (Y1-Y1' in FIG. 1) that is wider than an oxide film 16b (FIG. 3) that contacts the channel region 5 in the short-side direction of the trench (Y1-Y1' in FIG. 1). In particular, in the semiconductor device 100, a portion of the gate electrode 7 at the upper corner of the trench on the short side of the trench (i.e., in the short direction of the trench) that does not include the channel region 5 is narrowed, and the thickness of the oxide film 16a (Figure 3) on the substrate surface is made thicker (wider).

[0024] In this embodiment, the oxide film is thickened at the upper corners of the trench in the short direction of the trench, not including the channel surface. This allows the electric field at the three-dimensional corners of the trench to be relaxed without affecting the embedding of the gate electrode 7. The range of the upper corners of the trench is not limited, and there is no problem even if the oxide film is thick on the entire sidewall of the trench in the short direction, for example.

[0025] If the oxide film were to be thickened in all directions along the trench, it would also be thickened along the short sides of the trench, which would impair the embedding of the gate electrode. While it is possible to thicken the oxide film in the active region, a uniform film is required in the channel region, so thermal oxidation control is required.

[0026] The gate electrodes 7 disposed inside the trench 2 are connected to each other outside the trench 2. The gate electrodes 7 may be formed of, for example, polysilicon. An interlayer insulating film 14 (FIG. 2) is formed between the connected portions of the gate electrodes 7 and the second source region 4. This interlayer insulating film 14 also covers the top and side portions of the connected portions of the gate electrodes 7.

[0027] The channel region 5 is electrically connected to the body region 9. Below the channel region 5, there is a first conductivity type JFET region 8 arranged between the body regions 9 and electrically connected to the drift region 10. As shown in FIG. 2 , the trench 2 is formed so that its longitudinal length overlaps the body regions 9 on both sides of the JFET region 8. The depth of the trench 2 is shallower than that of the body region 9 and deeper than that of the channel region 5. 1 and 2, the trench 2 indicated by the dashed line in the cross section shows a hypothetical position corresponding to the trench 2 in order to explain the positional relationship between other components and the trench 2.

[0028] The semiconductor device 100 has a JFET region 8 of a first conductivity type arranged below the channel region 5, a body region 9 of a second conductivity type arranged to the side of the JFET region 8, a drift region 10 of the first conductivity type arranged below the JFET region 8, a drain region 11 of the first conductivity type arranged below the drift region 10, a source electrode 12 connected to the upper surface side of the first source region 3, and a drain electrode 13 connected to the lower surface side of the drain region 11.

[0029] The second source region 4 has a lower impurity concentration than the first source region 3 and is shallower from the surface than the first source region 3. In this embodiment, as an example, the first source region 3 is a highly doped n+ type, the second source region 4 is a lightly doped n type, and the channel region 5 is a p type.

[0030] In this embodiment, an example has been shown in which the second source region 4 has a lower impurity concentration than the first source region 3 and is shallower from the surface than the first source region 3, but such a configuration is not an essential requirement. That is, the semiconductor device 100 may be any trench-type MIS as long as the oxide film 16a (FIG. 3) on the substrate surface in the short-side direction of the trench (Y1-Y1' in FIG. 1) is thicker (wider) than the oxide film 16b (FIG. 3) in contact with the channel region 5 in the short-side direction of the trench (Y1-Y1' in FIG. 1).

[0031] In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited to this and the first conductivity type may be p-type and the second conductivity type may be n-type. Here, the JFET region 8 is n-type, the body region 9 is p-type, the drift region 10 is low-concentration n-type, and the drain region 11 is high-concentration n+ type, but for example, the JFET region 8 may be low-concentration n-type. Furthermore, for electrical connection of the body region 9 with the source electrode 12, a heavily doped P++ potential fixing region may be present on the substrate surface and connected to the source electrode 12.

[0032] In addition, in this embodiment, a part of the second source region 4 has a fin structure, and the other part is connected to the first source region 3, but this is not limited to this, and the entire second source region 4 may have a fin structure.

[0033] Furthermore, in the semiconductor device 100, as shown by the width arrow a in Figure 4A, in the trench short direction (Y1-Y1' in Figure 1), the gate electrode 7 closer to the substrate surface than a predetermined depth in the second source region 4 is narrower than the width (not shown) of the gate electrode at the depth of the channel region 5 on the trench long side (Figure 5).

[0034] The operation of the semiconductor device 100 configured as described above will now be described. <Operation description> In the semiconductor device 100, a channel current flows vertically in the channel region 5 of the fin structure by inputting and controlling a gate drive signal to the gate electrode 7 inside the trench 2. In other words, the device is a trench MOSFET with a vertical channel fin structure. Therefore, by narrowing the trench pitch and increasing the density of the trenches 2, the channel density can be increased, thereby reducing the channel resistance and on-resistance. However, after trench formation, it is necessary to uniformly form the gate oxide film 16 along the channel region 5 and embed the gate electrode 7 in the trench 2. Therefore, the trench 2 must be wide enough to embed the gate electrode 7. Furthermore, the gate insulating film 16 in contact with the channel region 5 must be as uniform as possible and uniform across each trench and in the trench depth direction.

[0035] As described above, in the semiconductor device 100, the oxide film 16a (FIG. 3) on the top of the trench on the short side of the trench that does not include the channel region 5 is wider than the oxide film 16b (FIG. 3) that contacts the channel on the long side of the trench that includes the channel region 5 (i.e., the width arrow a in FIG. 4B).

[0036] Since the short sides of the trench do not include the channel region 5, the thick oxide film 16a (Figure 3) on the top of the trench on the short sides of the trench may be only near the substrate surface of the trench 2, or it may extend to a depth where the channel region 5 exists. The semiconductor device 100 has a wide oxide film 16a (FIG. 3), which narrows the width of the gate electrode 7. The change in width of the gate electrode 7 may be continuous or discontinuous, but a continuous change is preferable because corners in the gate electrode 7 cause electric field concentration. However, the sidewalls on the long sides of the trench (FIG. 5) including the channel region 5 have the same structure as in the conventional structure (e.g., the semiconductor device 1 in FIG. 15), and therefore do not affect the channel characteristics. Such a thick oxide film is formed, for example, by oxidizing the gate electrode after its formation.

[0037] <Manufacturing method> The manufacturing method of the semiconductor device 100 includes the steps of forming a trench on the surface of the substrate in the semiconductor device 100, forming an insulating film that covers the side and bottom surfaces of the trench, burying a gate electrode inside the trench and on the semiconductor layer, and, after forming the gate electrode 7, thickening the insulating film on the upper part of the trench in the short direction of the trench, not including the channel region.

[0038] In this embodiment, the insulating film is an oxide film, and in the process of thickening the insulating film at the top of the trench in the short direction of the trench, after the gate electrode 7 is formed, oxidation is performed from the short direction of the trench to the top of the trench, and the oxide film 16a on the substrate surface in the short direction of the trench is formed to be thicker (wider) than the oxide film in contact with the body region in the long direction of the trench.

[0039] The wide oxide film 16a (FIG. 3) at the top of the trench on the short side (FIG. 5) of the trench is formed, for example, by performing oxidation (dashed arrow in FIG. 5) after the formation of the gate electrode 7. Oxidation from the short side (FIG. 5) to the top of the trench is relatively easy. As a result, the oxide film 16a (FIG. 3) on the substrate surface in the short side direction of the trench (Y1-Y1' in FIG. 1) is formed thicker (wider) than the oxide film 16b (FIG. 3) in contact with the body region 9 (P-type region) in the long side direction of the trench (X2-X2' in FIG. 1).

[0040] The material of the gate electrode 7 is, for example, phosphorus-doped polysilicon, but is not limited to this. The oxidation after the formation of the gate electrode 7 may be wet oxidation or dry oxidation, and by performing the oxidation at a temperature of 700° C. to 1100° C., only Si is oxidized while minimizing the oxidation of SiC, thereby producing a high-quality oxide film with little crystallinity. However, in this embodiment, the temperature for manufacturing the semiconductor device 100 is not limited.

[0041] The semiconductor device 100 can be formed, for example, using an n+ type SiC substrate, but is not limited to this. Also, since the semiconductor device 100 can be manufactured by a general semiconductor device manufacturing method, for example, by forming an n+ type drain region 11 on an n+ type SiC substrate and then forming an n- type drift region by epitaxial growth, detailed description thereof will be omitted.

[0042] [Effects of the first embodiment] As described above, the semiconductor device 100 has a longitudinal direction in a first direction when viewed in a plan view, a plurality of trenches 2 arranged in the second direction, a first source region 3 of a first conductivity type disposed outside the trenches 2 in the first direction, a second source region 3 of a first conductivity type including a region at least a part of which has a fin structure separated by the plurality of trenches 2, a channel region 5 of a second conductivity type in contact with a lower surface of the second source region 4 and having a fin structure separated by the plurality of trenches 2, and a second source region 4 of a second conductivity type. 2, a gate electrode 7 including a region at least a portion of which is disposed inside the trench 2, a JFET region 8 of a first conductivity type disposed below the channel region 5, and a body region 9 (P body layer) of a second conductivity type disposed on a side of the JFET region 8, and the gate insulating film 16 has an oxide film 16a (FIG. 3) on the substrate surface in the short-side direction of the trench (Y1-Y1' in FIG. 1) that is thicker (wider) than an oxide film 16b (FIG. 3) that contacts the channel region 5 in the short-side direction of the trench (Y1-Y1' in FIG. 1).

[0043] In the semiconductor device 100, the electric field can be alleviated at the three-dimensional corners of the trench by narrowing a portion of the gate electrode 7 at the upper corners of the trench on the short side of the trench that does not include the channel region 5 and thickening the oxide film 16a (i.e., the oxide film on the substrate surface on the short side is thick). By thickening only the oxide film at the upper corners of the trench on the short side wall of the trench that does not include the channel region 5, the opening width in the short direction of the trench is not narrowed, and therefore the embedding of the gate electrode 7 is not affected. In this way, electric field can be alleviated at the three-dimensional corners of the trench in a trench MOSFET with a vertical channel fin structure, and the reliability of the trench MOSFET with a vertical channel fin structure can be further improved.

[0044] In the semiconductor device 100, a channel current flows vertically in the channel region 5 of the fin structure by inputting and controlling a gate drive signal to the gate electrode 7 inside the trench 2. In other words, the semiconductor device 100 is a trench MOSFET with a vertical channel fin structure. Therefore, by narrowing the trench pitch and increasing the density of the trenches 2, the channel density can be increased, and the channel resistance and on-resistance can be reduced.

[0045] In addition, in the semiconductor device 100, in the trench short-side direction (Y1-Y1' in FIG. 1), the gate electrode 7 on the substrate surface side from a predetermined depth in the second source region 4 is wider than the width of the gate electrode on the trench short side (the channel region 5 depth in FIG. 4B (width arrow a in FIG. 4B)). As a result, the gate electrode 7 is thick on the long sides of the trench as well as the short sides thereof, so that the oxide film at the corners of the trench can be thickened while maintaining the embeddability of the gate electrode 7, thereby enabling electric field relaxation. When oxidizing the gate electrode 7 from the short side of the trench, it is also desirable to promote oxidation of the upper corners of the trench on the long side of the trench. Specific methods for achieving this will be described later in the third and fourth embodiments.

[0046] (Second embodiment) A semiconductor device 100A according to a second embodiment of the present invention will be described. Fig. 6 is a cross-sectional view of a trench in a semiconductor device 100A according to a second embodiment of the present invention in the short direction. Fig. 7 is a diagram showing the positional relationship between the gate electrode, trench, and gate oxide film when viewed from the substrate surface side in the semiconductor device 100A of Fig. 6. The same components as in Fig. 4 are assigned the same reference numerals. As shown in Figure 6, the semiconductor device 100A has, in the short direction of the trench (Y2-Y2' in Figure 1), a first gate electrode 7a located closer to the substrate than an arbitrary depth in the source region, and a second gate electrode 7b located closer to the substrate surface than an arbitrary depth in the source region, and the width of the second gate electrode 7b in the trench 2 is narrower than the width of the first gate electrode 7a. The first gate electrode 7a and the second gate electrode 7b are made of different materials. The second embodiment differs from the first embodiment in that the gate electrode 7 has a first gate electrode 7a and a second gate electrode 7b. Since the rest is the same as the first embodiment, a duplicated description will be omitted.

[0047] <Manufacturing method> 8A to 8G are diagrams illustrating a method for manufacturing the semiconductor device 100A. After forming the trench, a gate oxide film is formed, and then a gate electrode is formed, which is the same as in the first embodiment (FIG. 8A). Thereafter, the gate electrode 7 (FIG. 8B) that has already been formed is etched back to the height of an arbitrary N+ source region (etching back of the gate electrode), thereby forming a first gate electrode 7a that will become a buried electrode (FIG. 8C).

[0048] Then, an oxide film is deposited to further thicken the oxide film at the upper corners of the trench (additional oxide film deposition) (Figure 8D) ("process for thickening the insulating film at the top of the trench in the short direction of the trench" in claim 7). Thereafter, oxidation is carried out at high temperature to round off the corners of the first gate electrode 7a formed by etching (thermal oxidation) (FIG. 8E). After that, the oxide film on the substrate surface side of the first gate electrode 7a is removed by further etching back (oxide film etch back) (Fig. 8F), and another gate electrode is formed. This gate electrode becomes the second gate electrode 7b, and the first gate electrode 7a and the second gate electrode 7b are electrically connected (additional electrode formation) (Fig. 8G).

[0049] In the semiconductor device 100A, the first gate electrode 7a and the second gate electrode 7b can be formed using different materials. The work function of the first gate electrode 7a determines the threshold voltage of the MOS channel. Therefore, the threshold voltage can be increased by selecting a material with a large work function, such as boron-doped polysilicon. On the other hand, the second gate electrode 7b spans the fin structures and is connected to the gate pad. Therefore, gate delay can be reduced by selecting a material with low resistance. For example, the first gate electrode 7a and the second gate electrode 7b may be made of phosphorus-doped polysilicon, or other materials such as tungsten, molybdenum, or titanium.

[0050] Furthermore, in this embodiment, as in the first embodiment, it is also possible to form a thicker oxide film on the upper part of the short side of the trench by, for example, performing oxidation after forming the gate electrode. The material of the gate electrode 7 is, for example, phosphorus-doped polysilicon, but is not limited to this. Oxidation after the gate electrode formation can be wet oxidation or dry oxidation, and by performing oxidation at a temperature between 700°C and 1100°C, only Si is oxidized while minimizing the oxidation of SiC, resulting in a high-quality oxide film with minimal crystallinity. However, in this embodiment, the manufacturing temperature is not limited.

[0051] [Effects of the second embodiment] In the semiconductor device 100A, in the short direction of the trench (Y2-Y2' in Figure 1), there is a first gate electrode 7a located closer to the substrate than an arbitrary depth in the source region, and a second gate electrode 7b located closer to the substrate surface than an arbitrary depth in the source region, and the width of the second gate electrode 7b in the trench 2 is narrower than the width of the first gate electrode 7a.

[0052] The first gate electrode 7a is located at a depth from the trench bottom 2a to the channel portion, and the second gate electrode 7b is located at a depth in the N region on the substrate side (shallower side) than the channel portion. With this structure, the oxide film is thicker by the amount that the second gate electrode 7b is thinner than the first gate electrode 7a, which makes it possible to alleviate the electric field at the upper corners of the trench on the longer sides of the trench, further improving reliability.

[0053] 8A to 8G, the first gate electrode 7a is buried in the same manner as in the first embodiment, so there is no problem with the embeddability in this embodiment either. Furthermore, although the second gate electrode 7b needs to be buried in a region narrower than the first gate electrode 7a, the buried portion is sufficiently shallow so there is no problem with the embeddability. Even if the embeddability deteriorates somewhat, it is not deep enough in the channel region, so there is no problem as long as it has sufficiently low conductivity compared to the first gate electrode 7a.

[0054] In the semiconductor device 100A, the first gate electrode 7a and the second gate electrode 7b are made of different materials, so that the threshold voltage can be increased by selecting a material with a large work function for the first gate electrode 7a, and the gate delay can be reduced by selecting a material with a low resistance for the second gate electrode 7b.

[0055] (Third embodiment) A semiconductor device 100B according to a third embodiment of the present invention will be described. Fig. 9 is a diagram showing the positional relationship between the gate electrode, trench, and gate oxide film when viewed from the substrate surface side in a semiconductor device 100B according to a third embodiment of the present invention. Fig. 10 is a cross-sectional view of the semiconductor device 100B in Fig. 9 in the longitudinal direction of the trench. In the explanation of Fig. 10, the same components as those in Figs. 1 to 3 are denoted by the same reference numerals. 9, the semiconductor device 100B includes a plurality of trenches 2 having a longitudinal direction in the first direction and a lateral direction in the second direction, and trenches 21 having thin fin portions that continuously connect the plurality of trenches 2 in the lateral direction. The structure in which the plurality of trenches 2 are connected by the thin trenches 21 can be likened to a fishbone structure. The narrow trenches 21 allow the gate electrodes to connect between the trenches.

[0056] As shown in FIG. 10, the semiconductor device 100B has a longitudinal direction in a first direction in a plan view, a lateral direction in a second direction, and a plurality of trenches 2 arranged in the second direction; trenches 21 having a fin portion with a narrow part so that the trenches are continuous in the lateral direction between the plurality of trenches 2; a first source region 3 of a first conductivity type arranged outside the trenches 2 in the first direction; a second source region 3 of the first conductivity type including a region with a fin structure at least a part of which is separated by the plurality of trenches 2; and a second source region 4 (see FIG. 2) in contact with a lower surface of the second source region 4 and including a plurality of trenches. The device comprises a second conductivity type channel region 5 (see FIG. 2) of a fin structure separated by trenches 2, a gate insulating film 16 arranged inside the trench 2, a gate electrode 7 including a region at least a portion of which is arranged inside the trench 2, a first conductivity type JFET region 8 arranged below the channel region 5 (see FIG. 2), and a second conductivity type body region 9 arranged to the side of the JFET region 8, and in the trench short direction (Y1-Y1' in FIG. 1), the width of the gate electrode 7 on the substrate surface side of an arbitrary depth in the source region 4 is narrower than the width of the gate electrode at a depth of the body region 9 on the long side of the trench.

[0057] Here, the width of the gate electrode 7 on the substrate surface side from an arbitrary depth in the source region 4 may be 0, in which case the gate electrode 7 is buried only below the substrate surface. In other words, when the width of the gate electrode 7 is 0, the gate electrode 7 is buried below the substrate surface and connected by the narrow trench 21 portion.

[0058] <Manufacturing method> 11A to 11E are diagrams illustrating a method for manufacturing the semiconductor device 100B. After forming the trench, a gate oxide film is formed, and then a gate electrode is formed, which is the same as in the first embodiment (FIG. 11A). Thereafter, the gate electrode 7 (FIG. 11B) that has already been formed is etched back to the height of an arbitrary N+ source region (etching back of the gate electrode), thereby forming a first gate electrode 7a that will become a buried electrode (FIG. 11C).

[0059] Then, an oxide film is deposited to further thicken the oxide film at the upper corners of the trench (additional oxide film deposition) ("process of thickening the insulating film at the top of the trench in the short direction of the trench" in claim 7). Thereafter, oxidation is carried out at high temperature to round off the corners of the first gate electrode 7a formed by etching (thermal oxidation) (FIG. 11D). Then, the oxide film on the substrate surface side of the first gate electrode 7a is removed by further etching back, and another gate electrode is formed. This gate electrode becomes the second gate electrode 7b, and the first gate electrode 7a and the second gate electrode 7b are electrically connected (interlayer film formation) (Fig. 11E).

[0060] [Effects of the third embodiment] The semiconductor device 100B has narrow trenches 21 that continuously connect the multiple trenches 2 in the short-side direction. With this structure, even if oxidation is performed after the gate electrode 7 is formed, oxidation of the gate electrode 7 also progresses from the short-side direction of the trench. Because oxidation continues and accelerates through the trenches 21, even on the long-side sides of the trench, the gate electrode 7 on the substrate surface side can be formed narrower at any depth in the source region than the width of the gate electrode 7 at the depth of the P-type region on the long-side side of the trench. This makes it possible to thicken the oxide film at the corners of the trench while maintaining the embeddability of the gate electrode 7, thereby alleviating the electric field. Furthermore, the manufacturing method shown in Figures 11A to 11E allows the gate electrode to be completely embedded in the trench at the center of the chip, specifically, on the substrate side from a desired depth in the source region, eliminating the need for the gate electrode to straddle fins.

[0061] Moreover, the depth in the source region can be changed, and the width of the gate electrode on the substrate surface side can be set to 0. Furthermore, even when the gate electrode is buried in the trench, the gate electrode needs to run onto the SiC substrate in order to connect to the gate pad at the end of the gate electrode, but by combining this with the second embodiment, it becomes possible to alleviate the electric field at the trench corner at the end.

[0062] (Fourth embodiment) A semiconductor device 100C according to a fourth embodiment of the present invention will be described. 12 is a diagram showing the positional relationship between the gate electrode, trench, and gate oxide film when viewed from the substrate surface side in a semiconductor device 100C according to a fourth embodiment of the present invention. In the description of FIG. 12, the same components as those in FIG. 5 are denoted by the same reference numerals. The semiconductor device 100C shown in FIG. 12 differs from the semiconductor device 100C shown in FIG. 5 in that the gate electrode 7 spanning the Fin has holes 22 opened periodically in the lateral direction and parallel to the longitudinal direction. As shown in FIG. 12, the gate electrode 7 of the semiconductor device 100C has trenches 2 and holes 22 parallel to the longitudinal direction formed periodically (here, alternately) in the lateral direction, giving the gate electrode 7 a ladder-like structure.

[0063] [Effects of the fourth embodiment] The semiconductor device 100C has a ladder-like structure in which holes 22 are formed periodically in the lateral direction and parallel to the longitudinal direction in the gate electrode 7 that straddles the Fins. With this structure, the semiconductor device 100C can be formed with the gate electrode 7 as described in the first embodiment and then oxidized, thereby oxidizing the gate electrode at the upper corner of the trench at the long side of the trench through the holes 22 aligned in the short direction of the polysilicon trench, thereby thickening the oxide film. Therefore, in the structure of Figure 12, as in the second embodiment, the oxide film at the upper corners of the trench in both the longitudinal and lateral directions is thick, but since the oxide film is formed after embedding the gate electrode 7 as in Figure 6 of the second embodiment, it does not affect the embeddability of the gate electrode 7. 12, after the gate electrode is formed, only the etching and oxidation steps for forming the hole 22 in the gate electrode 7 are added. This allows the oxide film on the top of the trench on both the long and short sides to be thickened while minimizing the additional steps.

[0064] [Modification of the fourth embodiment] The number of holes in the gate electrode 7 on the Fin shown in FIG. 12 may be two or more, which is shown as an example of a modified example. 13 is a diagram showing the positional relationship between the gate electrode, trench, and gate oxide film when viewed from the substrate surface side in the semiconductor device 100D of Modification 1. The same components as in FIG. 12 are denoted by the same reference numerals. A semiconductor device 100D of the first modification shown in FIG. 13 has two (a pair of) holes 23 in the gate electrode 7 near the long sides of the trench. For example, if the fin is very thick, the area of ​​the hole on the fin can be reduced by forming two holes in the gate electrode 7 near the long side of the trench, which may lower the resistance of the gate electrode 7.

[0065] 14 is a diagram showing the positional relationship between the gate electrode, trench, and gate oxide film when viewed from the substrate surface side in a semiconductor device 100E of Modification 2. The same components as in FIG. 12 are denoted by the same reference numerals. In a semiconductor device 100E of the second modification shown in FIG. 14, the hole 24 in the gate electrode 7 is opened up to a position close to the corner of the long side of the trench. For example, when the width of the gate electrode 7 is very large, by opening the hole 24 up to a position close to the trench corner, the oxide film can be made thick up to a position close to the three-dimensional corner of the trench.

[0066] In both variant 1 of Figure 13 and variant 2 of Figure 14, after the gate electrode is formed, only the etching and oxidation processes for forming holes 23 and 24 in the gate electrode 7 are added, so the oxide film on the top of the trench on both the long and short sides can be thickened while minimizing the additional process.

[0067] The present invention is not limited to the above-described embodiments, and includes other modifications and applications without departing from the spirit of the present invention as defined in the claims. For example, the above-described embodiments have been described in detail to facilitate understanding of the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0068] 1. Semiconductor device 2. Trench 3 First Source Region 4 Second Source Region 5 Channel Region 7. Gate electrode 7a First gate electrode 7b Second gate electrode 8 JFET area 9. Body Region 10 Drift Region 11 Drain region 12 Source electrode 13 Drain electrode 14 Interlayer insulating film 16 Gate insulating film 16a Oxide film on the substrate surface in the short direction of the trench 16b Oxide film in contact with the body region in the longitudinal direction of the trench 21 A narrow trench that connects multiple trenches in the short direction 22, 23, 24 holes 100, 100A, 100B, 100C, 100E Semiconductor device Y1-Y1' Trench short side (short side of trench) Y2-Y2' Trench short side (short side of trench) X1-X1', X2-X2' Trench longitudinal direction In the short direction of the trench, the gate electrode on the substrate surface side from a predetermined depth in the source region is narrower than the gate electrode width at the depth of the body region on the long side of the trench.

Claims

1. A plurality of trenches having a longitudinal direction in a first direction and a lateral direction in a second direction when viewed in a plane, the trenches being arranged in the second direction; a first source region of a first conductivity type disposed outside the trench in a first direction; and a second source region of the first conductivity type including a region having a fin structure at least a portion of which is separated by a plurality of the trenches; a second conductivity type channel region of a fin structure in contact with a lower surface of the second source region and separated by a plurality of the trenches; a gate insulating film disposed inside the trench; a gate electrode including a region at least partially disposed within the trench; a JFET region of a first conductivity type disposed below the channel region; a body region of a second conductivity type disposed on a side of the JFET region, The gate insulating film has an oxide film on the substrate surface in the short direction of the trench that is wider than the oxide film in contact with the channel region in the short direction of the trench. A semiconductor device characterized by:

2. The gate electrode has a first gate electrode located closer to the substrate than a predetermined depth in the second source region in the short direction of the trench, and a second gate electrode located closer to the substrate surface than a predetermined depth in the second source region, and the width of the second gate electrode in the trench is narrower than the width of the first gate electrode.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

3. The first gate electrode and the second gate electrode are made of different materials.

3. The semiconductor device according to claim 2.

4. a plurality of the trenches; and a trench in which a part of the fin portion is narrow, the trenches continuously connecting the plurality of trenches in a lateral direction, In the short direction of the trench, the gate electrode located closer to the substrate surface than a predetermined depth in the second source region has a width narrower than that of the gate electrode located at a depth of the body region on a long side of the trench.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

5. the gate electrode has holes that are periodically arranged in a lateral direction and parallel to a longitudinal direction, In the short direction of the trench, the gate electrode located closer to the substrate surface than a predetermined depth in the second source region has a width narrower than that of the gate electrode located at a depth of the body region on a long side of the trench.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

6. forming a trench in a surface of a substrate in a semiconductor device; forming an insulating film covering the side and bottom surfaces of the trench; burying a gate electrode inside the trench and on the semiconductor layer; and after forming the gate electrode, thickening the insulating film in the upper portion of the trench in the lateral direction of the trench, not including the channel region.

10. A method for manufacturing a semiconductor device comprising the steps of:

7. the insulating film is an oxide film, In the step of thickening the insulating film, after the gate electrode is formed, oxidation is performed from the short side of the trench to the upper part of the trench, and the oxide film on the substrate surface in the short side of the trench is formed thicker than the oxide film in contact with the body region in the long side of the trench.

7. The method for manufacturing a semiconductor device according to claim 6.

8. In the step of forming the trench, a rectangular trench is formed having a trench short side in a short direction of the trench and a trench long side perpendicular to the trench short side when viewed from above; In the step of thickening the insulating film, after the gate electrode is formed, oxidation is performed from the long side direction of the trench to the upper part of the trench.

7. The method for manufacturing a semiconductor device according to claim 6.

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