Operational amplifier

Abstract

To reduce and suppress intrusion of high-frequency external noise from a power supply line and to improve output voltage characteristics at a relatively low cost.SOLUTION: In an operational amplifier including: a differential amplification circuit 100A configured to enable differential amplification of an input signal; an amplification circuit 200A for amplifying an output signal of the differential amplification circuit 100A; and an output circuit 300A capable of outputting an output signal of the amplification circuit 200A at a desired output level, the differential amplification circuit 100A includes a first transistor (M1) 1 and a second transistor (M2) 2, which are formed by using P-channel MOSFETs and reduces and suppresses intrusion of high-frequency noise from a power supply node by applying a power supply voltage VDD to back gates of the first transistor (M1) 1 and the second transistor (M2) 2 via a back-gate resistor (RX1) 41.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an operational amplifier, and more particularly to an operational amplifier which is designed to prevent deterioration of output voltage characteristics due to external noise entering a power supply line and to improve stability. [Background technology]

[0002] In an operational amplifier, which is an analog integrated circuit, it is important to take measures against various noises from the viewpoint of ensuring high-precision operating characteristics and high stability. For example, high-frequency external noise that invades power lines has a significant impact on the quality of output voltage characteristics, so adequate countermeasures are necessary. For this reason, various measures have been proposed to reduce the effects of high-frequency external noise, such as shielding the chip surface by covering it with a ground potential metal layer (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 4-369226 Summary of the Invention [Problem to be solved by the invention]

[0004] However, while the above-mentioned method of covering the chip surface with a metal layer at ground potential provides a reliable shielding effect against high-frequency external noise that enters directly from the chip surface, it requires a multi-layer wiring process to shield the chip surface, which increases manufacturing costs.

[0005] The present invention has been made in view of the above circumstances, and provides an operational amplifier which is less expensive than conventional ones, reduces or prevents the intrusion of high frequency external noise from a power supply line, and also improves output voltage characteristics and operational stability. [Means for solving the problem]

[0006] In order to achieve the above object of the present invention, an operational amplifier according to the present invention comprises: An operational amplifier comprising: a differential amplifier circuit configured to be capable of differentially amplifying an input signal; an amplifier circuit that amplifies an output signal of the differential amplifier circuit; and an output circuit configured to be capable of outputting the output signal of the amplifier circuit at a desired output level, The differential amplifier circuit is configured using a P-channel MOSFET, and a power supply voltage is applied to the back gate of the P-channel MOSFET via an impedance element. [Effects of the Invention]

[0007] According to the present invention, by configuring the back gate of the MOSFET to receive power supply via a resistor, high-frequency noise entering from the power supply node is reduced and suppressed by the resistor, and high-frequency noise is also reduced and suppressed by the low-pass filter formed by the resistor and the parasitic capacitance of the MOSFET, thereby reliably preventing malfunction of the operational amplifier and improving the output voltage characteristics. Furthermore, unlike conventional high-frequency noise countermeasures, no multilayer wiring process is required, which has the effect of enabling implementation at relatively low cost. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a circuit diagram showing a first example of a circuit configuration of an operational amplifier according to an embodiment of the present invention. [Figure 2] FIG. 4 is a circuit diagram showing a second example of a circuit configuration of an operational amplifier according to an embodiment of the present invention. [Figure 3] FIG. 10 is a circuit diagram showing a third example of a circuit configuration of an operational amplifier according to an embodiment of the present invention. [Figure 4] FIG. 10 is a circuit diagram showing a fourth example of a circuit configuration of an operational amplifier according to an embodiment of the present invention. [Figure 5] FIG. 10 is a circuit diagram showing a fifth example of a circuit configuration of an operational amplifier according to an embodiment of the present invention. [Figure 6] 1 is an explanatory diagram for schematically explaining a propagation state in an internal circuit due to the intrusion of high-frequency noise from a power supply node in an operational amplifier; [Figure 7] 7A and 7B are schematic diagrams illustrating the parasitic capacitance of a P-channel MOSFET, where FIG. 7A is a schematic cross-sectional view of a P-channel MOSFET, and FIG. 7B is a schematic diagram illustrating the parasitic capacitance of a P-channel MOSFET. [Figure 8] This is an equivalent circuit diagram including the parasitic capacitance of a P-channel MOSFET. [Figure 9] This is an equivalent circuit diagram including a parasitic diode of a P-channel MOSFET. [Figure 10] FIG. 1 is a circuit diagram showing an example of the configuration of an evaluation circuit used to evaluate high-frequency noise resistance in a power supply terminal. [Figure 11] 4 is a characteristic diagram showing an example of change characteristics of an output voltage in response to high-frequency noise that has entered a power supply terminal of an operational amplifier according to an embodiment of the present invention; FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to FIGS. The components, arrangements, etc. described below do not limit the present invention, and various modifications can be made within the scope of the present invention. First, a first circuit configuration example of an operational amplifier according to an embodiment of the present invention will be described with reference to FIG. The operational amplifier in the first circuit configuration example of the embodiment of the present invention is configured to be roughly divided into an input stage differential amplifier circuit 100A, a source grounded amplifier circuit 200A, and an output circuit 300A. The input stage differential amplifier circuit 100A constitutes the input stage of this operational amplifier, and is mainly composed of first and second transistors 1 and 2 (denoted as "M1" and "M2" in FIG. 1, respectively), a constant current source 15, and a back gate resistor 41 (denoted as "RX1" in FIG. 1).

[0010] The first and second transistors 1 and 2 are connected as described below to form a differential pair, enabling differential amplification. The first and second transistors 1 and 2 are P-channel MOSFETs, with their sources connected to each other, and a constant current source 15 is connected between the connection point and a positive power supply terminal 53. The positive power supply terminal 53 is configured to receive an external power supply voltage VDD.

[0011] On the other hand, the drains of the first and second transistors 1 and 2 are connected to a common-source amplifier circuit 200A, which will be described next. In addition, the gate of the first transistor 1 is connected to an inverting input terminal (denoted as "IMN" in FIG. 1) 51, and the gate of the second transistor 2 is connected to a non-inverting input terminal (denoted as "IMP" in FIG. 1) 52. Furthermore, the back gates of the first and second transistors 1 and 2 are both connected to a positive power supply terminal 53 via a back gate resistor 41 serving as an impedance element.

[0012] The common-source amplifier circuit 200A is an amplifier circuit that amplifies the differential output signal of the input-stage differential amplifier circuit 100A. This common-source amplifier circuit 200A is configured by being roughly divided into an amplifier section 200A-1 and a constant current source section 200A-2. The amplifier section 200A-1 is configured with fifth and sixth transistors 5 and 6 (respectively indicated as "M5" and "M6" in FIG. 1) and third and fourth resistors 33 and 34 (respectively indicated as "R3" and "R4" in FIG. 1) as its main components.

[0013] In the embodiment of the present invention, N-channel MOSFETs are used for the fifth and sixth transistors 5 and 6, and are connected as described below to enable source-grounded amplification. That is, the gates of the fifth and sixth transistors 5 and 6 are connected to each other and to the drain of the fifth transistor 5. The drain of the fifth transistor 5 is connected to a constant current source unit 200A-2, which will be described later. On the other hand, the drain of the sixth transistor 6 is connected to the input stage of an output circuit 300A, which will be described later.

[0014] The source of the fifth transistor 5 is connected to the drain of the first transistor 1 and is also connected to the negative power supply terminal 54 via the third resistor 33 . On the other hand, the source of the sixth transistor 6 is connected to the drain of the second transistor 2 and is also connected to the negative power supply terminal 54 via the fourth resistor 34 . Furthermore, the back gates of the fifth and sixth transistors 5 and 6 are both connected to the negative power supply terminal 54 .

[0015] The constant current source section 200A-2 is a circuit that supplies a constant current to the above-mentioned amplifier section 200A-1. This constant current source section 200A-2 is configured with third and fourth transistors (represented as "M3" and "M4" in FIG. 1, respectively) 3, 4 and first and second resistors (represented as "R1" and "R2" in FIG. 1, respectively) 31, 32 as its main components. In this embodiment of the present invention, the third and fourth transistors 3 and 4 are P-channel MOSFETs.

[0016] The source of the third transistor 3 is connected to a positive power supply terminal 53 via a first resistor 31 , and the source of the fourth transistor 4 is connected to a positive power supply terminal 53 via a second resistor 32 . The drain of the third transistor 3 is connected to the drain of the fifth transistor 5, and the drain of the fourth transistor 4 is connected to the input stage of an output circuit 300A, which will be described next. Furthermore, the back gates of the third and fourth transistors 3 and 4 are both connected to the positive power supply terminal 53 . A required bias voltage Vbias generated within a circuit (not shown) of the operational amplifier is applied to the gates of the third and fourth transistors 3 and 4, respectively.

[0017] The output circuit 300A is configured to be roughly divided into an output stage control section (denoted as "CTL" in FIG. 1) 300A-1 and a final stage section 300A-2. The output stage control section 300A-1 performs level conversion, impedance conversion, etc. on the output signal of the source grounded amplifier circuit 200A, and has a conventionally well-known circuit configuration. The final stage section 300A-2 is configured as a push-pull circuit using seventh and eighth transistors (represented as "M7" and "M8" in FIG. 1, respectively) 7 and 8. The final stage section 300A-2 buffers and amplifies the output signal of the output stage control section 300A-1 and outputs the amplified signal. In this embodiment of the present invention, the seventh transistor 7 is a P-channel MOSFET, and the eighth transistor 8 is an N-channel MOSFET.

[0018] The seventh and eighth transistors 7 and 8 have their drains connected to each other and to the output terminal 55 . The source and back gate of the seventh transistor 7 are both connected to a positive power supply terminal 53, and the source and back gate of the eighth transistor 8 are both connected to a negative power supply terminal 54, respectively. The gate of the seventh transistor 7 and the gate of the eighth transistor 8 are each connected to the output stage of the output stage control section 300A-1. In this configuration, a folded cascode amplifier circuit is configured by the input stage differential amplifier circuit 100A and the next stage common-source amplifier circuit 200A, and the operational amplifier according to the embodiment of the present invention is thus a folded cascode operational amplifier.

[0019] In this first circuit configuration example, the back gates of the first and second P-channel MOSFET transistors 1 and 2 constituting the input stage differential amplifier circuit 100A are connected to the positive power supply terminal 53, which is the power supply node, via the back gate resistor 41. Therefore, high frequency noise that enters from the power supply node and enters the first and second transistors 1 and 2 via the back gates is reduced by the back gate resistor 41. This reduces the intrusion of high frequency noise into the operational amplifier, thereby reducing and suppressing the occurrence of malfunctions of the operational amplifier.

[0020] Here, the intrusion of high frequency noise from the power supply node will be described with reference to FIGS. First, the general structure of a P-channel MOSFET will be described with reference to FIG. FIG. 7A is a schematic diagram showing the cross-sectional structure of a P-channel MOSFET formed on a p-type substrate 61. An n-type well 62 is formed on a p-type substrate 61 so as to be surrounded by the p-type substrate 61. Furthermore, a p-type diffusion layer 56a which will become a drain D and a p-type diffusion layer 56b which will become a source S are formed on this n-type well 62 so as to be surrounded by the n-type well 62. A conductive member 58 such as polysilicon is provided to form a gate G, and a gate oxide film is formed directly below the gate G to insulate the gate G from the source S, the drain D, and the n-type well (see FIG. 7(A)). Furthermore, on the n-type well 62, an n-type diffusion layer region 57 that serves as a back gate BG is formed in the vicinity of the source (see FIG. 7(A)).

[0021] In a P-channel MOSFET with such a structure, as shown in Figure 7(B), the drain-bulk capacitance Cdb, the source-bulk capacitance Csb, and the gate-bulk capacitance Cgb occur as parasitic capacitances with respect to the back gate (bulk) BG, and are each connected to the back gate (bulk) BG. Furthermore, with respect to the gate G, a gate-drain capacitance Cgd, a gate-source capacitance Cgs, and a gate-bulk capacitance Cgb occur as parasitic capacitances, and are all connected to the gate G. Taking these parasitic capacitances into consideration, the P-channel MOSFET can be expressed as an equivalent circuit shown in Fig. 8. In Fig. 8, "SB" stands for substrate.

[0022] Usually, the back gate potential of a P-channel MOSFET is set to the same potential as the source potential or is connected to a power supply node so as to be at the highest potential. Therefore, when the back gate is connected to the power supply node, high frequency noise that has entered the power supply node enters the back gate and propagates to the source, drain, and gate via the above-mentioned parasitic capacitance.

[0023] Here, the route by which high frequency noise enters the inside of an operational amplifier will be described with reference to FIG. Fig. 6 is a circuit diagram in which the back gates of the first and second transistors 1 and 2 are directly connected to the power supply node without providing the back gate resistor 41 in the circuit shown in Fig. 1. Note that the same components as those shown in Fig. 1 are denoted by the same reference numerals and detailed description thereof will be omitted. In this case, when high-frequency noise enters the power supply node, the high-frequency noise enters the source, drain, and gate nodes of each of the first and second transistors 1 and 2 via the back gate (see the thick arrows in Figure 6).

[0024] On the other hand, in the third and fourth transistors 3 and 4, the first resistor 31 and the second resistor 32 are connected to the sources of the transistors, respectively, so that the intrusion of high-frequency noise from the power supply node is reduced by the resistance. However, since the back gates of the third and fourth transistors 3 and 4 are directly connected to the power supply node, high frequency noise penetrates into the source, drain, and gate nodes via the back gates, just like the first and second transistors 1 and 2. As a result, high frequency noise enters the operational amplifier circuit through the back gates of the first to fourth transistors 1 to 4, causing malfunction of the circuit and fluctuations in output voltage.

[0025] The back gate resistor 41 in the first circuit configuration example shown in FIG. 1 serves to reduce and suppress high frequency noise entering from the back gate as described above, and the selection of the resistance value of the back gate resistor 41 will be described below. First, the selection of the upper limit value of the back gate resistor 41 will be described. First, as explained above, the back gate of a P-channel MOSFET is an n-type semiconductor, and the substrate is a p-type semiconductor (see Fig. 7), so a parasitic diode (p-type inter-substrate parasitic diode) exists between the back gate and the substrate, as shown in Fig. 9. Note that Fig. 9 is an equivalent circuit diagram that shows the parasitic diode present in a P-channel MOSFET. In FIG. 9, "S" denotes a source, "D" denotes a drain, "G" denotes a gate, "BG" denotes a back gate, and "SB" denotes a substrate.

[0026] The backgate is at the highest potential and the substrate is at the lowest potential, so the parasitic diode between the backgate and the substrate is reverse biased. It is generally known that a leakage current Ileak flows through a diode in a reverse bias state, and that this leakage current increases as the temperature rises. In the first circuit configuration example, since the back gate resistor 41 is provided, when the above-mentioned leakage current flows, the back gate potential becomes lower than the power supply node due to the voltage drop in the back gate resistor 41.

[0027] For a P-channel MOSFET to operate normally, the backgate potential Vbg must be higher than the source potential Vso so that the potential of the p-type diffusion layer that forms the source and drain and the potential of the backgate of the n-type well are not forward biased. From this point of view, the resistance value of the back gate resistor 41 must be selected so that the potential relationship between the back gate potential and the source potential satisfies Vso≦Vbg.

[0028] In the first circuit configuration example, if the magnitude of the voltage drop due to the bias current I1 from the constant current source 15 is VI1, the source potential Vso of the first and second transistors 1 and 2 is Vso=VDD-VI1. Furthermore, when the back gate leakage current of the first and second transistors 1 and 2 is ILeak2 and the resistance value of the back gate resistor 41 is Rx1, the above relational expression Vso≦Vbg can be rewritten as follows:

[0029] VDD-VI1≦VDD-Rx1×ILeak2

[0030] Therefore, it is preferable to select the resistance value Rx1 of the back gate resistor 41 within a range in which its upper limit satisfies the following inequality.

[0031] Rx1≦VI1 / ILeak2 [Ω]

[0032] Next, the lower limit of the resistance value Rx1 of the back gate resistor 41 will be described. As explained above, a parasitic diode exists between the n-type well, which is the back gate of the P-channel MOSFET, and the p-type substrate (see FIG. 9). Furthermore, a parasitic capacitance Cbsub exists at the junction. For this reason, the lower limit of the resistance value Rx1 of the back gate resistor 41 must be selected so that the cutoff frequency fc of the low-pass filter consisting of the resistance Rx1 and the parasitic capacitance Cbsub is equal to or lower than the high-frequency noise frequency whose influence is to be reduced.

[0033] FIG. 11 is a characteristic diagram showing the output voltage fluctuation characteristics with respect to changes in the input power of high-frequency noise to an operational amplifier in an embodiment of the present invention, and FIG. 10 is a circuit diagram showing an example of the circuit configuration of an evaluation circuit used to obtain the characteristics shown in FIG. 11. Below, we will explain the output voltage fluctuation characteristics with respect to changes in the input power of high-frequency noise with reference to FIGS. 10 and 11. First, the evaluation circuit shown in FIG. 10 will be described. The operational amplifier OP1 to be evaluated constitutes a voltage follower circuit. A DC voltage V2 of 6 V is applied to the non-inverting input terminal of the operational amplifier OP1. A DC voltage V1 of 12 V is applied to the positive power supply terminal VDD of the operational amplifier OP1 via an inductance LA.

[0034] Furthermore, a high frequency signal is applied to the positive power supply terminal VDD of the operational amplifier OP1 from an AC voltage source RF via a DC blocking capacitor CA. In this evaluation circuit configuration, the input power Pin of the radio frequency signal from the AC voltage source RF was gradually increased, and the DC level of the output voltage Vout of the operational amplifier OP1 was measured at regular intervals with a DC voltmeter, resulting in the characteristics diagram shown in Figure 11. The frequency of the radio frequency signal output from the AC voltage source RF was 1 GHz.

[0035] Next, in FIG. 11, the horizontal axis represents the power of the high frequency signal, and the vertical axis represents the output voltage of the operational amplifier. In the figure, the dashed characteristic line marked with the symbol A indicates the evaluation results of the operational amplifier in the first circuit configuration example, the solid characteristic line marked with the symbol B indicates the evaluation results of the operational amplifier in the second circuit configuration example described below, and the dotted characteristic line marked with the symbol C indicates the evaluation results of the operational amplifier in the conventional circuit.

[0036] According to FIG. 11, in both the operational amplifier according to the embodiment of the present invention and the conventional circuit, the output voltage Vout is 6 V when there is no input power from the AC voltage source RF. Furthermore, in the case of a conventional circuit, i.e., a circuit in which no proactive measures are taken against high frequency noise entering from power supply noise, unlike the operational amplifier in the embodiment of the present invention, it can be confirmed that the output voltage drops sharply when the input power from the AC voltage source RF exceeds 25 dBm (see the dotted characteristic line marked with the symbol C in FIG. 11).

[0037] In contrast, in the operational amplifier of the first circuit configuration example, when Rx1=1 kΩ, it can be confirmed that the output voltage Vout=6 V can be maintained even when the input power from the AC voltage source RF becomes 30 dBm (see the dashed characteristic line marked with the symbol A in Figure 11).

[0038] Next, a second circuit configuration example will be described with reference to FIG. The same components as those in the first circuit configuration example shown in FIG. 1 are given the same reference numerals, and detailed description thereof will be omitted. The following description will focus on the differences. In the operational amplifier in this second circuit configuration example, the input stage differential amplifier circuit 100B and the source-grounded amplifier circuit 200B have configurations different from those described in the first circuit configuration example, and the output circuit 300A is the same as that described in the first circuit configuration example.

[0039] To explain more specifically below, first, the input stage differential amplifier circuit 100B differs from the input stage differential amplifier circuit 100A in the first circuit configuration example in that the back gates of the first and second transistors 1 and 2 are directly connected to the positive power supply terminal 53. On the other hand, the common-source amplifier circuit 200B is configured by being roughly divided into an amplifier section 200A-1 and a constant current source section 200B-2, and the amplifier section 200A-1 has the configuration explained in the first circuit configuration example.

[0040] On the other hand, the constant current source section 200B-2 differs from the constant current source section 200A-2 in the first circuit configuration example in that the back gates of the third and fourth transistors 3, 4 are connected to the positive power supply terminal 53 via a second back gate resistor (denoted as "RX2" in Figure 2) 42. In the operational amplifier in the second circuit configuration example having such a configuration, as in the first circuit configuration example, even if high-frequency noise enters from the power supply node, the second backgate resistor 42 reduces the high-frequency noise entering the third and fourth transistors 1 and 2 from the backgate, thereby reducing the intrusion of high-frequency noise into the operational amplifier and reducing or suppressing the occurrence of malfunction of the operational amplifier.

[0041] Next, the upper and lower limits of the resistance value of the second back gate resistor 42 in this configuration will be described. First, the upper limit of the resistance value of the second back gate resistor 42 will be described. As explained in the first circuit configuration example above, the upper limit of the resistance value of the second backgate resistor 42 must be selected so that the potential relationship between the source potential Vso and the backgate potential Vbg satisfies the relationship Vso≦Vbg. In this second circuit configuration example, if the source current Iso flowing through the third and fourth transistors 3 and 4 is 50 μA, the resistance values ​​R1 and R2 of the first and second resistors 31 and 32 are R1=R2=2 kΩ, and the leakage current Ileak flowing from the back gate to the substrate in the CMOS process of the operational amplifier is approximately 500 nA at 150°C, the upper limit value of the second back gate resistor 42 can be calculated as follows:

[0042] First, the source potential Vso(M3) of the third transistor 3 is calculated as follows: Vso(M3)=VDD-R1×Iso. Here, “R1” is the resistance value of the first resistor 31. The back gate potential Vbg(M3) of the third transistor 3 is calculated as follows: Vbg(M3)=VDD-Rx2×Ileak, where Rx2 is the resistance value of the second back gate resistor . Substituting these relationships into the above inequality Vso≦Vbg yields the following:

[0043] VDD-R1×Iso≦VDD-Rx2×Ileak

[0044] By rearranging this equation and substituting the specific values ​​mentioned above, we obtain the following equation 1.

[0045] Rx2≦R1×(Iso / Ileak)=2k×(50μA / 500nA)=200k[Ω]...Formula 1

[0046] Therefore, the resistance value Rx2 of the second back gate resistor 42 should be set to 200 kΩ or less.

[0047] Next, the lower limit of the resistance value Rx2 of the second back gate resistor 42 will be described. As explained in the first circuit configuration example, the lower limit of the resistance value of the second backgate resistor 42 is selected so that the cutoff frequency fc of the low-pass filter formed by Rx2 and the parasitic capacitance Cbsub is equal to or lower than the frequency of the high-frequency noise whose influence is to be reduced. In this second circuit configuration example, the third and fourth transistors 3 and 4 are formed on the same n-type well, and the parasitic capacitance Cbsub between the n-type well, which serves as the back gate in the CMOS process used, and the p-type substrate is approximately 4.8 pF.

[0048] Furthermore, for example, to reduce the influence of high frequency noise above 100 MHz, the cutoff frequency fc of the low-pass filter must be set to 100 MHz or less, and the lower limit of Rx2 under these conditions will be found below. Under the above conditions, the cutoff frequency fc must satisfy the following formula:

[0049] fc=1 / (2π×Rx2×Cbsub)≦100M[Hz]

[0050] If we rearrange this equation into an equation for Rx2, we get the following equation 2.

[0051] Rx2≧1 / (2π×fc×Cbsub)=1 / (2π×100M×4.8p)=332[Ω]...Formula 2

[0052] Therefore, the resistor Rx2 is selected from the range defined by the following formula 3 based on the above formulas 1 and 2.

[0053] 332Ω≦Rx2≦200kΩ...Formula 3

[0054] In this second circuit configuration example, the second backgate resistor 42 is a resistor having the same structure as the first and second resistors 31 and 32. Therefore, selecting a resistance value for the second backgate resistor 42 that is significantly different from the resistance values ​​of the first and second resistors 31 and 32 is not advisable because it would increase chip size and cost. Therefore, in this second circuit configuration example, a resistance value that satisfies Equation 3 is preferably selected to be on the same kΩ order as the resistance values ​​R1 and R2 of the first and second resistors 31 and 32, with Rx2 = 1 kΩ.

[0055] In FIG. 11, the fluctuation characteristics of the output voltage in response to high frequency noise of the operational amplifier in this second circuit configuration example are shown by the solid characteristic line marked with a symbol . In the case of the operational amplifier in this second circuit configuration example, the output voltage Vout = 6 can be maintained up to an input power of 27 dBm. Compared to the conventional circuit (see the characteristic line marked with symbol C in Figure 11), the output voltage does not fluctuate even at input powers with high high-frequency noise, and it can be confirmed that the impact of high-frequency noise on the output voltage has been reliably improved.

[0056] Next, a third example of the circuit configuration will be described with reference to FIG. Note that components that are the same as those in the first circuit configuration example shown in FIG. 1 or the second circuit configuration example shown in FIG. 2 are given the same reference numerals, and detailed descriptions thereof will be omitted. The following description will focus on the differences. The operational amplifier in this third circuit configuration example is configured to be roughly divided into an input stage differential amplifier circuit 100A, a source grounded amplifier circuit 200B, and an output circuit 300A. The input stage differential amplifier circuit 100A has the same configuration as that described in the first circuit configuration example shown in Fig. 1. The common-source amplifier circuit 200B has the same configuration as that described in the second circuit configuration example shown in Fig. 2.

[0057] Therefore, the operational amplifier in this third circuit configuration example, like the first circuit configuration example, is capable of reducing and suppressing the intrusion of high-frequency noise from the back gate of the input stage P-channel MOSFET, and like the second circuit configuration example, is capable of reducing and suppressing the intrusion of high-frequency noise from the back gate of the P-channel MOSFET of the constant current source section 200B-2.

[0058] Next, a fourth example of the circuit configuration will be described with reference to FIG. Note that components that are the same as those in the first circuit configuration example shown in FIG. 1 or the second circuit configuration example shown in FIG. 2 are given the same reference numerals, and detailed descriptions thereof will be omitted. The following description will focus on the differences. The operational amplifier in this fourth circuit configuration example is configured to be roughly divided into an input stage differential amplifier circuit 100C, a source grounded amplifier circuit 200B, and an output circuit 300A.

[0059] As will be described later, the input stage differential amplifier circuit 100C has a different configuration from the first to third circuit configuration examples. On the other hand, the source-grounded amplifier circuit 200B has the configuration as described in the second circuit configuration example shown in FIG. 2, and the output circuit 300A has the configuration as described in the first circuit configuration example shown in FIG. 1.

[0060] The input stage differential amplifier circuit 100C is configured to enable differential amplification by two differential pair circuits 100C-1 and 100C-2 provided in parallel with the input. The first differential pair circuit 100C-1 is configured mainly by first and second transistors 1 and 2 using P-channel MOSFETs and a constant current source 15, and its basic configuration is the same as that of the input stage differential amplifier circuit 100A described in the first circuit configuration example. Therefore, a detailed description of the circuit configuration of the first differential pair circuit 100C-1 will be omitted here.

[0061] The second differential pair circuit 100C-2 is configured with first and second transistors 21 and 22 for the second differential pair (denoted as "M1b" and "M2b" respectively in FIG. 4) and a constant current source 16 for the second differential pair as its main components. First, N-channel MOSFETs are used for the first and second transistors 21 and 22 for the second differential pair, and their sources are connected to each other. A constant current source 16 for the second differential pair is connected between the connection point and the negative power supply terminal 54.

[0062] In addition, the drain of the first transistor 21 for the second differential pair is connected to the source of the third transistor 3 of the source-grounded amplifier circuit 200B, and the drain of the second transistor 22 for the second differential pair is connected to the source of the fourth transistor 4. Furthermore, the back gates of the first and second transistors 21 and 22 for the second differential pair are both connected to the negative power supply terminal 54. The gate of the first transistor 21 for the second differential pair is connected to the inverting input terminal 51, and the gate of the second transistor 22 for the second differential pair is connected to the non-inverting input terminal 52, respectively. In this way, the provision of the second differential pair circuit 100C-2 makes it possible to accommodate a wider range of input signal levels, and stabilizes the output voltage.

[0063] The operational amplifier in this fourth circuit configuration example is basically capable of reducing and suppressing high-frequency noise that enters the power supply node in the same manner as the operational amplifier in the third circuit configuration example.

[0064] Next, a fifth example of the circuit configuration will be described with reference to FIG. Note that components that are the same as those in the first circuit configuration example shown in FIG. 1 or the second circuit configuration example shown in FIG. 2 are given the same reference numerals, and detailed descriptions thereof will be omitted. The following description will focus on the differences.

[0065] The operational amplifier in this fifth circuit configuration example is configured to be roughly divided into an input stage differential amplifier circuit 100A, a source grounded amplifier circuit 200C, and an output circuit 300A. The input stage differential amplifier circuit 100A and the output circuit 300A have the same configuration as that described in the first circuit configuration example shown in FIG. The common-source amplifier circuit 200C differs from the other circuit configuration examples in that the amplifier section 200C-1 and the constant current source section 200C-2 each have a configuration in which MOSFETs are cascode-connected, as will be described in detail below.

[0066] The specific details will be explained below. First, the amplifier section 200C-1 is configured mainly with fifth and sixth transistors 5 and 6, third and fourth resistors 33 and 34, and eleventh and twelfth transistors (represented as "M11" and "M12" in FIG. 5, respectively) 11 and 12. Note that the eleventh and twelfth transistors 11 and 12 are N-channel MOSFETs. This amplifier section 200C-1 has a configuration in which eleventh and twelfth transistors 11 and 12 are added in cascode connection to the fifth and sixth transistors 5 and 6 in the circuit configuration example of the amplifier section 200A-1 described in the first circuit configuration example, as will be described below.

[0067] First, a third resistor 33 is provided between the source of the fifth transistor 5 and the negative power supply terminal 54, and a fourth resistor 34 is provided between the source of the sixth transistor 6 and the negative power supply terminal 54, which is the same as in the first circuit configuration example. The source of the eleventh transistor 11 is connected to the drain of the fifth transistor 5, and the source of the twelfth transistor 12 is connected to the drain of the sixth transistor 6, respectively. In addition, the drain of the first transistor 1 is connected to the connection point between the source of the eleventh transistor 11 and the drain of the fifth transistor 5, and the drain of the second transistor 2 is connected to the connection point between the source of the twelfth transistor 12 and the drain of the sixth transistor 6.

[0068] On the other hand, the drain of the eleventh transistor 11 is connected to a constant current source section 200C-2, which will be described later, and is also connected to the gates of the fifth and sixth transistors 5 and 6, respectively. The drain of the twelfth transistor 12 is connected to the input stage of the output circuit 300A.

[0069] Furthermore, a required third bias voltage VBias3 generated within a circuit (not shown) of the operational amplifier is applied to the gates of the eleventh and twelfth transistors 11 and 12, respectively. Furthermore, the back gates of the eleventh and twelfth transistors 11 and 12, as well as the fifth and sixth transistors 5 and 6, are connected to the negative power supply terminal .

[0070] Next, the constant current source section 200C-2 is mainly composed of third and fourth transistors 3 and 4, first and second resistors 31 and 32, and ninth and tenth transistors (represented as "M9" and "M10" in FIG. 5, respectively) 9 and 10. Note that the ninth and tenth transistors 9 and 10 are P-channel MOSFETs. This constant current source section 200C-2 has a configuration in which ninth and tenth transistors 9 and 10 are added in cascode connection to the third and fourth transistors 3 and 4 in the circuit configuration example of the constant current source section 200B-2 described in the second circuit configuration example, as will be described below.

[0071] First, a first resistor 31 is provided between the source of the third transistor 3 and the positive power supply terminal 53, and a second resistor 32 is provided between the source of the fourth transistor 4 and the positive power supply terminal 53, which is the same as in the second circuit configuration example. Also, the back gates of the third and fourth transistors 3 and 4 are both connected to the positive power supply terminal 53 via the second back gate resistor 42, which is the same as in the second circuit configuration example, but in addition, the back gates of the ninth and tenth transistors 9 and 10 are also connected to the positive power supply terminal 53 via the second back gate resistor 42.

[0072] The source of the ninth transistor 9 is connected to the drain of the third transistor 3, and the source of the tenth transistor 10 is connected to the drain of the fourth transistor 4, respectively. The drain of the ninth transistor 9 is connected to the drain of the eleventh transistor 11, and the drain of the tenth transistor 10 is connected to the input stage of the output circuit 300A.

[0073] A required first bias voltage VBias1 generated within the circuit (not shown) of the operational amplifier is applied to the gates of the third and fourth transistors 3 and 4, and a required second bias voltage VBias2 similarly generated within the circuit is applied to the gates of the ninth and tenth transistors 9 and 10. Therefore, in this fifth circuit configuration example, it is possible to obtain the same high-frequency noise reduction and suppression effect against the intrusion of high-frequency noise into the power supply node as in the operational amplifier in the third circuit configuration example. [Industrial Applicability]

[0074] This can be applied to operational amplifiers where it is desired to reduce or suppress the intrusion of high frequency external noise from the power supply line while keeping manufacturing costs down. [Explanation of symbols]

[0075] 1...first transistor 2...Second transistor 3...Third transistor 4...Fourth transistor 41...Back gate resistor 42...Second back gate resistor 51...Inverting input terminal 52...Non-inverting input terminal 53...Positive power supply terminal 54...Negative power supply terminal 55...Output terminal 100A, 100B, 100C...Differential amplifier circuit 200A, 200B, 200C...Amplifier circuit 300A...Output circuit

Claims

1. An operational amplifier comprising: a differential amplifier circuit configured to be capable of differentially amplifying an input signal; an amplifier circuit that amplifies an output signal of the differential amplifier circuit; and an output circuit configured to be capable of outputting the output signal of the amplifier circuit at a desired output level, 10. An operational amplifier, wherein the differential amplifier circuit is configured using a P-channel MOSFET, and a power supply voltage is applied to a back gate of the P-channel MOSFET via an impedance element.

2. 2. The operational amplifier according to claim 1, wherein the amplifier circuit has a constant current source section using a P-channel MOSFET, and the back gate of the P-channel MOSFET of the constant current source section is configured so that a power supply voltage is applied to the back gate via an impedance element.

3. An operational amplifier comprising: a differential amplifier circuit configured to be capable of differentially amplifying an input signal; an amplifier circuit that amplifies an output signal of the differential amplifier circuit; and an output circuit configured to be capable of outputting the output signal of the amplifier circuit at a desired output level, The amplifier circuit has a constant current source section using a P-channel MOSFET, and a power supply voltage is applied to a back gate of the P-channel MOSFET of the constant current source section via an impedance element.

4. The impedance element is a resistor, and the upper limit value of the resistor is selected so that the potential relationship between the back gate potential and the source potential, which is determined by a voltage drop occurring in the resistor due to a leakage current flowing through a parasitic diode between an n-type well connected to the back gate of the P-channel MOSFET connected to the resistor and a p-type substrate, is such that the back gate potential is higher than the source potential; 4. An operational amplifier according to claim 1, wherein the lower limit value of the resistor is selected so that the cutoff frequency of a low-pass filter formed by the resistor and a parasitic capacitance between the n-type well and the p-type substrate is lower than a high-frequency noise frequency.

5. 5. The operational amplifier according to claim 4, wherein the differential amplifier circuit comprises a first differential pair circuit made up of P-channel MOSFETs and a second differential pair circuit made up of N-channel MOSFETs, which are provided in parallel with respect to the input.

6. the amplifier circuit includes an amplifier section and a constant current source section, The amplifier section is configured by cascode-connecting P-channel MOSFETs to form a source-grounded amplifier circuit, 6. The operational amplifier according to claim 5, wherein said constant current source section is configured by cascode connection of N-channel MOSFETs.

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