Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing defects caused by cracks.SOLUTION: The semiconductor device includes: a substrate including: at least one wiring layers; a first insulating film provided on the upper surface of a first wiring layer, the first wiring layer being the uppermost layer of the one or more wiring layers; and a second insulating film 21 provided on a lower surface of a second wiring layer 11, the second wiring layer 11 being the lowermost layer of the one or more wiring layers; and a semiconductor chip provided on the substrate, the second wiring layer 11 including: first wiring and second wiring 11a that extend from an opening 1b formed in the second insulating film 21 and have linear parts D1-D4; and third wiring 11a provided at a position facing the opening between the first wiring and the second wiring, the third wiring 11a having parts R1-R4.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Cracks can be a problem in semiconductor packages. For example, cracks can propagate from EB (etch-back) openings in the SR (solder resist) layer into the SR layer, causing problems in the semiconductor package. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. US2022 / 0352023 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of suppressing defects caused by cracks is provided. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor device includes a substrate including one or more wiring layers, a first insulating film provided on an upper surface of a first wiring layer that is the uppermost layer of the one or more wiring layers, and a second insulating film provided on a lower surface of a second wiring layer that is the lowermost layer of the one or more wiring layers. The device further includes a semiconductor chip provided on the substrate. The first or second wiring layer includes a first wiring and a second wiring extending from an opening provided in the first or second insulating film, and a third wiring provided between the first wiring and the second wiring and facing the opening. [Brief explanation of the drawings]

[0006] [Figure 1]1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 2] 4 is a cross-sectional view illustrating a crack in the semiconductor device according to the first embodiment. FIG. [Figure 3] FIG. 2 is a plan view showing the structure of a semiconductor device of a comparative example of the first embodiment. [Figure 4] FIG. 10 is a plan view illustrating an EB opening of a semiconductor device according to a comparative example of the first embodiment. [Figure 5] FIG. 10 is a plan view for explaining cracks in a semiconductor device of a comparative example of the first embodiment. [Figure 6] FIG. 10 is another plan view for explaining cracks in the semiconductor device of the comparative example of the first embodiment. [Figure 7] 1 is a plan view showing the structure of a semiconductor device according to a first embodiment. [Figure 8] 2A to 2C are plan views showing various examples of dummy wirings of the semiconductor device of the first embodiment. [Figure 9] 10A and 10B are plan views showing EB openings of first and second modified examples of the first embodiment. [Figure 10] 10A and 10B are plan views showing EB openings in third and fourth modified examples of the first embodiment. [Figure 11] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. In Figures 1 to 11, the same components are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0008] (First embodiment) FIG. 1 is a cross-sectional view showing the structure of a semiconductor device of a first embodiment. In FIG. 1, the semiconductor device of this embodiment has the form of a semiconductor package. The semiconductor device of this embodiment includes a substrate 1, a semiconductor chip 3, a resin layer 4, a resin layer 5, a plurality of bonding wires 6, and a plurality of solder balls 7. The cross section of FIG. 1 shows one of the plurality of bonding wires 6 and one of the plurality of solder balls 7, with the other bonding wires 6 and solder balls 7 being included in another cross section.

[0009] The substrate 1 includes a wiring layer 11, a plurality of via plugs 12, a wiring layer 13, a plurality of via plugs 14, a wiring layer 15, and resin layers 21-27. The cross section of FIG. 1 shows two of the plurality of via plugs 12 and two of the plurality of via plugs 14, with the remaining via plugs 12 and 14 being included in another cross section. The wiring layers 11, 13, and 15 are examples of one or more wiring layers. The wiring layer 15 is an example of a first wiring layer, and the wiring layer 11 is an example of a second wiring layer. The resin layer 27 is an example of a first insulating film, and the resin layer 21 is an example of a second insulating film.

[0010] Substrate 1 is, for example, a wiring board such as a printed circuit board. Fig. 1 shows an upper surface Fa of substrate 1 and a lower surface Fb of substrate 1. Fig. 1 also shows an X direction and a Y direction that are parallel to and perpendicular to the upper surface Fa and the lower surface Fb of substrate 1, and a Z direction that is perpendicular to the upper surface Fa and the lower surface Fb of substrate 1. The X direction, the Y direction, and the Z direction intersect with each other.

[0011] The wiring layers 11, 13, and 15 form a multilayer wiring structure within the substrate 1. The wiring layer 11 is the lowest layer among the wiring layers 11, 13, and 15. The wiring layer 15 is the highest layer among the wiring layers 11, 13, and 15. The wiring layer 13 is provided between the wiring layers 11 and 15, and is located above the wiring layer 11 and below the wiring layer 15. Each of the wiring layers 11, 13, and 15 is a metal layer including, for example, a Cu (copper) layer. Each of the wiring layers 11, 13, and 15 is configured to include multiple wires. The multilayer wiring structure within the substrate 1 may include four or more wiring layers, or may include only one or two wiring layers.

[0012] Each via plug 12 is provided between the wiring layer 11 and the wiring layer 13, and electrically connects the wiring layer 11 and the wiring layer 13. Each via plug 14 is provided between the wiring layer 13 and the wiring layer 15, and electrically connects the wiring layer 13 and the wiring layer 15. Each of the via plugs 12 and 14 is, for example, a metal layer including a Cu layer.

[0013] Resin layers 21 to 27 are laminated in order from the lower surface Fb to the upper surface Fa of substrate 1. Resin layer 21 is provided on the lower surface of wiring layer 11, and forms the lower surface Fb of substrate 1. Resin layers 22 and 23 are provided in order between the upper surfaces of resin layer 21 and wiring layer 11 and the lower surface of resin layer 24. Resin layer 24 is provided so as to surround wiring layer 13. Resin layers 25 and 26 are provided in order between the upper surface of resin layer 24 and the lower surface of resin layer 27 and wiring layer 15. Resin layer 27 is provided on the upper surface of wiring layer 15, and forms the upper surface Fa of substrate 1.

[0014] Each of the resin layers 21 to 27 is, for example, an insulating film. More specifically, the resin layers 21 and 27 are, for example, SR (solder resist) layers. The resin layers 22, 24, and 26 are, for example, prepreg layers. The resin layers 23 and 25 are, for example, glass cloth layers.

[0015] FIG. 1 further shows a plurality of EB (etch-back) openings 1a and 1b formed in the substrate 1. Each EB opening 1b is formed in the resin layer 21 and the wiring layer 11 on the lower surface Fb of the substrate 1. Meanwhile, each EB opening 1a is formed in the resin layer 27 and the wiring layer 15 on the upper surface Fa of the substrate 1. The left EB opening 1a shown in FIG. 1 is not formed in the wiring layer 15 in the cross section of FIG. 1, but is formed in the wiring layer 15 in another cross section. The EB openings 1a and 1b of this embodiment are formed when the resin layers 27 and 21 and the wiring layers 15 and 11 are processed by etch-back, respectively. Further details of the EB openings 1a and 1b of this embodiment will be described later.

[0016] The semiconductor chip 3 is provided on the substrate 1 via a resin layer 4. The semiconductor chip 3 is, for example, a memory chip including a 3D NAND memory. Note that the semiconductor device of this embodiment may include two or more semiconductor chips.

[0017] The resin layers 4 and 5 are provided on the substrate 1. More specifically, the resin layer 4 is provided between the substrate 1 and the semiconductor chip 3 and in the EB opening 1a of the substrate 1. The resin layer 5 is provided on the substrate 1 so as to cover the semiconductor chip 3. The resin layer 4 is, for example, an adhesive layer. The resin layer 5 is, for example, an epoxy resin layer.

[0018] Each bonding wire 6 electrically connects one of the semiconductor chips 3 to the wiring layer 15. The bonding wire 6 shown in Fig. 1 electrically connects a bonding pad 3a provided on the upper surface of the semiconductor chip 3 to a wiring (bonding pad) in the wiring layer 15. In Fig. 1, the resin layer 27 has an opening for joining the wiring and the bonding wire 6.

[0019] Each solder ball 7 is provided on the lower surface of the wiring layer 11 and is electrically connected to the wiring layer 11. The solder balls 7 shown in FIG. 1 are provided on the lower surface of the wiring (external connection pads) in the wiring layer 11. In FIG. 1, the resin layer 21 has openings for joining the wiring and the solder balls 7. The wiring can be electrically connected to a device external to the semiconductor device of this embodiment via the solder balls 7. Note that the wiring may also be electrically connected to a device external to the semiconductor device of this embodiment via a member other than the solder balls 7 (for example, a metal bump).

[0020] FIG. 2 is a cross-sectional view for explaining cracks in the semiconductor device of the first embodiment.

[0021] 2 shows examples of various cracks that may occur in the semiconductor device of this embodiment. In FIG. 2, cracks B1 and B2 are generated from starting points A1 and A2, respectively. Specifically, crack B1 is generated from starting point A1 on the side surface of one EB opening 1b and propagates within substrate 1, while crack B2 is generated from starting point A2 on the side surface of another EB opening 1b and propagates within substrate 1. In FIG. 2, these cracks B1 and B2 cause fractures in substrate 1.

[0022] During a temperature cycling test (TCT) of the semiconductor device of this embodiment, the resin layers 27 and 21 are likely to crack due to thermal stress near the EB openings 1a and 1b. As a result, cracks may occur in the substrate 1, and the wiring layers 11, 13, and 15 in the substrate 1 may be broken by the cracks. If the wiring layers 11, 13, and 15 are broken by the cracks, the semiconductor device of this embodiment may suffer from defects. For example, cracks are likely to occur at the interface between the wiring layer 11 and the resin layer 21 or the interface between the wiring layer 15 and the resin layer 27, and tend to propagate along the wiring layer 11 or the wiring layer 15.

[0023] Next, a semiconductor device of a comparative example of the first embodiment will be described with reference to Figures 3 to 5. The semiconductor device of this comparative example has roughly the same structure as the semiconductor device of the first embodiment, and the structure shown in Figure 1 is roughly common between the first embodiment and this comparative example. Therefore, in describing the semiconductor device of this comparative example, the same reference numerals as those used in the description of the semiconductor device of the first embodiment will be used, and Figure 1 will be referred to as appropriate.

[0024] FIG. 3 is a plan view showing the structure of a semiconductor device as a comparative example of the first embodiment.

[0025] 3 corresponds to a plan view of the lower surface Fb of the substrate 1 shown in FIG. 1 viewed upward. FIG. 3 shows the wiring layer 11, the resin layer 21 (shown by dot hatching), a plurality of solder balls 7, and a plurality of EB openings 1b. However, in order to show the shape of the wiring layer 11, FIG. 3 does not show the resin layer 21 covering the lower surface of the wiring layer 11, and shows only the resin layer 21 provided within the wiring layer 11. In other words, FIG. 3 shows an XY cross section of the semiconductor device of this comparative example at the height of the lower surface of the wiring layer 11.

[0026] The wiring layer 11 of this comparative example includes a plurality of wirings 11a that are separated from one another. In FIG. 3, these wirings 11a include 12 island-shaped wirings 11a (hereinafter also referred to as "island wirings 11a") as indicated by the symbol Ia, and one wiring 11a (hereinafter also referred to as "peripheral wiring 11a") provided around these island-shaped wirings 11a as indicated by the symbol Ib. Each island-shaped wiring 11a is used as an external connection pad that is electrically connected to a solder ball 7. In FIG. 3, a solder ball 7 is provided on the lower surface of each island-shaped wiring 11a. The lower surface of each island-shaped wiring 11a includes a portion covered with the solder ball 7 and a portion located around the solder ball 7, and FIG. 3 shows the portion of the lower surface of each island-shaped wiring 11a that is located around the solder ball 7.

[0027] As shown in FIG. 3, each island-shaped wiring 11a has one or more linear portions having a linear shape. Each linear portion extends to one of the EB openings 1b. Similarly, the peripheral wiring 11a also has one or more linear portions extending to one or more EB openings 1b outside the region shown in FIG. 3. The multiple wirings 11a (island-shaped wirings 11a and peripheral wirings 11a) in this comparative example are connected to each other by these linear portions before the EB openings 1b are formed, but are separated from each other after the EB openings 1b are formed. The reason these wirings 11a are connected to each other before the EB openings 1b are formed is to plate these wirings 11a (i.e., wiring layer 11). The plating is formed using, for example, an Au (gold) layer. On the other hand, the reason these wirings 11a are separated from each other after the EB openings 1b are formed is to eliminate short circuits between these wirings 11a.

[0028] In FIG. 3, each EB opening 1b is disposed between four island-shaped wirings 11a. These island-shaped wirings 11a are connected to each other before the EB opening 1b is formed, but are separated from each other after the EB opening 1b is formed. Note that, like the two island-shaped wirings 11a in the center and the two EB openings 1b to the lower left shown in FIG. 3, each island-shaped wiring 11a may extend to the EB opening 1b in a form other than a linear portion. As shown in FIG. 3, the openings 1b in this comparative example have a circular shape in a plan view.

[0029] FIG. 3 shows the X, Y, and Z directions, as well as the X' and Y' directions, which are parallel to the upper surface Fa and lower surface Fb of the substrate 1 and perpendicular to each other. The X' direction is a 45-degree direction in the XY plane. The Y' direction is a 135-degree direction in the XY plane. In FIG. 3, each linear portion extends parallel to the X' or Y' direction. The X' and Y' directions will be used in the explanations of FIGS. 5 to 10.

[0030] FIG. 4 is a plan view for explaining an EB opening of a semiconductor device as a comparative example of the first embodiment.

[0031] 4(a) includes four planar portions C1 to C4, four linear portions D1 to D4, and one connecting portion E. The linear portions D1 to D4 extend from the planar portions C1 to C4, respectively, to the connecting portion E and are connected to each other at the connecting portion E.

[0032] 4(a) shows the wiring layer 11 before the EB opening 1b is formed, while FIG. 4(b) shows the wiring layer 11 after the EB opening 1b is formed. In FIG. 4(b), the EB opening 1b is formed in the connecting portion E. As a result, the wiring layer 11 is processed into a shape including wiring 11a having a planar portion C1 and a linear portion D1, wiring 11a having a planar portion C2 and a linear portion D2, wiring 11a having a planar portion C3 and a linear portion D3, and wiring 11a having a planar portion C4 and a linear portion D4. These wirings 11a are separated from each other by the EB opening 1b.

[0033] These wirings 11a correspond to the island-shaped wirings 11a shown in Fig. 3. Furthermore, the planar portions C1 to C4 of these wirings 11a correspond to the external connection pads described above. Therefore, solder balls 7 (not shown) are provided on the lower surfaces of the planar portions C1 to C4.

[0034] 5 and 6 are plan views for explaining cracks in a semiconductor device of a comparative example of the first embodiment.

[0035] Figure 5(a) shows the same wiring layer 11 as the wiring layer 11 in Figure 4(b). However, in order to make the explanation of the cracks easier to understand, the plan view in Figure 5(a) is rotated 45 degrees from the plan view in Figure 4(b) so that the X' direction is horizontal and the Y' direction is vertical.

[0036] Fig. 5(a) shows the wiring layer 11 before cracks occur, while Fig. 5(b) shows the wiring layer 11 after cracks occur. Fig. 5(b) shows multiple cracks B that have occurred from multiple starting points A. These cracks B have occurred from starting points A on the side of the EB opening 1b and from starting points A of linear portions D1 to D4 near the EB opening 1b. The arrows in Fig. 5(b) indicate the direction in which the cracks B propagate.

[0037] As described above, crack B is likely to initiate from starting point A near EB opening 1b. In FIG. 5(b), crack B initiated from starting point A near EB opening 1b propagates through resin layer 21 between linear portion D1 and linear portion D2, between linear portion D1 and linear portion D3, between linear portion D3 and linear portion D4, and between linear portion D2 and linear portion D4. In FIG. 5(b), crack B propagates in the in-plane direction of the XY plane, but it also propagates in the Z direction. When crack B propagates in the in-plane direction of the XY plane, crack B is likely to propagate in the Z direction as well.

[0038] 5(a) and 5(b) show planar portions C1-C4 and linear portions D1-D4 near one EB opening 1b, while FIG. 6 shows planar portions C1-C7 and linear portions D1-D7 near two EB openings 1b. For example, as shown in FIG. 6, if cracks B originate from multiple EB openings 1b and propagate in the in-plane direction of the XY plane, the cracks B in adjacent EB openings 1b may connect to each other, causing the cracks B to propagate over a wide area. As a result, if the wiring layer 11 is broken by the cracks B, defects may occur in the semiconductor device of this comparative example. For example, if the wiring 11a used as a signal line is broken by the cracks B, necessary signals may not be transmitted within the semiconductor device. Similarly, if the cracks B propagate in the Z direction, the wiring in the wiring layers 13 and 15 used as signal lines may also be broken by the cracks B (this will be described in detail in the second embodiment).

[0039] 3 to 6 can be applied not only to the EB opening 1b, the wiring layer 11, and the resin layer 21, but also to the EB opening 1a, the wiring layer 15, and the resin layer 27. This also applies to FIGS. 7 to 11, which will be described later.

[0040] FIG. 7 is a plan view showing the structure of the semiconductor device of the first embodiment.

[0041] Fig. 7 is a plan view corresponding to Fig. 5(b). However, the EB opening 1b shown in Fig. 7 has a quadrilateral (e.g., square) shape in plan view. Fig. 7 shows four side surfaces S1 to S4 of the EB opening 1b and four corner portions P1 to P4 between the side surfaces S1 to S4. In plan view of the EB opening 1b, the side surfaces S1 to S4 correspond to the four sides of the quadrilateral, and the corner portions P1 to P4 correspond to the four corners of the quadrilateral.

[0042] The corner portions P1 to P4 protrude from the resin layer 21 in a plan view. As a result of investigation, it was found that cracks B tend to occur from starting points A on the corner portions P1 to P4. FIG. 7 shows cracks B that have occurred from starting points A on the corner portion P1, cracks B that have occurred from starting points A on the corner portion P2, cracks B that have occurred from starting points A on the corner portion P3, and cracks B that have occurred from starting points A on the corner portion P4. In the corner portions P1 to P4, the cracks B are connected to the EB openings 1b. Furthermore, as shown in FIG. 7, the cracks B tend to propagate along the wiring 11a. The corner portions P1 to P4 are examples of one or more protruding portions and examples of first protruding portions.

[0043] According to this embodiment, by providing corner portions P1 to P4 at the EB opening 1b, it is possible to control the location of crack B. For example, by providing corner portion P1 between linear portions D1 and D3 rather than on linear portions D1 and D3, it is possible to prevent crack B from originating on linear portions D1 and D3, thereby making it easier to prevent crack B from breaking linear portions D1 and D3. In FIG. 7, corner portion P1 is provided far from linear portion D1 and far from linear portion D3. The same applies to corner portions P2 to P4. Corner portion P2 is provided between linear portions D1 and D2 rather than on linear portions D1 and D2; corner portion P3 is provided between linear portions D3 and D4 rather than on linear portions D3 and D4; and corner portion P4 is provided between linear portions D2 and D4 rather than on linear portions D2 and D4.

[0044] The EB opening 1b shown in FIG. 7 has, for example, a square shape in plan view. Therefore, the corner P1 has a shape that forms a right angle in plan view. That is, the angle between the side S1 and the side S3 in plan view is 90 degrees. The same applies to the corners P2 to P4. Each of the corners P1 to P4 may have a shape that forms an acute angle in plan view, or a shape that forms an obtuse angle in plan view. However, because an acute-angle corner is more likely to become the starting point A of a crack B than an obtuse-angle corner, it is preferable that the shape of the corner be an acute angle rather than an obtuse angle.

[0045] The EB opening 1b may have a polygonal shape (e.g., a regular polygonal shape) other than a quadrangle in plan view. Examples of such polygonal shapes include a triangle and a hexagon. Various examples of the planar shape of the EB opening 1b will be described later.

[0046] Similar to the wiring layer 11 of the comparative example, the wiring layer 11 of this embodiment includes wiring 11a having a planar portion C1 and a linear portion D1, wiring 11a having a planar portion C2 and a linear portion D2, wiring 11a having a planar portion C3 and a linear portion D3, and wiring 11a having a planar portion C4 and a linear portion D4. However, FIG. 7 does not show the planar portions C1 to C4. The linear portions D1 to D4 extend from the side surfaces S1 to S4 of the EB opening 1b to the planar portions C1 to C4, respectively. The linear portions D1 to D4 of these wirings 11a are examples of first and second wirings, and the planar portions C1 to C4 of these wirings 11a are examples of first and second pads.

[0047] The wiring layer 11 of this embodiment further includes a wiring 11a having a portion R1, a wiring 11a having a portion R2, a wiring 11a having a portion R3, and a wiring 11a having a portion R4. The wiring 11a having the portion R1 is provided between the linear portion D1 and the linear portion D3 at a position facing the corner P1 of the EB opening 1b. The wiring 11a having the portion R2 is provided between the linear portion D1 and the linear portion D2 at a position facing the corner P2 of the EB opening 1b. The wiring 11a having the portion R3 is provided between the linear portion D3 and the linear portion D4 at a position facing the corner P3 of the EB opening 1b. The wiring 11a having the portion R4 is provided between the linear portion D2 and the linear portion D4 at a position facing the corner P4 of the EB opening 1b. The wiring 11a having the portions R1 to R4 is an example of a third wiring.

[0048] The wiring 11a having the portions R1 to R4 is, for example, a dummy wiring that does not function as a wiring capable of controlling the semiconductor device of this embodiment. Therefore, each of the wirings 11a having the portions R1 to R4 is not electrically connected to the semiconductor chip 3 or the solder balls 7, and is unable to control the semiconductor chip 3. Each of the wirings 11a having the portions R1 to R4 may be electrically connected to the semiconductor chip 3 or the solder balls 7, but may not be used to control the semiconductor chip 3. The dummy wiring of this embodiment may be realized in either the former or latter manner. Hereinafter, the wiring 11a having the portions R1 to R4 will be referred to as a "dummy wiring 11a" or a "dummy wiring R." In FIG. 7, each dummy wiring R is electrically insulated from wirings 11a other than the dummy wiring R (such as the wirings 11a having the linear portions D1 to D4) and is also electrically insulated from other dummy wirings R.

[0049] The dummy wirings 11a will be described in further detail below with continued reference to Fig. 7. In this description, Fig. 8 will also be referred to as appropriate. Fig. 8 is a plan view showing various examples of the dummy wirings 11a of the semiconductor device of the first embodiment.

[0050] 7 and 8(a), the dummy wiring 11a having the portion R1 has a circular shape in a plan view. Hereinafter, the dummy wiring 11a having the portion R1 will also be referred to as a "dummy wiring R1" to distinguish it from other dummy wirings 11a.

[0051] In FIG. 7, a crack B that has started from a starting point A on the corner portion P1 reaches the dummy wiring R1. As a result, the direction in which the crack B propagates changes at the dummy wiring R1. This is because the crack B propagates more easily toward the resin layer 21 than toward the dummy wiring R1. According to this embodiment, by arranging the dummy wiring R1 near the corner portion P1, the range in which the crack B propagates near the corner portion P1 can be limited, and the crack B can be prevented from propagating over a wide area. In other words, the dummy wiring R1 functions as a guide that changes the direction in which the crack B propagates.

[0052] 7 and 8(b), the dummy wiring 11a having the portion R2 has an arc shape in plan view. Hereinafter, the dummy wiring 11a having the portion R2 will also be referred to as a "dummy wiring R2."

[0053] FIG. 8(b) shows the side surface S of the dummy wiring R2 in the -Y direction with a thick line. As shown in FIG. 7, the side surface S of the dummy wiring R2 faces the corner portion P2 in a planar view. Specifically, the side surface S of the dummy wiring R2 has a curved shape in a planar view, and has a shape that is recessed in a direction away from the EB opening 1b. In this embodiment, since the shape of the dummy wiring R2 is an arc in a planar view, the side surface S of the dummy wiring R2 has a shape that forms an arc (part of a circle) in a planar view. The shape of the side surface S of the dummy wiring R2 is a concave shape that is recessed in the +Y direction in a planar view.

[0054] In FIG. 7 , a crack B generated from a starting point A on the corner P2 reaches the side surface S of the dummy wiring R2 and returns to the EB opening 1b. This is because the side surface S of the dummy wiring R2 is recessed, so that the crack B that reaches the side surface S of the dummy wiring R2 easily propagates along the side surface S of the dummy wiring R2 in a direction returning to the EB opening 1b. According to this embodiment, by disposing the dummy wiring R2 near the corner P2, the crack B that reaches the dummy wiring R2 can be returned to the EB opening 1b. In other words, the dummy wiring R2 not only functions as a guide that changes the propagation direction of the crack B but also functions as a guide that returns the crack B to the EB opening 1b. The dummy wiring R2 can not only suppress the propagation of the crack B generated at the corner P2 in the +Y direction but also return the crack B to the EB opening 1b. Note that the propagation direction of the crack B may depend on chance, so the crack B that reaches the dummy wiring R2 may not return to the EB opening 1b.

[0055] 7 and 8(c), the dummy wiring 11a having the portion R3 has an L-shape in plan view. Hereinafter, the dummy wiring 11a having the portion R3 will also be referred to as "dummy wiring R3."

[0056] Figure 8(c) shows the side surface S of the dummy wiring R3 in the +Y direction with a thick line. Figure 8(c) also shows the angle θ formed by the side surface S of the dummy wiring R3 in a planar view. As shown in Figure 7, the side surface S of the dummy wiring R3 faces the corner portion P3 in a planar view. Specifically, the side surface S of the dummy wiring R3 has a shape that forms a right angle in a planar view (θ = 90°) and has a shape that is recessed in a direction away from the EB opening 1b. The shape of the side surface S of the dummy wiring R3 is concave, recessed in the -Y direction in a planar view.

[0057] In FIG. 7, a crack B initiated from a starting point A on the corner portion P3 reaches a side surface S of the dummy wiring R3 and returns to the EB opening 1b along the side surface S of the dummy wiring R3 and the side surface of the linear portion D4. Like the dummy wiring R2, the dummy wiring R3 can not only prevent the crack B initiated from the corner portion P3 from propagating in the −Y direction, but also return the crack B to the EB opening 1b. Furthermore, since the side surface S of the dummy wiring R3 has a right-angled shape rather than an arc shape in a plan view, the dummy wiring R3 can more effectively prevent the crack B from spreading than the dummy wiring R2. Note that the propagation direction of the crack B may depend on chance, so the crack B that reaches the dummy wiring R3 may not return to the EB opening 1b.

[0058] 7 and 8(d), the dummy wiring 11a having the portion R4 has a V-shape in plan view. Hereinafter, the dummy wiring 11a having the portion R4 will also be referred to as "dummy wiring R4."

[0059] FIG. 8(d) shows the side surface S of the dummy wiring R4 in the -X direction with a thick line. FIG. 8(d) further shows the angle θ formed by the side surface S of the dummy wiring R4 in a planar view. As shown in FIG. 7, the side surface S of the dummy wiring R4 faces the corner portion P4 in a planar view. Specifically, the side surface S of the dummy wiring R4 has a shape that forms an acute angle in a planar view (θ<90°) and has a shape that is recessed in a direction away from the EB opening 1b. The shape of the side surface S of the dummy wiring R4 is concave, recessed in the +X direction in a planar view.

[0060] In FIG. 7, a crack B initiated from a starting point A on the corner P4 reaches a side surface S of the dummy wiring R4 and returns along the side surface S of the dummy wiring R4 to the EB opening 1b. Like the dummy wirings R2 and R3, the dummy wiring R4 can not only prevent the crack B initiated from the corner P3 from propagating in the −Y direction, but also return the crack B to the EB opening 1b. Furthermore, since the side surface S of the dummy wiring R4 has an acute angled shape rather than an arc or a right angle in plan view, the dummy wiring R4 can more effectively prevent the crack B from spreading than the dummy wirings R2 and R3. Note that the propagation direction of the crack B may depend on chance, so the crack B that reaches the dummy wiring R4 may not return to the EB opening 1b.

[0061] 7, the four dummy wirings R1 to R4 arranged near one EB opening 1b have different shapes. On the other hand, two or more of the dummy wirings R1 to R4 may have the same shape. In order to explain various examples of the shapes of the dummy wirings R1 to R4, FIG. 7 illustrates dummy wirings R1 to R4 having different shapes.

[0062] Furthermore, the shapes of the EB opening 1b and the dummy wirings R1 to R4 of this embodiment may have height dependency (Z-direction dependency). For example, such height dependency is observed when the side surfaces of the EB opening 1b and the dummy wirings R1 to R4 have a tapered shape. In this case, the shapes of the EB opening 1b and the dummy wirings R1 to R4 shown in FIG. 7 may be established in a predetermined XY cross section of the semiconductor device of this embodiment. This also applies to FIGS. 9 and 10 described later.

[0063] Next, with reference to FIGS. 9 and 10, semiconductor devices according to first to fourth modifications of the first embodiment will be described.

[0064] 9A and 9B are plan views showing the EB opening 1b of the first and second modified examples of the first embodiment, respectively.

[0065] 9(a) shows the wiring layer 11, resin layer 21, EB opening 1b, etc. of the first modified example. FIG. 9(a) shows linear portions D1 to D4 and dummy wirings R1 to R4, but does not show planar portions C1 to C4.

[0066] The EB opening 1b of this modification has a planar shape with four corners (protruding portions) on a circle. Each corner has a shape that forms an angle α in a planar view. The angle α may be less than 90 degrees (acute angle), greater than 90 degrees (obtuse angle), or equal to 90 degrees (right angle), but is preferably 90 degrees or less. FIG. 9(a) shows a corner between linear portion D1 and linear portion D3, a corner between linear portion D1 and linear portion D2, a corner between linear portion D3 and linear portion D4, and a corner between linear portion D2 and linear portion D4. These corners are examples of one or more protruding portions and are examples of first protruding portions.

[0067] 9(a) shows a crack B generated from a starting point A on a corner portion having an angle α. According to this modification, similar to the first embodiment, by providing a corner portion at the EB opening 1b, it is possible to control the generation position of the crack B.

[0068] 9(b) shows the wiring layer 11, resin layer 21, EB opening 1b, etc. of the second modified example. FIG. 9(b) shows the linear portions D1 to D4 and dummy wirings R1 to R4, but does not show the planar portions C1 to C4.

[0069] The EB opening 1b of this modification has a square planar shape with 12 corners (protruding portions). Each corner has a shape that forms an angle α1 or an angle α2 in a planar view. The angles α1 and α2 may be less than 90 degrees (acute angle), greater than 90 degrees (obtuse angle), or equal to 90 degrees (right angle), but are preferably equal to or less than 90 degrees. In this modification, the angle α2 is set to be greater than the angle α1 (α2 > α1). In the region between the linear portion D1 and the linear portion D3, one corner having the angle α1 is provided between two corners having the angle α2. This is also true for the region between the linear portion D1 and the linear portion D2, the region between the linear portion D3 and the linear portion D4, and the region between the linear portion D2 and the linear portion D4. The corner having the angle α1 is an example of one or more protruding portions and is an example of a first protruding portion. On the other hand, the corner portion having the angle α2 is an example of one or more protruding portions and is also an example of a second protruding portion.

[0070] Figure 9(b) shows a crack B originating from a starting point A on one corner with an angle α1. This crack B returns to two corners (end points) with an angle α2. Our investigation revealed that the corners of the EB opening 1b are likely to be the starting point A or end point of the crack B. This is thought to be because large stress is likely to occur at corners. Furthermore, we found that the corner with an angle α1 is likely to be the starting point A of the crack B, and the corner with an angle α2 is likely to be the end point of the crack B. This is thought to be because the smaller the angle, the greater the stress. According to this modification, by providing these corners at the EB opening 1b, it is possible to control the initiation and end points of the crack B. Furthermore, according to this modification, by providing one corner with an angle α1 between two corners with an angle α2, it is possible to address the two propagation directions of the crack B, as shown in Figure 9(b).

[0071] The initiation and termination positions of crack B may depend on chance. For example, a corner with an angle α1 may be the end point of crack B, and a corner with an angle α2 may be the initiation point A of crack B. Also, while crack B shown in FIG. 9(b) initiates from initiation point A and then branches into two branches, each of which returns to two end points, crack B initiated from initiation point A may not branch and return to only one of the two end points. In this case, if crack B initiates from initiation point A and progresses to the left, the corner with an angle α2 to the left of the corner with angle α1 can accommodate the progression of crack B. If crack B initiates from initiation point A and progresses to the right, the corner with an angle α2 to the right of the corner with angle α1 can accommodate the progression of crack B.

[0072] FIG. 9(b) further shows the angle β between the side of linear portion D1 and the side of EB opening 1b, and between the side of linear portion D3 and the side of EB opening 1b, in the region between linear portion D1 and linear portion D3. When angle β is acute, the boundary between the side of linear portion D1 and the side of EB opening 1b (hereinafter referred to as "boundary 1") and the boundary between the side of linear portion D3 and the side of EB opening 1b (hereinafter referred to as "boundary 2") are likely to become the starting point A or the ending point of crack B. Therefore, to prevent boundary 1 or boundary 2 from becoming the starting point A or the ending point of crack B, it is desirable to make angle β larger than angle α1 and angle α2 (α1<α2<β). On the other hand, to prevent boundary 1 or boundary 2 from becoming the starting point A of crack B, angle β may be larger than angle α1 and smaller than angle α2 (α1<β<α2). This also applies to the region between the linear portion D1 and the linear portion D2, the region between the linear portion D3 and the linear portion D4, and the region between the linear portion D2 and the linear portion D4.

[0073] 10A and 10B are plan views showing EB openings 1b according to third and fourth modified examples of the first embodiment, respectively.

[0074] FIG. 10(a) shows an EB opening 1b of a third modified example. The EB opening 1b of this modified example has a triangular (e.g., equilateral) shape in a planar view. Therefore, the EB opening 1b of this modified example has three side surfaces and three corner portions (protruding portions). FIG. 10(a) also shows linear portions D1-D3 (wirings 11a) extending from these side surfaces of the EB opening 1b. FIG. 10(a) does not show planar portions C1-C3 of these wirings 11a or dummy wirings 11a.

[0075] FIG. 10(b) shows an EB opening 1b of a fourth modified example. The EB opening 1b of this modified example has a hexagonal (e.g., regular hexagonal) shape in a planar view. Therefore, the EB opening 1b of this modified example has six side surfaces and six corners (protruding portions). FIG. 10(b) also shows linear portions D1-D6 (wirings 11a) extending from these side surfaces of the EB opening 1b. FIG. 10(b) does not show planar portions C1-C6 of these wirings 11a or dummy wirings 11a.

[0076] As described above, the semiconductor device of this embodiment includes the dummy wiring 11a disposed at a position facing the EB opening 1b. This makes it possible to prevent the crack B from spreading over a wide area. Therefore, according to this embodiment, for example, the dummy wiring 11a can prevent the wiring layer 11 from breaking. In other words, according to this embodiment, it is possible to prevent defects caused by the crack B from occurring in the semiconductor device.

[0077] (Second embodiment) FIG. 11 is a cross-sectional view showing the structure of the semiconductor device of the second embodiment.

[0078] FIG. 11 corresponds to an enlarged view of FIG. 1. FIG. 11 shows the thickness T1 of the wiring layer 11 and the thickness T2 of the resin layer 21 on the lower surface of the wiring layer 11. In the present embodiment, the thickness T2 is set to be thinner than the thickness T1 (T2 < T1). As a result, the ratio of the volume of the wiring layer 11 to the total volume of the wiring layer 11 and the resin layer 21 increases, and the influence of the wiring layer 11 on the crack B increases. Thereby, as shown in FIG. 7, it becomes possible to easily advance the crack B along the wiring 11a.

[0079] Note that the relationship between the thickness T1 of the wiring layer 11 and the thickness T2 of the resin layer 21 may also hold between the wiring layer 15 and the resin layer 27.

[0080] FIG. 11 further shows a region H that overlaps the EB opening 1b in plan view. Individual portions within the region H are located in the Z direction of the EB opening 1b. FIG. 11 further shows a plurality of wirings 11a in the wiring layer 11, a plurality of wirings 13a in the wiring layer 13, and a plurality of wirings 15a in the wiring layer 15. The wiring layers 11, 13, and 15 of the present embodiment do not include the wirings 11a, 13a, and 15a within the region H that overlaps the EB opening 1b in plan view. The reason is that, like the crack B9 shown in FIG. 2, cracks tend to progress in the Z direction from the EB opening 1b. If the wirings 11a, 13a, and 15a are arranged within the region H, there is a risk that the wirings 11a, 13a, and 15a will be broken by such cracks. According to the present embodiment, by not arranging the wirings 11a, 13a, and 15a at positions that overlap the EB opening 1b in plan view, it is possible to suppress such breakage.

[0081] Note that the arrangement of the EB opening 1b as shown in FIG. 11 is preferably applied to other EB openings 1b of the semiconductor device of the present embodiment and each EB opening 1a of the semiconductor device of the present embodiment.

[0082] According to this embodiment, it is possible to further suppress the occurrence of defects due to crack B in the semiconductor device. Note that the semiconductor device of this embodiment has a first property that the wiring layer 11 and the resin layer 21 have a relationship of T2 < T1, and a second property that the wiring layers 11, 13, and 15 do not include the wirings 11a, 13a, and 15a in the region H overlapping with the EB opening 1b. However, it may have only one of the first and second properties instead.

[0083] As described above, several embodiments have been explained. However, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel device described in this specification can be implemented in various other forms. Also, various omissions, substitutions, and changes can be made to the form of the device described in this specification without departing from the gist of the invention. The appended claims and the equivalents thereof are intended to include such forms and modifications included in the scope and gist of the invention.

Explanation of Reference Numerals

[0084] 1: Substrate, 1a: EB opening, 1b: EB opening, 3: Semiconductor chip, 3a: Bonding pad, 4: Resin layer, 5: Resin layer, 6: Bonding wire, 7: Solder ball, 11: Wiring layer, 11a: Wiring, 12: Via plug, 13: Wiring layer, 13a: Wiring, 14: Via plug, 15: Wiring layer, 15a: Wiring, 21: Resin layer, 22: Resin layer, 23: Resin layer, 24: Resin layer, The resin layer 25, the resin layer 26, the resin layer 27

Claims

1. a substrate including one or more wiring layers, a first insulating film provided on an upper surface of a first wiring layer that is the uppermost layer of the one or more wiring layers, and a second insulating film provided on a lower surface of a second wiring layer that is the lowermost layer of the one or more wiring layers; a semiconductor chip provided on the substrate, the first or second wiring layer includes a first wiring and a second wiring extending from an opening provided in the first or second insulating film, and a third wiring provided between the first wiring and the second wiring and at a position facing the opening.

2. 2. The semiconductor device according to claim 1, wherein at least one of said first and second insulating films is a solder resist layer.

3. The semiconductor device according to claim 1 , wherein said third wiring has a side surface facing said opening in a plan view, said side surface having a recessed shape in a direction away from said opening.

4. The semiconductor device according to claim 3 , wherein the side surface has a curved shape in a plan view.

5. The semiconductor device according to claim 3 , wherein the side surface has a shape that forms an acute angle or a right angle in a plan view.

6. 2. The semiconductor device according to claim 1, wherein said third wiring is electrically insulated from said first and second wirings.

7. 2. The semiconductor device according to claim 1, wherein said third wiring is a dummy wiring that is not used for controlling said semiconductor device.

8. 2. The semiconductor device according to claim 1, wherein said third wiring functions as a guide for changing the direction of propagation of a crack generated in said first or second insulating film from said opening.

9. 2. The semiconductor device according to claim 1, wherein said opening has one or more protruding portions protruding from said first or second insulating film in a plan view.

10. 10. The semiconductor device according to claim 9, wherein the one or more protruding portions include a first protruding portion provided between the first wiring and the second wiring in a plan view.

11. The semiconductor device according to claim 10 , wherein the first protruding portion has a shape that forms an acute angle or a right angle in a plan view.

12. The semiconductor device according to claim 10 , wherein the one or more protruding portions further include a second protruding portion provided between the first wiring and the second wiring in a plan view.

13. the first protruding portion has a shape that forms a first angle in a plan view, the second protruding portion has a shape that forms a second angle different from the first angle in a plan view; The semiconductor device according to claim 12.

14. The semiconductor device according to claim 13 , wherein the second angle is greater than the first angle.

15. 10. The semiconductor device according to claim 9, wherein the crack in said first or second insulating film is connected to any one of said one or more protruding portions.

16. 13. The semiconductor device according to claim 12, wherein the crack in the first or second insulating film is connected to the first protruding portion and the second protruding portion.

17. The semiconductor device according to claim 1 , wherein the opening has a polygonal shape having three or more corners in a plan view.

18. 2. The semiconductor device according to claim 1, wherein the thickness of the first insulating film on the upper surface of the first wiring layer is thinner than the thickness of the first wiring layer, or the thickness of the second insulating film on the lower surface of the second wiring layer is thinner than the thickness of the second wiring layer.

19. The semiconductor device according to claim 1 , wherein each of said one or more wiring layers does not include a wiring provided at a position overlapping said opening in a plan view.

20. the first wiring is electrically connected to a first pad for external connection; the second wiring is electrically connected to a second pad for external connection; The semiconductor device according to claim 1 .

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