Wiring board and method for manufacturing conductive layer

Abstract

To provide a wiring board in which cracks occurring in wiring patterns are suppressed.SOLUTION: A wiring board includes a base material and a conductive conductor film disposed inside the base material, the conductor film having a pair of main surfaces and end surface portions connecting the ends of the pair of main surfaces, and in a cross section along the thickness direction of the conductor film, at least one of the angles formed by a first imaginary line along one of the pair of main surfaces and a second imaginary line along a portion connected to one of the end surface portions, and an angle formed by a third imaginary line along the other of the pair of main surfaces and a fourth imaginary line along a portion connected to the other of the end surface portions is 45 degrees or more and 90 degrees or less.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a wiring board and a conductive layer. [Background technology]

[0002] Conventionally, a printing process using a screen mask has been known as a method for patterning metal wiring in electronic components and the like (see, for example, Patent Document 1). Patent Document 1 discloses a method for manufacturing a conductive layer in which a wiring pattern is formed by laser processing. In this manufacturing method, a wiring pattern is processed by a laser onto a solid electrode printed on polyethylene terephthalate (PET). Then, after the excess portion is removed (by a peeling process or the like), the solid electrode is transferred onto a desired green sheet. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-064999 Summary of the Invention [Problem to be solved by the invention]

[0004] For miniaturization of components and precise temperature control, there is a demand for finer and more accurate patterning methods. By using the manufacturing method described in Patent Document 1, it is possible to achieve highly accurate patterning with a simpler process than methods using photolithography, etc. However, with this manufacturing method, a conductive layer having an inverted trapezoidal cross section is formed on a substrate, and there is a risk of cracks occurring in the wiring pattern due to pressure during lamination.

[0005] The present invention has been made to solve at least part of the above-mentioned problems, and has an object to provide a wiring board in which cracks occurring in wiring patterns are suppressed. [Means for solving the problem]

[0006] The present invention has been made to solve at least part of the above-mentioned problems, and can be realized in the following forms.

[0007] (1) According to one aspect of the present invention, there is provided a wiring board comprising: a substrate; and a conductive conductor film disposed inside the substrate and having a pair of main surfaces and end surface portions connecting end portions of the pair of main surfaces, wherein, in a cross section of the conductor film taken along a thickness direction thereof, at least one of an angle formed by a first imaginary line along one of the pair of main surfaces and a second imaginary line along a portion of the end surface portion connected to the one main surface, and an angle formed by a third imaginary line along the other of the pair of main surfaces and a fourth imaginary line along a portion of the end surface portion connected to the other main surface, is between 45 degrees and 90 degrees.

[0008] According to this configuration, a conductive film formed by laser processing is processed into a predetermined shape by irradiating one of a pair of principal surfaces with laser light. The cross section of the conductive film after laser processing is processed into a trapezoidal shape with the side irradiated with the laser as the shorter side. When pressure is applied to the conductive film after laser processing during lamination, cracks may occur, causing damage to the long side of the trapezoidal cross section. If damage occurs, the acute angle at the end of the long side LS may be chipped, which may result in voids due to the chipping in the wiring substrate after lamination. In this regard, in this configuration, in the conductive film, at least one of the angle formed by the first virtual line and the second virtual line and the angle formed by the third virtual line and the fourth virtual line is an acute angle of 45 degrees or more. If chipping occurs at the end of the long side of the trapezoidal cross section due to pressure during lamination, both of these two angles become an angle of 90 degrees or more. In other words, the conductive film of this configuration maintains the trapezoidal shape at the time of laser processing and does not have chipping. Furthermore, because no chipping occurs, this configuration suppresses the occurrence of cracks before chipping, and suppresses the occurrence of voids inside the substrate due to chipping or cracking. Thus, this configuration provides a wiring board in which cracks occurring in the wiring pattern are suppressed.

[0009] (2) In the wiring board of the above form, in a cross section of the base material and the conductor film along the thickness direction of the conductor film, if a virtual line that is tangent to a part of the end surface portion of the conductor film in a direction along the first virtual line, which is the farthest from a first intersection point where the first virtual line and the second virtual line intersect, and is perpendicular to the first virtual line, is defined as a fifth virtual line, the base material may be provided with 20 regions surrounded by the first intersection point, a second intersection point where the third virtual line and the fourth virtual line intersect, a third intersection point where the third virtual line and the fifth virtual line intersect, and a fourth intersection point where the fifth virtual line and the first virtual line intersect, then voids may exist in one or less of the 20 regions. According to this configuration, when 20 regions surrounded by the first intersection, the second intersection, the third intersection, and the fourth intersection are prepared, there is one or less region containing a void. In other words, the probability of voids occurring due to cracks caused by pressure during lamination is 5% or less. Therefore, fewer voids occur near the conductive film inside the base material of the wiring board, improving the performance of the wiring board.

[0010] (3) According to another aspect of the present invention, there is provided a method for manufacturing a conductive layer, comprising: a coating step of coating a first substrate with a conductive paste containing metal powder to form a conductive paste layer; a laser processing step of irradiating the conductive paste layer with laser light to process the shape of the conductive paste layer; a first transfer step of transferring the conductive paste layer formed on the first substrate to a second substrate; and a second transfer step of transferring the conductive paste layer transferred to the second substrate to a green sheet. According to this configuration, the cross section of the conductive paste layer formed on the first substrate after the laser processing process is processed into a trapezoidal shape with the longer side facing the first substrate. Therefore, the cross section of the conductive paste layer transferred to the second substrate after the first transfer process is a trapezoidal shape with the shorter side facing the second substrate. Then, the cross section of the conductive paste layer transferred from the second substrate to the green sheet after the second transfer process is a trapezoidal shape with the longer side facing the green sheet. Unlike this configuration, if a different green sheet or the like is stacked from above the green sheet and pressure is applied when the shorter side is located on the green sheet side, cracks may occur in part of the upper side of the conductive paste layer. In contrast, in this configuration, the shorter side of the trapezoidal shape of the conductive paste layer is located on the side where pressure is applied, thereby suppressing cracks from occurring in the conductive paste layer.

[0011] (4) In the wiring board of the above aspect, the peel strength when the conductive paste layer is peeled off from the first base material may be smaller than the peel strength when the conductive paste layer is peeled off from the second base material. According to this configuration, during the second transfer step, the conductive paste layer formed on the first substrate is in a state of being adhered to both the first substrate and the second substrate. In this configuration, the peel strength at which the conductive paste layer is peeled from the first substrate is smaller than the peel strength at which the conductive paste layer is peeled from the second substrate, so that the conductive paste layer is successfully transferred from the first substrate to the second substrate in the second transfer step.

[0012] The present invention can be realized in various forms, for example, in the form of a wiring board, a wiring layer, an electronic component, a system including these, a method for manufacturing a conductive layer, a method for manufacturing a wiring board, and a system including these. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a schematic cross-sectional view of a wiring board according to an embodiment of the present invention; [Figure 2] FIG. 2 is an enlarged cross-sectional view of the vicinity of an end face of one conductive film. [Figure 3] FIG. 2 is a schematic perspective view of a wiring board. [Figure 4] 3 is a flowchart of a method for manufacturing a wiring substrate having a conductive layer according to the present embodiment. [Figure 5] FIG. 4 is a schematic cross-sectional view of a first substrate and a conductive paste layer after a coating step. [Figure 6] FIG. 4 is a schematic cross-sectional view of the first substrate and the conductive layer after a laser processing step. [Figure 7] FIG. 4 is a schematic cross-sectional view of the first substrate and the conductive layer after the marginal portion has been removed. [Figure 8] FIG. 3 is a schematic cross-sectional view of a first substrate, a second substrate, and a conductive layer during a first transfer step. [Figure 9] FIG. 4 is a schematic cross-sectional view of the second substrate and the conductive layer after the first transfer step. [Figure 10] FIG. 10 is a schematic cross-sectional view of a second substrate, a conductive layer, and a green sheet during a second transfer step. [Figure 11] FIG. 10 is a schematic cross-sectional view of a laminate including a green sheet and a conductive layer after a second transfer step. [Figure 12] FIG. 2 is a schematic cross-sectional view of a laminate in which a plurality of laminates are stacked after a stacking step. [Figure 13] 1 is a schematic cross-sectional view of a portion of a wiring board manufactured by screen printing in Comparative Example 1. FIG. [Figure 14] 10 is a schematic cross-sectional view of a portion of a wiring board of Comparative Example 2. FIG. [Figure 15] 10 is a flowchart of a method for manufacturing a wiring board according to Comparative Example 2. [Figure 16] 10 is a schematic cross-sectional view of the green sheet, the conductive layer, and the first substrate during the first transfer step of Comparative Example 2. FIG. [Figure 17] 10 is a schematic cross-sectional view of a wiring board according to Comparative Example 2 during manufacturing. FIG. [Figure 18] FIG. 10 is an enlarged cross-sectional view of the vicinity of an end face portion of a conductive film according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0014] <Embodiment> FIG. 1 is a schematic cross-sectional view of a wiring board 100 according to one embodiment of the present invention. The wiring board 100 of this embodiment is used to form circuits in electronic components, IC packages, sensor devices, semiconductor manufacturing equipment, and the like. The wiring board 100 shown in FIG. 1 includes four substrates 10 and three conductive layers 20 disposed inside each of the four substrates 10. While a detailed manufacturing method for the wiring board 100 will be described later, the wiring board 100 is manufactured by stacking the four substrates 10 and the three conductive layers 20. The substrates 10 are made of a ceramic material and have a rectangular, flat plate shape. The Cartesian coordinate system CS shown in FIG. 1 has two axes, X and Y, that are orthogonal to the Z-axis direction, with the Z-axis direction being the stacking direction of the substrates 10 and the conductive layers 20. The X and Y axes are axes parallel to each side of the rectangular substrate 10. The Cartesian coordinate system CS shown in FIG. 1 corresponds to the Cartesian coordinate systems CS shown in FIG. 2 and subsequent figures.

[0015] Each of the three conductive layers 20 is formed from a plurality of conductive films 21. The plurality of conductive films 21 included in each conductive layer 20 are processed into a predetermined wiring pattern by laser trimming. As shown in FIG. 1 , the conductive film 21 of this embodiment has a first main surface F1 and a second main surface F2 that form a pair of main surfaces in the stacking direction, and end surface portions EP1 and EP2 that connect the ends of the first main surface F1 and the second main surface F2. The end surface portions EP1 and EP2 form slopes that move away from each other on the X-axis as they move toward the negative Z-axis direction. Therefore, the cross section of the conductive film 21 shown in FIG. 1 is substantially trapezoidal. The conductive film 21 is made from a conductive paste containing metal powder such as copper, aluminum, silver, gold, platinum, nickel, titanium, iron, chromium, molybdenum, and tungsten. Note that the dashed line in FIG. 1 represents the boundary between the two stacked substrates 10. The boundary line may not be distinguishable in the cross section of the wiring board 100.

[0016] FIG. 2 is an enlarged cross-sectional view of the vicinity of an end surface EP1 of one conductive film 21. As shown in FIG. 2, the pair of main surfaces F1, F2 and the end surface EP1 do not form a flat plane without any irregularities, but are formed by combining multiple planes that are not parallel to each other. As shown in FIG. 2, in the cross section of the conductive film 21, a first imaginary line AL1 along the first main surface F1 and a second imaginary line AL2 along a portion of the end surface EP1 that connects to the first main surface F1 form an angle θ1. Similarly, a third imaginary line AL3 along the second main surface F2 and a fourth imaginary line AL4 along a portion of the end surface EP1 that connects to the second main surface F2 form an angle θ2.

[0017] Here, the first virtual line AL1 is determined by a vertex V1 formed by the first main surface F1 and the end surface portion EP1 and two points P11 and P12 on the first main surface F1. The first virtual line AL1 in the cross section shown in FIG. 2 is a straight line calculated by the least squares method from the vertex V and the two points P11 and P12. The distance between the vertex V1 and point P11 is equal to the distance between the points P11 and P12. This distance is calculated from the distance between the vertex V1 and vertex V2. The vertex V2 is a vertex formed by the second main surface F2 and the end surface portion EP1. In this embodiment, the distance between the vertex V1 and point P11 is set to 1 / 6 of the distance between the vertex V1 and vertex V2. The distance between the vertex V1 and point P11 may be set appropriately based on the shapes of the pair of main surfaces F1 and F2 and the end surface portion EP1.

[0018] The second virtual line AL2 is a straight line calculated by the least squares method from three points: vertex V1 and two points P21 and P22. The distance between vertex V1 and point P21 and the distance between point P21 and point P22 are the same as the distance between vertex V1 and vertex P11. As described above, after the first virtual line AL1 and the second virtual line AL2 are determined, the angle θ1 is determined. Similar to the first virtual line AL1, the second virtual line AL2, and the angle θ1, the third virtual line AL3, the fourth virtual line AL4, and the angle θ2 are determined from the second main surface F2 and the end surface portion EP1 connected to the second main surface F2.

[0019] In this embodiment, the conductive film 21 is disposed inside the substrate 10 so that at least one of the angle θ1 and the angle θ2 is 45 degrees or more and 90 degrees or less. In addition, in the wiring board 100 of this embodiment, when 20 cross sections including the conductive layer 20 shown in Fig. 1 are prepared, in each of the multiple conductive films 21 in the 20 cross sections, the number of cross sections in which a void exists in the region RG1 shown in Fig. 2 is one or less.

[0020] 2 is a region surrounded by a vertex V1 (first intersection) where the first virtual line AL1 and the second virtual line AL2 intersect, a vertex V2 (second intersection) where the third virtual line AL3 and the fourth virtual line AL4 intersect, a third intersection CP3 where the third virtual line AL3 and the fifth virtual line AL5 intersect, and a fourth intersection V1 where the fifth virtual line AL5 intersects with the first virtual line AL1. The fifth virtual line AL5 is a virtual line that is tangent to a portion of the end surface portion EP1 that is farthest from the vertex V1 where the first virtual line AL1 and the second virtual line AL2 intersect in the direction along the first virtual line AL1 and is perpendicular to the first virtual line AL1.

[0021] In the cross section shown in Fig. 2, the point located furthest along the first imaginary line AL1 in the negative X-axis direction is vertex V1. Therefore, the intersection of the first imaginary line AL1 and the second imaginary line AL2 and the point of contact with the portion of the end surface portion EP1 that is furthest from the first imaginary line AL1 are the same vertex V1. As a result, the region RG1 shown in Fig. 2 is a triangular region (vertical hatched region) surrounded by three points: vertex V1, vertex V2, and intersection point CP3. In other embodiments, however, if the vertices V1 do not overlap, the region will be a quadrangular region.

[0022] FIG. 3 is a schematic perspective view of the wiring substrate 100. In this embodiment, 18 cross sections parallel to the ZX plane between the A1-A1 cross section and the A20-A20 cross section parallel to the ZX plane are used as the 20 cross sections for confirming the presence of voids. The A1-A1 cross section, the A20-20 cross section, and the 18 cross sections between the A1-A1 cross section and the A20-A20 cross section are prepared so that the conductor film 21 is included in the total of 20 cross sections. To prevent the position of the conductor film 21 from being misaligned, the spacing along the Y axis among the 20 cross sections is preferably equal or close to equal within the range including the conductor film 21. Furthermore, the A1-A1 cross section is preferably closer to the end face of the wiring substrate 100 on the negative side of the Y axis within the range including the conductor film 21. Similarly, the A20-A20 cross section is preferably closer to the end face of the wiring substrate 100 on the positive side of the Y axis within the range including the conductor film 21. By selecting these 20 cross sections, it is not necessary to determine only the presence of voids near a specific conductive film 21. In the wiring board 100 of this embodiment, of the 20 cross sections prepared in this manner, voids exist in one or less locations within the region RG. In other words, if voids exist in n cross sections out of N cross sections, n / N is 0.05 (5%) or less. In the cross section shown in FIG. 2, no voids exist within the region RG1.

[0023] FIG. 4 is a flowchart of a method for manufacturing a wiring board 100 including a conductive layer 20 according to this embodiment. The manufacturing flow for the wiring board 100 shown in FIG. 4 begins with a coating process (step S1) in which a conductive paste containing metal powder is applied to the first base material MA1. FIG. 5 is a schematic cross-sectional view of the first base material MA1 and the conductive paste layer 20A after the coating process. As shown in FIG. 5, in the coating process, the conductive paste layer 20A containing metal powder and resin is applied to the surface of the first base material MA1 by screen printing, a coater method, a doctor blade method, or the like. The metal used for the metal powder is appropriately selected depending on the purpose, and examples thereof include copper, aluminum, silver, gold, platinum, nickel, titanium, iron, chromium, molybdenum, tungsten, and alloys thereof. The thickness of the conductive paste layer 20A formed on the surface of the first base material MA1 is approximately 0.5 to 100 μm. A known resin (binder) is used as the resin contained in the conductive paste. The conductive paste may contain other components (solvent, filler, etc.) in addition to the metal powder and resin, as long as the object of the present invention is not impaired.

[0024] The first base material MA1 is a film-like or sheet-like member. The thickness of the first base material MA1 is such that it will not be cut by the laser processing step described below, for example, about 25 to 200 μm. Examples of materials for the first base material MA1 include rigid films of polyester resins such as PET and polybutylene terephthalate (PBT).

[0025] After the coating step (step S1), a drying step is performed to dry the conductive paste layer 20A formed on the first substrate MA1 (step S2 in FIG. 4). In the drying step, the conductive paste layer 20A coated on the first substrate MA1 is placed in, for example, a batch dryer and dried with hot air. The temperature inside the dryer is, for example, 80 to 90 degrees Celsius (°C). The drying time is, for example, 5 to 15 minutes. The drying conditions (heating temperature, drying time, etc.) in the drying step may be set appropriately depending on the material (resin, etc.) used for the conductive paste. For example, if the conductive paste layer 20A dries naturally at room temperature, the drying step may not be performed.

[0026] After the drying step (step S2), a laser processing step is performed in which the conductive layer 20B, on which the conductive paste layer 20A has dried, is irradiated with laser light to cut the conductive layer 20B into a pattern (step S3). In the laser processing step, the laser light is irradiated from a substantially perpendicular direction onto the conductive layer 20B on the first base material MA1.

[0027] FIG. 6 is a schematic cross-sectional view of the first base material MA1 and the conductive layer 20B after the laser processing step. The cut surface of the conductive layer 20B processed by the laser beam LA irradiated from the positive direction of the Z axis rises substantially vertically, forming a trapezoidal shape as shown in FIG. 6. In this trapezoidal shape, the long side LS is located on the first base material MA1 side, and the short side SS is located on the side irradiated by the laser beam LA. The conductive layer 20B irradiated by the laser beam LA is vaporized and disappears. In addition to cutting the conductive layer 20B, the irradiation of the laser beam LA also forms a V-shaped groove in the first base material MA1. Note that the conductive layer 20B shown in FIG. 6 includes a margin 29 that will not be used as a wiring pattern in the finished wiring board 100.

[0028] As the laser light LA, for example, a green laser (wavelength: 532 nm) is used. The output of the laser light LA ​​is, for example, 1 W to 6 W. Note that the conditions of the laser light LA ​​in the laser processing step (for example, wavelength, output, scanning speed, number of passes, etc.) are appropriately set within a range in which the conductive layer 20B can be cut without cutting the first base material MA1.

[0029] A laser beam having a higher transmittance for the laser beam LA through the first base material MA1 than through the conductive layer 20B is used. The transmittance for the laser beam LA through the first base material MA1 is, for example, preferably 50% or more, more preferably 60% or more, and even more preferably 70% or more. In contrast, the transmittance for the laser beam LA through the conductive layer 20B is, for example, preferably 20% or less, more preferably 10% or less. When the transmittances for the first base material MA1 and the conductive layer 20B are within these ranges, the first base material MA1 is not cut even when irradiated with the laser beam LA. Furthermore, heat accumulates in the first base material MA1, and the accumulated heat prevents cracks and the like from occurring in the conductive layer 20B. Note that, as shown in FIG. 5, the conductive layer 20B after the laser processing step includes a margin 29 that is not used as wiring.

[0030] After the laser processing step (step S3 in FIG. 4), a marginal portion removing step is performed to remove marginal portions 29 included in conductive layer 20B (step S4). FIG. 7 is a schematic cross-sectional view of first base material MA1 and conductive layer 20C after marginal portions 29 have been removed. In the marginal portion removing step, marginal portions 29 are removed from conductive layer 20B shown in FIG. 6 so that conductive layer 20C has a desired wiring pattern. For example, marginal portions 29 may be removed using adhesive tape or a sheet. Alternatively, a film may be placed on conductive layer 20B from the side opposite to the first base material MA1 (positive Z-axis direction side), and marginal portions 29 are pressed against the film from the back side of first base material MA1 (negative Z-axis direction side). Only marginal portions 29 are transferred to the film. When marginal portions 29 are transferred to the film, the positions of first base material MA1 and the film may be reversed upside down. In addition to these methods, the marginal portion 29 may be removed using a known method used in forming this type of conductive layer.

[0031] After the margin removal process (step S4 in FIG. 4), a first transfer process is performed in which the conductive layer 20C is transferred from the first substrate MA1 to the second substrate MA2 (step S5). FIG. 8 is a schematic cross-sectional view of the first substrate MA1, the second substrate MA2, and the conductive layer 20C during the first transfer process. As shown in FIG. 8, in the first transfer process, the conductive layer 20C and the first substrate MA1 are placed on the second substrate MA2 so that the conductive layer 20C faces the second substrate MA2. The second substrate MA2 is a film-like or sheet-like member. Examples of materials that can be used for the second substrate MA2 include synthetic resin films made of polyester resins such as PET and PBT.

[0032] After the conductive layer 20C and the first substrate MA1 are stacked on the second substrate MA2, the conductive layer 20C is pressed against the second substrate MA2 using a jig or the like from the side of the first substrate MA1 on which the conductive layer 20C is not formed (the positive Z-axis side). In this embodiment, the peel strength when the conductive layer 20C is peeled off from the first substrate MA1 is smaller than the peel strength when the conductive layer 20C is peeled off from the second substrate MA2. Therefore, after the conductive layer 20C is pressed against the second substrate MA2, when the conductive layer 20C and the first substrate MA1 are peeled off from the second substrate MA2, the conductive layer 20C is transferred to the second substrate MA2.

[0033] 9 is a schematic cross-sectional view of the second substrate MA2 and the conductive layer 20C after the first transfer step. As shown in Fig. 9, the conductive layer 20C transferred onto the second substrate MA2 is formed on the second substrate MA2 so that the short side SS of the trapezoidal cross section faces the second substrate MA2.

[0034] After the first transfer step (step S5 in FIG. 4), the second transfer step (step S6) is performed to transfer the conductive layer 20C from the second substrate MA2 to the green sheet GS. FIG. 10 is a schematic cross-sectional view of the second substrate MA2, conductive layer 20C, and green sheet GS during the second transfer step. As shown in FIG. 10, in the second transfer step, the conductive layer 20C and the second substrate MA2 are placed on the green sheet GS so that the conductive layer 20C faces the green sheet GS. The green sheet GS is produced, for example, by kneading a mixture of material powders in a ball mill and then forming the resulting mixture into a sheet using a doctor blade method. The material powder mixture is a mixture containing appropriate amounts of aluminum nitride powder, yttrium oxide powder, acrylic resin (binder), dispersant, plasticizer, etc., to which an organic solvent such as toluene is added. Note that other known green sheets GS may also be used.

[0035] After the conductive layer 20C and the second base material MA2 are stacked on the green sheet GS, the conductive layer 20C is pressed against the second base material MA2 using a jig or the like from the side of the second base material MA2 where the conductive layer 20C is not formed (the positive Z-axis side). After being pressed in this manner, the conductive layer 20C has a stronger adhesive force to the green sheet GS than to the second base material MA2. Therefore, by peeling the second base material MA2 from the green sheet GS side, the conductive layer 20C is peeled off from the second base material MA2 and transferred to the green sheet GS.

[0036] Fig. 11 is a schematic cross-sectional view of a laminate 31 including a green sheet GS and a conductive layer 20C after the second transfer step. In the laminate 31 shown in Fig. 11, the conductive layer 20C transferred onto the green sheet GS is formed on the green sheet GS so that the long side LS of the trapezoidal cross section faces the green sheet GS.

[0037] After the second transfer step (step S6 in FIG. 4), a lamination step is performed in which a plurality of laminates 31 are laminated (step S7). FIG. 12 is a schematic cross-sectional view of a laminate 30 in which a plurality of laminates 31 are laminated after the lamination step. The laminate 30 shown in FIG. 12 is formed by laminating three laminates 31 (FIG. 11) and one green sheet GS. After lamination, the laminate 30 is formed by applying pressure from the positive Z-axis direction. Note that the laminate 30 shown in FIG. 12 is an example, and for example, four or more laminates may be laminated.

[0038] After the lamination step (step S7 in FIG. 4), a firing step (step S8) is performed to sinter the laminate 30 to manufacture the wiring board 100 shown in FIG. 1, thereby completing the manufacturing flow for the wiring board 100. The firing step is performed, for example, by firing the laminate 30 in a humidified hydrogen-nitrogen atmosphere at a predetermined temperature (e.g., 1900°C) for a predetermined time (e.g., 4 hours). The firing step sinters the green sheets GS in the laminate 30 to form the substrate 10. The conductive layer 20C is then sintered to form the conductive layer 20. Note that, if necessary, a degreasing step may be performed before the firing step in which the laminate 30 is degreased by heating in a nitrogen atmosphere (e.g., at 550°C for 12 hours).

[0039] FIG. 13 is a schematic cross-sectional view of a portion of a wiring board 100x manufactured by screen printing according to Comparative Example 1. FIG. 13 shows an enlarged schematic view of the vicinity of an end surface portion EP1x of one conductive film 21x of the wiring board 100x according to Comparative Example 1, corresponding to FIG. 2. The end surface portion EP1x connecting the ends of a pair of main surfaces F1x, F2x of the conductive film included in the wiring board 100x according to Comparative Example 1 is gentler than the wiring board 100 shown in FIG. 2. Specifically, the angle θ1x formed by the first virtual line AL1x and the second virtual line AL2x is an acute angle of less than 45 degrees. Furthermore, the angle θ2x formed by the third virtual line AL3x and the fourth virtual line AL4x is an obtuse angle of 135 degrees or more. Because the wiring board 100x according to Comparative Example 1 is manufactured by screen printing, the difference between the size of the first main surface F1x and the size of the second main surface F2x is greater than that of the wiring board 100 according to the embodiment. As a result, in wiring board 100 of this embodiment, a wiring pattern closer to the desired size is formed compared to wiring board 100x of Comparative Example 1.

[0040] FIG. 14 is a schematic cross-sectional view of a portion of a wiring board 100y of Comparative Example 2. FIG. 15 is a flowchart of a method for manufacturing the wiring board 100y of Comparative Example 2. As shown in FIG. 15, the wiring board 100y of Comparative Example 2 is a board manufactured by removing the second transfer step of step S6 of FIG. 4 from the wiring board 100 of the embodiment. In the manufacturing flow of Comparative Example 2 of FIG. 15, the same steps as steps S1 to S4 of FIG. 4 are performed, and then a first transfer step is performed to transfer the conductive layer 20C from the first base material MA1 to the green sheet GS (step S5y). In Comparative Example 2, the conductive layer 20C is transferred from the first base material MA1 to the green sheet GS without transferring the second base material MA2.

[0041] Fig. 16 is a schematic cross-sectional view of the green sheet GS, conductive layer 20C, and first substrate MA1 during the first transfer step of Comparative Example 2. The conductive layer 20C transferred onto the green sheet GS after the first transfer step (S5y) shown in Fig. 16 is formed on the green sheet GS so that the short side SS of the trapezoidal cross section faces the green sheet GS.

[0042] After the first transfer step (step S5y), a lamination step of laminating a plurality of laminates 31y (step S7y) is performed, and a firing step (step S8) is performed, thereby manufacturing the wiring board 100y of the comparative example 2.

[0043] FIG. 17 is a schematic cross-sectional view of a portion of a laminate 30y in which multiple laminates are stacked during the stacking process. FIG. 17 illustrates a state in which two green sheets GS and a conductive layer 20C located between the two green sheets GS are pressed from the positive Z-axis direction during the stacking process. In the pressurized state shown in FIG. 17, force is applied to the conductive layer 20C near the ends RG2 and GR3 of the long side LS. This may result in cracks CR and voids VD near the ends RG2 and GR3 of the conductive layer 20C. As a result, a conductive film 21y of Comparative Example 2 having the cross-section shown in FIG. 14 is manufactured.

[0044] In the cross section of the conductive film of Comparative Example 2 shown in Figure 14, a portion of the second main surface F2y that formed the long side LS during lamination is missing from the end surface portion EP1y. Furthermore, cracks CR occur in the end surface portion EP1y, and voids VD occur near the first main surface F1y. As a result, as shown in Figure 13, the angle θ1y formed by the first virtual line AL1y and the second virtual line AL2y is an obtuse angle exceeding 90 degrees. Furthermore, the angle θ2y formed by the third virtual line AL3y and the fourth virtual line AL4y is an obtuse angle exceeding 90 degrees.

[0045] 14 includes a void VD. The region RG1y (the region hatched with vertical lines) is a rectangular region surrounded by a vertex V1y, which is the intersection of the first virtual line AL1y and the second virtual line AL2y, a vertex V2y, which is the intersection of the third virtual line AL3y and the fourth virtual line AL4y, an intersection CP3y, which is the intersection of the third virtual line AL3y and the fourth virtual line AL4y, and an intersection CP4y, which is the intersection of the fifth virtual line AL5y and the first virtual line AL1y. In Comparative Example 2, unlike the embodiment and Comparative Example 1, the fifth virtual line AL5y does not pass through the vertex V1y, which is the intersection of the first virtual line AL1y and the second virtual line AL2y. The fifth virtual line AL5y is a virtual line that touches the vertex P3 located at the part of the end surface portion EP1y that is farthest from the vertex V1y, which is the intersection of the first virtual line AL1y and the second virtual line AL2y, in the direction along the first virtual line AL1y, and is perpendicular to the first virtual line AL1y.

[0046] As described above, in this embodiment, in the cross section of the conductive film 21 shown in FIG. 2 , the first virtual line AL1 along the first main surface F1 and the second virtual line AL2 along the portion of the end surface EP1 that connects to the first main surface F1 form an angle θ1. The third virtual line AL3 along the second main surface F2 and the fourth virtual line AL4 along the portion of the end surface EP1 that connects to the second main surface F2 form an angle θ2. In this embodiment, the conductive film 21 is disposed inside the substrate 10 so that at least one of the angles θ1 and θ2 is between 45 degrees and 90 degrees. In this embodiment, the conductive film 21 formed by laser processing is irradiated with laser light LA ​​from one of the pair of main surfaces F1 and F2 to form a predetermined wiring pattern. After processing with the laser light LA, the cross section of the conductive film 21 is processed into a trapezoidal shape with the shorter side facing the laser light LA. When pressure is applied to the conductor film 21 after processing with the laser beam LA during the lamination process, cracks may occur, causing damage to the end of the long side LS of the trapezoidal cross section. If damage occurs, the acute angle at the end of the long side LS of the trapezoidal shape may be chipped, potentially resulting in the generation of voids VD due to the chipping in the wiring substrate after lamination. In this regard, in this embodiment, in the conductor film 21, at least one of the angle θ1 between the first virtual line AL1 and the second virtual line AL2 and the angle θ2 between the third virtual line AL3 and the fourth virtual line AL4 is an acute angle of 45 degrees or greater. When chipping occurs at the end of the long side LS of the trapezoidal cross section, both angles θ1 and θ2 become 90 degrees or greater. That is, the conductor film 21 of this embodiment maintains its trapezoidal shape during laser processing, and no chipping occurs at the end of the long side LS. Furthermore, because no chipping occurs, the occurrence of cracks CR before chipping is suppressed, and the occurrence of voids VD caused by chipping or cracks CR inside the substrate 10 is suppressed. Thus, in this embodiment, a wiring board 100 is provided in which cracks CR occurring in the wiring pattern are suppressed.

[0047] Furthermore, in the wiring board 100 of this embodiment, when 20 cross sections including the conductive layer 20 shown in Fig. 1 are prepared, in each of the 20 cross sections of the plurality of conductive films 21, there is one or less cross section in which a void exists in the region RG1 shown in Fig. 2. As shown in Fig. 2, the region RG1 is a region surrounded by a vertex V1 at the intersection of the first virtual line AL1 and the second virtual line AL2, a vertex V2 at the intersection of the third virtual line AL3 and the fourth virtual line AL4, an intersection CP1 at the intersection of the third virtual line AL3 and the fifth virtual line AL5, and a vertex V1 at the intersection of the fifth virtual line AL5 and the first virtual line AL1. In this embodiment, when 20 regions RG1 surrounded by the vertices V1, V2, CP1, and V1 are prepared, there is one or less region in which a void VD exists. That is, the probability of voids VD occurring due to cracks CR generated by the pressure during the lamination process is 5% or less. Therefore, fewer voids VD occur near the conductive film 21 inside the base material 10 of the wiring board 100, improving the performance of the wiring board 100.

[0048] In this embodiment, as shown in the manufacturing flow of the wiring board 100 in FIG. 4, a coating process is performed in which a conductive paste containing metal powder is applied to the first substrate (step S1). A laser processing process is performed in which a laser beam is applied to the conductive layer 20B after the conductive paste layer 20A has dried, cutting the conductive layer 20B into a pattern (step S3). A first transfer process is performed in which the conductive layer 20C is transferred from the first substrate MA1 to the second substrate MA2 (step S5). A second transfer process is performed in which the conductive layer 20C is transferred from the second substrate MA2 to a green sheet (step S6). In this embodiment, the cross section of the conductive layer 20C formed on the first substrate MA1 after the laser processing process is processed into a trapezoidal shape with the long side LS facing the first substrate MA1. Therefore, the cross section of the conductive layer 20C transferred to the second substrate MA2 after the first transfer process is a trapezoidal shape with the short side SS facing the second substrate MA2. The cross section of the conductive layer 20C after the second transfer step, which is transferred from the second substrate MA2 to the green sheet GS, is trapezoidal with the long side LS on the green sheet GS side. Unlike this embodiment, as in Comparative Example 2, when the short side is located on the green sheet GS side (FIG. 16), if a different green sheet GS is stacked from above the green sheet GS and the conductive layer 20C and pressure is applied, cracks CR may occur in part of the upper side of the conductive layer 20C. In contrast, in this embodiment, as shown in FIG. 12, the short side SS of the trapezoidal shape of the conductive layer 20C is located on the side where pressure is applied, thereby suppressing cracks CR from occurring in the conductive layer 20C.

[0049] Furthermore, in the present embodiment, in the manufacturing flow of the wiring board 100, the peel strength when the conductive layer 20C is peeled off from the first base material MA1 is smaller than the peel strength when the conductive layer 20C is peeled off from the second base material MA2. In the present embodiment, during the second transfer step (S6) in the manufacturing flow of the wiring board 100 shown in FIG. 4, there is a state (FIG. 8) in which the conductive layer 20C formed on the first base material MA1 is adhered to both the first base material MA1 and the second base material MA2. In the present embodiment, the peel strength when the conductive layer 20C is peeled off from the first base material MA1 is smaller than the peel strength when the conductive layer 20C is peeled off from the second base material MA2. Therefore, in the second transfer step (S6), the conductive layer 20C is successfully transferred from the first base material MA1 to the second base material MA2.

[0050] <Modification of this embodiment> The present invention is not limited to the above-described embodiment, and can be embodied in various forms without departing from the spirit of the invention. For example, the following modifications are also possible.

[0051] <Variation 1> The manufacturing method of the wiring board 100 and the conductive layer 20 of the above embodiment is an example and can be modified. In the wiring board 100, at least one of the angle θ1 formed by the first virtual line AL1 and the second virtual line AL2 and the angle θ2 formed by the third virtual line AL3 and the fourth virtual line AL4 in the cross section of the conductive film 21 disposed inside the base material 10 can be modified within a range of 45 degrees or more and 90 degrees or less. Furthermore, the manufacturing method of the conductive layer 20 can be modified within a range in which both the first transfer step (S5) and the second transfer step (S6) are performed.

[0052] The materials of the substrate 10, conductive layer 20, first substrate MA1, and second substrate MA2 in the above embodiment are merely examples, and well-known materials can be used. The number of substrates 10 and conductive layers 20 stacked to form the wiring board 100 may be one layer or two or more layers. A layer other than the conductive layer 20 may be formed between two substrates 10, and when three or more substrates 10 are stacked, there may be a layer between the substrates 10 where the conductive layer 20 is not stacked.

[0053] <Variation 2> Fig. 18 is a schematic cross-sectional view of a portion of a wiring board 100a according to a modified example. Fig. 18 shows an enlarged schematic view of the vicinity of an end surface portion EP1a of one of the conductive films 21a of the wiring board 100a according to the modified example, corresponding to Fig. 2. In this modified example, an example of a method for determining each imaginary line when the vertices that are the boundaries between each of the pair of main surfaces F1a, F2a and the end surface portion EP1a are unclear, as shown in Fig. 18, will be described.

[0054] In the cross section of the conductive film 21a shown in FIG. 18, first, an imaginary point P01a is arbitrarily determined as the boundary point between the first principal surface F1a and the end surface portion EP1a. Similarly, an imaginary point P02a is arbitrarily determined as the boundary point between the second principal surface F2a and the end surface portion EP1a. After that, the linear distance between the imaginary points P01a and P02a is determined. Then, a point P11a on the boundary line between the base material 10a and the conductive film 21a is determined, the point P11a being a distance obtained by dividing the determined linear distance into m equal parts (dividing it into 5 equal parts in FIG. 18) from the imaginary point P01a toward the first principal surface F1a (positive direction of the X-axis). Similarly, a point P12a is determined that is a linear distance of m equal parts from point P11a toward the first principal surface F1a. In the same manner, the remaining three points P13a to P15a are determined. The first virtual line AL1a is determined by using the least squares method for a total of five points P11a to P15a.

[0055] Next, point P21a is determined on the boundary line between the substrate 10a and the conductive film 21a, at a distance equal to m of the determined linear distance from imaginary point P01a toward the second principal surface F2a (positive Z-axis direction). Similarly, point P22a is determined at a distance equal to m of the linear distance from point P21a toward the first principal surface F1a. In the same manner, a total of five points are determined, or, if the length of the end surface portion EP1a is not sufficient to determine five points, as many points as possible are determined between imaginary points P01a and P02a (a total of four points P21a-P24a in FIG. 18). A second imaginary line AL2a is determined by applying the least squares method to the determined four points P21a-P24a. 18, only four points could be determined between imaginary points P01a and P02a, so the second imaginary line AL2a and the fourth imaginary line AL4a are the same straight line. In other embodiments, when there are only a few points that can be determined, the value of "m" used to divide the straight-line distance into m equal parts may be re-determined.

[0056] In the same manner as the first virtual line AL1a, a third virtual line AL3a and a fourth virtual line AL4a are determined from the virtual point P02a and the second principal surface F2a. Next, a fifth virtual line AL5a is determined, which is tangent to a portion of the end surface portion EP1a that is farthest from the intersection (first intersection) CP1a of the first virtual line AL1a and the second virtual line AL2a in the direction along the first virtual line AL1a and is perpendicular to the first virtual line AL1a. Thereafter, the region RG1a used in determining the void VD is a rectangular region (vertical hatched region) surrounded by the intersection CP1a, the intersection (second intersection) CP2a between the third virtual line AL3a and the fourth virtual line AL4a, the intersection (third intersection) CP3a between the third virtual line AL3a and the fifth virtual line AL5a, and the intersection (fourth intersection) CP4a between the fifth virtual line AL5a and the first virtual line AL1a. Note that the region surrounded by the four intersections CP1a to CP4a refers to a rectangular region surrounded by the four intersections CP1a to CP4a if none of the four intersections are the same.

[0057] As shown in the above-described Modification 2, the determination of each virtual line can be changed depending on the shape of the conductive film 21. The first virtual line corresponding to the first main surface and the third virtual line corresponding to the second main surface are preferably determined with reference to the overall shapes of the first and second main surfaces. The end surface portion EP1 is preferably determined near each main surface, taking chips and cracks CR into consideration.

[0058] This aspect has been described above based on embodiments and modifications. However, the above-described embodiments are intended to facilitate understanding of this aspect and are not intended to limit this aspect. This aspect may be modified or improved without departing from the spirit and scope of the claims, and equivalents thereof are included in this aspect. Furthermore, if a technical feature is not described as essential in this specification, it may be deleted as appropriate.

[0059] The present invention can also be realized in the following forms. [Application example 1] A wiring board, A substrate; a conductive film disposed inside the base material and having electrical conductivity, the conductive film having a pair of main surfaces and end surface portions connecting the ends of the pair of main surfaces; Equipped with The conductive film has, in a cross section along a thickness direction of the conductive film, an angle formed by a first imaginary line along one of the pair of main surfaces and a second imaginary line along a portion of the end surface portion connected to the one main surface; an angle formed by a third imaginary line along the other of the pair of main surfaces and a fourth imaginary line along a portion of the end surface portion connected to the other main surface; At least one of the above angles is 45 degrees or more and 90 degrees or less. [Application example 2] The wiring board according to Application Example 1, In a cross section of the substrate and the conductor film along the thickness direction of the conductor film, a fifth virtual line is defined as a virtual line that contacts a portion of the end surface of the conductor film that is farthest from a first intersection point, which is an intersection point between the first virtual line and the second virtual line, in a direction along the first virtual line and is perpendicular to the first virtual line. The substrate is the first intersection point; a second intersection point which is an intersection point between the third virtual line and the fourth virtual line; a third intersection point which is an intersection point between the third virtual line and the fifth virtual line; a fourth intersection point which is an intersection point between the fifth virtual line and the first virtual line; 20 regions surrounded by a void are prepared, and among the 20 regions, one or less regions contains a void. [Application example 3] A method for manufacturing a conductive layer, comprising: a coating step of coating a conductive paste containing metal powder on a first substrate to form a conductive paste layer; a laser processing step of processing the shape of the conductive paste layer by irradiating the conductive paste layer with laser light; a first transfer step of transferring the conductive paste layer formed on the first substrate to a second substrate; a second transfer step of transferring the conductive paste layer transferred to the second substrate onto a green sheet; A manufacturing method comprising: [Application example 4] The manufacturing method according to Application Example 3, A manufacturing method, characterized in that the peel strength when the conductive paste layer is peeled off from the first substrate is smaller than the peel strength when the conductive paste layer is peeled off from the second substrate. [Explanation of symbols]

[0060] θ1, θ1x, θ1y, θ2, θ2x, θ1y...Angle 10,10a…Base material 20,20B,20C…conductive layer 20A...Conductive paste layer 21,21a,21x…Conductor film 29...Margin 30, 30y...Laminate 31, 31y...Laminate 100, 100a, 100x, 100y...wiring board AL1, AL1a, AL1x, AL1y...First virtual line AL2, AL2a, AL2x, AL2y...Second virtual line AL3, AL3a, AL3x, AL3y...Third virtual line AL4, AL4a, AL4x, AL4y...4th virtual line AL5, AL5a, AL5y...5th virtual line CR…Crack CS...Cartesian coordinate system EP1, EP1a, EP1x, EP1y…End face part F1, F1a, F1x, F1y...First principal surface (principal surface) F2, F2a, F2x, F2y...Second principal surface (principal surface) GS...Green Sheet LA...laser light LS...long side SS...short side MA1...first base material MA2…Second base material RG1, RG1a, RG1y…area RG2, RG3...near the end V1...Vertex (1st intersection, 4th intersection) CP1a…(1st intersection) V2…Vertex (second intersection) CP2a…Second intersection CP3a...Third intersection CP4a…4th intersection VD...Void

Claims

1. A wiring board, A substrate; a conductive film disposed inside the base material and having electrical conductivity, the conductive film having a pair of main surfaces and end surface portions connecting the ends of the pair of main surfaces; Equipped with The conductive film has, in a cross section along a thickness direction of the conductive film, an angle formed by a first imaginary line along one of the pair of main surfaces and a second imaginary line along a portion of the end surface portion connected to the one main surface; an angle formed by a third imaginary line along the other of the pair of main surfaces and a fourth imaginary line along a portion of the end surface portion connected to the other main surface; and at least one of the angles is 45 degrees or more and 90 degrees or less.

2. 2. The wiring board according to claim 1, In a cross section of the substrate and the conductor film along the thickness direction of the conductor film, a fifth virtual line is defined as a virtual line that contacts a portion of the end surface of the conductor film that is farthest from a first intersection point, which is an intersection point between the first virtual line and the second virtual line, in a direction along the first virtual line and is perpendicular to the first virtual line. The substrate is the first intersection point; a second intersection point which is an intersection point between the third virtual line and the fourth virtual line; a third intersection point which is an intersection point between the third virtual line and the fifth virtual line; a fourth intersection point which is an intersection point between the fifth virtual line and the first virtual line; 20 regions surrounded by a void are prepared, and among the 20 regions, the number of regions containing a void is one or less.

3. A method for manufacturing a conductive layer, comprising: a coating step of coating a conductive paste containing metal powder on a first substrate to form a conductive paste layer; a laser processing step of processing the shape of the conductive paste layer by irradiating the conductive paste layer with laser light; a first transfer step of transferring the conductive paste layer formed on the first substrate to a second substrate; a second transfer step of transferring the conductive paste layer transferred to the second substrate onto a green sheet; A manufacturing method comprising:

4. The manufacturing method according to claim 3, A manufacturing method, characterized in that the peel strength when the conductive paste layer is peeled off from the first substrate is smaller than the peel strength when the conductive paste layer is peeled off from the second substrate.

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