Game machine

Abstract

To improve a performance effect.SOLUTION: A Pachinko game machine 1 includes a performance control board 300 capable of adjusting a sound volume of second sound data assigned to a second track on the basis of a sound volume of first sound data assigned to a first track. Sound volume peak value information indicating a peak value of the sound volume is stored for each predetermined unit time on the first sound data, in particular. The sound volume of the second sound data can be adjusted on the basis of the sound volume peak value information.SELECTED DRAWING: Figure 52

Description

[Technical Field]

[0001] The present invention relates to a gaming machine capable of reproducing effect sounds. [Background technology]

[0002] Conventionally, a gaming machine capable of reproducing effect sounds is known (see Patent Document 1). In this gaming machine, it is possible to adjust the volume of audio data assigned to one audio bus based on the volume of audio data assigned to another audio bus. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-132831 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in conventional gaming machines, volume adjustment is performed on an audio bus basis, which may make it difficult to improve the presentation effect. An object of the present invention is to improve the presentation effect. [Means for solving the problem]

[0005] In order to achieve the above object, the gaming machine of the first invention is characterized in that it is equipped with a control means capable of adjusting the volume of second audio data assigned to a second track based on the volume of first audio data assigned to a first track, and volume data indicating the peak volume value for the first audio data is stored at predetermined time intervals, and the volume of the second audio data can be adjusted based on the volume data. In the gaming machine according to the first invention, it is possible to adjust the volume of the second audio data assigned to the second track based on the volume of the first audio data assigned to the first track. This makes it possible to adjust the volume on an audio data basis (track basis), which allows for more detailed adjustments than adjusting the volume on an audio bus basis, thereby improving the presentation effect. In particular, in the gaming machine according to the first invention, volume data indicating the peak volume value of the first sound data is stored for each predetermined time, and the volume of the second sound data can be adjusted based on the volume data, thereby simplifying the process for adjusting the volume.

[0006] A gaming machine according to a second invention is the gaming machine according to the first invention, characterized in that an adjustment amount for the volume of the second audio data is calculated for each predetermined time period. In the gaming machine according to the second aspect of the present invention, the volume of the second sound data can be finely adjusted in predetermined time units. [Effects of the Invention]

[0007] According to the present invention, it is possible to improve the presentation effect. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a perspective view showing the overall configuration of a pachinko machine. [Figure 2] FIG. 2 is a diagram showing the front of the game board, and is a schematic diagram showing parts particularly necessary for explanation. [Figure 3] FIG. 2 is a block diagram showing the configuration of a control system of a pachinko machine. [Figure 4] FIG. 2 is a block diagram showing the configuration of a firing condition detection circuit and a firing control circuit. [Figure 5] FIG. 2 is a block diagram showing the configuration of the performance control board. [Figure 6] 1 is an address map of a memory area used by the CPU 210. [Figure 7] 10 is a flowchart showing a CPU initialization process. [Figure 8] 10 is a flowchart showing a main loop process. [Figure 9] 10 is a flowchart showing a save process when power is cut off. [Figure 10] 10 is a flowchart showing a timer interrupt process. [Figure 11] 10 is a flowchart illustrating a dynamic port output process. [Figure 12] 10 is a flowchart showing a performance display device output process. [Figure 13] 10 is a flowchart showing a setting-related process. [Figure 14] 10 is a flowchart illustrating a switch management process. [Figure 15] 10 is a flowchart showing the normal starting ball detection process. [Figure 16] Special Figure 1 is a flowchart showing the starting ball detection process. [Figure 17] This is a flowchart showing the starting ball detection process for Special Figure 2. [Figure 18] 10 is a flowchart showing a special pattern random number acquisition process. [Figure 19] 10 is a flowchart showing a special game management process. [Figure 20] 10 is a flowchart showing a special chart change waiting process. [Figure 21] 10 is a flowchart showing processing during special chart change. [Figure 22] 10 is a flowchart showing processing during special chart stop. [Figure 23] This is a flowchart showing the processing before the large prize opening. [Figure 24] 10 is a flowchart showing a special electric utility opening / closing switching process. [Figure 25] 10 is a flowchart showing the process for controlling the opening of the large prize opening. [Figure 26] 10 is a flowchart showing the process of validating the closing of the large prize opening. [Figure 27]A flowchart showing the waiting process for the end of the large prize opening. [Figure 28] 10 is a flowchart showing a normal game management process. [Figure 29] 10 is a flowchart showing the process of waiting for a change in the general map. [Figure 30] 10 is a flowchart showing the processing during normal map fluctuation. [Figure 31] 10 is a flowchart showing the processing performed when the map is stopped. [Figure 32] This is a flowchart showing the pre-opening process for normal electric devices. [Figure 33] 10 is a flowchart showing the normal electric utility opening / closing switching process. [Figure 34] 10 is a flowchart showing the normal electric accessory opening control process. [Figure 35] This is a flowchart showing the normal electric device closure validity process. [Figure 36] This is a flowchart showing the waiting process for the end of the release of a normal electric device. [Figure 37] 10 is a flowchart showing a performance display device control process. [Figure 38] 10 is a flowchart illustrating an initial transfer process. [Figure 39] 10 is a flowchart showing a sub-timer interrupt process. [Figure 40] 10 is a flowchart showing a command analysis process. [Figure 41] 10 is a flowchart showing a hold command receiving process. [Figure 42] 10 is a flowchart illustrating a read-ahead command reception process. [Figure 43] 10 is a flowchart showing a variable command receiving process. [Figure 44] 10 is a flowchart showing a stop command reception process. [Figure 45] 10 is a flowchart illustrating an opening command receiving process. [Figure 46] 10 is a flowchart showing a Vsync interrupt process. [Figure 47] 10 is a flowchart showing a command construction task process. [Figure 48] 10 is a flowchart showing a sound interrupt process. [Figure 49] 10 is a flowchart illustrating a lamp interruption process. [Figure 50] 10 is a flowchart showing a movable body interrupt process. [Figure 51] FIG. 2 is a block diagram showing the configuration of a sound circuit. [Figure 52] 10 is a diagram showing volume peak value information corresponding to audio data A. FIG. [Figure 53] FIG. 10 is a diagram illustrating a track ducking function. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In this embodiment, a gaming machine according to the present invention is applied to a pachinko machine 1.

[0010] (Overall configuration of Pachinko machine 1) First, the overall configuration of the pachinko machine 1 will be described. 1 is a perspective view showing the overall configuration of a pachinko machine 1. The pachinko machine 1 is configured to include an outer frame unit 2, an inner frame unit 3, an integrated door unit 4, and a game board unit 10. The outer frame unit 2, inner frame unit 3, and integrated door unit 4 are fixed to one another via a hinge mechanism, which allows the inner frame unit 3 to be opened and closed relative to the outer frame unit 2. Furthermore, the integrated door unit 4 can be opened and closed relative to both the inner frame unit 3 and the outer frame unit 2.

[0011] The outer frame unit 2 is configured to include a rectangular frame body (outer frame). The outer frame of the outer frame unit 2 is fixed to the island equipment of the game center. The inner frame unit 3 is configured to include a rectangular frame body (inner frame). The inner frame unit 3 is disposed inside the outer frame unit 2. The integrated door unit 4 is formed in the shape of a rectangular door and has a transparent plate 4a disposed in the approximate center, a decorative portion 4b disposed around the transparent plate 4a, a tray unit 5 disposed below the transparent plate 4a, and a firing handle unit 6 disposed to the side of the tray unit 5. The transparent plate 4a is formed in a flat plate shape from a transparent material such as resin or glass. The decorative portion 4b is formed from a transparent or translucent resin material and has a shape that bulges out toward the front. At each corner on the upper side of the decorative portion 4b, a sound vent 4c is provided, inside which a speaker 22 (see FIG. 3) is disposed. Each sound vent 4c is provided with a plurality of sound vent holes that allow the sound output by the speaker 22 to pass through. In addition, a frame lamp 20 (see FIG. 3) is disposed on the decorative portion 4b. The frame lamp 20 is configured to include a plurality of light-emitting elements (LEDs) that are driven by dynamic lighting control.

[0012] The tray unit 5 includes a tray 5a for receiving game balls (loan balls and prize balls) and various operating means that can be operated by the player. In this embodiment, various operation means include a performance button 5b, a rotary selector 5c, a light intensity adjustment button (not shown), a volume adjustment button (not shown), a cross key button (not shown), and the like. The effect button 5b includes an operation part that can be pressed by the player, and a button switch 25 (see FIG. 3) that detects the pressing of the operation part. The button switch 25 outputs a detection signal to the effect control board 300 (see FIG. 3) every time the operation part is pressed. The rotary selector 5c (so-called "jog dial") includes an operating section that can be rotated by the player, and a dial switch 26 (see FIG. 3) that detects the rotation of the operating section. The dial switch 26 outputs a detection signal to the performance control board 300 each time the operating section is rotated by a predetermined angle (for example, 60°).

[0013] The light intensity adjustment button is configured to include two operation parts (a first operation part and a second operation part) that can be pressed by the player, and a light intensity adjustment switch 27 (see FIG. 3) that detects the pressing of each operation part. The light intensity adjustment switch 27 outputs a first detection signal to the performance control board 300 each time the first operation part is pressed, and outputs a second detection signal to the performance control board 300 each time the second operation part is pressed. The volume adjustment button is configured to include two operation parts (a first operation part and a second operation part) that can be pressed by the player, and a volume adjustment switch 28 (see FIG. 3) that detects the pressing of each operation part. Volume adjustment switch 28 outputs a first detection signal to performance control board 300 each time the first operation part is pressed, and outputs a second detection signal to performance control board 300 each time the second operation part is pressed.

[0014] The cross key button is configured to include four operation units (up button, down button, left button, and right button) that can be pressed by the player, and a cross key switch 29 (see FIG. 3) that detects the pressing of each operation unit. Each time the up button is pressed, the cross key switch 29 outputs a first detection signal to the performance control board 300, each time the down button is pressed, a second detection signal to the performance control board 300, each time the left button is pressed, a third detection signal to the performance control board 300, and each time the right button is pressed, a fourth detection signal to the performance control board 300.

[0015] A loan operation unit 7 is disposed on the top surface of the tray unit 5. The loan operation unit 7 has a ball loan button 7a, a return button 7b, and a degree display device 7c. Here, the pachinko machine 1 is communicably connected to a CR unit 700 that can read and update information recorded on a prepaid card. When a prepaid card (not shown) is inserted into the CR unit 700, the remaining number of points of the valuable medium recorded on the prepaid card inserted into the CR unit 700 is displayed on the point display device 7c. Furthermore, when the ball loan button 7a is operated while the prepaid card is inserted into the CR unit 700, a predetermined number of game balls are paid out to the tray 5a. At this time, the remaining number of points of the valuable medium recorded on the prepaid card is updated according to the number of game balls paid out, and the updated remaining number of points of the valuable medium is displayed on the point display device 7c. Furthermore, when the return button 7b is operated while a prepaid card with remaining points of valuable media is inserted into the CR unit 700, the prepaid card is returned from the CR unit 700. Here, examples of prepaid cards include magnetic storage media, media with built-in storage ICs, and the like.

[0016] The firing handle unit 6 includes a handle base portion (not shown), a handle operating portion (not shown), and a firing stop button (not shown). The handle base portion is attached to the front side of the integrated door unit 4. A bearing portion is provided on the front side of the handle base portion. The handle operating unit is configured in a shape that allows it to be gripped by a player. A rotating shaft is provided on the back side of the handle operating unit. The rotating shaft is supported by a bearing in the handle base, so that the handle operating unit is rotatably attached to the handle base. The handle operating unit can be rotated (displaced) between a predetermined initial position and a predetermined limit position. A biasing means (a spring in this embodiment) that biases the handle operating unit toward the initial position is disposed inside the launch handle unit 6. This allows the handle operating unit to be positioned (displaced) at the initial position when the player is not rotating it. The firing stop button is provided on the side of the handle operation part and can be pressed by the player.

[0017] The firing handle unit 6 also includes a firing volume 411, a touch sensor 412, and a firing stop switch 413. The firing volume 411 is composed of a variable resistor. The firing volume 411 detects the amount of rotation of the handle operating unit (the angle at which the handle operating unit is rotated). Specifically, the firing volume 411 is composed of a rotation shaft and a resistor whose resistance value changes depending on the amount of rotation of the rotation shaft (rotation angle). The rotation shaft of the firing volume 411 is fixed coaxially to the rotation shaft portion of the handle operating unit. As a result, the rotation shaft of the firing volume 411 rotates depending on the rotation operation of the handle operating unit, and the resistance value of the firing volume 411 changes depending on the amount of rotation of the handle operating unit. The firing volume 411 is electrically connected to the operation detection unit 421 (see FIG. 4). The operation detection unit 421 detects the rotation operation (rotation operation amount) of the handle operation unit based on a change in the resistance value (voltage value) of the firing volume 411. The touch sensor 412 detects the player's contact (grasping) with the handle operation unit based on a change in capacitance. When the touch sensor 412 detects the player's contact with the handle operation unit, it outputs a touch signal to the launch enable condition detection unit 422 (see FIG. 4) (sets the touch signal to a high level). On the other hand, when the touch sensor 412 does not detect the player's contact with the handle operation unit, it stops outputting the touch signal to the launch enable condition detection unit 422 (sets the touch signal to a low level). The firing stop switch 413 detects the pressing of the firing stop button. When the firing stop switch 413 does not detect the pressing of the firing stop button, it outputs a firing stop signal to the firing enable condition detection unit 422 (sets the firing stop signal to high level). On the other hand, when the firing stop switch 413 detects the pressing of the firing stop button, it stops outputting the firing stop signal to the firing enable condition detection unit 422 (sets the firing stop signal to low level).

[0018] (Configuration of game board unit 10) Next, the configuration of the game board unit 10 will be described. FIG. 2 shows the front of the game board, and is a diagram that shows in schematic form parts particularly necessary for explanation. The game board unit 10 is supported by the inner frame unit 3. Specifically, the game board unit 10 is attached to the inside of the inner frame of the inner frame unit 3. This allows the game board unit 10 to be disposed on the back side of the integrated door unit 4. A player can then view the game board 11 (play area 30) described later through the transparent plate 4a. In this embodiment, the play area 30 described later is formed between the back side of the transparent plate 4a and the front side of the game board 11. As shown in Figure 2, the game board unit 10 includes a set board (not shown), a game board 11 attached to the set board, and various presentation devices (main image display device 31, sub-image display device 32, movable body unit, etc.) attached to the set board.

[0019] The set plate is formed in a box shape with an open front side, and an opening formed as a through hole is provided in the approximate center of the rear plate of the set plate. The gaming board 11 is attached to the front side of the set board. The gaming board 11 is made of resin and is formed into a flat plate. An opening (not shown) consisting of a through-hole is provided in the approximate center of the gaming board 11. The player can view the display screen 31a of the main image display device 31 through the opening provided in the gaming board 11 and the opening provided in the set board. A game area 30 is formed around the opening on the front of the game board 11, through which game balls flow down when the launch handle unit 6 is rotated. The game area 30 is configured with two paths for game balls to flow down: a left path formed on the left side of the main image display device 31 and a right path formed on the right side of the main image display device 31. Furthermore, a board lamp 21 (see FIG. 3) is disposed in the play area 30 of the game board 11. The board lamp 21 is configured to include a plurality of light-emitting elements (LEDs) that are driven by dynamic lighting control.

[0020] The main image display device 31 is attached to the rear side of the set board and is configured by a variable display device such as a liquid crystal display or a CRT (Cathode Ray Tube) display. The main image display device 31 includes a display screen 31a capable of displaying various types of effect images (moving images and still images). The display screen 31a can be configured to have three first performance pattern display areas a1 to a3 (not shown) in which the first performance pattern z1 (not shown) is displayed, and one second performance pattern display area a4 (not shown) in which the second performance pattern z2 (not shown) is displayed. The first effect symbol z1 is composed of identification information (symbols) such as numbers, letters, symbols, characters, etc. In each of the first effect symbol display areas a1 to a3, it is possible to display the first effect symbol z1 in a variable and stationary manner. The second effect symbol z2 is composed of color bars. In the second effect symbol display area a4, it is possible to display the second effect symbol z2 in a variable and stationary manner.

[0021] The variable display of the performance patterns z1 and z2 refers to a display in which the first performance pattern z1 is moved (scrolled) in each of the first performance pattern display areas a1 to a3, and the type of the second performance pattern z2 displayed in the second performance pattern display area a4 is changed (the color represented by the color bar is changed sequentially). The stopped display of the performance patterns z1 and z2 refers to a display in which one type of first performance pattern z1 is stopped at the lottery result display position of each first performance pattern display area a1 to a3, and one type of second performance pattern z2 is displayed in the second performance pattern display area a4 (the color bar shows a specified color). The result of the special pattern lottery (first special pattern lottery or second special pattern lottery) is displayed based on the combination of the first performance pattern z1 displayed in a stopped state in the three first performance pattern display areas a1 to a3 and the second performance pattern z2 displayed in a stopped state in the second performance pattern display area a4. Furthermore, the display screen 31a can be configured with reserved symbol display areas b1 and b2 (not shown) in which reserved symbol h (not shown) is displayed. The reserved symbol display area b1 displays a reserved symbol h corresponding to the game information during the notification display (variable display and stop display of special symbols). The reserved symbol display area b2 displays a reserved symbol h corresponding to the game information for which the notification display is pending.

[0022] The sub image display device 32 is disposed at a position on the front side of the main image display device 31 . The sub-image display device 32 is configured by a variable display device such as a liquid crystal display, a CRT display, etc. The sub-image display device 32 has a display screen 32a that can display a performance image. The sub-image display device 32 can be displaced (moved) in the vertical direction by a drive mechanism (not shown). Specifically, the sub-image display device 32 can be displaced within a predetermined range including an origin position (see FIG. 2) and a performance position (not shown) below the origin position. The sub-image display device 32 disposed (displaced) at the origin position is disposed above the display screen 31a of the main image display device 31 and does not cover the display screen 31a. On the other hand, the sub-image display device 32 disposed (displaced) at the performance position is disposed in front of the display screen 31a of the main image display device 31 and covers part of the display screen 31a.

[0023] A first start opening 51 is provided below the display screen 31a in the game area 30. The first start opening 51 is an entry opening (a so-called "navel") that opens upward and allows game balls to enter at all times. The first start opening 51 allows game balls that flow down the left path to enter (game balls that flow down the right path cannot enter). A special symbol 1 start port switch 101 (see FIG. 3) is disposed within the first start port 51. The special symbol 1 start port switch 101 outputs a detection signal to the main control board 200 in response to the detection of a game ball entering the first start port 51 (entry of a game ball into the first start port 51). In response to the input of the detection signal from the special symbol 1 start port switch 101, the main control board 200 executes a first special symbol lottery.

[0024] To the left of the first starting opening 51 in the gaming area 30, there are provided an upper left other winning opening 55, a middle left other winning opening 56, and a lower left other winning opening 57. Each of the other winning openings 55-57 is an opening that opens upward and allows game balls to enter at all times. Each of the other winning openings 55-57 allows game balls that flow down the left path to enter (game balls that flow down the right path cannot enter). A left prize opening switch 106 (see FIG. 3) is disposed on the gaming board 11. The left prize opening switch 106 outputs a detection signal to the main control board 200 in response to detection of a gaming ball that has entered the upper left other prize opening 55 (entry of a gaming ball into the upper left other prize opening 55), a gaming ball that has entered the center left other prize opening 56 (entry of a gaming ball into the center left other prize opening 56), and a gaming ball that has entered the lower left other prize opening 57 (entry of a gaming ball into the lower left other prize opening 57). In response to the input of the detection signal from the left prize opening switch 106, the main control board 200 causes the gaming ball payout device 440 to perform a payout operation of prize balls.

[0025] A start gate 41 is provided to the right of the display screen 31a in the gaming area 30. The start gate 41 is formed so that gaming balls can always pass through it. The start gate 41 allows gaming balls flowing down the right path to pass through (but does not allow gaming balls flowing down the left path to pass through). A gate switch 104 (see FIG. 3) is provided on the start gate 41. The gate switch 104 outputs a detection signal to the main control board 200 in response to the detection of a gaming ball passing through the start gate 41 (passage of the gaming ball through the start gate 41). In response to the input of the detection signal from the gate switch 104, the main control board 200 executes a normal symbol lottery.

[0026] A large prize opening 53 is provided below the start gate 41 in the gaming area 30. The large prize opening 53 is provided with a special electric device (special electric device) 53a (so-called "attacker") that can be displaced between a closed state that prevents game balls from entering the large prize opening 53 and an open state that allows game balls to enter the large prize opening 53. The special electric device 53a is opened and closed by a special electric device solenoid 65 (see FIG. 3). Normally, the special electric device 53a is closed and the big prize opening 53 does not allow game balls to enter, but if the first special symbol lottery or the second special symbol lottery is won and a big win game state is created, the special electric device 53a is opened and game balls can enter. The big prize opening 53 allows game balls flowing down the right path to enter (game balls flowing down the left path cannot enter). A count switch 103 (see FIG. 3) is disposed inside the large prize opening 53. The count switch 103 outputs a detection signal to the main control board 200 in response to the detection of a game ball entering the large prize opening 53 (entry of a game ball into the large prize opening 53). In response to the input of the detection signal from the count switch 103, the main control board 200 causes the game ball payout device 440 to perform the payout operation of the prize balls.

[0027] A second starting opening 52 is provided below the big winning opening 53 in the gaming area 30. The second starting opening 52 is provided with a normal electric device (normal electric device) 52a (so-called "electric tulip") that can be displaced between a closed state that prevents game balls from entering the second starting opening 52 and an open state that allows game balls to enter the second starting opening 52. The normal electric device 52a is opened and closed by a normal electric device solenoid 64 (see FIG. 3). Normally, the second starting opening 52 has the normal electric device 52a in a closed state, preventing game balls from entering, but if the normal symbol lottery is won, the normal electric device 52a is opened, allowing game balls to enter. The second starting opening 52 allows game balls flowing down the right path to enter (game balls flowing down the left path cannot enter). A special symbol 2 start port switch 102 (see FIG. 3) is disposed within the second start port 52. The special symbol 2 start port switch 102 outputs a detection signal to the main control board 200 in response to the detection of a game ball entering the second start port 52 (entry of a game ball into the second start port 52). The main control board 200 executes a second special symbol lottery in response to the input of the detection signal from the special symbol 2 start port switch 102.

[0028] A right other winning opening 54 is provided below the second starting opening 52 in the gaming area 30. The right other winning opening 54 is an opening that opens upward and allows game balls to enter at all times. The right other winning opening 54 allows game balls that flow down the right path to enter (game balls that flow down the left path cannot enter). A right prize opening switch 105 (see FIG. 3) is disposed inside the right other prize opening 54. The right prize opening switch 105 outputs a detection signal to the main control board 200 in response to the detection of a game ball entering the right other prize opening 54 (entry of a game ball into the right other prize opening 54). In response to the input of the detection signal from the right prize opening switch 105, the main control board 200 causes the game ball payout device 440 to perform the payout operation of the prize balls.

[0029] At the lowest position in the gaming area 30, an outlet 58 is provided for discharging gaming balls that do not enter any of the winning holes 51 to 57 (win). Here, the inner frame unit 3 includes a discharge path (not shown) through which game balls discharged from the play area 30 pass. Specifically, the discharge path is attached to the back side of the inner frame of the inner frame unit 3. The pachinko machine 1 is configured so that all game balls shot into the play area 30 (all game balls discharged from the play area 30) pass through the discharge path. That is, the game balls shot into the play area 30 are discharged from the play area 30 by entering any of the winning holes 51 to 57 or by passing through the outlet 58, and then flow into the discharge path. Specifically, the game balls that enter the winning holes 51 to 57 are detected by the switches 101 to 103, 105, and 106 disposed in the winning holes, and then guided to the discharge path. In addition, the game balls that are discharged from the outlet 58 are also guided to the discharge path. An out switch 109 (see FIG. 3) is disposed in the inner frame unit 3. The out switch 109 outputs a detection signal to the main control board 200 in response to the detection of a gaming ball passing through the discharge path (a gaming ball discharged from the gaming area 30). As a result, all gaming balls discharged from the gaming area 30 are detected by the out switch 109. Furthermore, in the game area 30, a plurality of nails (not shown) are arranged so as to guide game balls to each of the winning holes 51 to 57 and the starting gate 41.

[0030] A main display device 60 is disposed on the game board 11. The main display device 60 is configured to include a plurality of lighting elements (segments). Each lighting element is configured by a light-emitting element (in this embodiment, an LED). The main display device 60 displays information related to the game. The main display device 60 is configured to include a special chart 1 display device, a special chart 2 display device, a regular chart display device, a special chart 1 reserve display device, a special chart 2 reserve display device, a regular chart reserve display device, a round display device, a right-hand hit display device, a probability change display device, and a time-saving display device. Specifically, the main display device 60 is configured to include 32 lighting elements (LED1 to LED32). In the main display device 60, LED1 to LED8 constitute the special chart 1 display device, LED7 to LED16 constitute the special chart 2 display device, LED17 and 18 constitute the normal chart display device, LED19 to LED23 constitute the round display device, LED24 constitutes the right-hit display device, LED25 and 26 constitute the special chart 1 reserve display device, LED27 and 28 constitute the special chart 2 reserve display device, LED29 and 30 constitute the normal chart reserve display device, LED31 constitutes the probability change display device, and LED32 constitutes the time-saving display device.

[0031] The special chart 1 display device is capable of displaying the variation and stopping of the first special pattern, which consists of numbers, patterns, etc. Then, the special chart 1 display device displays the result of the first special pattern lottery by the first special pattern that is stopped and displayed. The special symbol 2 display device is capable of displaying the variation and stopping of the second special symbol, which consists of numbers, symbols, etc. The special symbol 2 display device then displays the result of the second special symbol lottery based on the stopped second special symbol. Here, the display of the special pattern (first special pattern or second special pattern) on the special pattern display device and the display of the performance patterns z1 and z2 in the performance pattern display areas a1 to a4 are associated with the time when the variable display starts, the time when the stopped display starts, and the lottery result indicated by the stopped displayed pattern. Then, when the first special pattern (stop pattern) displayed in a stopped state on the special chart 1 display device becomes a specific pattern (jackpot pattern), or when the second special pattern (stop pattern) displayed in a stopped state on the special chart 2 display device becomes a specific pattern (jackpot pattern), a jackpot game state, which is a game state advantageous to the player, is created.

[0032] The normal symbol display device is capable of displaying the fluctuations and stopping of normal symbols consisting of numbers, symbols, etc. The normal symbol display device then displays the results of the normal symbol lottery based on the normal symbol that is stopped. When the normal symbol that is stopped and displayed on the normal symbol display device becomes a specific symbol (a normal symbol winning symbol), a normal symbol winning game state, which is a game state advantageous to the player, is created.

[0033] The special pattern 1 pending display device displays the number of times the display of the lottery results of the first special pattern lottery has been pending (special pattern 1 pending number). The special pattern 2 reserved display device displays the number of times the display of the lottery results of the second special pattern lottery has been reserved (special pattern 2 reserved number). The regular symbol reserved display device displays the number of times the display of the lottery result of the regular symbol lottery has been reserved (regular symbol reserved number). The round display device displays the number of rounds of play executed during the jackpot game state (type of jackpot game state). The right-hand shot display device displays the path (left-hand path or right-hand path) along which the game ball should be shot. The probability variation display device displays the game status (whether a special chart high probability state is occurring or a special chart low probability state is occurring) when the power is restored. The time-saving display device displays the current game status (time-saving control is running or stopped).

[0034] In addition, one or more movable body units (not shown) are arranged in the pachinko machine 1. In this embodiment, one or more movable body units are arranged in the integrated door unit 4, and one or more movable body units are arranged in the game board unit 10. Each movable body unit of the integrated door unit 4 is disposed on the front surface of the decorative portion 4b, on the upper surface of the tray unit 5, etc., and is capable of performing a predetermined performance operation. Each movable body unit of the game board unit 10 is attached to the front side of the set board. Specifically, each movable body unit is disposed in the space (hereinafter referred to as "performance space") between the game board 11 and the main image display device 31 (display screen 31a). Each movable body unit is capable of performing a predetermined performance action in the performance space. Each movable body unit includes a performance member, a drive mechanism, a drive source, and a position detection sensor 24 (see FIG. 3). In this embodiment, a motor 23 (see FIG. 3) is used as the drive source. The motor 23 is a stepping motor. Note that a solenoid may also be used as the drive source. The effect member can be displaced in a predetermined direction by a drive mechanism. Specifically, the effect member can be displaced to a plurality of positions including an initial position and an effect position. The effect member is driven (displaced) by a motor 23.

[0035] The position detection sensor 24 is composed of a photosensor or the like. The position detection sensor 24 detects the position of the performance component. Specifically, the position detection sensor 24 includes a light-projecting unit and a light-receiving unit that receives light projected from the light-projecting unit. The position detection sensor 24 outputs a detection signal to the performance control board 300 in response to the light-receiving unit receiving (detecting) the light projected from the light-projecting unit. On the other hand, the position detection sensor 24 stops outputting the detection signal to the performance control board 300 when the light-receiving unit does not receive (detect) the light projected from the light-projecting unit. Furthermore, a shielding plate is provided at a predetermined position of the performance member. When the performance member is placed in its initial position, the shielding plate is placed between the light-emitting portion and light-receiving portion of the position detection sensor 24, blocking light from entering the light-receiving portion. As a result, when the performance member is placed in its initial position, the output of a detection signal from the position detection sensor 24 to the performance control board 300 is stopped. On the other hand, when the performance member is not placed in its initial position, a detection signal is output from the position detection sensor 24 to the performance control board 300. This makes it possible for the performance control board 300 to detect whether or not the performance component is placed in the initial position depending on the input status of the detection signal from the position detection sensor 24.

[0036] The pachinko machine 1 is also provided with detection sensors that detect various abnormal conditions. In this embodiment, a glass frame opening sensor 107, an inner frame opening sensor 108, a vibration detection sensor 113, a radio wave detection sensor 114, a magnetic detection sensor 115, and the like are provided as detection sensors. The glass frame opening sensor 107 detects the opening of the integrated door unit 4 relative to the inner frame unit 3. Then, in response to the opening of the integrated door unit 4 relative to the inner frame unit 3, the glass frame opening sensor 107 transmits a detection signal to the main control board 200 via the dispensing control board 400. The inner frame opening sensor 108 detects the opening of the inner frame unit 3 relative to the outer frame unit 2. Then, in response to the opening of the inner frame unit 3 relative to the outer frame unit 2, the inner frame opening sensor 108 transmits a detection signal to the main control board 200 via the dispensing control board 400.

[0037] The vibration detection sensor 113 detects vibrations of the game board 11. In this embodiment, the vibration detection sensor 113 is disposed on the game board 11. Then, the vibration detection sensor 113 transmits a detection signal to the main control board 200 in response to detecting vibrations of the game board 11. The radio wave detection sensors 114 detect radio waves generated around the gaming board 11. In this embodiment, two radio wave detection sensors 114 are arranged on the gaming board 11. Each radio wave detection sensor 114 transmits a detection signal to the main control board 200 in response to the detection of a radio wave. The magnetic detection sensor 115 detects magnetism generated around the gaming board 11. In this embodiment, three magnetic detection sensors 115 are provided. Specifically, one magnetic detection sensor 115 is provided in the inner frame unit 3 (discharge path). Two magnetic detection sensors 115 are provided in the gaming board 11. The magnetic detection sensor 115 provided in the inner frame unit 3 transmits a detection signal to the main control board 200 via the payout control board 400 in response to the detection of magnetism. Each magnetic detection sensor 115 provided on the gaming board 11 transmits a detection signal to the main control board 200 in response to the detection of magnetism.

[0038] (Control system configuration) Next, the configuration of the control system in the pachinko machine 1 will be described. Fig. 3 is a block diagram showing the configuration of the control system of the pachinko machine. Fig. 6 is an address map of the memory area used by the CPU 210. The pachinko machine 1 is equipped with various control boards. Specifically, as shown in Figure 3, the pachinko machine 1 is equipped with multiple control boards, such as a main control board 200, a performance control board 300, a payout control board 400, a power supply board 600 that supplies power (electricity) to each of the control boards 200, 300, 400, etc., a driver board 330, a sub-connection board 340, etc. The control boards 200, 300, 400, and 600 are independent (separate) circuit boards, and each of the control boards 200, 300, 400, and 600 is housed in an individual board case. The main control board 200 and the performance control board 300 are included in the game board unit 10. Specifically, the main control board 200 and the performance control board 300 are attached to the back side of the game board 11. The dispensing control board 400 is included in the inner frame unit 3. Specifically, the dispensing control board 400 is attached to the back side of the inner frame that the inner frame unit 3 has.

[0039] (Configuration of main control board 200) First, the configuration of the main control board 200 will be described. The main control board 200 controls the progress of the game. The main control board 200 is configured to include a one-chip microcomputer, a clock generating circuit 202, a random number generating circuit 203, an input port 204, an output port 205, a performance display device 206, a RAM clear switch 207, a setting key switch 208, a sink driver 240, source drivers 250a, 250b, etc. The one-chip microcomputer is an LSI that integrates a CPU core, a register, a semiconductor memory, etc. Specifically, the one-chip microcomputer is configured to include a CPU 210, a ROM 220, a RAM 230, etc.

[0040] The main control board 200 is configured to include a memory area used by the CPU 210. As shown in Fig. 6, the memory area used by the CPU 210 is configured to include a memory area (0000H to 2FFFH) allocated to the ROM 220 and a memory area (F000H to F3FFH) allocated to the RAM 230. Here, in FIG. 6, addresses for specifying memory areas are shown in hexadecimal numbers ("H" indicates that the numbers are hexadecimal).

[0041] The ROM 220 (memory area of ​​the ROM 220) is configured to include a used area m1 (0000H to 1A7AH) and an unused area m2 (2000H to 2BFFH). The used area m1 is configured to include a program area, an unused area, and a data area. The program area stores a program (program code) for controlling the progress of the game. The data area stores data (program data) for controlling the progress of the game. Note that the used area m1 may be configured without including an unused area.

[0042] The unused area m2 includes a program area and a data area. The program area stores a program (program code) for executing processing related to tests defined in the Gaming Machine Regulations, and a program (program code) for controlling the display of the performance display device 206 (specifically, calculating the base ratio). The data area stores data (program data) for executing processing related to tests defined in the Gaming Machine Regulations, and data (program data) for controlling the display of the performance display device 206. In addition to the used area m1 and unused area m2, the ROM 220 is also provided with an unused area, a ROM comment area, a program management area, and the like. The ROM comment area stores arbitrary data such as the program title, version, etc. On the other hand, the program management area stores information necessary for the CPU 210 to execute various programs. In addition, an unused area m3 of a predetermined number of bytes (for example, 16 bytes or more) is provided between the used area m1 and the unused area m2 in the ROM 220. This clarifies the boundary between the used area m1 and the unused area m2.

[0043] The RAM 230 (memory area of ​​the RAM 230) is configured to include a used area M1 (F000H to F1FFH) and a non-used area M2 (F300H to F3FFH). The used area M1 includes a work area and a stack area. The work area is used as an area for temporarily storing various data during execution of the program (program for controlling the progress of the game) stored in the used area m1. On the other hand, the stack area is used as an area for temporarily saving various data during execution of the program (program for controlling the progress of the game) stored in the used area m1. Note that the used area M1 does not have to be configured to include an unused area. Specifically, the work area is composed of a setting value area, a gaming machine status flag area, a checksum area, a backup flag area, an error-related area, a normal game-related area 1, and a normal game-related area 2. The set value area stores set values. The gaming machine status flag area stores gaming machine status flags. The checksum area stores checksums. The backup flag area stores backup flags. The error-related area stores information related to errors. The normal game-related area 1 stores subcommand pointers, etc. The normal game-related area 2 stores input / output data for the main control board 200, data for arithmetic processing, various counters (random number counters, timer counters, etc.), flags for managing lottery results and gaming status, etc. In particular, the normal game-related area 2 includes an area (a gaming information storage area, described later) for storing gaming information acquired in response to the input of detection signals from the special chart 1 start port switch 101, the special chart 2 start port switch 102, and the gate switch 104.

[0044] The unused area M2 is configured to include a work area and a stack area. The work area is used as an area for temporarily storing various data during execution of a program stored in the unused area m2 (a program for executing processing related to a test defined by the gaming machine regulations, or a program for controlling the display of the performance display device 206). On the other hand, the stack area is used as an area for temporarily saving various data during execution of a program stored in the unused area m2 (a program for executing processing related to a test defined by the gaming machine regulations, or a program for controlling the display of the performance display device 206). Specifically, the work area includes a performance display related area, which is used as an area for temporarily storing various data during execution of a program for controlling the display of the performance display device 206. Additionally, an unused area M3 of a predetermined number of bytes (16 bytes or more) is provided between the used area M1 and the unused area M2 in RAM 230. This clarifies the boundary between the used area M1 and the unused area M2.

[0045] In this embodiment, processing based on a program (a program for controlling the progress of the game) stored in the use area m1 is permitted to refer to data stored in the non-use area M2. On the other hand, data stored in the unused area M2 is prohibited from being rewritten (changed) by processing based on the program (program for controlling the progress of the game) stored in the used area m1. In addition, in processing based on a program stored in the unused area m2 (a program for executing processing related to tests specified in the gaming machine regulations, or a program for controlling the display of the performance display device 206), it is permitted to refer to data stored in the used area M1. On the other hand, it is prohibited for data stored in the use area M1 to be rewritten (changed) by processing based on a program stored in the non-use area m2 (a program for executing processing related to tests specified in the gaming machine regulations, or a program for controlling the display of the performance display device 206). The game in the pachinko machine 1 can be progressed (completed) by a program (a program for controlling the progress of the game) stored in the use area m1.

[0046] The clock generation circuit 202 generates a clock (synchronization signal) at a predetermined clock frequency (12 MHz in this embodiment), and outputs this clock to the CPU 210 and the random number generation circuit 203, respectively. The random number generating circuit 203 is configured to include a first loop counter that generates a winning random number for the normal symbol lottery, a second loop counter that generates a jackpot random number for the first special symbol lottery, a third loop counter that generates a jackpot random number for the second special symbol lottery, and a fourth loop counter that generates a reach group random number. The first loop counter generates a winning random number for the normal symbol lottery by updating the value of the loop counter by one within a predetermined range (in this embodiment, within the range of 0 to 65535) every time one clock is input from the clock generation circuit 202. In this embodiment, the value of the first loop counter is updated every 0.083 [μs] (1 [s] / 12 [MHz] = 0.083 [μs]). The second loop counter generates a jackpot random number for the first special symbol lottery by updating the loop counter value by one within a predetermined range (in this embodiment, within the range of 0 to 65535) every time one clock is input from the clock generation circuit 202. In this embodiment, the value of the second loop counter is updated every 0.083 [μs] (1 [s] / 12 [MHz]=0.083 [μs]).

[0047] The third loop counter generates a jackpot random number for the second special symbol lottery by updating the value of the loop counter by one within a predetermined range (in this embodiment, within the range of 0 to 65535) every time one clock is input from the clock generation circuit 202. In this embodiment, the value of the third loop counter is updated every 0.083 [μs] (1 [s] / 12 [MHz]=0.083 [μs]). The fourth loop counter generates a reach group random number by updating the value of the loop counter by one within a predetermined range (in this embodiment, within the range of 0 to 10006) every time 32 clocks are input from the clock generation circuit 202 (once for each 32 divisions of the clock frequency). In this embodiment, the value of the fourth loop counter is updated every 2.666 μs (32 s / 12 MHz = 2.666 μs).

[0048] The input port 204 is configured to include a plurality of input ports (in this embodiment, input ports 0 to 3). Input port 0 receives a detection signal from the glass frame opening sensor 107, a detection signal from the inner frame opening sensor 108, a detection signal from the vibration detection sensor 113, a detection signal from one of the radio wave detection sensors 114, a detection signal from the magnetic detection sensor 115, etc. To the input port 1, a RAM clear signal from the RAM clear switch 207, a detection signal from the setting key switch 208, a handle detection signal from the launch enabling condition detection unit 422, and the like are input. Input port 2 receives detection signals from the count switch 103, the right prize slot switch 105, the left prize slot switch 106, the out switch 109, and the other radio wave detection sensor 114. Input port 3 receives detection signals from special diagram 1 start port switch 101, detection signals from special diagram 2 start port switch 102, detection signals from gate switch 104, etc. Each input port (input port 0 to input port 3) has a reception storage area corresponding to each switch / sensor (detection signal). In the reception storage area corresponding to each switch / sensor, one bit of data is set that indicates the reception status of the detection signal from that switch / sensor. Specifically, the receiving memory area corresponding to each switch / sensor is set to "1" when a detection signal is input from the switch / sensor (high level), and is set to "0" when a detection signal is not input from the switch / sensor (low level).

[0049] The output port 205 is configured to include a plurality of output ports (output port 0 to output port 4 in this embodiment). The output port 0 outputs data signals ("SEGDATA0" to "SEGDATA7") for controlling the lighting of the main display device 60. The data signals output from the output port 0 are input to the source driver 250a. Output port 1 outputs common signals ("COM0" to "COM3") for controlling the lighting of the main display device 60 and the performance display device 206, a launch permission signal for detecting the launch conditions described below, etc. The common signals output from output port 1 are input to the sink driver 240. The output port 2 outputs an external signal. At this time, the external signal output from the output port 2 is input to the hall computer via the payout control board 400 and the external terminal board 450. The output port 3 outputs a control signal for controlling the driving of the normal electric accessory solenoid 64, a control signal for controlling the driving of the special electric accessory solenoid 65, and the like. The output port 4 outputs data signals ("7SEGDATA0" to "7SEGDATA7") for controlling the lighting of the performance display device 206. The data signals output from the output port 4 are input to the source driver 250b.

[0050] Furthermore, the main control board 200 is configured to include a command output port 1 and a command output port 2. The CPU 210 transmits a control command (sub-command) from the command output port 1 to the performance control board 300, and transmits a control command (dispensing command) from the command output port 2 to the dispensing control board 400. Each of the command output ports 1 and 2 has a transmission data register (not shown), a FIFO (First In First Out) buffer (not shown), and a transmission shift register (not shown). The transmission data register outputs the control command input based on the subcommand transmission process (step S2-4) described later to the FIFO buffer. The FIFO buffer is made up of multiple registers and is capable of storing multiple control commands. The FIFO buffer stores the control commands input from the transmission data register and outputs the stored control commands to the transmission shift register in the order in which they were input. The transmission shift register performs parallel-to-serial conversion on the control commands input from the FIFO buffer and transmits them as serial data to the performance control board 300 or the payout control board 400.

[0051] The performance display device 206 is configured to include a plurality of lighting elements (segments). Each lighting element is configured with a light-emitting element (in this embodiment, an LED). Note that the performance display device 206 is arranged on the back side of the game board 11, so that it cannot be seen by the player. As will be described later, the following gaming machine states (hereinafter referred to as "gaming machine states") are defined for the pachinko machine 1: a playable state, a setting change state, a setting check state, a setting abnormal state, a RAM abnormal state, and a backup abnormal state. The information displayed on the performance display device 206 changes depending on the gaming machine state that has occurred.

[0052] The performance display device 206 is configured to include four (four-digit) display units (not shown). Each display unit is made up of eight lighting elements. That is, each display unit is made up of a 7-segment LED capable of displaying numbers, symbols, etc., and a dot-segment LED capable of displaying dots such as decimal points. Specifically, the performance display device 206 is configured to include 32 lighting elements (LED33 to LED64). In the performance display device 206, LED33 to LED40 are the display unit for the first digit, LED41 to LED48 are the display unit for the second digit, LED49 to LED56 are the display unit for the third digit, and LED57 to LED64 are the display unit for the fourth digit.

[0053] During the playable state, the game can proceed. During the playable state, the performance display device 206 displays the base ratio. In this embodiment, while a playable state is occurring, the performance display device 206 alternately displays the first base ratio and the second base ratio every predetermined time (5.0 [s] in this embodiment). The "first base ratio" is the base ratio for the current section (the base ratio calculated for the period from the start of the current section to the present time). The "second base ratio" is the base ratio for the previous section (the final base ratio calculated for the previous section). Specifically, in the performance display device 206, the top two digits of the four-digit display section display information to identify the type of base ratio (first base ratio or second base ratio), and the bottom two digits display a number indicating the base ratio (percentage).

[0054] When the setting change state is occurring, the setting value can be changed. When the setting change state is occurring, the setting value stored (set) in the setting value area of ​​RAM 230 is displayed on the performance display device 206. Specifically, in the performance display device 206, the top three digits of the four-digit display section display information indicating that a setting change state is occurring (specifically, the top one digit displays "r", the second top digit displays "n.", and the third top digit displays "-"), and the bottom digit displays a number indicating the setting value stored in the setting value area. During the setting confirmation state, it becomes possible to check the setting values. During the setting confirmation state, the performance display device 206 displays the setting values ​​stored (set) in the setting value area of ​​the RAM 230. Specifically, in the performance display device 206, the top three digits of the four-digit display section display information indicating that the setting confirmation state is occurring (specifically, the top one digit displays "r", the second digit displays "n.", and the top three digit displays no display), and the bottom digit displays a number indicating the setting value stored in the setting value area.

[0055] During a game stop state (setting abnormal state, RAM abnormal state, or backup abnormal state), game progress becomes impossible. During a game stop state, an error code corresponding to the abnormality that has occurred is displayed on the performance display device 206. Specifically, in the performance display device 206, the top three digits of the four-digit display section display information indicating that a game stop state is occurring (specifically, the top digit displays "E", the second top digit displays "r.", and the top digit displays no display), and the lowest digit displays a number indicating an error code corresponding to the abnormality that has occurred (setting abnormality state, RAM abnormality state, or backup abnormality state).

[0056] The RAM clear switch 207 is a tactile switch. That is, the RAM clear switch 207 includes an operation unit that can be pressed. When the operation unit is pressed, the RAM clear switch 207 outputs a RAM clear signal to the input port 1. The setting key switch 208 is a key lock switch. That is, the setting key switch 208 is configured to include an operation unit with a keyhole. The operation unit is unlocked by inserting a dedicated key into the keyhole, and can be rotated (switched) from the OFF state to the ON state. When the operation unit of the setting key switch 208 is in the ON state, it outputs a detection signal to the input port 1.

[0057] The sink driver 240 controls the output of common signals to each of the display devices 60 and 206 in accordance with the common signals (“COM0” to “COM3”) output from the output port 1. The source driver 250a controls the output of data signals to the main display device 60 in accordance with the data signals (“SEGDATA0” to “SEGDATA7”) output from the output port 0. The source driver 250b controls the output of data signals to the performance display device 206 in accordance with the data signals (“7SEGDATA0” to “7SEGDATA7”) output from the output port 4. The pachinko machine 1 is provided with a source driver 250a corresponding to the main display device 60 and a source driver 250b corresponding to the performance display device 206. The application of the power supply voltage Vcc to the data signal lines is controlled separately for the main display device 60 and the performance display device 206. On the other hand, in the pachinko machine 1, a common sink driver 240 is provided for the main display device 60 and the performance display device 206. The grounding of the common signal line is controlled collectively by the main display device 60 and the performance display device 206. This eliminates the need to provide a sink driver 240 corresponding to each of the main display device 60 and the performance display device 206, and as a result, it eliminates the need to provide an output port (output port for outputting a common signal) corresponding to each of the main display device 60 and the performance display device 206. Therefore, it is possible to reduce the number of components required to control the lighting of the main display device 60 and the performance display device 206, and it is no longer necessary for the main control board 200 (CPU 210) to generate common signals corresponding to each of the main display device 60 and the performance display device 206, making it possible to reduce the control load for controlling the lighting of the main display device 60 and the performance display device 206.

[0058] Furthermore, the main control board 200 is configured to include a test signal output circuit (not shown). In a test signal output process (step S4-24) described later, the CPU 210 generates test information (test signal) indicating the internal state (jackpot game state, execution state of time-saving control, probability state of special symbol lottery, etc.) and stores the generated test signal in a port output request buffer of the RAM 230. As a result, the test signal stored in the port output request buffer is output from a predetermined output port. Then, the test signal output from the predetermined output port is input to an interface board of a test computer (not shown) via a test signal output circuit. In addition, in the main control board 200, detection signals from the special diagram 1 start port switch 101, the special diagram 2 start port switch 102, the gate switch 104, the count switch 103, the right prize port switch 105, the left prize port switch 106, the out switch 109, etc. are input to the input port 204 and are input to the interface board of the test computer via the test signal output circuit. Furthermore, in the main control board 200, control signals for controlling the operation of each solenoid (normal electric role solenoid 64, special electric role solenoid 65, etc.) output from output port 3 are input to each solenoid 64, 65, and are also input to the interface board of the test computer via the test signal output circuit.

[0059] (Configuration of dispensing control board 400) Next, the configuration of the dispensing control board 400 will be described. FIG. 4 is a block diagram showing the configuration of the firing condition detection circuit and the firing control circuit. The payout control board 400 controls the launch of game balls into the game area 30 and the payout of game balls. The dispensing control board 400 is configured to include a one-chip microcomputer. A one-chip microcomputer is an LSI that integrates a CPU core, registers, semiconductor memory, etc. Specifically, a one-chip microcomputer is composed of a CPU, ROM, RAM, etc. The payout control board 400 controls the game ball payout operation (prize ball payout operation) by the game ball payout device 440 based on the control command received from the main control board 200. In addition, the payout control board 400 controls the game ball payout operation (loan ball payout operation) by the game ball payout device 440 based on the ball loan instruction signal received from the CR unit 700. In addition, the payout control board 400 controls the game ball launching operation by the game ball launching device 430 (launch solenoid 431) based on the resistance value (voltage value) input from the launch volume 411, the touch signal input from the touch sensor 412, the launch stop signal input from the launch stop switch 413, the launch permission signal input from the main control board 200, and the CR connection signal input from the CR unit 700. The method of controlling the game ball launching operation by the payout control board 400 will be described in detail below.

[0060] As shown in FIG. 4, the payout control board 400 is configured to include a launch condition detection circuit 420 and a launch control circuit 425 as circuits for controlling the game ball payout operation. The firing condition detection circuit 420 is a circuit that detects whether a firing condition, which will be described later, is met. The firing condition detection circuit 420 includes an operation detection unit 421 , a firing enable condition detection unit 422 , and a firing condition detection unit 423 . The operation detection unit 421 is a circuit that detects the rotation operation (amount of rotation operation) of the handle operation unit. Operation detection unit 421 includes an operational amplifier that controls the output of an operation detection signal in accordance with the resistance value (voltage value) of firing volume 411 (setting the operation detection signal to a high level or a low level). Specifically, in firing handle unit 6, the resistance value of firing volume 411 changes according to the amount of rotation of the handle operation section. Then, operation detection section 421 detects the resistance value (voltage value) of firing volume 411, and detects whether or not the handle operation section is being rotated and the amount of rotation of the handle operation section based on the detected resistance value (voltage value). When the operation detection unit 421 detects a rotation operation of the handle operation unit, it generates an operation detection signal and outputs the generated operation detection signal to the launch enable condition detection unit 422 (sets the operation detection signal to high level). On the other hand, when the operation detection unit 421 does not detect a rotation operation of the handle operation unit, it stops outputting the operation detection signal to the launch enable condition detection unit 422 (sets the operation detection signal to low level). In addition, when the operation detection unit 421 detects a rotational operation of the handle operation unit, it generates a firing intensity signal corresponding to the amount of rotational operation of the handle operation unit (the resistance value of the firing volume 411), and outputs the generated firing intensity signal to the firing control circuit 425.

[0061] The firing enable condition detection unit 422 is a circuit that detects whether a firing enable condition is met. The firing condition detection unit 422 includes an AND gate IC (logic IC) that controls the output / stop of a predetermined signal depending on the result of the logical AND operation of the operation detection signal, the touch signal, and the firing stop signal, and a transistor that switches the output / stop of the handle detection signal depending on the predetermined signal output from the AND gate IC. The "launch enabling condition" is a condition related to the player's operation (player's intention) among the multiple conditions that make up the launch conditions described below. The conditions for enabling firing include (1) a condition based on the detection status of the firing volume 441 and the operation detection unit 421 (detection status of the rotation operation of the handle operation unit), (2) a condition based on the detection status of the touch sensor 412 (detection status of the player's contact with the handle operation unit), and (3) a condition based on the detection status of the firing stop switch 413 (detection status of the operation of pressing the firing stop button). In this embodiment, the firing enable condition is met when all of the following conditions are met: (1) the firing volume 441 and the operation detection unit 421 detect a rotation operation of the handle operation unit, (2) the touch sensor 412 detects contact with the handle operation unit by the player, and (3) the firing stop switch 413 does not detect a press operation of the firing stop button. On the other hand, the firing enable condition is not met when at least one of the conditions (1) to (3) is not met. Here, the conditions for enabling firing include (1) a condition based on the detection status of the firing volume 441 and the operation detection unit 421 (detection status of the rotation operation of the handle operation unit), and (2) a condition based on the detection status of the touch sensor 412 (detection status of the player's contact with the handle operation unit), and (3) a condition based on the detection status of the firing stop switch 413 (detection status of the operation of pressing the firing stop button) may not be included. In other words, the launch condition is met when both of the following conditions are met: (1) the launch volume 441 and the operation detection unit 421 detect the rotation operation of the handle operation unit, and (2) the touch sensor 412 detects the player's contact with the handle operation unit. Alternatively, the launch condition may not be met when at least one of the conditions (1) and (2) is not met.

[0062] Specifically, the launch condition detection unit 422 detects whether the launch condition is met or not based on the operation detection signal input from the operation detection unit 421, the touch signal input from the touch sensor 412, and the launch stop signal input from the launch stop switch 413. At this time, the firing enable condition detection unit 422 detects that the firing enable condition is met when the operation detection signal, touch signal, and firing stop signal are all input. On the other hand, when at least one of the operation detection signal, touch signal, and firing stop signal is not input, the firing enable condition is not detected. When the launchable condition detection unit 422 detects that the launchable condition is met, it generates a handle detection signal and outputs the generated handle detection signal to both the main control board 200 and the launch condition detection unit 423 (sets the handle detection signal to a high level). On the other hand, when the launchable condition detection unit 422 does not detect that the launchable condition is met, it stops outputting the handle detection signal to both the main control board 200 and the launch condition detection unit 423 (sets the handle detection signal to a low level).

[0063] The firing condition detection unit 423 is a circuit that detects whether the firing condition is met. The firing condition detection unit 423 includes an AND gate IC (logic IC) that controls the output / stop of the firing signal according to the result of logical AND calculation of the handle detection signal, the firing permission signal, and the CR connection signal. The "launch condition" is a condition for executing the launch of a game ball (game ball launching operation) into the game area 30 by the game ball launching device 430 (launch solenoid 431). In this embodiment, the launch condition is met when all of the following conditions are met: (1) the launch enable condition is met, (2) a launch permission signal is input from the main control board 200, and (3) a CR connection signal is input from the CR unit 700. On the other hand, the launch condition is not met when at least one of the conditions (1) to (3) is not met. The "launch permission signal" is output from the main control board 200 to the launch condition detection unit 423 when a playable state is set, assuming that communication is possible between the main control board 200 and the payout control board 400 (the main control board 200 and the payout control board 400 are electrically connected). Here, while the main control board 200 is powered on, regardless of the state of the gaming machine, a launch permission signal may be output from the main control board 200 to the launch condition detection unit 423. In other words, when communication is possible between the main control board 200 and the payout control board 400 (when the main control board 200 and the payout control board 400 are electrically connected), a launch permission signal may be output from the main control board 200 to the launch condition detection unit 423. The "CR connection signal" is output from the CR unit 700 to the firing condition detection unit 423 when communication is possible between the CR unit 700 and the dispensing control board 400 (when the CR unit 700 and the dispensing control board 400 are electrically connected).

[0064] Specifically, the launch condition detection unit 423 detects whether the launch conditions are met based on the handle detection signal input from the launch enable condition detection unit 422, the launch permission signal input from the main control board 200, and the CR connection signal input from the CR unit 700. At this time, the firing condition detection unit 423 detects that the firing condition is met when all of the handle detection signal, the firing permission signal, and the CR connection signal are input. On the other hand, when at least one signal among the handle detection signal, the firing permission signal, and the CR connection signal is not input, the firing condition detection unit 423 does not detect that the firing condition is met. When the firing condition detection unit 423 detects that the firing condition is met, it generates a firing signal and outputs the generated firing signal to the firing control circuit 425 (sets the firing signal to a high level). On the other hand, when the firing condition detection unit 423 does not detect that the firing condition is met, it stops outputting the firing signal to the firing control circuit 425 (sets the firing signal to a low level).

[0065] The launch control circuit 425 is a circuit that controls the launch strength of the game balls by the game ball launcher 430 and the launch timing of the game balls by the game ball launcher 430. In other words, the launch control circuit 425 controls the output of a drive signal to the game ball launcher 430 (launch solenoid 431). Specifically, the firing control circuit 425 includes a clock generating unit (not shown), a firing timing control unit (not shown), and a firing solenoid driving unit (not shown). The clock generating section outputs a clock signal of a predetermined frequency to the emission timing control section. The firing timing control unit generates a pulse signal for controlling the firing timing based on the clock signal input from the clock generating unit, and outputs the generated pulse signal to the firing solenoid driving unit. At this time, the firing timing control unit generates the pulse signal so that the number of game balls fired per minute is a predetermined number (for example, 100 balls). The firing solenoid drive unit controls the output of a drive signal to the firing solenoid 431 based on a firing signal input from the firing condition detection unit 423, a pulse signal input from the firing timing control unit, and a firing intensity signal input from the operation detection unit 421. Specifically, when a launch signal is input from the launch condition detection unit 423, the launch solenoid drive unit, in response to input of a pulse signal from the launch timing control unit, outputs a drive signal (drive current) corresponding to the launch intensity signal input from the operation detection unit 421 to the launch solenoid 431. This causes the gaming ball to be launched at an intensity corresponding to the launch intensity signal input from the operation detection unit 421. On the other hand, when the launch signal is not input from the launch condition detection unit 423, the launch solenoid drive unit stops outputting the drive signal to the launch solenoid 431. This stops the launch of the game balls.

[0066] The game ball launcher 430 includes a battering hammer (not shown) and a launch solenoid 431 that drives the battering hammer. The launch solenoid 431 is a rotary solenoid. However, the battering hammer may be driven by another drive source such as a motor. A game ball is supplied to the game ball launcher 430 from a ball feeding unit (not shown). When a drive signal is input to the launch solenoid 431, the launch solenoid 431 is driven in response to the input drive signal, and the game ball is launched by the hitting hammer. This launches the game ball into the game area 30.

[0067] As described above, in the pachinko machine 1, assuming that a playable state is set in the main control board 200 and that communication is possible between the CR unit 700 and the payout control board 400, when the handle operation unit is rotated (displaced from the initial position toward the limit position) by contact with the player without the release stop button being pressed, the game ball release operation by the game ball release device 430 is started. Then, while the game ball release operation by the game ball release device 430 is being executed, game balls are released into the game area 30 with a strength according to the amount of rotation of the handle operation unit. Furthermore, when the launch stop button is pressed, the game ball launching operation by the game ball launcher 430 is stopped. That is, even if the handle operation unit is being rotated by contact with the player, when the launch stop button is pressed, the game ball launching operation by the game ball launcher 430 is stopped. Furthermore, when the handle operation unit is returned to the initial position (when the handle operation unit is not being rotated), the game ball launching operation by the game ball launcher 430 is stopped. In other words, even if the player is in contact with the handle operation unit, when the handle operation unit is returned to the initial position, the game ball launching operation by the game ball launcher 430 is stopped.

[0068] In particular, in the pachinko machine 1, the output of the handle detection signal from the launch enabling condition detection unit 422 to the main control board 200 is maintained while a state in which the launch enabling condition is satisfied (hereinafter referred to as the "launch enabling state") occurs. In other words, while a state occurs in which rotation of the handle operating unit is detected, contact with the handle operating unit is detected, and pressing of the fire stop button is not detected (a state in which firing is possible), the output of a handle detection signal from the firing condition detection circuit 420 to the main control board 200 is maintained. In this case, as long as the launch-enabled state is occurring, the output of the handle detection signal from the launch condition detection circuit 420 to the main control board 200 is maintained regardless of whether a launch permission signal is input from the main control board 200 to the launch condition detection circuit 420 (regardless of the gaming machine state set in the main control board 200). Furthermore, as long as the firing state is occurring, the output of a handle detection signal from the firing condition detection circuit 420 to the main control board 200 is maintained regardless of whether a CR connection signal is input from the CR unit 700 to the firing condition detection circuit 420 (regardless of whether communication is possible between the CR unit 700 and the dispensing control board 400). As a result of the above, the main control board 200 is able to detect (understand) whether or not a launchable state is occurring, and it becomes possible to control the progress of the game, the content of the presentation, etc. depending on the occurrence status of the launchable state.

[0069] In other words, when the main control board 200 detects that the handle detection signal has changed from a state where it is not being input to a state where it is being input (the handle detection signal has changed from a low level to a high level), it transmits a game status designation command to the performance control board 300 that specifies the occurrence (start) of a launch-ready state. On the other hand, when the main control board 200 detects that the handle detection signal has changed from an input state to an input state (the handle detection signal has changed from a high level to a low level), it sends a game status designation command to the performance control board 300, which designates the release (end) of the launch-ready state. This enables the performance control board 300 to detect the occurrence of a launch-ready state by receiving a game status designation command that specifies the occurrence of a launch-ready state, and to detect the cancellation of the launch-ready state by receiving a game status designation command that specifies the cancellation of the launch-ready state. The performance control board 300 can then change the performance content depending on whether or not a firing state is occurring.

[0070] (Configuration of performance control board 300) Next, the configuration of the performance control board 300 will be described. Fig. 5 is a block diagram showing the configuration of the performance control board. Fig. 51 is a block diagram showing the configuration of the sound circuit. The performance control board 300 controls the performances (display performances, sound performances, lamp performances, movable body performances, etc.) based on the control commands received from the main control board 200. As shown in FIG. 5, the performance control board 300 is configured to include a microcomputer (one-chip microcomputer) 301 and various external devices externally connected to the microcomputer 301. In this embodiment, various external devices include a control ROM 302, a character generator read only memory (CGROM) 303, a dynamic random access memory (DRAM) 304, a digital amplifier 305, and the like.

[0071] (Control ROM 302) The control ROM 302 stores a control program for controlling the operation of the microcomputer 301, various data required for executing the control program, various command lists set in the control register of the sound circuit 323, various operation parameters (such as frequency correction parameters) sent to the digital amplifier 305, etc. In particular, the control ROM 302 stores (memorizes) performance scenario data corresponding to each performance number, an animation table corresponding to each display performance number, a command list corresponding to each sound performance control number, various compressed lamp drive data, and various compressed motor drive data. The "compressed lamp drive data" is lamp drive data compressed (encoded) in a predetermined format. The "lamp drive data" is data for driving the various lamps 20, 21 (data specifying the brightness values ​​of the lamps 20, 21 belonging to each system). "Compressed motor drive data" is data obtained by compressing (encoding) motor drive data in a predetermined format. "Motor drive data" is data for driving various motors 23 (data that specifies the output value of each motor 23). In this embodiment, a NOR flash memory (NOR ROM) is used as the control ROM 302. However, the control ROM 302 may be configured to use an EEPROM (Electrically Erasable Programmable Read Only Memory). The control ROM 302 is connected to a host interface 313 of the microcomputer 301 .

[0072] (CGROM303) The CGROM 303 stores various types of compressed image data, various types of compressed audio data, and the like. "Compressed image data" is data that has been compressed (encoded) using a specific format. "Image data (material data)" is image (moving image / still image) data that is used as the material for drawing processing. The "compressed audio data" is audio data that has been compressed (encoded) in a predetermined format. The "audio data" is audio data output from the various speakers 22. In this embodiment, a NAND flash memory (NAND ROM) is used as the CGROM 303. Specifically, the CGROM 303 is configured by an SSD (Solid State Drive) that uses a NAND flash memory as a storage unit. The CGROM 303 is connected to a CG bus interface 314 of the microcomputer 301. The CG bus interface 314 is a connection interface conforming to the SATA (Serial AT Attachment) standard, and various data stored in the CGROM 303 is read and transferred via SATA.

[0073] (DRAM304) A preload area is provided in the DRAM 304. Various data (specifically, compressed image data, compressed audio data, etc.) stored in the CGROM 303 is transferred (preloaded) to the preload area. A drawing command buffer area is also provided in the DRAM 304. In this embodiment, a double buffering method is adopted for the drawing command buffer area, and the DRAM 304 is provided with two drawing command buffer areas. The two drawing command buffer areas are configured to be the same size. While one of the two drawing command buffer areas is designated as a construction area, the other drawing command buffer area is designated as a transfer area. Furthermore, for each drawing command buffer area, its designation as a construction area and its designation as a transfer area are alternated every frame. Then, for each drawing command buffer area, a display list (described later) is stored (generated and constructed) in that drawing command buffer area during the period specified in the construction area, and the display list stored in that drawing command buffer area is transferred to the VDP (specifically, the preloader circuit 319) during the period specified in the transfer area. The DRAM 304 is connected to a DRAM interface 315 of the microcomputer 301 .

[0074] (Microcomputer 301) The microcomputer 301 is an LSI in which a CPU core, a register, a semiconductor memory, and the like are integrated. The microcomputer 301 controls the performance actions of various performance means based on the control commands received from the main control board 200. The "various production means" include various image display devices 31, 32, various speakers 22, various lamps 20, 21, and various motors 23 (various movable bodies). Therefore, the "production actions by various production means" include the display of production images by the various image display devices 31, 32, the output of sound by the various speakers 22, the driving (lighting) of the various lamps 20, 21, the driving of the various motors 23 (various movable bodies), etc. The microcomputer 301 includes internal devices such as a CPU 310, a CPU work memory 311, a CPU interface 312, a host interface 313, a CG bus interface 314, a DRAM interface 315, a VRAM 316, a serial communication controller 317, a transfer circuit 318, a preloader circuit 319, a display circuit 320, a graphics decoder circuit 321, a drawing circuit 322, and a sound circuit 323, and these internal devices are connected to a data bus 324.

[0075] (CPU310) The CPU 310 is connected to a host interface 313 via a CPU interface 312. The host interface 313 is also connected to the main control board 200, and receives control commands from the main control board 200. The host interface 313 is also connected to a data bus 324. This allows the CPU 310 to receive control commands (sub-commands) from the main control board 200 via the HOST interface 313. Furthermore, the CPU 310 is capable of communicating with internal devices such as a serial communication controller 317 , a preloader circuit 319 , a display circuit 320 , and a sound circuit 323 via a host interface 313 and a data bus 324 . Furthermore, the CPU 310 is capable of reading out various data (control programs, control data, etc.) stored in the control ROM 302 via a host interface 313. The CPU 310 is also capable of reading out various data (compressed audio data) stored in the CGROM 303 via the HOST interface 313 , the data bus 324 , and the CG bus interface 314 . Furthermore, the CPU 310 is capable of reading and writing data from and to the DRAM 304 via a host interface 313 , a data bus 324 , and a DRAM interface 315 .

[0076] The CPU 310 executes various arithmetic processes required to control the performance actions of various performance means, control processes for internal devices in accordance with the various arithmetic processes, and the like. At this time, the CPU 310 uses the CPU work memory (RAM) 311 and the DRAM 304 as a work area for various arithmetic processing, a buffer area for various arithmetic processing data, a table data area, a buffer area for various input / output data, and the like. That is, the CPU 310 selects the effect (effect number) to be executed based on the control command received from the main control board 200, and selects and sets the effect scenario data corresponding to the selected effect number. Also, in accordance with the selected and set effect scenario data, it generates command information (internal commands) for sequentially controlling various internal devices (VDP, sound circuit 323, lamp controller 317a, motor controller 317b, etc.).

[0077] Specifically, the CPU 310 sets an animation table in the animation table setting area in accordance with the command information, and then generates a display list in the drawing command buffer area specified in the construction area in accordance with the set animation table. A "display list" is a collection of drawing commands for one frame. That is, a group of drawing commands for one frame is written in a predetermined order in the display list. Then, in the VDP, drawing data for one frame is generated by executing processing based on each drawing command in the order written in the display list. A "drawing command" is information that specifies the content of the drawing process (drawing control) to be executed by the VDP. In particular, the drawing command specifies the address of the memory area where the compressed image data used for drawing is stored (hereinafter referred to as "image address"), the magnification (enlargement / reduction rate) at which the image data is drawn, the coordinates at which the image data is drawn (coordinates in the frame buffer area), and the transparency (transparency / transparency) at which the image data is drawn.

[0078] Furthermore, the CPU 310 transfers (preloads) the compressed audio data stored in the CGROM 303 to the preload area of ​​the DRAM 304 when the power is turned on. That is, while NAND flash memories such as the CGROM 303 can be easily made larger in capacity than NOR flash memories such as the control ROM 302, they have a slower data read speed. For this reason, if compressed audio data is read directly from the CGROM 303 (NAND flash memory) when the sound circuit 323 executes audio output processing, there is a risk that processing performance will be significantly reduced. Therefore, in the pachinko machine 1, before the sound output process is executed, the compressed sound data stored in the CGROM 303 is transferred in advance to the DRAM 304, which is a storage means having a faster data read speed than the CGROM 303. Then, when the sound output process is executed, the compressed sound data is read from the DRAM 304, thereby preventing a decrease in processing performance.

[0079] Specifically, when power is turned on, the CPU 310 transfers (preloads) predetermined compressed audio data from among the compressed audio data stored in the CGROM 303 to a preload area of ​​the DRAM 304. At this time, in this embodiment, all of the compressed audio data stored in the CGROM 303 is transferred to the preload area of ​​the DRAM 304. Here, a configuration may be adopted in which only a portion of the compressed audio data stored in the CGROM 303 is transferred to the preload area of ​​the DRAM 304. Then, in the pachinko machine 1, after the transfer of the above-mentioned predetermined compressed audio data is completed, it becomes possible to control the output of audio from the various speakers 22 (audio output processing by the sound circuit 323). In other words, before the transfer of the above-mentioned predetermined compressed audio data is completed, it becomes impossible to control the output of audio from the various speakers 22 (audio output processing by the sound circuit 323). Furthermore, after the transfer of the above-mentioned predetermined compressed audio data is completed, it becomes possible to control the display of the effect image (drawing process by VDP) by the various image display devices 31, 32. In other words, before the transfer of the above-mentioned predetermined compressed audio data is completed, it becomes impossible to control the display of the effect image by the various image display devices 31, 32 (drawing process by VDP). On the other hand, before the transfer of the predetermined compressed audio data is completed, it becomes possible to control the driving (light emission) of the various lamps 20, 21 (lamp driving process by the lamp controller 317a). Furthermore, before the transfer of the predetermined compressed audio data is completed, it becomes possible to execute control of the drive of the various motors 23 (various movable bodies) (motor drive processing by the motor controller 317b).

[0080] (Transfer circuit 318) The transfer circuit 318 transfers various types of data between internal devices. Specifically, the transfer circuit 318 transfers the display list stored in the drawing command buffer area designated as the transfer area to the preloader circuit 319. In addition, the transfer circuit 318 transfers the display list rewritten by the preloader circuit 319 to the drawing circuit 322.

[0081] (VRAM316) An image development area is provided in the VRAM 316. Image data (material data) developed (restored and decoded) by the graphics decoder circuit 321 is temporarily stored in the image development area. A frame buffer area is also provided in the VRAM 316. In this embodiment, a double buffering method is adopted for the frame buffer area, and two frame buffer areas are provided in the VRAM 316. The two frame buffer areas are the same size. While one of the two frame buffer areas is designated as the drawing area, the other frame buffer area is designated as the output area. Furthermore, for each frame buffer area, the designation as the drawing area and the output area are alternated every frame. Then, for each frame buffer area, one frame's worth of drawing data is stored (generated and drawn) in that frame buffer area during the period specified as the drawing area, and a video signal is output based on one frame's worth of drawing data stored in that frame buffer area during the period specified as the output area.

[0082] (VDP) In the microcomputer 301, a preloader circuit 319, a display circuit 320, a graphics decoder circuit 321, a drawing circuit 322, etc. function as a VDP (Video Display Processor). The VDP controls the display of effect images by the various image display devices 31, 32. Specifically, the VDP generates drawing data in response to receiving a display list (drawing commands) from the CPU 310, generates a video signal based on the generated drawing data, and outputs the generated video signal to the various image display devices 31, 32. The preloader circuit 319 is capable of reading out various data (compressed image data) stored in the CGROM 303 via the CG bus interface 314. In particular, the preloader circuit 319 transfers (preloads) compressed image data stored in the CGROM 303 to a preload area of ​​the DRAM 304 before the rendering circuit 322 performs rendering processing. That is, as described above, NAND flash memories such as CGROM 303 can be easily made larger in capacity than NOR flash memories such as control ROM 302, but their data read speed is slower. For this reason, if compressed image data is read directly from CGROM 303 (NAND flash memory) when the rendering circuit 322 executes rendering processing, there is a risk that processing performance will be significantly reduced. Therefore, in the pachinko machine 1, before the drawing process is executed, the compressed image data stored in the CGROM 303 is transferred in advance to the DRAM 304, which is a storage means having a faster data read speed than the CGROM 303. Then, when the drawing process is executed, the compressed image data is read from the DRAM 304, thereby preventing a decrease in processing performance.

[0083] Specifically, every time the preloader circuit 319 receives a display list, it transfers (preloads) compressed image data for one frame specified in the display list from the compressed image data stored in the CGROM 303 to a preload area in the DRAM 304. At this time, the preloader circuit 319 rewrites the display list. That is, in the display list generated by the CPU 310, an address specifying a storage area in the CGROM 303 is written as the image address included in each drawing command. Therefore, for each drawing command included in the display list, the preloader circuit 319 transfers the compressed image data stored in the storage area (storage area in the CGROM 303) specified by the image address included in the drawing command to a predetermined area in the DRAM 304, and then rewrites the image address included in the drawing command to an address specifying the storage area after transfer (the predetermined area in the DRAM 304). In this way, a new display list with the rewritten image address is generated. In this embodiment, the preloader circuit 319 is configured to transfer (preload) the compressed image data stored in the CGROM 303 to a preload area of ​​the DRAM 304. However, the preloader circuit 319 may be configured to transfer the compressed image data stored in the CGROM 303 to a predetermined area (preload area) of the VRAM 316. The display list rewritten by the preloader circuit 319 is transferred to the drawing circuit 320 by the transfer circuit 318 .

[0084] The drawing circuit 322 stores (generates and draws) one frame's worth of drawing data in the frame buffer area designated as the drawing area in accordance with the display list received from the preloader circuit 319. Specifically, each time the rendering circuit 320 receives a display list, it reads out one frame of compressed image data specified in the display list from the DRAM 304. The one frame of compressed image data read out from the DRAM 304 is restored (decoded) by the graphics decoder circuit 321 and stored (rendered) in an image rendering area of ​​the VRAM 316. Then, the rendering circuit 320 uses the image data stored in the image rendering area to generate one frame of rendering data in the frame buffer area specified as the rendering area.

[0085] The display circuit 320 generates a video signal based on one frame of drawing data stored (generated and drawn) in a frame buffer area designated as an output area, and outputs the generated video signal to various image display devices 31, 32. In this embodiment, a digital RGB signal is output as the video signal. However, a configuration may also be adopted in which an LVDS (Low Voltage Differential Signaling) signal is output as the video signal. Specifically, the display circuit 320 is configured to include a data acquisition circuit (not shown), a scaler circuit (not shown), a color correction circuit (not shown), a ditherer circuit (not shown), a synchronization signal generation circuit (not shown), etc. The data acquisition circuit reads out the drawing data stored in the frame buffer area designated as the output area. The scaler circuit is capable of performing scaling (enlarging and reducing) on ​​the drawing data read out by the data acquisition circuit. The color correction circuit is capable of performing color correction processing on the drawing data after processing by the scaler circuit. The ditherer circuit is capable of performing dithering processing on the drawing data after processing by the color correction circuit. The drawing data processed by the dithering circuit is then output as a video signal (digital RGB signal). The synchronization signal generation circuit generates a horizontal synchronization signal and a vertical synchronization signal (Vsync). The synchronization signal generation circuit then outputs the generated horizontal synchronization signal and vertical synchronization signal to the various image display devices 31 and 32. The synchronization signal generation circuit also outputs the generated vertical synchronization signal to the CPU 310. In this embodiment, the display of the effect image (the display of the effect image based on one frame of drawing data) on each of the image display devices 31, 32 is updated every 16.66 [ms]. Therefore, the synchronization signal generation circuit outputs a vertical synchronization signal (set to high level) to the CPU 310 every 16.66 [ms].

[0086] (Sound Circuit 323) The sound circuit 323 (built-in sound source) controls the output (reproduction) of sounds (effect sounds) from the various speakers 22. As shown in FIG. 51, the sound circuit 323 is configured to include 40 tracks (track 1 to track 40), 8 audio buses (audio bus 1 to audio bus 8), 8 channels (channel 1 to channel 8), and a control register (not shown). In this embodiment, the various speakers 22 include an upper left speaker, an upper right speaker, a center left speaker, a center right speaker, a lower speaker, and a woofer. Each channel is electrically connected to one speaker via a digital amplifier 305. Specifically, the upper left speaker is connected to channel 1, the upper right speaker is connected to channel 2, the center left speaker is connected to channel 3, the center right speaker is connected to channel 4, the bottom speaker is connected to channel 5, and a woofer is connected to channel 6. On the other hand, no speakers are connected to channels 7 and 8. Here, the upper left speaker, upper right speaker, center left speaker, and center right speaker are configured as high- and mid-range speakers (full-range speakers). On the other hand, the lower speaker and woofer are configured as low-range speakers. Compared to the lower speaker, the woofer has a lower output frequency band (its frequency characteristics are in a low frequency band) and a larger output (W). The sound circuit 323 is equipped with an independent sequencer (not shown) for each track, which makes it possible to control the playback, stop, volume, etc. of audio data independently for each track. Each track is provided with a compressed audio decoder 351, a track volume control unit 352, a programmable pan 353, and the like. The compressed audio decoder 351 restores (decodes) compressed audio data. The track volume control unit 352 sets the volume of the track. The programmable pan 353 controls the positioning of the sound by outputting the audio data of the track to any audio bus.

[0087] The eight audio buses are provided with a switcher 354, a ducking control section 355, a channel router 356, and the like. The switcher 354 allocates audio data from eight audio buses and audio data from eight external serial inputs (not shown) to the eight audio buses. In this embodiment, the eight external serial inputs are unused. The ducking control unit 355 ducks (reduces) the volume of the other audio buses based on the volume of audio data input from a specific audio bus among the eight audio buses. The channel router 356 sets the association between each audio bus (audio bus 1 to audio bus 8) and each channel (channel 1 to channel 8).

[0088] In this embodiment, the channel router 356 connects audio bus 1 and channel 1. In addition, the audio signal generated by channel 1 is input to the upper left speaker. As a result, audio based on the audio data assigned to audio bus 1 is output from the upper left speaker. Additionally, the channel router 356 connects audio bus 2 to channel 2. Additionally, the audio signal generated by channel 2 is input to the top right speaker. As a result, audio based on the audio data assigned to audio bus 2 is output from the top right speaker. Additionally, the channel router 356 connects the audio bus 3 to the channel 3. The audio signal generated by the channel 3 is input to the left center speaker. As a result, audio based on the audio data assigned to the audio bus 3 is output from the left center speaker. Additionally, audio bus 4 and channel 4 are linked by channel router 356. Furthermore, the audio signal generated by channel 4 is input to the center right speaker. As a result, audio based on the audio data assigned to audio bus 4 is output from the center right speaker. Additionally, the channel router 356 connects the audio bus 5 to the channel 5. Furthermore, the audio signal generated by the channel 5 is input to the lower speaker. As a result, audio based on the audio data assigned to the audio bus 5 is output from the lower speaker. Additionally, the channel router 356 connects the audio bus 6 to the channel 6. Additionally, the audio signal generated by the channel 6 is input to the woofer. As a result, audio based on the audio data assigned to the audio bus 6 is output by the woofer. Furthermore, the channel router 356 connects the audio bus 7 to the channel 6. As a result, the sound based on the audio data assigned to the audio bus 7 is output by the woofer. On the other hand, audio bus 8 is not connected to any channel by channel router 356. As described above, in this embodiment, channels 7 and 8 are unused and no audio data is input to them.

[0089] The eight channels are configured to include a channel volume control section 357, an equalizer 358, a limiter 359, a post-effector 360, an overall volume control section 361, an audio serial output 362, and the like. The channel volume control unit 357 sets the volume for each channel. The equalizer 358 sets the emphasis or attenuation of a specific frequency band for each channel (corrects the frequency). The limiter 359 prevents clipping for each channel by compressing sounds that exceed a threshold. The post-effector 360 sets the emphasis or attenuation of a specific frequency band, volume, sound generation timing delay, etc. for each channel. The overall volume control unit 361 sets the volume for all channels collectively. The audio serial output 362 converts the audio data for each channel so that it can be transmitted serially to the digital amplifier 305.

[0090] In accordance with the instruction information, the CPU 310 sets the command list read from the control ROM 302 in the control register of the sound circuit 323. As a result, the sound circuit 323 operates in accordance with the command list set in the control register. The "command list" is information that specifies the operation of the sound circuit 323. As described above, a command list corresponding to each sound effect control number is stored. In this embodiment, the command list includes a command list that specifies the start of a sound effect, a command list that specifies the end of a sound effect, and the like. The command list that specifies the start of sound performance includes information that specifies the compressed audio data to start playing, information that specifies the track to which the compressed audio data is assigned, information that specifies the number of times the compressed audio data is played, information that specifies the volume of the compressed audio data (audio data), information that specifies the panpot ratio of the compressed audio data (audio data), information that specifies the preset data (preset number) to be set on the track (the compressed audio data), etc. Preset data will be described later. The "panpot ratio" is information that specifies the audio bus (audio bus 1 to audio bus 8) to which audio data is assigned. In other words, the panpot ratio is information that specifies the volume of each audio bus when assigning audio data to each audio bus. In this embodiment, the panpot ratio specifies the volume balance of the eight audio buses (audio bus 1 to audio bus 8). Specifically, the panpot ratio specifies the volume ratio of audio bus 1 to audio bus 8. On the other hand, the command list specifying the end of the sound performance includes information specifying the track at which playback is to be stopped. As described above, in this embodiment, playback, stopping, volume adjustment, etc. of audio data are controlled for each track.

[0091] (Serial communication controller 317) The serial communication controller 317 includes a lamp controller 317a and a motor controller 317b. The lamp controller 317a controls the driving (light emission) of the various lamps 20 and 21. Specifically, the CPU 310 sets the LED register according to command information (messages) set in a lamp command buffer area (described later). The lamp controller 317a then generates lamp drive data according to the settings of the LED register, and outputs the generated lamp drive data together with a clock signal to the lamp drivers 332 and 342. At this time, the lamp drive data is output as serial data. The lamp controller 317a is configured to include a lamp decoder circuit (not shown). The lamp decoder circuit reads compressed lamp drive data specified by command information from the control ROM 302. It also restores (decodes and decodes) the read compressed lamp drive data. Then, it generates lamp drive data based on the restored lamp drive data and outputs the generated lamp drive data to the lamp drivers 332 and 342.

[0092] The motor controller 317b controls the driving of the various motors 23 (various movable bodies). Specifically, CPU 310 sets the motor register according to command information (messages) set in a movable body command buffer area (described later). Then, motor controller 317b generates motor drive data according to the settings of the motor register, and outputs the generated motor drive data together with a clock signal to motor drivers 333 and 343. At this time, the motor drive data is output as serial data. The motor controller 317b is configured to include a motor sequencer circuit (not shown). The motor sequencer circuit reads compressed motor drive data specified by the command information from the control ROM 302. It also restores (decodes and decodes) the read compressed motor drive data. It then generates motor drive data based on the restored motor drive data and outputs the generated motor drive data to the motor drivers 333 and 343. In addition, information indicating the detection status of the various sensors 24 is input to the motor controller 317b from the driver board 330, and information indicating the detection status of each switch 25 to 29 and information indicating the detection status of the various sensors 24 are input from the sub-connection board 340.

[0093] (About the track ducking function) Next, the track ducking function will be described. Fig. 52 is a diagram showing volume peak value information corresponding to audio data A. Fig. 53 is a diagram explaining the track ducking function. The track volume control section 352 is capable of realizing a track ducking function (software ducking). The "track ducking function" adjusts (specifically, decreases or lowers) the volume of audio data assigned to one track (hereinafter referred to as the "trigger track") based on the volume of audio data assigned to other tracks (hereinafter referred to as the "ducking track"). The track ducking function can be set for each track (trigger track). In particular, the track ducking function makes it possible to individually adjust the volume of audio data assigned to each ducking track based on the volume of audio data assigned to one trigger track. In the following description, audio data assigned to the trigger track will be referred to as "trigger audio data," and audio data assigned to the ducking track will be referred to as "ducking audio data." The "trigger audio data" is audio data that triggers ducking. In other words, the trigger audio data is audio data that triggers a decrease in the volume of the ducking audio data. The "ducking audio data" is audio data that is the target of ducking. In other words, the ducking audio data is audio data whose volume is reduced by ducking. "Ducking" is the process of adjusting (reducing, lowering, or lowering) the volume.

[0094] As described above, the command list that specifies the start of sound performance includes information that specifies the compressed audio data to start playing, information that specifies the track to which the compressed audio data is to be assigned, a preset number that specifies the preset data to be set on the track (the compressed audio data), etc. The control ROM 302 stores preset data corresponding to each preset number. The "preset data" is data for controlling the volume. In particular, the preset data is data that specifies the content of the track ducking function that the track volume control unit 352 executes. Specifically, the preset data includes volume peak value information corresponding to the compressed audio data (audio data) assigned to the track, information specifying whether to activate or deactivate the track ducking function using the track as the trigger track (whether to activate the track ducking function), information specifying the ducking track in the track ducking function using the track as the trigger track, track ducker parameters corresponding to each ducking track, etc.

[0095] The "volume peak value information" is information indicating the peak volume value for each predetermined unit time of compressed audio data (audio data) assigned to the track. In other words, the volume peak value information is information that divides the entire compressed audio data (audio data) (from the beginning to the end) into predetermined unit time segments and summarizes the peak volume values ​​for each predetermined unit time for the entire compressed audio data (audio data). The volume peak value information is generated in advance by sampling the compressed audio data (audio data). In this embodiment, volume peak value information corresponding to each audio data is stored for all audio data. In this embodiment, the predetermined unit time is one frame (16.6 ms). That is, the volume peak value information indicates the peak volume value of the compressed audio data (the audio data) for each frame (16.6 ms). For example, as shown in FIG. 52, the volume peak value information corresponding to audio data A specifies 120 [db] as the peak volume value for the first frame (the period from the start of the audio data until one frame (16.6 [ms]) has elapsed), 123 [db] as the peak volume value for the second frame (the period from the end of the first frame until one frame (16.6 [ms]) has elapsed), 125 [db] as the peak volume value for the third frame (the period from the end of the second frame until one frame (16.6 [ms]) has elapsed), and 46 [db] as the peak volume value for the 801st frame (the period from the end of the 800th frame until one frame (16.6 [ms]) has elapsed).

[0096] The "track ducker parameters" include a minimum threshold, a minimum ducking amount, a maximum threshold, a maximum ducking amount, the number of fade-in frames, the number of fade-out frames, and the like. The "minimum threshold" is the threshold value of the volume of the trigger audio data at which ducking of the ducking audio data begins. In other words, when the volume of the trigger audio data reaches (or exceeds) the minimum threshold, ducking is executed (starts) for the ducking audio data. The "minimum ducking amount" is the ducking amount (the rate at which the volume is reduced) of the ducking audio data when the volume of the trigger audio data reaches the minimum threshold. The "maximum threshold" is the threshold value for the volume of the trigger audio data at which the amount of ducking of the ducking audio data reaches its maximum (upper limit). In other words, when the volume of the trigger audio data reaches (or exceeds) the maximum threshold, the amount of ducking of the ducking audio data reaches its maximum (upper limit), and the amount of ducking does not increase any further. The "maximum ducking amount" is the amount of ducking (the rate at which the volume is reduced) of the ducking audio data when the volume of the trigger audio data reaches the maximum threshold. The "number of fade-in frames" is the time (number of frames) from when the volume of the trigger audio data reaches the minimum threshold until the ducking amount of the ducking audio data reaches the target ducking amount (for example, the minimum ducking amount). The "fade-out frame count" is the time (number of frames) from when the volume of the trigger audio data falls below the minimum threshold until the volume of the ducking audio data returns to its original volume (the volume when ducking is not being performed).

[0097] As described above, the command list that specifies the start of sound performance includes information that specifies the audio data to start playing, information that specifies the track to which the audio data is to be assigned, information that specifies the number of times the audio data is to be played, information that specifies the volume of the audio data, information that specifies the panpot ratio of the audio data, and a preset number that specifies the preset data to be set on the track. Then, in accordance with the instruction information, the CPU 310 sets the command list read from the control ROM 302 in the control register of the sound circuit 323. As a result, the sound circuit 323 operates in accordance with the command list set in the control register. At this time, if the preset data corresponding to the preset number specified by the command list has the track ducking function set to operate, the track ducking function is set for the track to which the audio data specified by that command list is assigned. At this time, the track to which the audio data specified by that command list is assigned becomes the trigger track. In other words, the audio data specified by that command list becomes trigger audio data. Then, ducking is performed on the audio data (ducking audio data) assigned to the ducking track specified by that preset data. In particular, in this embodiment, it is possible to specify multiple ducking tracks in the preset data and perform ducking of the audio data (ducking audio data) assigned to each ducking track. At this time, it is possible to specify (set) track ducker parameters individually for the multiple ducking tracks in the preset data. This makes it possible to perform detailed ducking control for each ducking track (ducking audio data).

[0098] When the track ducking function is set, ducking is controlled according to the contents of the preset data. That is, when the track ducking function is set, the volume of the trigger audio data is monitored during playback of the trigger audio data in the trigger track, and the volume of each ducking audio data is adjusted (ducked) according to the volume of the trigger audio data. At this time, in this embodiment, the volume of each ducking audio data is adjusted (ducked) based on the volume peak value information corresponding to the trigger audio data. Specifically, the CPU 310 executes the track ducking process for each predetermined unit time (in this embodiment, 1 frame = 16.6 [ms]). In each track ducking process, first, the peak volume value (hereinafter referred to as the "trigger peak value") corresponding to the current frame (the time elapsed since playback of the trigger audio data started) is obtained based on the volume peak value information corresponding to the trigger audio data. Next, for each ducking track (each ducking audio data), the amount of ducking (the rate at which the volume is reduced) is calculated based on the track ducker parameter corresponding to the ducking track and the obtained trigger peak value. Then, for each ducking track (each ducking audio data), the volume is adjusted according to the calculated amount of ducking. This completes each track ducking process. In this manner, in this embodiment, the ducking amount is calculated for each predetermined unit time, and the volume of the ducking audio data is adjusted (ducked) according to the calculated ducking amount. This enables fine ducking control for each predetermined unit time. At this time, volume peak value information indicating the peak value of the volume for each predetermined unit time is stored for the trigger audio data, and ducking control is performed based on this volume peak value information. This makes it possible to simplify the process for performing ducking.

[0099] Here, the track volume control unit 352 is configured to include a first track volume (not shown), a second track volume (not shown), a first track attenuator (not shown), and a second track attenuator (not shown). The first track volume, the second track volume, the first track attenuator, and the second track attenuator are means capable of adjusting the volume of the audio data assigned to the respective tracks. In this embodiment, the second track attenuator is used to adjust the volume (ducking) in each ducking track. Specifically, for each ducking track, the calculated ducking amount (proportion of volume reduction) is set as the attenuation rate of the second track attenuator for that ducking track for each predetermined unit time, and the volume of the ducking audio data assigned to that ducking track is adjusted (ducked) in accordance with the calculated ducking amount.

[0100] As a result, as shown in Figure 53, for each ducking track, if the trigger peak value does not reach the minimum threshold for that ducking track, the ducking amount of the ducking audio data assigned to that ducking track becomes "0" and ducking is not performed. On the other hand, for each ducking track, when the trigger peak value reaches the minimum threshold for that ducking track, ducking of the ducking audio data assigned to that ducking track begins. When ducking of the ducking audio data begins, the ducking amount increases and the volume of the ducking audio data decreases as the trigger peak value increases. Here, the ducking amount is calculated, for example, using the following (Equation 1). Ducking amount [%] = Trigger peak value [dB] / (Maximum threshold [dB] - Minimum threshold [dB]) (Equation 1) Furthermore, when the trigger peak value for each ducking track reaches the maximum threshold for that ducking track, the ducking amount does not increase any further and the volume of the ducking audio data does not decrease any further. After that, when the trigger peak value for each ducking track falls below the maximum threshold for that ducking track, the ducking amount decreases as the trigger peak value decreases and the volume of the ducking audio data increases. Furthermore, for each ducking track, when the trigger peak value falls below the minimum threshold for that ducking track, the volume of the ducking audio data returns to its original volume (the volume when ducking is not being performed) after a number of fade-out frames. As a result, it is possible to reduce (duck) the volume of the ducking track (ducking audio data) during the period when the volume (trigger peak value) of the trigger track (trigger audio data) reaches the minimum threshold corresponding to each ducking track.

[0101] As described above, in this embodiment, the track ducking function can be set for each track. As a result, one track may be subject to the track ducking function for multiple tracks. In other words, one ducking track may be subject to ducking based on multiple trigger tracks. In this case, in each track ducking process, the largest ducking amount among the ducking amounts calculated for the multiple trigger tracks is adopted as the ducking amount for the single ducking track. For example, there is a case where the ducking of the volume of the audio data assigned to track 3 (ducking track) is set based on the volume of the audio data assigned to track 1 (trigger track), and the ducking of the volume of the audio data assigned to track 3 (ducking track) is set based on the volume of the audio data assigned to track 2 (trigger track). In this case, in each track ducking process, a first ducking amount is calculated based on the trigger peak value for track 1 and the track ducker parameter set for track 3 (track ducker parameter corresponding to the track ducking function for track 1), and a second ducking amount is calculated based on the trigger peak value for track 2 and the track ducker parameter set for track 3 (track ducker parameter corresponding to the track ducking function for track 2). At this time, in each track ducking process, the largest ducking amount (the ducking amount that reduces the volume by a larger percentage) of the first and second ducking amounts is adopted as the ducking amount for track 3, and the volume of the audio data assigned to track 3 is adjusted (ducked) according to the adopted ducking amount. This makes it possible to perform appropriate ducking control even when ducking operations targeting the same track overlap.

[0102] (Example of using the track ducking function) Next, an example of how to use the track ducking function will be described. In the pachinko machine 1, a track ducking function can be used to make a predetermined effect sound stand out. For example, during playback of audio data corresponding to a first sound effect (e.g., background music for a first half variable sound effect), playback of audio data corresponding to a second sound effect (e.g., background music for a main preview sound effect) is started in overlapping relation with the playback of the audio data corresponding to the first sound effect, and further, playback of audio data corresponding to a third sound effect (e.g., an error sound for a full tank error) is started in overlapping relation with the playback of the audio data corresponding to the first sound effect and the audio data corresponding to the second sound effect, making it possible to highlight the third sound effect. Specifically, when playback of the first sound effect starts, a command list corresponding to the first sound effect is set and executed. In the command list corresponding to the first sound effect, the audio data of the first sound effect (hereinafter referred to as "audio data 1") is specified as the audio data to start playback, and track 1 is specified as the track to which audio data 1 is assigned. Furthermore, when playback of the second sound effect begins, a command list corresponding to the second sound effect is set and executed. In the command list corresponding to the second sound effect, the audio data of the second sound effect (hereinafter referred to as "audio data 2") is specified as the audio data to start playback, track 2 is specified as the track to which audio data 2 is assigned, and preset data x is specified as the preset data corresponding to track 2. In the preset data x, volume peak value information x corresponding to audio data 2 is specified, operation of the track ducking function is specified, track 1 is specified as the ducking track, and track ducker parameter x corresponding to track 1 (ducking track) is specified. In this case, the volume peak value information x indicates that the peak volume value in each predetermined unit time for the entirety of audio data 2 (from the beginning to the end) is greater than a first predetermined value. In addition, in the track ducker parameter x, a volume less than the first predetermined value is set as the minimum threshold. Furthermore, when playback of the third sound effect begins, a command list corresponding to the third sound effect is set and executed. In the command list corresponding to the third sound effect, the audio data of the third sound effect (hereinafter referred to as "audio data 3") is specified as the audio data to start playback, track 3 is specified as the track to which audio data 3 is assigned, and preset data y is specified as the preset data corresponding to track 3. In preset data y, volume peak value information y corresponding to audio data 3 is specified, operation of the track ducking function is specified, all tracks other than track 3 are specified as ducking tracks, and track ducker parameter y corresponding to each track other than track 3 (ducking track) is specified. In this case, the volume peak value information y specifies that the peak volume value in each predetermined unit time for the entire audio data 3 (from the beginning to the end) is greater than a second predetermined value. In addition, a minimum value (-∞ [db]) is set as the minimum threshold for track ducker parameter y.

[0103] As a result, when playback of the second effect sound starts, track ducking processing is executed for each predetermined unit time. At this time, in each track ducking processing, the trigger peak value of audio data 2 exceeds the minimum threshold set for track 1, so the volume of audio data 1 assigned to track 1 is adjusted (ducked) according to the calculated ducking amount. Therefore, during playback of the second effect sound, the volume of the first effect sound is reduced, making it possible to make the second effect sound stand out against the first effect sound. Furthermore, with the start of playback of the third sound effect, a track ducking process is executed for each predetermined unit time. At this time, in each track ducking process, the trigger peak value of audio data 3 exceeds the minimum threshold set for track 1 and also exceeds the minimum threshold set for track 2, so that the volume of audio data 1 assigned to track 1 is adjusted (ducked) and the volume of audio data 2 assigned to track 2 is also adjusted (ducked) in accordance with the calculated ducking amount. At this time, for audio data 1 assigned to track 1, the largest ducking amount (the ducking amount that reduces the volume by a larger percentage) of the ducking amount calculated based on track ducker parameter x and the ducking amount calculated based on track ducker parameter y is adopted. Therefore, during playback of the third sound effect, the volume of the first and second sound effect is reduced, making it possible to make the third sound effect stand out relative to the first and second sound effect.

[0104] (Method for controlling performance using performance control board 300) Next, a method for controlling the performance using the performance control board 300 will be described. The CPU 310 selects the effect (effect number) to be executed in response to the control command received from the main control board 200. Then, the CPU 310 sets the effect scenario data corresponding to the selected effect number and the effect scenario timer corresponding to the effect scenario data in the effect scenario setting area of ​​the DRAM 304. "Rendering scenario data" is information that defines the progression of a rendering. Specifically, the rendering scenario data contains multiple pieces of process data registered in chronological order. That is, the rendering scenario data contains multiple pieces of process data and information that specifies the start time (start timing) of processing based on each piece of process data. Each process data includes one or more pieces of command information. For example, command information specifying the start of a sub-effect (display effect, sound effect, lamp effect, or movable object effect), command information specifying the end of a sub-effect (display effect, sound effect, lamp effect, or movable object effect) (hereinafter referred to as a "effect end command"), etc. are specified as command information.

[0105] Furthermore, the CPU 310 controls the progress of the presentation based on the presentation scenario data set in the presentation scenario setting area. Specifically, CPU 310 periodically updates the rendering scenario timer set in the rendering scenario setting area, and determines whether or not there is any process data whose start time has arrived among the process data registered in the rendering scenario data set in the rendering scenario setting area based on the updated value of the rendering scenario timer. If it determines that there is any process data whose start time has arrived, it stores (memorizes) each piece of command information included in the process data in the corresponding buffer area. At this time, command information related to the display performance (command information specifying the start of the display performance, command information specifying the end of the display performance, etc.) is stored in the display command buffer area. On the other hand, command information related to the sound performance (command information specifying various sound performance control numbers) is stored in the sound command buffer area. On the other hand, command information related to the lamp performance (command information specifying the start of the lamp performance, command information specifying the end of the lamp performance, etc.) is stored in the lamp command buffer area. On the other hand, command information related to the movable body performance (command information specifying the start of the movable body performance, command information specifying the end of the movable body performance, etc.) is stored in the movable body command buffer area.

[0106] (Display control method) Next, a method for controlling the display performance (display) by the performance control board 300 will be described. The control ROM 302 stores animation tables corresponding to each display effect (each display effect number). The animation tables corresponding to each display effect are associated with display priority information corresponding to the display effect (the images constituting the display effect). "Display priority information" is information that specifies the display priority. "Display priority" is information that specifies the display (drawing) priority. When multiple display effects (displays) are executed at the same time, the display on the display screen 31a (the effect image displayed on the display screen 31a) is configured based on the multiple display effects (images related to the multiple display effects). In this case, of the multiple display effects (multiple images) that make up the display (the effect image), the display effect (image) with the higher display priority is displayed with priority over the display effect (image) with the lower display priority. In other words, of the multiple display effects (multiple images) that make up the effect image, the higher the display priority, the higher the display priority is displayed with priority.

[0107] In other words, among the multiple display effects (multiple images) that make up the effect image, the display effect (image) with a higher display priority is displayed closer to the player than the display effects (images) with a lower display priority. In other words, among the multiple display effects (multiple images) that make up the effect image, the higher the display priority, the closer the display effect (image) is displayed. As a result, if there is an overlapping portion between a display effect (image) with a higher display priority and a display effect (image) with a lower display priority among the multiple display effects (multiple images) that make up the effect image, the display effect (image) with the higher display priority will be displayed preferentially for the overlapping portion.

[0108] The CPU 310 (display control unit) periodically determines whether command information is stored in the display command buffer area. If it determines that command information is stored in the display command buffer area, it analyzes the command information stored in the display command buffer area and executes processing according to the analysis result. At this time, if command information specifying the start of a display effect is stored in the display command buffer area, the animation table corresponding to the display effect number specified by the command information is read out from the animation tables stored in the control ROM 302. Then, the read animation table is set (stored and registered) in the animation table setting area of ​​the DRAM 304. As a result, the animation table stored in the control ROM 302 is copied to the animation table setting area. Note that it is possible to set multiple animation tables in the animation table setting area.

[0109] The "animation table" is information (various parameters for controlling the display of images) that defines the progress of display effects (display of effect images) by the various image display devices 31, 32. In other words, the animation table is information that defines the movement of images. Specifically, a predetermined number of frames of information are registered in chronological order in the animation table, and the display performance progresses by sequentially displaying images based on each frame of information in the order in which it is registered for the predetermined number of frames of information registered in the animation table. Each frame information is a set of various parameters for controlling (executing and configuring) the display of one frame's worth of image. That is, each frame information is composed of information specifying the image data (compressed image data) used for drawing (image address information), information specifying the display priority of the image data (the display performance) (display priority information), information specifying the magnification (enlargement / reduction rate) when drawing the image data (hereinafter referred to as "display magnification information"), information specifying the coordinates (coordinates in the frame buffer area) at which the image data is drawn (hereinafter referred to as "display coordinate information"), information specifying the transmittance (transparency / transparency / opacity) when drawing the image data (hereinafter referred to as "transparency information"), etc.

[0110] Then, CPU 310 controls the display of the effect image corresponding to each frame based on one or more animation tables set in the animation table setting area. Specifically, the CPU 310 executes a command construction process, which will be described later, at predetermined intervals. In the command construction process, first, the sub-scenario timers corresponding to each animation data set in the display scenario setting area are updated, and then a display list is constructed in the drawing command buffer area specified in the construction area based on all the animation tables set in the animation table setting area.

[0111] Specifically, for all animation tables set in the animation table setting area, the frame information selected as the target for constructing a display list is acquired from the frame information registered in each animation table, and a display list is constructed based on all the acquired frame information. As a result, the VDP is controlled in accordance with the display list generated in the drawing command buffer area, and the display presentation (the display of the presentation image by the main image display device 31) is controlled. That is, when one piece of animation data is set in the display scenario setting area, a display list is constructed that specifies the rendering of the image data specified by that piece of animation data. On the other hand, if multiple animation data are set in the display scenario setting area, a display list is constructed that specifies that the drawing of the image data specified by the multiple animation data is to be executed in a predetermined order (sequence). At this time, the order in which the image data corresponding to the display priority information is drawn is set based on the display priority specified by the display priority information set in the display scenario setting area.

[0112] (Sound production control method) Next, a method for controlling sound effects using the effect control board 300 will be described. The CPU 310 (sound control unit) periodically determines whether command information is stored in the sound command buffer area. If it determines that command information is stored in the sound command buffer area, it analyzes the command information stored in the sound command buffer area and executes processing according to the analysis result. Specifically, a command list corresponding to the sound effect control number specified by the instruction information is read from the control ROM 302, and the read command list is set in the control register of the sound circuit 323. As a result, the sound circuit 323 operates according to the command list set in the control register.

[0113] (Lamp effect control method) Next, a method for controlling lamp effects using the effect control board 300 will be described. The CPU 310 periodically determines whether command information is stored in the lamp command buffer area. If it determines that command information is stored in the lamp command buffer area, it analyzes the command information stored in the lamp command buffer area and executes processing according to the analysis result. At this time, if command information specifying the start of a lamp effect is stored in the lamp command buffer area, the compressed lamp drive data corresponding to the lamp effect number specified by the command information is read out and the read compressed lamp drive data is set in the lamp register. As a result, the lamp controller 317a controls the lamp effect (driving (lighting) of the various lamps 20, 21) according to the compressed lamp drive data set in the lamp register.

[0114] (Method for controlling movable object effects) Next, a method for controlling the movable body performance using the performance control board 300 will be described. The CPU 310 periodically determines whether command information is stored in the movable body command buffer area, and if it determines that command information is stored in the movable body command buffer area, it analyzes the command information stored in the movable body command buffer area and executes processing according to the analysis result. At this time, if command information specifying the start of a movable body performance is stored in the movable body command buffer area, the compressed motor drive data specified by the command information is read out and the read compressed motor drive data is set in the motor register. As a result, the motor controller 317b controls the movable body performance (the drive of the various motors 23 (various movable bodies)) according to the compressed motor drive data set in the motor register.

[0115] (Configuration of driver board 330) The driver board 330 includes a parallel-serial conversion circuit 331 , a lamp driver 332 , and a motor driver 333 . The lamp driver 332 controls the driving (light emission) of the light emitting element groups of each system that constitute the panel lamp 21 in accordance with the lamp driving data input from the lamp controller 317a. At this time, the lamp drive data specifies a brightness value corresponding to each system that constitutes the panel lamp 21. An excitation signal (drive current) according to the brightness value specified in the lamp drive data is supplied to each system that constitutes the panel lamp 21. This controls the drive (light emission) of the light-emitting element group that constitutes each system. The motor driver 333 controls the output of excitation signals (drive currents) to the various motors 23 (motors 23 that constitute the various movable body units) arranged in the game board unit 10 according to the motor drive data input from the motor controller 317b. At this time, the motor drive data specifies the output value of each motor 23 arranged in the game board unit 10. Then, an excitation signal (drive current) according to the output value specified in the motor drive data is supplied to each motor 23. This controls the drive of each motor 23. The parallel-serial conversion circuit 331 receives detection signals from the various sensors 24. The parallel-serial conversion circuit 331 converts the detection signals from the various sensors 24 into serial data and outputs the serial data to the serial communication controller 317.

[0116] (Configuration of sub-connection board 340) The sub-connection board 340 includes a parallel-serial conversion circuit 341 , a lamp driver 342 , and a motor driver 343 . The lamp driver 342 controls the driving (light emission) of the light emitting element groups of each system that constitute the frame lamp 20 in accordance with the lamp driving data input from the lamp controller 317a. At this time, the lamp driving data specifies a brightness value corresponding to each system that constitutes the frame lamp 20. An excitation signal (driving current) according to the brightness value specified in the lamp driving data is supplied to each system that constitutes the frame lamp 20. This controls the driving (light emission) of the light-emitting element group that constitutes that system for each system. The motor driver 343 controls the output of excitation signals (drive currents) to the various motors 23 (motors 23 that constitute the various movable body units) arranged in the integrated door unit 4 according to the motor drive data input from the motor controller 317b. At this time, the motor drive data specifies the output value of each motor 23 arranged in the integrated door unit 4. Then, an excitation signal (drive current) according to the output value specified in the motor drive data is supplied to each motor 23. This controls the drive of each motor 23. The parallel-serial conversion circuit 341 receives detection signals from the various sensors 24 and detection signals from the various switches 25 to 29. The parallel-serial conversion circuit 341 then converts the detection signals from the various sensors 24 and detection signals from the various switches 25 to 29 into serial data and outputs the serial data to the serial communication controller 317.

[0117] (Configuration of digital amplifier 305) Next, the configuration of the digital amplifier 305 will be described. The digital amplifier 305 converts and amplifies the audio data (digital signal) input from the sound circuit 323 into an analog signal and outputs it to the various speakers 22 (upper left speaker, upper right speaker, center left speaker, center right speaker, and woofer). At this time, the digital amplifier 305 performs frequency correction, volume correction, etc. for each channel (channel 1 to channel 8). In particular, the digital amplifier 305 has a built-in DSP (Digital Signal Processor).The digital amplifier 305 can set a 10-band (frequency band) PEQ (Parametric Equalizer), a 3-band (frequency band) DRC (Dynamic Range Controller), a crossover filter, a bass boost function, and the like for each channel (channel 1 to channel 8) by transmitting frequency correction parameters from the CPU 310 to the digital amplifier 305.

[0118] Specifically, the digital amplifier 305 is configured to include four CPU cores (core 1 to core 4). Core 1 performs frequency correction, volume correction, etc. on the audio data of channels 1 and 2 (top left speaker and top right speaker). Core 2 performs frequency correction, volume correction, etc. on the audio data of channels 3 and 4 (center left speaker and center right speaker). Core 3 performs frequency correction, volume correction, etc. on the audio data of channel 5 (woofer). Core 4 is unused. The digital amplifier 305 is also provided with a frequency correction parameter setting register in which a frequency correction parameter is set (stored).The digital amplifier 305 then performs frequency correction on the audio data of each channel (channel 1 to channel 8) in accordance with the frequency correction parameter set in the frequency correction parameter setting register.

[0119] In this embodiment, the frequency correction parameter setting register includes a frequency correction parameter setting unit 1 corresponding to core 1 (channels 1 and 2), a frequency correction parameter setting unit 2 corresponding to core 2 (channels 3 and 4), and a frequency correction parameter setting unit 3 corresponding to core 3 (channels 5 and 6). Then, core 1 performs frequency correction on the audio data of channels 1 and 2 (upper left speaker and upper right speaker) according to the frequency correction parameters set in frequency correction parameter setting unit 1. Core 2 also performs frequency correction on the audio data of channels 3 and 4 (center left speaker and center right speaker) according to the frequency correction parameters set in frequency correction parameter setting unit 2. Furthermore, core 3 performs frequency correction on the audio data of channel 5 (woofer) according to the frequency correction parameters set in frequency correction parameter setting unit 3.

[0120] (Regarding gaming machine status) In the pachinko machine 1, six states (specifically, a playable state, a setting change state, a setting confirmation state, a setting abnormal state, a RAM abnormal state, and a backup abnormal state) are defined as the gaming machine state. A gaming machine state flag area is provided in the RAM 230 of the main control board 200. In the gaming machine state flag area, a value corresponding to one of six gaming machine states (specifically, a playable state, a setting change state, a setting confirmation state, a setting abnormal state, a RAM abnormal state, and a backup abnormal state) is stored (set) as a gaming machine state flag. Then, in the pachinko machine 1, a gaming machine state corresponding to the value stored in the gaming machine state flag area is generated.

[0121] The "playable state" is a gaming machine state in which game progress is possible. While the game-playable state is occurring, execution of the processes of steps S4-9 to S4-18, which will be described later, is permitted, thereby allowing the game (normal game and special game) to proceed. Furthermore, while the game is in a playable state, the base ratio is displayed on the performance display device 206. Furthermore, information related to the game is displayed on the main display device 60.

[0122] The "setting change state" is a gaming machine state in which the setting values ​​stored in the setting value area of ​​RAM 230 can be changed. The setting change state occurs when the setting change conditions are met. In this embodiment, the setting change conditions are met when a detection signal is input from the inner frame open sensor 108, a detection signal is input from the setting key switch 208, and a detection signal is input from the RAM clear switch 207 at power-on. In other words, the setting change state occurs when the inner frame unit 3 is open, the key switch 208 is rotated to the ON state, and the RAM clear switch 207 is pressed at power-on. While the setting change state is occurring, the execution of the processes of steps S4-9 to S4-18, which will be described later, is prohibited, thereby stopping the game (specifically, the normal game and the special game). Furthermore, while the setting change state is occurring, the setting value stored in the setting value area is displayed on the performance display device 206. Furthermore, all lighting elements constituting the main display device 60 are turned off. Furthermore, security information (external information) is output to the external device. Furthermore, while the setting change state is occurring, it is possible to change the setting values ​​stored in the setting value area by pressing the RAM clear switch 207. Then, when the key switch 208 is rotated to the OFF state while the setting change state is occurring, the setting change state is replaced by a playable state, and the setting values ​​stored in the setting value area are confirmed.

[0123] The "setting confirmation state" is a gaming machine state in which the setting values ​​stored in the setting value area of ​​RAM 230 can be confirmed. The setting confirmation state is established when the setting confirmation conditions are met. In this embodiment, the setting confirmation conditions are established when, at power-on, a detection signal is input from the inner frame open sensor 108, a detection signal is input from the setting key switch 208, and a detection signal is not input from the RAM clear switch 207. In other words, at power-on, if the inner frame unit 3 is open, the key switch 208 is rotated to the ON state, and the RAM clear switch 207 is not pressed, the setting confirmation state is established. While the setting confirmation state is occurring, the execution of the processes of steps S4-9 to S4-18, which will be described later, is prohibited, thereby stopping the game (specifically, the normal game and the special game). Furthermore, while the setting confirmation state is occurring, the setting values ​​stored in the setting value area are displayed on the performance display device 206. This makes it possible to check the setting values ​​stored in the setting value area. Furthermore, all lighting elements constituting the main display device 60 are turned off. Furthermore, security information (external information) is output to the external device. It should be noted that while the setting confirmation state is occurring, the setting values ​​stored in the setting value area cannot be changed. When the key switch 208 is turned to the OFF state while the setting confirmation state is occurring, the setting confirmation state is replaced with a playable state.

[0124] The "setting abnormality state" is the state of the gaming machine in which a setting abnormality has occurred. The abnormal setting state occurs when, during a playable state, it is determined that the setting value set in the setting value area is not within a specified range. During the occurrence of the setting abnormal state, the execution of the processes of steps S4-9 to S4-18, which will be described later, is prohibited, thereby stopping the game (specifically, the normal game and the special game). Furthermore, while a setting abnormality state occurs, an error code specifying the occurrence of a setting abnormality is displayed on the performance display device 206. Furthermore, all lighting elements constituting the main display device 60 are turned off. Furthermore, security information (external information) is output to an external device. To recover from the abnormal setting state, it is necessary to turn the power off and on again to cause a setting change state.

[0125] "RAM abnormal state" refers to the state of the gaming machine in which a RAM abnormality has occurred. The RAM abnormal state occurs when it is determined that a read / write abnormality has occurred in the RAM 230 at power-on. During the occurrence of the RAM abnormal state, the execution of the processes of steps S4-9 to S4-18, which will be described later, is prohibited, thereby stopping the game (specifically, the normal game and the special game). Furthermore, while a RAM abnormality state is occurring, an error code specifying the occurrence of a RAM abnormality is displayed on the performance display device 206. Furthermore, all lighting elements constituting the main display device 60 are turned off. Furthermore, security information (external information) is output to an external device. To recover from the RAM abnormality state, it is necessary to perform a power-off and power-on to cause a setting change state.

[0126] The "backup abnormality state" is the state of the gaming machine in which a backup abnormality has occurred. The backup abnormality state occurs when it is determined that a backup abnormality (specifically, an abnormality in the backup flag or an abnormality in the checksum) has occurred in the RAM 230 when the power is turned on. During the occurrence of the backup abnormal state, the execution of the processes of steps S4-9 to S4-18, which will be described later, is prohibited, thereby stopping the game (specifically, the normal game and the special game). Furthermore, when a backup abnormality occurs, an error code specifying the occurrence of a backup abnormality is displayed on the performance display device 206. Furthermore, all lighting elements constituting the main display device 60 are turned off. Furthermore, security information (external information) is output to an external device. To recover from the backup abnormality state, it is necessary to perform a power-off and power-on to cause a setting change state.

[0127] (About the setting value) Next, the setting values ​​(setting information) set in the pachinko machine 1 will be described. The "setting value" is information that specifies the winning probability (probability of winning the jackpot game state) of the special symbol lottery (first special symbol lottery and second special symbol lottery). In this embodiment, the setting value is specified as a value of "0" to "5". A set value area is provided in the RAM 230 of the main control board 200. In the set value area, one of values ​​"0" to "5" is stored (set) as a set value. In the pachinko machine 1, the probability of winning the special symbol lottery is determined according to the value set in the set value area. In this embodiment, the winning probability of the special pattern lottery corresponding to each setting value is, in order from highest to lowest, the winning probability corresponding to setting value = "5", the winning probability corresponding to setting value = "4", the winning probability corresponding to setting value = "3", the winning probability corresponding to setting value = "2", the winning probability corresponding to setting value = "1", and the winning probability corresponding to setting value = "0" (high winning probability → low winning probability).

[0128] In particular, in the pachinko machine 1, it is possible to change (select) the setting values ​​stored in the setting value area while the setting change state is occurring. Here, the change of the setting value is executed by the manager of the pachinko machine 1 (such as an employee of the gaming parlor where the pachinko machine 1 is installed). That is, as described above, when the power is turned on, if the inner frame unit 3 is open, the key switch 208 is rotated to the ON state, and the RAM clear switch 207 is pressed, a setting change state is generated. While the setting change state is occurring, the setting value stored in the setting value area is displayed on the performance display device 206. Furthermore, each time the RAM clear switch 207 is pressed, the setting value stored in the setting value area is changed. At this time, if the setting value set in the setting value area is changed, the setting value displayed on the performance display device 206 is also changed accordingly. When the key switch 208 is turned to the OFF state while the setting change state is occurring, the setting change state is replaced by a playable state, and the setting value stored in the setting value area is confirmed.

[0129] (Base ratio) In the pachinko machine 1, while a playable state is occurring, a base ratio (base value) is calculated by the CPU 210. In this embodiment, the base ratio is calculated only while a predetermined play state is occurring (specifically, while a special low probability state is occurring and while time-saving control is stopped). Then, while the game is in a playable state, the calculated base ratio is displayed on the performance display device 206. The "base ratio" is information calculated based on the number of game balls shot into the game area 30 and the number of prize balls paid out in response to the game balls entering predetermined entry holes (in this embodiment, the first start hole 51, the second start hole 52, and the other prize holes 54 to 57). Specifically, the base ratio is the ratio (percentage) of the number of paid-out balls to the number of out-out balls.

[0130] In this embodiment, a base ratio for each predetermined interval (period) is calculated. The predetermined interval is defined as an interval during which a predetermined number of out balls (60,000 balls in this embodiment) are detected (discharged). That is, each interval begins when the previous interval ends, and ends when the number of out balls detected during the current interval reaches the predetermined number (60,000 balls). The CPU 210 calculates the base ratio as needed (in real time) during each interval.

[0131] Note that a predetermined time may be defined as the predetermined section, and the CPU 210 may calculate the base ratio for each predetermined time. The "number of out balls" refers to the number of out balls. "Out balls" refer to game balls that have been discharged from the game area 30. Specifically, out balls are game balls that have passed through the discharge path (game balls detected by the out switch 109). It is also possible to use the gaming ball discharged from outlet 58 as the out ball. Specifically, out switch 109 may be configured to detect only gaming balls discharged from outlet 58, and the gaming ball detected by out switch 109 may be used as the out ball. The "number of payouts" refers to the total number of prize balls paid out in response to game balls entering the first start hole 51, the second start hole 52 and the other prize holes 54-57.

[0132] (About various lotteries) Next, various lotteries executed in the pachinko machine 1 will be described. In the pachinko machine 1, a normal symbol lottery is executed when a gaming ball passes through the start gate 41. If the normal symbol lottery is won, a normal symbol winning game state is generated. In the normal symbol winning game state, the normal electric device 52a is shifted (opened) from a closed state to an open state, and the gaming ball can enter the second start gate 52. In this embodiment, one type of "normal symbol win" is set as the type of normal symbol win game state that occurs when the normal symbol lottery is won.

[0133] When the "regular winning" is won (the regular pattern lottery is won), the regular pattern display device is controlled to stop and display the regular pattern as the "regular winning pattern." On the other hand, if the player loses the regular symbol lottery, the regular symbol display device is controlled to stop and display the regular symbol as a "losing symbol." In the pachinko machine 1, it is possible to execute time-saving control as auxiliary control that is advantageous to the player. While the time-saving control is being executed, the time for which the variable display of the special symbols is performed (hereinafter referred to as "variation time") is shortened compared to when the time-saving control is stopped. In this embodiment, while the time-saving control is being executed, the probability of winning the normal symbol lottery is improved and the time for which the variable display of the normal symbols is performed is shortened compared to when the time-saving control is stopped. Also, while the time-saving control is being executed, the number of times the normal electric device 52a is opened is increased and the opening time of the normal electric device 52a is extended in the normal winning game state compared to when the time-saving control is stopped.

[0134] When a "normal win" is won, the number of times that the normal electric device 52a opens is set to 1 [time] or 3 [times], and the opening time of the normal electric device 52a each time is set to 0.5 [s] or 2.0 [s]. At this time, while the time-saving control is being executed, the number of times that the normal electric device 52a opens is set to 3 [times], and the opening time of the normal electric device 52a each time is set to 2.0 [s]. On the other hand, while the time-saving control is stopped, the number of times that the normal electric device 52a opens is set to 1 [time], and the opening time of the normal electric device 52a each time is set to 0.5 [s].

[0135] In addition, in the pachinko machine 1, the entry of a gaming ball into the first starting hole 51 triggers the execution of a first special symbol lottery, and the entry of a gaming ball into the second starting hole 52 triggers the execution of a second special symbol lottery. If the first special symbol lottery or the second special symbol lottery is won, a jackpot gaming state is generated. In the jackpot gaming state, a round game is executed in which the special electric device 53a is shifted from a closed state to an open state, and it becomes possible for a gaming ball to enter the jackpot winning hole 53. In this embodiment, "Jackpot 1" and "Jackpot 2" are set as the types of jackpot game states that occur when the first special pattern lottery is won, and "Jackpot 3" to "Jackpot 6" are set as the types of jackpot game states that occur when the second special pattern lottery is won.

[0136] When "Jackpot 1" is won, the stop pattern (display mode) corresponding to the "Jackpot 1 pattern" is stopped and displayed on the special chart 1 display device. Also, in the performance pattern display area a1 to a4, the stop pattern (display mode) corresponding to the "probability variable pattern" is stopped and displayed. Here, the "probable change pattern" is a display mode in which, for example, the first performance pattern z1 stopped and displayed at the lottery result display position of the three first performance pattern display areas a1 to a3 is a "number pattern" showing the same odd numbers, such as "7, 7, 7," and the second performance pattern z2 stopped and displayed in the second performance pattern display area a4 shows a predetermined color. When "Big Hit 2" is won, the stop pattern (display mode) corresponding to the "Big Hit 2 pattern" is stopped and displayed on the special chart 1 display device. Also, in the performance pattern display area a1 to a4, the stop pattern (display mode) corresponding to the "normal pattern" is stopped and displayed. Here, the "normal pattern" is, for example, a display mode in which the first performance pattern z1 stopped and displayed at the lottery result display position of the three first performance pattern display areas a1 to a3 is a "number pattern" showing the same even numbers, such as "2, 2, 2," and the second performance pattern z2 stopped and displayed in the second performance pattern display area a4 shows a predetermined color.

[0137] When "Jackpot 3" is won, the stop pattern (display mode) corresponding to the "Jackpot 3 pattern" is stopped and displayed on the special chart 2 display device. Also, in the performance pattern display area a1 to a4, the stop pattern (display mode) corresponding to the "probability variable pattern" is stopped and displayed. When "Jackpot 4" is won, the stop pattern (display mode) corresponding to the "Jackpot 4 pattern" is stopped and displayed on the special chart 2 display device. Also, in the performance pattern display area a1 to a4, the stop pattern (display mode) corresponding to the "probability variable pattern" is stopped and displayed. When "Jackpot 5" is won, the stop pattern (display mode) corresponding to the "Jackpot 5 pattern" is stopped and displayed on the special chart 2 display device. Also, in the performance pattern display area a1 to a4, the stop pattern (display mode) corresponding to the "latent pattern" is stopped and displayed. Here, the "latent pattern" is, for example, a display mode in which the first performance pattern z1 stopped and displayed at the lottery result display position of the three first performance pattern display areas a1 to a3 is a combination with a predetermined regularity, such as "1, 2, 3," and the second performance pattern z2 stopped and displayed in the second performance pattern display area a4 shows a predetermined color. When "Jackpot 6" is won, the stop pattern (display mode) corresponding to the "Jackpot 6 pattern" is stopped and displayed on the special chart 2 display device. Also, in the performance pattern display area a1 to a4, the stop pattern (display mode) corresponding to the "latent pattern" is stopped and displayed.

[0138] On the other hand, if you lose the special symbol lottery (in the case of a "lose"), the stop symbol (display mode) corresponding to the "lose symbol" is stopped and displayed on the special symbol 1 display device or the special symbol 2 display device. Also, the stop symbol (display mode) corresponding to the "lose symbol" is stopped and displayed in the performance symbol display areas a1 to a4. Here, a "losing pattern" is, for example, a display mode in which the first performance pattern z1 stopped and displayed in the three first performance pattern display areas a1 to a3 has a combination of numbers, such as "1, 6, 9," that is different from the numbers indicated by the "number pattern" stopped and displayed in at least one area and the "number pattern" stopped and displayed in the other areas, and the second performance pattern z2 stopped and displayed in the second performance pattern display area a4 shows a predetermined color.

[0139] If any of "Jackpot 1" to "Jackpot 6" is won, a predetermined number of rounds of play will be executed in the jackpot game state. In this embodiment, if "Jackpot 1," "Jackpot 2," "Jackpot 5," or "Jackpot 6" is won, the number of rounds of play is set to 5 [times]. On the other hand, if "Jackpot 3" is won, the number of rounds of play is set to 15 [times]. On the other hand, if "Jackpot 4" is won, the number of rounds of play is set to 10 [times]. When "Jackpot 1" to "Jackpot 6" are won, the maximum opening time of the special electric device 53a in each round of play is set to a predetermined time (29.0 [s] in this embodiment). Each round of play is ended when one of the following conditions is met: the maximum opening time has elapsed since the special electric device 53a was set to the open state, or the number of game balls entering the big prize opening 53 in that round of play has reached a predetermined upper limit (10 [balls] in this embodiment).

[0140] In addition, in the pachinko machine 1, a "special pattern low probability state" and a "special pattern high probability state" are defined as game states related to the probability of winning the special pattern lottery (first special pattern lottery and second special pattern lottery). During the occurrence of the "special pattern low probability state," the probability of winning the special pattern lottery is set to the first probability (hereinafter referred to as the "low probability"). During the occurrence of the "special symbol high probability state," the probability of winning the special symbol lottery is set to a second probability (hereinafter referred to as "high probability") that is higher than the first probability. The main control board 200 sets the winning probability of each lottery so that the winning probability of the first special symbol lottery and the winning probability of the second special symbol lottery are synchronized. Here, the winning probability of the special symbol lottery refers to the probability of winning a "jackpot" ("jackpot 1" to "jackpot 6") that will cause a jackpot gaming state. In particular, in pachinko machine 1, the probability of winning the special pattern lottery is determined according to the combination of the setting value set in the setting value area and the game state (special pattern low probability state or special pattern high probability state).

[0141] Specifically, when the setting value is "0" and the "special symbol low probability state" is occurring, the probability of winning the special symbol lottery (jackpot probability) is 1 / 319.69. On the other hand, when the setting value is "0" and the "special symbol high probability state" is occurring, the probability of winning the special symbol lottery (jackpot probability) is 1 / 32.13. On the other hand, when the setting value is "1" and the "special symbol low probability state" is occurring, the probability of winning the special symbol lottery (jackpot probability) is 1 / 312.08. On the other hand, when the setting value is "1" and the "special symbol high probability state" is occurring, the probability of winning the special symbol lottery (jackpot probability) is 1 / 31.36. On the other hand, when the setting value is "2" and the "special symbol low probability state" is occurring, the probability of winning the special symbol lottery (jackpot probability) is 1 / 304.82. On the other hand, when the setting value is "2" and the "special symbol high probability state" is occurring, the probability of winning the special symbol lottery (jackpot probability) is 1 / 30.62.

[0142] On the other hand, when the setting value is "3" and the "special symbol low probability state" is occurring, the probability of winning the special symbol lottery (jackpot probability) is 1 / 297.89. On the other hand, when the setting value is "3" and the "special symbol high probability state" is occurring, the probability of winning the special symbol lottery (jackpot probability) is 1 / 29.93. On the other hand, when the setting value is "4" and the "special symbol low probability state" is occurring, the probability of winning the special symbol lottery (jackpot probability) is 1 / 291.27. On the other hand, when the setting value is "4" and the "special symbol high probability state" is occurring, the probability of winning the special symbol lottery (jackpot probability) is 1 / 29.26. On the other hand, when the setting value is "5" and the "special symbol low probability state" is occurring, the probability of winning the special symbol lottery (jackpot probability) is 1 / 284.94. On the other hand, when the setting value is "5" and the "special symbol high probability state" is occurring, the probability of winning the special symbol lottery (jackpot probability) is 1 / 28.62.

[0143] If you win "Jackpot 2" or "Jackpot 6", a "special chart low probability state" will occur during the period from the end of the jackpot game state to the occurrence of the next jackpot game state. On the other hand, if "Jackpot 1" or "Jackpot 3" to "Jackpot 5" is won, a "special symbol high probability state" is generated according to the end of the jackpot game state. In this embodiment, the "special symbol high probability state" starts according to the end of the jackpot game state and ends according to the start of the next jackpot game state (the end of the stop display of the "jackpot symbol"). In addition, the "special pattern high probability state" may be configured to start upon the end of a jackpot game state, and to end (a "special pattern low probability state" is generated) upon the number of special pattern lotteries executed during the occurrence of the "special pattern high probability state" reaching a predetermined number (for example, 10,000 times).

[0144] In addition, if any of "Big Hit 1" to "Big Hit 6" is won, the time-shortening control is executed after the big hit gaming state ends. The time-saving control is initiated when the jackpot game state ends, and is terminated when one of the following conditions is met: the special pattern lottery is won (the "jackpot pattern" is displayed as a stopped symbol), or the notification display of the special pattern (variable display and stopped display) is executed a predetermined number of times to shorten the time. If you win "Jackpot 2" or "Jackpot 6", the number of time-saving times will be set to 100. On the other hand, if you win "Big Hit 1" or "Big Hit 3" to "Big Hit 5", the number of times of time reduction is set to 10,000 [times].

[0145] (Regarding control commands) Next, the control commands sent from the main control board 200 to the performance control board 300, and the control commands sent and received between the main control board 200 and the payout control board 400 will be explained. The main control board 200 and the performance control board 300 are connected to each other via a serial communication harness. Here, communication between the main control board 200 and the performance control board 300 is carried out in only one direction, from the main control board 200 to the performance control board 300, and communication from the performance control board 300 to the main control board 200 is not carried out. Each control command sent from the main control board 200 to the performance control board 300 consists of one byte of upper data indicating the type of control command and one byte of lower data indicating the content of the control command. Then, the main control board 200 transmits a control command consisting of upper and lower data via serial communication to the performance control board 300. When the performance control board 300 receives a control command from the main control board 200, a serial communication reception interrupt occurs, and this interrupt processing causes the control command data to be stored in a specified area of ​​RAM.

[0146] In the pachinko machine 1, the control commands sent from the main control board 200 to the performance control board 300 include a pattern type designation command, a variation mode designation command, a variation pattern designation command, a stop designation command, a game status designation command, a number of reserved items designation command, an opening designation command, a round start designation command, a round end designation command, an ending designation command, a first look-ahead designation command, a second look-ahead designation command, a third look-ahead designation command, an error designation command, a demo designation command, a setting value designation command, a game status designation command, etc.

[0147] The symbol type designation command is a command that designates the type of the stopping symbol (stopping symbol number). Specifically, the symbol type designation command designates one type from among "missing symbol" and "jackpot 1 symbol" to "jackpot 6 symbol". The symbol type designation command is transmitted when the variable display of the special symbol starts. In this embodiment, the symbol type designation command is set to correspond to each of the first special symbol lottery and the second special symbol lottery.

[0148] The fluctuation mode designation command is a command that designates the type of fluctuation mode (fluctuation mode number). The fluctuation mode designation command designates the fluctuation time associated with the fluctuation mode number by designating the fluctuation mode number. The fluctuation mode designation command designates the fluctuation time of the first half period (the aspect of the first half period of the fluctuation performance) of the special pattern fluctuation display (fluctuation performance). In this embodiment, m (multiple) types of fluctuation modes are set, each associated with a different fluctuation time. The fluctuation mode designation command designates one ("fluctuation mode m") of the m types of fluctuation modes (fluctuation mode numbers).

[0149] The fluctuation pattern designation command is a command that designates the type of fluctuation pattern (fluctuation pattern number). The fluctuation pattern designation command designates the fluctuation time associated with the fluctuation pattern number by designating the fluctuation pattern number. The fluctuation pattern designation command designates the fluctuation time of the latter half period (the aspect of the latter half period of the fluctuation performance) of the special pattern fluctuation display (fluctuation performance). In this embodiment, n (plural) types of fluctuation patterns are set, each corresponding to a different fluctuation time. The fluctuation pattern designation command designates one ("fluctuation pattern n") of the n types of fluctuation patterns (fluctuation pattern numbers). The variation mode designation command and the variation pattern designation command are sent when the variation display of the special symbol starts.

[0150] The stop designation command is a command that designates the stop display of special symbols (effect symbols z1, z2). The stop designation command is sent when the stop display of the special symbols starts. The game state designation command is a command that designates the game state (game state offset value). Here, the "game state offset value" is information that specifies the game state. In this embodiment, the game state offset value is set to a value corresponding to each combination of the value of the time-saving control flag, the value of the special symbol high probability state flag, the value of the previous jackpot symbol flag, and the value of the post-jackpot spin counter. The gaming state designation command designates one gaming state offset value. The gaming state designation command is transmitted when the power is turned on, when a special gaming phase (described later) is changed, etc.

[0151] The reservation number designation command is a command to designate the reservation number. In this embodiment, the reservation number designation command designates that the reservation number (special drawing 1 reservation number or special drawing 2 reservation number) has increased by "1", that the reservation number has decreased by "1", or the reservation number, etc. Here, "number of reserved special symbols 1" refers to the number of reserved notification displays (variable and stationary) of the first special symbol on the special symbol 1 display device. Also, "number of reserved special symbols 2" refers to the number of reserved notification displays (variable and stationary) of the second special symbol on the special symbol 2 display device. The reserved number designation command is transmitted when the power is turned on, when game information is stored, when the variable display of the special symbol starts, etc. In this embodiment, reserved number designation commands corresponding to the first special symbol lottery and the second special symbol lottery are set.

[0152] The opening designation command is a command that designates the start of the opening period (the start of the jackpot gaming state). The opening designation command designates the type of jackpot gaming state (the type of "jackpot symbol"). Specifically, the opening designation command designates one type from "jackpot 1 symbol" to "jackpot 6 symbol". The opening designation command is sent at the start of the opening period (the start of the jackpot gaming state). The round start command is a command that specifies the start of a round of play and is transmitted at the start of a round of play. The round end designation command is a command that designates the end of a round of play and is transmitted when a round of play ends. The ending designation command is a command that designates the start of an ending period and is transmitted at the start of the ending period.

[0153] The first pre-reading designation command is a command that designates the type of the stopped symbol (one of the types of "missing symbol" and "jackpot 1 symbol" to "jackpot 6 symbol"). In this embodiment, the first pre-reading designation command is set to correspond to each of the first special symbol lottery and the second special symbol lottery. The second read-ahead designation command is a command that designates the content of the variation mode. Specifically, the second read-ahead designation command designates that the type of variation mode is indefinite ("indefinite value"), or designates one of m types of variation modes (variation mode number) ("variation mode m"). The second read-ahead designation command is transmitted when game information is stored. The third read-ahead designation command is a command that designates the content of the fluctuation pattern. Specifically, the third read-ahead designation command designates that the type of fluctuation pattern is indefinite ("indefinite value"), or designates one of n types of fluctuation patterns (fluctuation pattern number) ("fluctuation pattern n"). The third read-ahead designation command is transmitted when game information is stored.

[0154] The error specification command is a command that specifies the occurrence of various errors. In this embodiment, the error specification command specifies the occurrence of a vibration error, a magnetic error, a radio wave error, or a right-hit error. The error specification command is transmitted when the occurrence of various errors is detected. The demo designation command is a command that designates the start of a customer waiting state, and is sent at the start of the customer waiting state. The setting value designation command is a command that designates a setting value stored in the setting value area of ​​the RAM 230. The setting value designation command is sent when clearing the RAM, when power is restored after being turned on, when the setting change state ends, when the setting confirmation state ends, etc. The game status designation command is a command that designates the occurrence (start) or cancellation (end) of a playable state. The game status designation command is sent when a playable state is created (start) and when a playable state is cancelled (end).

[0155] The main control board 200 and the dispensing control board 400 are connected to each other via a serial communication harness. Here, communication between the main control board 200 and the dispensing control board 400 is bidirectional. Each control command sent and received between the main control board 200 and the dispensing control board 400 consists of one byte of data. The main control board 200 then transmits a control command to the dispensing control board 400 via serial communication. When the dispensing control board 400 receives a control command from the main control board 200, a serial communication reception interrupt occurs, and this interrupt processing causes the control command data to be stored in a predetermined area of ​​RAM. The dispensing control board 400 also transmits a control command to the main control board 200 via serial communication. When the main control board 200 receives a control command from the dispensing control board 400, a serial communication reception interrupt occurs, and this interrupt processing causes the control command data to be stored in a predetermined area of ​​RAM 230.

[0156] In the pachinko machine 1, a command to designate the number of prize balls and the like is set as a control command to be sent from the main control board 200 to the payout control board 400. The prize ball number designation command is a command that designates the number of prize balls to be paid out. In this embodiment, the prize ball number designation command designates the payout of n (n=1 to 15) prize balls. The prize ball number designation command is sent when the payout control board 400 executes the payout operation of the prize balls. In addition, in the pachinko machine 1, control commands that specify the occurrence and cancellation of a payout error, the occurrence and cancellation of a full tank error, the occurrence and cancellation of a ball jam error, etc. are set as control commands that are transmitted from the payout control board 400 to the main control board 200. Each control command is transmitted when the occurrence and cancellation of various errors is detected.

[0157] (Processing executed on the main control board 200) Next, the processing executed by the main control board 200 will be described. First, the functions of the hardware configured on the main control board 200 will be described. When the power supply to the pachinko machine 1 is turned on, the random number generating circuit 203 starts the hardware random number updating process. In the hard random number update process, the values ​​of the first loop counter to the third loop counter are updated by "1" within a predetermined range (in this embodiment, within the range of 0 to 65535) every time one clock is input from the clock generation circuit 202 (in this embodiment, every 0.083 [μs]).

[0158] In addition, in the hard random number update process, the value of the fourth loop counter is updated by "1" within a predetermined range (in this embodiment, within the range of 0 to 10006) every time 32 clocks are input from the clock generation circuit 202 (in this embodiment, every 2.666 [μs]). Then, the winning random number of the normal symbol lottery, the jackpot random number of the first special symbol lottery, the jackpot random number of the second special symbol lottery, and the reach group random number are updated by the hardware random number update process. Note that the hardware random number update process is executed as a function of the random number generation circuit 203 (hardware), and is executed independently of the process executed by the CPU 210 based on software, which will be described later.

[0159] Furthermore, when the power is turned on to the pachinko machine 1, the transmission shift registers of the command output ports 1 and 2 start a control command transmission process to transmit the control commands stored in the FIFO buffer to the performance control board 300 or the payout control board 400. The control command transmission process is executed as a function of the command output ports 1 and 2 (hardware), and is executed independently of the process executed by the CPU 210 based on software, which will be described later.

[0160] Next, a game control process that the CPU 210 of the main control board 200 executes based on a program (software) stored in the ROM 220 will be described.

[0161] (CPU initialization process) First, the CPU initialization process executed by the CPU 210 will be described. FIG. 7 is a flowchart showing the CPU initialization process. When the power is turned on to the pachinko machine 1, the CPU 210 starts the CPU initialization process shown in Fig. 7. The CPU initialization process is a process based on a program for controlling the progress of the game. In other words, the CPU initialization process is a process based on a program stored in the use area m1 (program area) of the ROM 220. When the CPU initialization process starts, the process first proceeds to step S1-1. In step S1-1, an initial setting process is executed, and the process proceeds to step S1-2. In the initial setting process, a boot program is read from the ROM 220, and settings required for executing various processes, such as register settings, are made.

[0162] In the initial setting process, the RAM clear signal from the RAM clear switch 207, the detection signal from the setting key switch 208, and the detection signal from the inner frame opening sensor 108 are read. Specifically, the value set in the receiving storage area corresponding to the RAM clear switch 207 is read twice, and based on the results of the two reads, it is determined whether or not the ON state of the RAM clear switch 207 has occurred. The determination result is then saved as switch information for the RAM clear switch 207. At this time, if it is determined that the ON state has occurred, a value indicating that the ON state has occurred ("1" in this embodiment) is saved as the switch information, and if it is determined that the ON state has not occurred, a value indicating that the ON state has not occurred ("0" in this embodiment) is saved as the switch information.

[0163] Furthermore, the value set in the receiving storage area corresponding to the setting key switch 208 is read twice, and based on the results of the two reads, it is determined whether or not the setting key switch 208 is in an ON state. The determination result is then saved as switch information for the setting key switch 208. At this time, if it is determined that the ON state is in an ON state, a value indicating that the ON state is in an ON state ("1" in this embodiment) is saved as the switch information, and if it is determined that the ON state is not in an ON state, a value indicating that the ON state is not in an ON state ("0" in this embodiment) is saved as the switch information.

[0164] Furthermore, the value set in the receiving memory area corresponding to the inner frame open sensor 108 is read twice, and based on the results of the two reads, it is determined whether or not the inner frame open sensor 108 is in an ON state. If it is determined that the ON state is not occurring, the switch information of the setting key switch 208 is rewritten to a value indicating that the ON state is not occurring ("0" in this embodiment). On the other hand, if it is determined that the ON state is occurring, the switch information of the setting key switch 208 is not rewritten.

[0165] In step S1-2, a wait processing time setting process is executed, and the process proceeds to step S1-3. In the wait processing time setting process, a predetermined wait processing time (3.1 [s] in this embodiment) is set in a timer counter. This causes the timer counter to start measuring the set wait processing time. In step S1-3, it is determined whether the wait processing time set in step S1-2 has elapsed. If it is determined that the wait processing time has elapsed (Yes), the process proceeds to step S1-4. If it is determined that the wait processing time has not elapsed (No), the process of step S1-3 is repeated.

[0166] In step S1-4, RAM access permission processing is performed, and the process proceeds to step S1-5. In the RAM access permission processing, processing required to permit access to the work area of ​​the RAM 230 is performed. Specifically, in the RAM access permission process, a value corresponding to the access permission is stored as a RAM protect value in the RAM access protection area of ​​the RAM 230. This allows the CPU 210 to access the RAM 230.

[0167] In step S1-5, a gaming machine status flag acquisition process is executed, and the process proceeds to step S1-6. In the gaming machine status flag acquisition process, a gaming machine status flag is acquired. Specifically, in the gaming machine status flag acquisition process, the value (gaming machine status flag) stored in the gaming machine status flag area of ​​the RAM 230 is saved (loaded) into the D register. In step S1-6, it is determined whether the backup valid flag is normal or not. If it is determined that the backup valid flag is normal (Yes), the process proceeds to step S1-7. If it is determined that the backup valid flag is not normal (No), the process proceeds to step S1-18. Here, if the value (backup valid flag) stored in the backup valid flag area of ​​RAM 230 is a predetermined valid value, the backup valid flag is determined to be normal, and if the value stored in the backup valid flag area is not the predetermined valid value, the backup valid flag is determined to be abnormal.

[0168] In step S1-7, a checksum calculation process is executed, and the process proceeds to step S1-8. In the checksum calculation process, a checksum is calculated based on the backup information. Specifically, in the checksum calculation process, first, a checksum is calculated based on the information stored in the used area M1 (F000H to F1FFH) of the RAM 230 out of the backup information. Next, a checksum is calculated based on the information stored in the unused area M2 (F300H to F3FFH) of the RAM 230 out of the backup information.

[0169] In step S1-8, it is determined whether the checksum calculated in step S1-7 is normal. If it is determined that the checksum is normal (Yes), the process proceeds to step S1-9. If it is determined that the checksum is not normal (No), the process proceeds to step S1-18. Here, if both of the following conditions are met: "The checksum value of the used area M1 calculated in step S1-7 matches the checksum value of the used area M1 stored in the checksum area of ​​RAM 230" and "The checksum value of the unused area M2 calculated in step S1-7 matches the checksum value of the unused area M2 stored in the checksum area," the checksum is determined to be normal. On the other hand, if at least one of the following conditions is not met: "The checksum value of the used area M1 calculated in step S1-7 matches the checksum value of the used area M1 stored in the checksum area of ​​RAM 230" and "The checksum value of the unused area M2 calculated in step S1-7 matches the checksum value of the unused area M2 stored in the checksum area," the checksum is determined to be abnormal.

[0170] In step S1-9, a process for setting an area to be cleared when power is turned on is executed, and the process proceeds to step S1-10. In the process for setting an area to be cleared when power is turned on, the range to be cleared (initialized) in the used area M1 of the RAM 230 is set to include areas other than the set value area and the gaming machine status flag area (specifically, the checksum area, the backup valid flag area, the error-related area, the normal game-related area 1, the normal game-related area 2, and the stack area). In step S1-10, it is determined whether the RAM clear switch 207 is in an ON state. If it is determined that the ON state is not occurring (No), the process proceeds to step S1-11. If it is determined that the ON state is occurring (Yes), the process proceeds to step S1-21. Here, based on the switch information of the RAM clear switch 207 saved in step S1-1, it is determined whether or not an ON state has occurred for the RAM clear switch 207. At this time, if a value indicating that an ON state has occurred is saved as the switch information, it is determined that an ON state has occurred, and if a value indicating that an ON state has not occurred is saved, it is determined that an ON state has not occurred.

[0171] In step S1-11, it is determined whether a playable state has occurred (set), and if it is determined that a playable state has occurred (Yes), the process proceeds to step S1-12, and if it is determined that a playable state has not occurred (No), the process proceeds to step S1-14. Here, it is determined whether or not a playable state has occurred based on the gaming machine state flag stored in the D register. At this time, if the gaming machine state flag stored in the D register is a value corresponding to the playable state, it is determined that the playable state has occurred, and if the value is not corresponding to the playable state, it is determined that the playable state has not occurred.

[0172] In step S1-12, it is determined whether the setting confirmation condition is met, and if it is determined that the setting confirmation condition is met (Yes), the process proceeds to step S1-13, and if it is determined that the setting confirmation condition is not met (No), the process proceeds to step S1-14. The "setting confirmation condition" is met when a playable state has occurred, the RAM clear switch 207 is not in the on state, the setting key switch 208 is in the on state, and the inner frame open sensor 108 is in the on state. Here, in step S1-1, if the inner frame open sensor 108 is not in an ON state, the switch information of the setting key switch 208 is rewritten to a value indicating that the ON state is not occurring. As a result, if the ON state is occurring for both the setting key switch 208 and the inner frame open sensor 108, a value indicating that the ON state is occurring is saved as the switch information of the setting key switch 208. On the other hand, if the ON state is not occurring for at least one of the setting key switch 208 and the inner frame open sensor 108, a value indicating that the ON state is not occurring is saved as the switch information of the setting key switch 208. Therefore, in step S1-12, it is determined whether or not the setting confirmation condition is met based on the switch information of the setting key switch 208 saved in step S1-1. At this time, if a value indicating that an ON state has occurred is saved as the switch information, it is determined that the setting confirmation condition is met, and if a value indicating that an ON state has not occurred is saved, it is determined that the setting confirmation condition is not met.

[0173] In step S1-13, a setting confirmation state setting process is executed, and the process proceeds to step S1-14. In the setting confirmation state setting process, a value corresponding to the setting value confirmation state is set as the gaming machine state flag in the D register. In step S1-14, a process for setting an area to be cleared when the power is restored is executed, and the process proceeds to step S1-15. In the process for setting an area to be cleared when the power is restored, the range to be cleared (initialized) in the used area M1 of the RAM 230 is set to include the set value area, the gaming machine status flag area, the normal game related area 2, and other areas excluding the stack area (specifically, the checksum area, the backup valid flag area, the error related area, and the normal game related area 1).

[0174] In step S1-15, power restoration initialization processing is executed, and the process proceeds to step S1-16. In the power restoration initialization processing, the range set in step S1-14 of the used area M1 of RAM 230 is cleared (initialized). In step S1-16, a subcommand transmission process upon power recovery is executed, and the process proceeds to step S1-17. In the subcommand transmission process upon power recovery, a subcommand (power recovery designation command) specifying that power has recovered from a power outage is stored in the subcommand output request buffer of RAM 230. In step S1-17, a dispensing command transmission process is executed when the power is restored, and the process proceeds to step S1-32. In the dispensing command transmission process when the power is restored, a dispensing command specifying that the power has been restored from a power cut is stored in the dispensing command output request buffer of RAM 230.

[0175] In step S1-18, a backup abnormal state setting process is executed, and the process proceeds to step S1-19. In the backup abnormal state setting process, a value corresponding to the backup abnormal state is set as the gaming machine state flag in the D register. In step S1-19, an unused area read / write check process is executed, and the process proceeds to step S1-20. In the unused area read / write check process, the unused area M2 of the RAM 230 is cleared (initialized) and a read / write check is performed. In step S1-20, an area to be cleared in an abnormal event setting process is executed, and the process proceeds to step S1-21. In the area to be cleared in an abnormal event setting process, all areas (specifically, the set value area, gaming machine status flag area, checksum area, backup valid flag area, error-related area, normal game-related area 1, normal game-related area 2, and stack area) are set as the range to be cleared (initialized) in the used area M1 of the RAM 230. In step S1-21, a used area read / write check process is executed, and the process proceeds to step S1-22. In the used area read / write check process, the range of the used area M1 of RAM 230 set in step S1-20 is cleared (initialized) and a read / write check is performed.

[0176] In step S1-22, it is determined whether the results of the read / write checks performed in steps S1-19 and S1-21 are normal. If it is determined that the results of the read / write checks are not normal (No), the process proceeds to step S1-23. If it is determined that the results of the read / write checks are normal (Yes), the process proceeds to step S1-24. In step S1-23, a RAM abnormal state setting process is executed, and the process proceeds to step S1- 28. In the RAM abnormal state setting process, a value corresponding to the RAM abnormal state is set as the gaming machine state flag in the D register. In step S1-24, it is determined whether a setting confirmation state has occurred (set), and if it is determined that a setting confirmation state has occurred (Yes), it proceeds to step S1-25, and if it is determined that a setting confirmation state has not occurred (No), it proceeds to step S1-26. Here, it is determined whether or not the setting confirmation state has occurred based on the gaming machine state flag stored in the D register. At this time, if the gaming machine state flag stored in the D register is a value corresponding to the setting confirmation state, it is determined that the setting confirmation state has occurred, and if the value is not corresponding to the setting confirmation state, it is determined that the setting confirmation state has not occurred. In step S1-25, a game-ready state setting process is executed, and the process proceeds to step S1-26. In the game-ready state setting process, a value corresponding to the game-ready state is set as the gaming machine state flag in the D register.

[0177] In step S1-26, it is determined whether the setting change condition is met, and if it is determined that the setting change condition is met (Yes), it proceeds to step S1-27, and if it is determined that the setting change condition is not met (No), it proceeds to step S1-28. The "setting change condition" is met when the RAM clear switch 207 is in the on state, the setting key switch 208 is in the on state, and the inner frame open sensor 108 is in the on state. Here, as described above, when the ON state occurs for both the setting key switch 208 and the inner frame open sensor 108, a value indicating that the ON state has occurred is saved as the switch information for the setting key switch 208. On the other hand, when the ON state has not occurred for at least one of the setting key switch 208 and the inner frame open sensor 108, a value indicating that the ON state has not occurred is saved as the switch information for the setting key switch 208. Therefore, in step S1-26, it is determined whether or not the setting change conditions are met based on the switch information of the RAM clear switch 207 and the switch information of the setting key switch 208 saved in step S1-1. At this time, if values ​​indicating that an ON state has occurred are stored for both the switch information of the RAM clear switch 207 and the switch information of the setting key switch 208, it is determined that the setting change condition is met. On the other hand, if a value indicating that an ON state has not occurred is stored for at least one of the switch information of the RAM clear switch 207 and the switch information of the setting key switch 208, it is determined that the setting change condition is not met.

[0178] In step S1-27, a setting change state setting process is executed, and the process proceeds to step S1-28. In the setting change state setting process, a value corresponding to the setting change state is set as the gaming machine state flag in the D register. In step S1-28, a gaming machine status flag saving process is executed, and the process proceeds to step S1-29. In the gaming machine status flag saving process, the gaming machine status flag set in the D register is saved in the gaming machine status flag area of ​​the RAM 230. In step S1-29, a RAM clear subcommand transmission process is executed, and the process proceeds to step S1-30. In the RAM clear subcommand transmission process, a subcommand (RAM clear designation command) specifying that RAM clear has been executed is stored in the subcommand output request buffer of RAM 230. In step S1-30, RAM clear initialization processing is executed, and the process proceeds to step S1-31. In the RAM clear initialization processing, the range set in step S1-9 or step S1-20 of the used area M1 of the RAM 230 is cleared (initialized). In step S1-31, a RAM clearing dispensing command sending process is executed, and the process proceeds to step S1-32. In the RAM clearing dispensing command sending process, a dispensing command specifying that RAM clearing has been executed is stored in the dispensing command output request buffer of RAM 230.

[0179] In step S1-32, a subcommand setting process is executed, and the process proceeds to step S1-33. In the subcommand setting process, a power-on gaming machine state designation command that designates the current gaming machine state is stored in the subcommand output request buffer of the RAM 230. Specifically, in the subcommand setting process, a power-on gaming machine state designation command that specifies the gaming machine state flag (gaming machine state) stored in the gaming machine state flag area of ​​RAM230 is stored in the subcommand output request buffer of RAM230. In step S1-33, a sub-command group setting process is executed, and the process proceeds to step S1-34. In the sub-command group setting process, the sub-command group is stored in the sub-command output request buffer of the RAM 230. Here, the group of subcommands includes a subcommand for specifying the phase when power is restored, a subcommand for specifying the game state (game state offset value), a subcommand for specifying the launch position, a subcommand for specifying the stopping pattern of the first special pattern, a subcommand for specifying the stopping pattern of the second special pattern, a subcommand for specifying the number of reserved special patterns 1, a subcommand for specifying the number of reserved special patterns 2, a subcommand for specifying the value of the time-saving counter, a setting value specification command for specifying the setting value stored in the setting value area of ​​RAM230, etc.

[0180] In step S1-34, an initial display time setting process is executed, and the process proceeds to step S1-35. In the initial display time setting process, the initial display time of the performance display device 206 is set in the initial display timer. In step S1-35, an interrupt setting process is executed, and the process proceeds to the main loop process (step S2-1). In the interrupt setting process, the CTC (counter / timer circuit), which is a peripheral device, is initialized. Specifically, in the interrupt setting process, an interrupt vector register is set, and an interrupt count value (4.0 [ms] in this embodiment) is set in the CTC.

[0181] (Main loop processing) Next, the main loop process executed by the CPU 210 will be described. FIG. 8 is a flowchart showing the main loop process. When the CPU initialization process (step S1-35) shown in Fig. 7 ends, the CPU 210 starts the main loop process shown in Fig. 8. The main loop process is based on a program for controlling the progress of the game. That is, the main loop process is based on a program stored in the use area m1 (program area) of the ROM 220. When the main loop process starts, the process first proceeds to step S2-1. In step S2-1, an interrupt disable process is executed, and then the process proceeds to step S2-2. In the interrupt disable process, an interrupt disable state is set, which disables interrupts from other processes. As a result, while the interrupt disable state is set, the execution of the power-off save process, timer interrupt process, etc., which will be described later, is prohibited. In step S2-2, an initial value random number update process is executed, and the process proceeds to step S2-3. In the initial value random number update process, the value of a loop counter for generating an initial value random number is updated. Here, "initial value random number" refers to a random number used to determine the initial value and end value of software random numbers (winning pattern random number, reach mode random number, variable pattern random number, etc.), which are random numbers generated on the program. That is, the value of the loop counter that generates the soft random number is updated within a preset range from the initial value to the end value. The initial value and end value of the loop counter that generates the soft random number are changed each time the value of the loop counter reaches the end value. At this time, the initial value and end value of the loop counter are determined based on the initial value random number.

[0182] In step S2-3, a main command analysis process is executed, and then the process proceeds to step S2-4. In the main command analysis process, the main command received from the dispensing control board 400 (the control command sent from the dispensing control board 400 to the main control board 200) is analyzed, and processing according to the analysis result is executed. In step S2-4, a subcommand transmission process is executed, and the process proceeds to step S2-5. In the subcommand transmission process, the subcommand stored in the subcommand output request buffer of RAM 230 is output to the transmission data register of output port 205 (command output port 1). As a result, the sub-commands input to the transmission data register are stored in the FIFO buffer. The sub-commands stored in the FIFO buffer are then transmitted to the performance control board 300 in a predetermined order by the transmission shift register. In step S2-5, an interrupt enable process is executed, and the process proceeds to step S2-6. In the interrupt enable process, the interrupt disable state is released. As a result, the period from when the interrupt enable process in step S2-5 is executed until when the interrupt disable process in step S2-1 is executed becomes an interrupt enable period in which the execution of power-off save process, timer interrupt process, etc. is permitted. In step S2-6, other random number update processing is executed, and the process proceeds to step S2-1. In the other random number update processing, software random numbers excluding winning symbol random numbers (specifically, reach mode random numbers, variable pattern random numbers, etc.) are updated.

[0183] (Evacuation process when power is cut off) Next, the power-off save process executed by the CPU 210 will be described. FIG. 9 is a flowchart showing the save process when power is cut off. The main control board 200 is configured to include a power interruption detection circuit (not shown). The power interruption detection circuit monitors the power supply voltage supplied from the power supply board 600, and outputs a power interruption warning signal to the input port 204 when the power supply voltage value falls below a predetermined reference value. When the CPU 210 receives the power cutoff warning signal, it starts the power cutoff save process shown in Fig. 9 during the interruption permitted period of the main loop process. The power cutoff save process is a process based on a program for controlling the progress of the game. In other words, the power cutoff save process is a process based on a program stored in the use area m1 (program area) of the ROM 220.

[0184] When the power-off save process is started, the process first proceeds to step S3-1. In step S3-1, a register save process is executed, and the process proceeds to step S3-2. In the register save process, the values ​​of the registers used during the execution of the main loop process are saved in a save area of ​​the RAM 230. In step S3-2, a power cutoff notice signal is read, and the process proceeds to step S3-3. In the power cutoff notice signal read process, the power cutoff notice signal is read from the power cutoff detection circuit. Specifically, in the power cutoff notice signal reading process, the value ("1" or "0") set in the reception storage area of ​​the input port 204 corresponding to the power cutoff notice signal is read. In step S3-3, based on the value read in step S3-2 (the value set in the receiving memory area corresponding to the power cutoff warning signal), it is determined whether or not a power cutoff warning signal has been input from the power cutoff detection circuit. If it is determined that a power cutoff warning signal has been input (Yes), the process proceeds to step S3-4; if it is determined that a power cutoff warning signal has not been input (No), the process proceeds to step S3-13.

[0185] In step S3-4, output port stop processing is executed, and the process proceeds to step S3-5. In the output port stop processing, the output of control signals and control commands by the output ports 205 (output ports 0 to 4) is stopped. Specifically, in the output port stopping process, the values ​​of all bits included in the port registers of the output ports 205 (output ports 0 to 4) are initialized, thereby stopping the output of control signals and control commands by the output ports 205 (output ports 0 to 4). In step S3-5, a backup valid flag setting process is executed, and the process proceeds to step S3-6. In the backup valid flag setting process, a predetermined valid value is saved in the backup valid flag area of ​​the RAM 230.

[0186] In step S3-6, a checksum storage process is executed, and the process proceeds to step S3-7. In the checksum storage process, a checksum is calculated and stored. Specifically, in the checksum saving process, first, a checksum is calculated based on the information stored in the used area M1 (F000H to F1FFH) of the RAM 230. Then, the calculated checksum value is saved in the checksum area of ​​the RAM 230. Next, a checksum is calculated based on the information stored in the unused area M2 (F300H to F3FFH) of the RAM 230. Then, the calculated checksum value is saved in the checksum area. In step S3-7, RAM access prohibition processing is executed, and the process proceeds to step S3-8. In the RAM access prohibition processing, processing for prohibiting access to the RAM 230 is executed. Specifically, in the RAM access prohibition process, a value corresponding to the access prohibition is stored as a RAM protect value in the RAM access protection area of ​​the RAM 230. As a result, access to the RAM 230 by the CPU 210 is prohibited.

[0187] In step S3-8, a loop counter setting process is executed, and the process proceeds to step S3-9. In the loop counter setting process, a predetermined number of times the power cutoff notice signal has been read is set as the value of the loop counter for recovery determination. In step S3-9, a power cutoff notice signal is read, and the process proceeds to step S3-10. In the power cutoff notice signal read process, the power cutoff notice signal is read from the power cutoff detection circuit. Specifically, in the power cutoff notice signal reading process, the value ("1" or "0") set in the reception storage area of ​​the input port 204 corresponding to the power cutoff notice signal is read. In step S3-10, based on the value read in step S3-9 (the value set in the receiving memory area corresponding to the power cutoff warning signal), it is determined whether or not a power cutoff warning signal has been input from the power cutoff detection circuit.If it is determined that a power cutoff warning signal has not been input (No), the process proceeds to step S3-11; if it is determined that a power cutoff warning signal has been input (Yes), the process proceeds to step S3-8.

[0188] In step S3-11, a loop counter update process is executed, and the process proceeds to step S3-12. In the loop counter update process, "1" is subtracted from the value set in the return determination loop counter. In step S3-12, it is determined whether the value of the loop counter for determining recovery is "0" or not. If it is determined that the value of the loop counter for determining recovery is "0" (Yes), the process proceeds to CPU initialization processing (step S1-1). If it is determined that the value of the loop counter for determining recovery is not "0" (No), the process proceeds to step S3-9. In step S3-13, register restoration processing is executed, the series of processing is terminated, and the program returns to the original processing. In the register restoration processing, the register values ​​saved in step S3-1 are restored. Then, after the register restoration processing is completed, the program returns to the main loop processing (the program address indicated by the stack pointer).

[0189] (Timer interrupt processing) Next, the timer interrupt process executed by the CPU 210 will be described. FIG. 10 is a flowchart showing the timer interrupt process. The clock generation circuit 202 generates an interrupt request signal at a predetermined interrupt period (4.0 ms in this embodiment). In response to the generation of an interrupt request signal, the CPU 210 starts the timer interrupt process shown in Fig. 10 during the interrupt permission period of the main loop process. The main loop process is based on a program for controlling the progress of the game. In other words, the main loop process is based on a program stored in the use area m1 (program area) of the ROM 220.

[0190] When the timer interrupt process is started, the process first proceeds to step S4-1. In step S4-1, a register save process is executed, and the process proceeds to step S4-2. In the register save process, the values ​​of all registers used during execution of the main loop process are saved in a save area in the RAM 230. In step S4-2, an interrupt permission process is executed, and the process proceeds to step S4-3. In the interrupt permission process, an interrupt is permitted. In step S4-3, dynamic port output processing is executed, and the process proceeds to step S4-4, which will be described later.

[0191] In step S4-4, port input processing is executed, and the process proceeds to step S4-5. In the port input processing, the state of each switch / sensor (each signal) is acquired. The RAM 230 has an input information storage area corresponding to each switch / sensor (each signal input to the input port 204) connected to the input port 204 (input port 0 to input port 3), and an on-state storage area corresponding to each switch / sensor (each signal input to the input port 204) connected to the input port 204 (input port 0 to input port 3). In the port input process, first, for each switch / sensor connected to input port 204 (input port 0 to input port 3), the information set in the receiving memory area corresponding to that switch / sensor is obtained, and the obtained information is saved (stored) in the input information memory area corresponding to that switch / sensor. As a result, for each switch sensor, if a detection signal is input from that switch sensor (high level), a "1" is stored in the input information memory area corresponding to that switch sensor, and if a detection signal is not input from that switch sensor (low level), a "0" is stored in the input memory area corresponding to that switch sensor.

[0192] Next, it is determined whether or not an ON state has occurred for each switch / sensor connected to input port 204 (input port 0 to input port 3). At this time, it is determined whether or not an ON state has occurred for each switch / sensor based on the value saved in the input information storage area in the previous port input process and the value saved in the input information storage area in the current port input process. The "on state" refers to a state in which the state has changed from a state in which no detection signal is being input (low level) to a state in which the detection signal is being input (high level). If it is determined that an ON state has occurred for each switch / sensor, "1" is set in the ON state storage area corresponding to that switch / sensor. On the other hand, if it is determined that an ON state has not occurred for each switch / sensor, "0" is set in the ON state storage area corresponding to that switch / sensor. In the following explanation, the value stored in the ON state storage area corresponding to each switch / sensor is referred to as the "switch bit data" of that switch / sensor. In particular, input port 1 is provided with a reception storage area corresponding to the handle detection signal input from launch enable condition detection unit 422. Then, in the port input process, information set in the reception storage area corresponding to the handle detection signal of input port 1 is acquired, and the acquired information is saved (stored) in the input information storage area corresponding to the handle detection signal.

[0193] In step S4-5, a gaming machine status flag acquisition process is executed, and the process proceeds to step S4-6. In the gaming machine status flag acquisition process, the gaming machine status flag stored in the gaming machine status flag area of ​​the RAM 230 is acquired. In step S4-6, it is determined whether a playable state has occurred (set), and if it is determined that a playable state has not occurred (No), the process proceeds to step S4-7, and if it is determined that a playable state has occurred (Yes), the process proceeds to step S4-9. Here, it is determined whether or not a playable state has occurred based on the gaming machine state flag acquired in step S4-5. At this time, if the acquired gaming machine state flag has a value corresponding to the playable state, it is determined that the playable state has occurred, and if the value does not correspond to the playable state, it is determined that the playable state has not occurred.

[0194] In step S4-7, it is determined whether an abnormal condition has occurred (set), and if it is determined that an abnormal condition has not occurred (No), the process proceeds to step S4-8, and if it is determined that an abnormal condition has occurred (Yes), the process proceeds to step S4-19. Here, it is determined whether an abnormal state has occurred based on the gaming machine status flag acquired in step S4-5. At this time, if the acquired gaming machine status flag is a value corresponding to any of the setting abnormal state, RAM abnormal state, and backup abnormal state, it is determined that an abnormal state has occurred. If the acquired gaming machine status flag is not a value corresponding to any of the setting abnormal state, RAM abnormal state, and backup abnormal state, it is determined that an abnormal state has not occurred.

[0195] In step S4-8, a setting-related process is executed, and the process proceeds to step S4-19, which will be described later. In step S4-9, a timer update process is executed, and the process proceeds to step S4-10. In the timer update process, various timers are updated. Specifically, the timer update process updates the values ​​of various timer counters (special game timer, normal game timer, security timer, etc.). In step S4-10, an initial value random number update process is executed, and the process proceeds to step S4-11. The initial value random number update process in step S4-10 is the same process as the initial value random number update process in step S2-2. Specifically, in the initial value random number update process, the value of the loop counter for generating the initial value random number is updated. In step S4-11, a winning symbol random number update process is executed, and the process proceeds to step S4-12. In the winning symbol random number update process, the value of the loop counter for generating the winning symbol random number among the software random numbers is updated. In step S4-12, a switch management process is executed, and the process proceeds to step S4-13. In the switch management process, processes (such as obtaining various random numbers) are executed according to the state (whether or not an ON state is detected) of each switch 101, 102, 104. The switch management process will be described later.

[0196] In step S4-13, a special game management process is executed, and the process proceeds to step S4-14. In the special game management process, the operation of the special symbol display device and the operation of the special electric accessory 53a are managed. The special game management process will be described later. In step S4-14, a normal game management process is executed, and the process proceeds to step S4-15. In the normal game management process, the operation of the normal map display device and the operation of the normal electric accessory 52a are managed. The normal game management process will be described later.

[0197] In step S4-15, a status management process is executed, and the process proceeds to step S4-16. In the status management process, the occurrence and release of various errors (abnormal states) is monitored. When the occurrence and release of various errors is detected, various settings (such as setting of subcommands) are executed. Furthermore, in the state management process, it is determined whether the handle detection signal has changed from a state where it is not input to a state where it is input, based on the value stored in the input information storage area corresponding to the handle detection signal (the value stored in the previous timer interrupt process and the value stored in the current timer interrupt process). If it is determined that the handle detection signal has changed from a state where it is not input to a state where it is input, a game status designation command that designates the occurrence of a launchable state is stored in the subcommand output request buffer of RAM 230. Furthermore, in the state management process, it is determined whether the handle detection signal has changed from an input state to an input state based on the value stored in the input information storage area corresponding to the handle detection signal (the value stored in the previous timer interrupt process and the value stored in the current timer interrupt process). Then, if it is determined that the handle detection signal has changed from an input state to an input state, a game status designation command that designates the release of the launch-enabled state is stored in the subcommand output request buffer of RAM 230. In step S4-16, a prize opening switch process is executed, and the process proceeds to step S4-17. In the prize opening switch process, processes (such as updating various counters) are executed according to the state of each switch 101 to 103, 105, 106 (whether or not the on state is detected).

[0198] In step S4-17, the payout control management process is executed, and the process proceeds to step S4-18. In the payout control management process, a payout command is generated based on the value of the prize ball control counter set in step S4-16, and the generated payout command is sent. In this embodiment, the prize ball control counters include prize ball control counter 1 which stores the number of game balls that have entered the large prize opening 53, prize ball control counter 2 which stores the number of game balls that have entered the right other prize opening 54, prize ball control counter 3 which stores the number of game balls that have entered the upper left, middle left and lower left other prize openings 55-57, prize ball control counter 4 which stores the number of game balls that have entered the first start opening 51, and prize ball control counter 5 which stores the number of game balls that have entered the second start opening 52. In the payout control management process, first, it is determined whether the value of the prize ball control counter 1 is equal to or greater than "1". If it is determined that the value of the prize ball control counter 1 is equal to or greater than "1", a payout command specifying the payout of a predetermined number of prize balls (15 balls in this embodiment) is generated, and the generated payout command is stored in the payout command output request buffer of the RAM 230. As a result, a payout command specifying the payout of the predetermined number of prize balls is transmitted to the payout control board 400. Thereafter, when the payout of the prize balls by the game ball payout device 440 is completed, the payout control board 400 transmits a main command specifying the completion of the payout to the main control board 200. Then, in response to receiving the main command specifying the completion of the payout, "1" is subtracted from the value of the prize ball control counter 1.

[0199] Next, it is determined whether the value of the prize ball control counter 2 is "1" or greater. If it is determined that the value of the prize ball control counter 2 is "1" or greater, a payout command specifying the payout of a predetermined number of prize balls (10 balls in this embodiment) is generated, and the generated payout command is stored in the payout command output request buffer of RAM 230. As a result, a payout command specifying the payout of a predetermined number of prize balls is sent to the payout control board 400. Thereafter, "1" is subtracted from the value of the prize ball control counter 2 in response to the reception of a main command specifying the completion of the payout. Next, it is determined whether the value of the prize ball control counter 3 is "1" or greater. If it is determined that the value of the prize ball control counter 3 is "1" or greater, a payout command specifying the payout of a predetermined number of prize balls (10 balls in this embodiment) is generated, and the generated payout command is stored in the payout command output request buffer of RAM 230. As a result, a payout command specifying the payout of a predetermined number of prize balls is sent to the payout control board 400. Thereafter, "1" is subtracted from the value of the prize ball control counter 3 in response to receiving a main command specifying the completion of the payout.

[0200] Next, it is determined whether the value of the prize ball control counter 4 is "1" or greater. If it is determined that the value of the prize ball control counter 4 is "1" or greater, a payout command specifying the payout of a predetermined number of prize balls (in this embodiment, 3 [balls]) is generated, and the generated payout command is stored in the payout command output request buffer of RAM 230. As a result, a payout command specifying the payout of a predetermined number of prize balls is sent to the payout control board 400. Thereafter, "1" is subtracted from the value of the prize ball control counter 4 in response to the reception of a main command specifying the completion of the payout. Next, it is determined whether the value of the prize ball control counter 5 is "1" or greater. If it is determined that the value of the prize ball control counter 5 is "1" or greater, a payout command specifying the payout of a predetermined number of prize balls (in this embodiment, 1 [ball]) is generated, and the generated payout command is stored in the payout command output request buffer of RAM 230. As a result, a payout command specifying the payout of a predetermined number of prize balls is sent to the payout control board 400. Thereafter, "1" is subtracted from the value of the prize ball control counter 5 in response to receiving a main command specifying the completion of the payout.

[0201] In step S4-18, a launch position designation management process is executed, and the process proceeds to step S4-19. In the launch position designation management process, processing related to the designation of the launch position is executed. Specifically, in the launch position designation management process, when a state is changed from one in which the launch of the game ball to the left path is designated to one in which the launch of the game ball to the right path is designated (such as when a jackpot game state starts), the launch position designation flag area of ​​the RAM 230 is set to "1," and a subcommand designating the launch of the game ball to the right path is stored in the subcommand output request buffer of the RAM 230. As a result, the subcommand designating the launch of the game ball to the right path is transmitted to the performance control board 300. On the other hand, when the state changes from specifying the launch of the game ball onto the right path to specifying the launch of the game ball onto the left path (such as when the time-saving control ends), the launch position designation flag area of ​​RAM230 is set to "0".

[0202] In step S4-19, an external information management process is executed, and the process proceeds to step S4-20. In the external information management process, external information (external signals) to be output to the hall computer (or data display device) is set. In this embodiment, the external information output from the pachinko machine 1 to an external device (electronic device such as a hall computer or data display device) includes information on the number of times a pattern has been determined, information on the starting port, information on a jackpot, security information, information on the number of payouts from the outlet, information on error occurrence, etc. The "information on the number of times that the symbol has been determined" is external information on the number of times that the special symbol lottery (variable display and stop display of the special symbol) has been executed. The CPU 210 outputs an external signal corresponding to the information on the number of times that the symbol has been determined to the hall computer (or data display device) every time the number of times that the special symbol has been stopped has reached a predetermined number.

[0203] The "start gate information" is external information relating to the entry of game balls into the start gates 51 and 52. Every time the CPU 210 detects the on state of the detection signal input from the start gate switches 101 and 102, it outputs an external signal corresponding to the start gate information to the hall computer (or data display device). The "jackpot information" is external information relating to the occurrence of a jackpot gaming state. Each time a jackpot gaming state occurs, the main control board 200 outputs an external signal corresponding to the jackpot information to the hall computer (or data display device). The "outlet payout information" is external information relating to the number of game balls discharged from the discharge path (or the number of game balls discharged from the outlet 58). Each time the value of the external information out ball number counter reaches a predetermined value, the CPU 210 outputs an external signal corresponding to the outlet payout number information to the hall computer. The "security information" is external information indicating that a setting change state, a setting confirmation state, or various errors (abnormalities) are occurring. When the value of the security timer is "1" or greater, the CPU 210 outputs an external signal corresponding to the security information to the hall computer.

[0204] In the external information management process, it is determined whether the value of the external information determination number counter has reached a predetermined value (1 [time] in this embodiment). If it is determined that the value of the external information determination number counter has reached the predetermined value, the symbol determination number information (external signal) is stored in the port output request buffer of RAM 230. Then, the predetermined value (1 [time] in this embodiment) is subtracted from the value of the external information determination number counter. As a result, the symbol determination number information (external signal) is output to the hall computer. Furthermore, in the external information management process, it is determined whether the value of the external information start gate ball scoring count counter has reached a predetermined value (1 [time] in this embodiment). If it is determined that the value of the external information start gate ball scoring count counter has reached the predetermined value, the start gate information (external signal) is stored in the port output request buffer of RAM 230. Then, a predetermined value (1 [time] in this embodiment) is subtracted from the value of the external information start gate ball scoring count counter. As a result, the start gate information (external signal) is output to the hall computer.

[0205] Furthermore, in the external information management process, it is determined whether the value of the external information jackpot count counter has reached a predetermined value (1 [time] in this embodiment). If it is determined that the value of the external information jackpot count counter has reached the predetermined value, the jackpot information (external signal) is stored in the port output request buffer of RAM 230. After that, the predetermined value (1 [time] in this embodiment) is subtracted from the value of the external information jackpot count counter. As a result, the jackpot information (external signal) is output to the hall computer. Furthermore, in the external information management process, it is determined whether the value of the out balls counter for external information has reached a predetermined value (10 [balls] in this embodiment). If it is determined that the value of the out balls counter for external information has reached the predetermined value, the out port payout information (external signal) is stored in the port output request buffer of RAM 230. Then, the predetermined value (10 [balls] in this embodiment) is subtracted from the value of the out balls counter for external information. As a result, the out port payout information (external signal) is output to the hall computer.

[0206] In addition, in the external information management process, it is determined whether or not the value (gaming machine state flag) stored in the gaming machine state flag area of ​​the RAM 230 is a value corresponding to a playable state. If it is determined that the value stored in the gaming machine status flag area is not a value corresponding to a playable status (i.e., it is determined that the value corresponds to a setting change status, a setting confirmation status, a setting abnormal status, a RAM abnormal status, or a backup abnormal status), the security information is stored in the port output request buffer of the RAM 230. As a result, the security information (external signal) is output to the hall computer. Furthermore, in the external information management process, it is determined whether the value of the security timer is equal to or greater than "1." If it is determined that the value of the security timer is equal to or greater than "1," the security information is stored in the port output request buffer of RAM 230. As a result, the security information (external signal) is output to the hall computer.

[0207] In step S4-20, an LED display setting process is executed, and the process proceeds to step S4-21. In the LED display setting process, display data to be output to the main display device 60 or the performance display device 206 is set. The RAM 230 is provided with a common 0 output request buffer (8 bits), a common 1 output request buffer (8 bits), a common 2 output request buffer (8 bits), and a common 3 output request buffer (8 bits). In the LED display setting process, first, the common 2 output request buffer is cleared (initialized), and then the common 3 output request buffer is cleared (initialized). Specifically, each bit value of the common 2 output request buffer is set to "0", and each bit value of the common 3 output request buffer is set to "0".

[0208] Next, the gaming machine status flag stored in the gaming machine status flag area of ​​the RAM 230 is obtained. Then, if the acquired gaming machine status flag is a value corresponding to a playable state, a normal time display data setting process described later is executed. On the other hand, if the acquired gaming machine status flag is a value corresponding to a setting change state, a setting change time display data setting process described later is executed. On the other hand, if the acquired gaming machine status flag is a value corresponding to a setting confirmation state, a setting confirmation time display data setting process described later is executed. On the other hand, if the acquired gaming machine status flag is a value corresponding to an abnormal state (setting abnormal state, RAM abnormal state, or backup abnormal state), an abnormal time display data setting process described later is executed.

[0209] In the normal display data setting process, first, the value of the special chart 1 display pattern counter is obtained, and the display data (8 bits) corresponding to the obtained value of the special chart 1 display pattern counter is set in the common 0 output request buffer. As a result, among the light-emitting elements constituting the main display device 60, LED1 to LED8 display the first special symbol. Next, the value of the special chart 2 display pattern counter is obtained, and the display data (8 bits) corresponding to the obtained value of the special chart 2 display pattern counter is set in the common 1 output request buffer. As a result, among the light-emitting elements constituting the main display device 60, the LED9 to LED16 display the second special symbol. Next, the value of the normal map display pattern counter is acquired, and the display data corresponding to the acquired value of the normal map display pattern counter is set as output data a.

[0210] Next, it is determined whether the value set in the special game phase flag area of ​​RAM230 is a value that specifies one of the special game phases among "state before opening of large prize opening," "state of controlling opening of large prize opening," "state of enabling closing of large prize opening," and "state of waiting for completion of opening of large prize opening." Then, if it is determined that the value set in the special game phase flag area is a value that specifies one of the special game phases among "state before opening of large prize opening," "state of controlling opening of large prize opening," "state of validity of closing of large prize opening," and "state of waiting for completion of opening of large prize opening," the value set in the special pattern determination flag area of ​​RAM230 (a value corresponding to the type of large prize opening pattern) is obtained, and the display data corresponding to the obtained value is set as output data b. On the other hand, if it is determined that the value set in the special game phase flag area is not a value that specifies one of the special game phases among "state before opening of large prize opening," "state of controlling opening of large prize opening," "state of enabling closing of large prize opening," and "state of waiting for completion of opening of large prize opening," output data b is not set.

[0211] Next, the value set in the launch position designation flag area of ​​the RAM 230 is obtained, and the display data corresponding to the obtained value is set as the output data c. Next, the display data (8 bits) obtained by logically ORing the output data a to output data c is set in the common 2 output request buffer. As a result, of the light-emitting elements that make up the main display device 60, LEDs 17 and 18 display normal symbols, LEDs 19 to 23 display the number of rounds of play to be performed during the jackpot game state (type of jackpot game state), and LED 24 displays the path (left path or right path) along which the game ball should be shot. Next, the value of the special chart 1 reserved number counter is obtained, and the display data corresponding to the obtained value is set as output data d. Next, the value of the special chart 2 reserved number counter is obtained, and the display data corresponding to the obtained value is set as output data e. Next, the value of the normal map reservation number counter is obtained, and the display data corresponding to the obtained value is set as output data f. Next, it is determined whether the power supply has been restored. Then, when it is determined that the power supply has been restored, the value set in the special chart high probability state flag area is acquired, and the display data corresponding to the acquired value is set as output data g. On the other hand, if it is determined that the power supply has not been restored, the output data g is not set. Next, the value set in the time-shortening control flag area of ​​the RAM 230 is obtained, and the display data corresponding to the obtained value is set as the output data h. Next, the display data (8 bits) obtained by logically ORing the output data d to output data h is set in the common 3 output request buffer. As a result, of the light-emitting elements that make up the main display device 60, LEDs 25 and 26 display the number of reserved special charts 1, LEDs 27 and 28 display the number of reserved special charts 2, LEDs 29 and 30 display the number of reserved regular charts, LED 31 displays the game status when power is restored (whether a high probability state for special charts is occurring or a low probability state for special charts is occurring), and LED 32 displays the current game status (whether time-saving control is being executed or stopped).

[0212] In the display data setting process when the setting is changed, information indicating that a setting change state is occurring is set in the common 0 output request buffer to the common 2 output request buffer, and information indicating the setting value stored in the setting value area of ​​RAM 230 is set in the common 3 output request buffer. Specifically, the display data (8 bits) of "r" is set in the common 0 output request buffer, the display data (8 bits) of "n." is set in the common 1 output request buffer, the display data (8 bits) of "-" is set in the common 2 output request buffer, and the display data corresponding to the setting value stored in the setting value area of ​​RAM 230 is set in the common 3 output request buffer. As a result, of the light-emitting elements that make up the performance display device 206, LED33 to LED40 display the letter "r", LED41 to LED48 display the letter "n.", LED49 to LED56 display the letter "-", and LED57 to LED64 display numbers indicating the set value.

[0213] In the display data setting process during setting confirmation, information indicating that the setting confirmation state is occurring is set in the common 0 output request buffer to the common 2 output request buffer, and information indicating the setting value stored in the setting value area of ​​RAM 230 is set in the common 3 output request buffer. Specifically, the display data (8 bits) of "r" is set in the common 0 output request buffer, the display data (8 bits) of "n." is set in the common 1 output request buffer, and the display data corresponding to the setting value stored in the setting value area of ​​RAM 230 is set in the common 3 output request buffer. Note that no display data is set for the common 2 output request buffer (it remains cleared). As a result, of the light-emitting elements that make up the performance display device 206, LED33 to LED40 display the letter "r," LED41 to LED48 display the letter "n," and LED57 to LED64 display numbers that indicate the set value. Note that LED49 to LED56 are turned off.

[0214] In the abnormality display data setting process, information indicating that an abnormal state (setting abnormal state, RAM abnormal state, or backup abnormal state) is occurring is set in the common 0 output request buffer to the common 2 output request buffer, and an error code corresponding to the abnormality that has occurred is set in the common 3 output request buffer. Specifically, the display data (8 bits) for "E" is set in the common 0 output request buffer, the display data (8 bits) for "r." is set in the common 1 output request buffer, and the display data (error code) corresponding to the abnormal state that has occurred (setting abnormal state, RAM abnormal state, or backup abnormal state) is set in the common 3 output request buffer. Note that no display data is set for the common 2 output request buffer (it remains cleared). As a result, among the light-emitting elements that make up the performance display device 206, LED33 to LED40 display the letter "E," LED41 to LED48 display the letter "r," and LED57 to LED64 display numbers that indicate an error code. Note that LED49 to LED56 are turned off.

[0215] In step S4-21, a solenoid data setting process is executed, and the process proceeds to step S4-22. In the solenoid data setting process, the control data (drive data) to be output to each solenoid 64, 65 is stored (set) in the port output request buffer of the RAM 230. In step S4-22, a port output process is executed, and the process proceeds to step S4-23. In the port output process, various signals are output to the hall computer, the solenoids 64, 65, and the like. Specifically, in the port output process, various information (external signals, control signals, etc.) set in the port output request buffer is output to the output port 205 (output port 2, output port 3). As a result, the external signals set in the port output request buffer are output to the hall computer. Also, the solenoids 64, 65 are driven and controlled based on the drive signals set in the port output request buffer. In step S4-23, an interrupt disable process is executed, and the process proceeds to step S4-24. In the interrupt disable process, an interrupt disable state is set, which disables interrupts from other processes. As a result, while the interrupt disable state is set, execution of the power-off save process, timer interrupt process, etc., which will be described later, is prohibited.

[0216] In step S4-24, a test signal output process is executed, and the process proceeds to step S4-25. In the test signal output process, test information (test signal) is set. The test signal output process is based on a program for executing test-related processes stipulated in the gaming machine regulations. That is, the test signal output process is based on a program stored in the unused area m2 (program area) of the ROM 220. The test signal output process is called during execution of the timer interrupt process. Specifically, in the test signal output process, test information (test signal) indicating the internal state (jackpot game state, time-saving control execution state, probability state of special pattern lottery, etc.) is stored in the port output request buffer of RAM230. In step S4-25, a performance display device control process is executed, and the process proceeds to step S4-26, which will be described later. In step S4-26, register restoration processing is executed, the series of processing is terminated, and the program returns to the original processing. In the register restoration processing, the register values ​​saved in step S4-1 are restored. After the register restoration processing is completed, the program returns to the main loop processing (the program address indicated by the stack pointer).

[0217] (Dynamic port output processing) Next, the dynamic port output process in step S4-3 will be described. FIG. 11 is a flowchart showing the dynamic port output process. When the dynamic port output process is executed in step S4-3, the process first proceeds to step S29-1 as shown in FIG. In step S29-1, an output data clear process is executed, and the process proceeds to step S29-2. In the output data clear process, the A register is cleared (initialized). Specifically, each bit value of the A register is set to "0." In step S29-2, a main display device data output process is executed, and the process proceeds to step S29-3. In the main display device data output process, the value of the A register (the value cleared in step S29-1) is output to output port 0. This clears (initializes) output port 0, and each data signal ("SEGDATA0" to "SEGDATA7") for controlling the lighting of the main display device 60 goes low.

[0218] In step S29-3, a performance display device data output process is executed, and the process proceeds to step S29-4. In the performance display device data output process, the value of the A register (the value cleared in step S29-1) is output to output port 4. This clears (initializes) output port 4, and each data signal ("7SEGDATA0" to "7SEGDATA7") for controlling the lighting of the performance display device 206 becomes low level. In step S29-4, a common selection process is executed, and the process proceeds to step S29-5. In the common selection process, the value of the common counter is updated. Specifically, in the common selection process, it is determined whether the value of the common counter has reached an upper limit value ("3" in this embodiment). If it is determined that the value of the common counter has not reached the upper limit value, "1" is added to the value of the common counter. On the other hand, if it is determined that the value of the common counter has reached the upper limit value, a predetermined initial value ("0" in this embodiment) is set as the value of the common counter.

[0219] In step S29-5, a common output process is executed, and the process proceeds to step S29-6. In the common output process, output data corresponding to the value of the common counter is output to output port 1. That is, when the value of the common counter is "0", output data in which "COM0" is at high level and "COM1", "COM2", and "COM3" are at low level is output to output port 1. As a result, "COM0" is selected (output) from among "COM0" to "COM3". On the other hand, if the value of the common counter is "1", output data that sets "COM1" to high level and "COM0", "COM2", and "COM3" to low level is output to output port 1. As a result, "COM1" is selected (output) from among "COM0" to "COM3". On the other hand, if the value of the common counter is "2", output data that sets "COM2" to high level and "COM0", "COM1", and "COM3" to low level is output to output port 1. As a result, "COM2" is selected (output) from among "COM0" to "COM3". On the other hand, if the value of the common counter is "3", output data that sets "COM3" to high level and "COM0", "COM1", and "COM2" to low level is output to output port 1. As a result, "COM3" is selected (output) from among "COM0" to "COM3".

[0220] In addition, in the common output process, the output data of the launch permission signal is output to output port 1. That is, first, it is determined whether or not a playable state has occurred (set). If it is determined that a playable state has been established, output data that sets the launch permission signal to a high level is output to the output port 1. As a result, the launch permission signal is output. On the other hand, if it is determined that the playable state has not occurred, output data that sets the launch permission signal to a low level is output to the output port 1. This stops the output of the launch permission signal. Here, it is determined whether or not a playable state has occurred based on the value (gaming machine state flag) stored in the gaming machine state flag area of ​​the RAM 230. At this time, if the value stored in the gaming machine state flag area is a value corresponding to the playable state, it is determined that the playable state has occurred, and if the value is not a value corresponding to the playable state, it is determined that the playable state has not occurred. In this embodiment, the common output process is configured to set the output of the launch permission signal only when it is determined that a playable state has occurred. As a result, the launch permission signal is output only while the playable state is occurring (being set). However, the common output process may be configured to set the output of the launch permission signal regardless of the gaming machine state. With this configuration, the launch permission signal can be output at all times while the main control board 200 is powered on.

[0221] In step S29-6, it is determined whether a playable state has occurred (set), and if it is determined that a playable state has occurred (Yes), the process proceeds to step S29-7, and if it is determined that a playable state has not occurred (No), the process proceeds to step S29-11. Here, it is determined whether or not a playable state has occurred based on the value (gaming machine state flag) stored in the gaming machine state flag area of ​​the RAM 230. At this time, if the value stored in the gaming machine state flag area is a value corresponding to the playable state, it is determined that the playable state has occurred, and if the value is not a value corresponding to the playable state, it is determined that the playable state has not occurred.

[0222] In step S29-7, a main display device data acquisition process is executed, and the process proceeds to step S29-8. In the main display device data acquisition process, display data for the main display device 60 is acquired, and the acquired display data is set in the A register. Specifically, in the main display device data acquisition process, first, the value of the common counter is confirmed, and then the display data set in the output request buffer corresponding to the confirmed common counter value among the common 0 output request buffer to the common 3 output request buffer in the RAM 230 is acquired, and the acquired display data is set in the A register. At this time, if the value of the common counter is "0", the display data set in the common 0 output request buffer is acquired, and the acquired display data is set in the A register. On the other hand, if the value of the common counter is "1", the display data set in the common 1 output request buffer is acquired, and the acquired display data is set in the A register. On the other hand, if the value of the common counter is "2", the display data set in the common 2 output request buffer is acquired, and the acquired display data is set in the A register. On the other hand, if the value of the common counter is "3", the display data set in the common 3 output request buffer is acquired, and the acquired display data is set in the A register. Here, the display data acquired in the main display device data acquisition process is the display data set in the common 0 output request buffer to common 3 output request buffer in the LED display setting process (specifically, the normal display data setting process) in step S4-20 included in the previous timer interrupt process.

[0223] In step S29-8, a main display device data output process is executed, and the process proceeds to step S29-9. In the main display device data output process, the display data set in the A register in step S29-7 is output to output port 0. As a result, data signals ("SEGDATA0" to "SEGDATA7") based on the display data set in the output request buffer (one of the common 0 output request buffer to common 3 output request buffer) are output to the source driver 250a. That is, the display on the main display device 60 is controlled based on the display data set in the output request buffer (one of the common 0 output request buffer to common 3 output request buffer).

[0224] In step S29-9, an interrupt disable process is executed, and the process proceeds to step S29-10. In the interrupt disable process, an interrupt disable state is set, which disables interrupts from other processes. As a result, while the interrupt disable state is set, execution of the power-off save process, timer interrupt process, etc., which will be described later, is prohibited. In step S29-10, a performance display device output process is executed, and the series of processes ends, and the process moves to the next process (step S4-4). The performance display device output process will be described later.

[0225] In step S29-11, a performance display device data acquisition process is executed, and the process proceeds to step S29-12. In the performance display device data acquisition process, display data for the performance display device 206 is acquired, and the acquired display data is set in the A register. Specifically, in the performance display device data acquisition process, first, the value of the common counter is confirmed, and then the display data set in the output request buffer corresponding to the confirmed common counter value among the common 0 output request buffer to the common 3 output request buffer in the RAM 230 is acquired, and the acquired display data is set in the A register. At this time, if the value of the common counter is "0", the display data set in the common 0 output request buffer is acquired, and the acquired display data is set in the A register. On the other hand, if the value of the common counter is "1", the display data set in the common 1 output request buffer is acquired, and the acquired display data is set in the A register. On the other hand, if the value of the common counter is "2", the display data set in the common 2 output request buffer is acquired, and the acquired display data is set in the A register. On the other hand, if the value of the common counter is "3", the display data set in the common 3 output request buffer is acquired, and the acquired display data is set in the A register. Here, the display data acquired in the performance display device data acquisition process is the display data set in the common 0 output request buffer to common 3 output request buffer in the LED display setting process of step S4-20 included in the previous timer interrupt process (specifically, the display data setting process when changing settings, the display data setting process when checking settings, or the display data setting process when an abnormality occurs).

[0226] In step S29-12, a performance display device data output process is executed, the series of processes is terminated, and the process proceeds to the next process (step S4-4). In the performance display device data output process, the display data set in the A register in step S29-11 is output to output port 4. As a result, data signals ("7SEGDATA0" to "7SEGDATA7") based on the display data set in the output request buffer (one of the common 0 output request buffer to common 3 output request buffer) are output to the source driver 250b. That is, the display of the performance display device 206 is controlled based on the display data set in the output request buffer (one of the common 0 output request buffer to common 3 output request buffer).

[0227] (Performance display device output processing) Next, the performance display device output process in step S29-10 will be described. FIG. 12 is a flowchart showing the performance display device output process. The performance display device output process is based on a program for controlling the display of the performance display device 206. In other words, the performance display device output process is based on a program stored in the unused area m2 (program area) of the ROM 220. The performance display device output process is called during execution of the dynamic port output process. When the performance display device output process is called in step S29-10, the process first proceeds to step S30-1 as shown in FIG. In step S30-1, a register save process is executed, and the process proceeds to step S30-2. In the register save process, the values ​​of all registers used during execution of the processing based on the program stored in the usage area m1 are saved to a save area in RAM. In addition, the values ​​of all stack pointers used during execution of the processing based on the program stored in the usage area m1 are saved to a save area in RAM.

[0228] In step S30-2, a performance display device data acquisition process is executed, and the process proceeds to step S30-3. In the performance display device data acquisition process, display data for the performance display device 206 is acquired, and the acquired display data is set in the A register. Specifically, in the performance display device data acquisition process, the value of the common counter is first confirmed, and then the display data set in the area corresponding to the confirmed common counter value in the identification segment output request buffer and the ratio segment output request buffer of RAM 230 is acquired, and the acquired display data is set in the A register. At this time, if the value of the common counter is "0", the display data set in the upper 8 bits of the identification segment output request buffer is acquired, and the acquired display data is set in the A register. On the other hand, if the value of the common counter is "1", the display data set in the lower 8 bits of the identification segment output request buffer is acquired, and the acquired display data is set in the A register. On the other hand, if the value of the common counter is "2", the display data set in the upper 8 bits of the ratio segment output request buffer is obtained, and the obtained display data is set in the A register. On the other hand, if the value of the common counter is "3", the display data set in the lower 8 bits of the ratio segment output request buffer is acquired, and the acquired display data is set in the A register. Here, the display data acquired in the performance display device data acquisition process is the display data set in the identification segment output request buffer or ratio segment output request buffer in the performance display device control process of step S4-25 included in the previous timer interrupt process.

[0229] In step S30-3, a performance display device data output process is executed, and the process proceeds to step S30-4. In the performance display device data output process, the display data set in the A register in step S30-2 is output to output port 4. As a result, data signals ("7SEGDATA0" to "7SEGDATA7") based on the display data set in the output request buffer (the discrimination segment output request buffer or the ratio segment output request buffer) are output to the source driver 250b. That is, the display of the performance display device 206 is controlled based on the display data set in the output request buffer (the discrimination segment output request buffer or the ratio segment output request buffer).

[0230] In step S30-4, a register restoration process is executed, and the process proceeds to step S30-5. In the register restoration process, the register values ​​saved in step S30-1 (register values ​​used during execution of the processing based on the program stored in the usage area m1) and the stack pointer value saved in step S30-1 (stack pointer value used during execution of the processing based on the program stored in the usage area m1) are restored. In step S30-5, interrupt permission processing is executed, the series of processing is terminated, and the process proceeds to the next processing (step S4-4). In the interrupt permission processing, the interrupt prohibition state is released, and the execution of power-off save processing, timer interrupt processing, etc. is permitted.

[0231] (Settings related processing) Next, the setting-related processing in step S4-8 will be described. FIG. 13 is a flowchart showing the setting-related processing. When the setting-related processing is executed in step S4-8, the processing first proceeds to step S37-1 as shown in FIG. In step S37-1, it is determined whether a setting change state has occurred (set), and if it is determined that a setting change state has occurred (Yes), it proceeds to step S37-2, and if it is determined that a setting change state has not occurred (No), it proceeds to step S37-8. Here, it is determined whether or not a setting change state has occurred based on the value (gaming machine state flag) stored in the gaming machine state flag area of ​​the RAM 230. At this time, if the value stored in the gaming machine state flag area is a value corresponding to the setting change state, it is determined that the setting change state has occurred, and if the value is not a value corresponding to the setting change state, it is determined that the setting change state has not occurred.

[0232] In step S37-2, a setting value acquisition process is executed, and the process proceeds to step S30-3. In the setting value acquisition process, the setting values ​​stored in the setting value area of ​​RAM 230 are acquired (loaded), and the acquired setting values ​​are stored in a register. In step S37-3, it is determined whether the RAM clear switch 207 has been pressed or not, and if it is determined that the RAM clear switch 207 has been pressed (Yes), the process proceeds to step S37-4, and if it is determined that the RAM clear switch 207 has not been pressed (No), the process proceeds to step S37-5. Here, if the RAM clear switch 207 is in an on state, it is determined that the RAM clear switch 207 has been pressed, and if the on state is not occurring, it is determined that the RAM clear switch 207 has not been pressed. In step S37-4, a set value update process is executed, and the process proceeds to step S37-5. In the set value update process, "1" is added to the set value stored in the register.

[0233] In step S37-5, it is determined whether the setting value stored in the register is less than a predetermined setting comparison value (in this embodiment, "6"), and if it is determined that the setting value stored in the register is not less than the predetermined setting comparison value (the setting value is greater than or equal to the predetermined setting comparison value) (No), it proceeds to step S37-6, and if it is determined that the setting value stored in the register is less than the predetermined setting comparison value (Yes), it proceeds to step S37-7. In step S37-6, a set value initialization process is executed, and the process proceeds to step S37-7. In the set value initialization process, the set values ​​stored in the registers are overwritten with predetermined initial values ​​("0" in this embodiment). In step S37-7, a set value save process is executed, and the process proceeds to step S37-8. In the set value save process, the set values ​​stored in the registers are saved in the set value area of ​​the RAM 230.

[0234] In step S37-8, it is determined whether the setting key switch 208 is in the ON state, and if it is determined that the setting key switch 208 is not in the ON state (is in the OFF state) (No), the process proceeds to step S37-9, and if it is determined that the setting key switch 208 is in the ON state (Yes), the process ends and the process proceeds to the next process (step S4-19). Here, if the setting key switch 208 is in an ON state, it is determined that the setting key switch 208 is in an ON state, and if the ON state is not occurring, it is determined that the setting key switch 208 is not in an ON state. In step S37-9, a subcommand setting process is executed, and the process proceeds to step S37-10. In the subcommand setting process, a setting-related end designation command (subcommand) is stored in the subcommand output request buffer of RAM 230.

[0235] In step S37-10, a sub-command group setting process is executed, and the process proceeds to step S37-11. In the sub-command group setting process, the sub-command group is stored in the sub-command output request buffer in RAM 230. Here, the group of subcommands includes a subcommand for specifying the game state (game state offset value), a subcommand for specifying the launch position, a subcommand for specifying the stopping pattern of the first special pattern, a subcommand for specifying the stopping pattern of the second special pattern, a subcommand for specifying the number of reserved special patterns 1, a subcommand for specifying the number of reserved special patterns 2, a subcommand for specifying the value of the time-saving counter, a setting value specification command for specifying the setting value stored in the setting value area of ​​RAM230, etc. In step S37-11, RAM set processing is executed, the series of processing is terminated, and the process proceeds to the next processing (step S4-19). In the RAM set processing, the gaming machine state is set to a playable state. Specifically, a value corresponding to the playable state is saved as the value of the gaming machine state flag area of ​​the RAM 230 (gaming machine state flag).

[0236] (Switch management process) Next, the switch management process in step S4-12 will be described. FIG. 14 is a flowchart showing the switch management process. When the switch management process is executed in step S4-12, the process first proceeds to step S5-1 as shown in FIG. In step S5-1, it is determined whether or not the on state of the gate switch 104 has been detected. If it is determined that the on state of the gate switch 104 has been detected (Yes), the process proceeds to step S5-2. If it is determined that the on state of the gate switch 104 has not been detected (No), the process proceeds to step S5-3. In step S5-2, a normal starting ball detection process is executed, and the process proceeds to step S5-3. The normal starting ball detection process will be described later. In addition, in the normal starting ball detection process, it is determined whether or not it is during the right-hand hitting period. If it is determined that it is not during the right-hand hitting period (it is during the left-hand hitting period), "1" is added to the value of the right-hand hitting error counter. In this embodiment, the period during which either the jackpot game state or the time-saving control is being executed is the right-hand hitting period, while the period during which the normal game state (a game state during which the jackpot game state is not being executed and the time-saving control is stopped) is being executed is the left-hand hitting period.

[0237] In step S5-3, it is determined whether the on state of the special diagram 1 start port switch 101 has been detected, and if it is determined that the on state of the special diagram 1 start port switch 101 has been detected (Yes), it proceeds to step S5-4, and if it is determined that the on state of the special diagram 1 start port switch 101 has not been detected (No), it proceeds to step S5-5. In step S5-4, a special drawing 1 starting ball detection process is executed, and the process proceeds to step S5-5. The special drawing 1 starting ball detection process will be described later. In step S5-5, it is determined whether the on state of the special diagram 2 start port switch 102 has been detected, and if it is determined that the on state of the special diagram 2 start port switch 102 has been detected (Yes), the process proceeds to step S5-6, and if it is determined that the on state of the special diagram 2 start port switch 102 has not been detected (No), the series of processes is terminated and the process proceeds to the next process (step S4-13). In step S5-6, the special drawing 2 starting ball detection process is executed, the series of processes is ended, and the process proceeds to the next process (step S4-13). The special drawing 2 starting ball detection process will be described later.

[0238] (Normal starting ball detection processing) Next, the normal starting ball detection process in step S5-2 will be described. FIG. 15 is a flowchart showing the normal starting ball detection process. When the normal starting ball detection process is executed in step S5-2, as shown in FIG. 15, the process first proceeds to step S6-1. In step S6-1, a normal symbol random number acquisition process is executed, and the process proceeds to step S6-2. In the normal symbol random number acquisition process, a winning random number (random number value) is acquired (loaded) from a loop counter corresponding to the normal symbol lottery. In step S6-2, it is determined whether the value of the regular map reserve counter is the upper limit (in this embodiment, "4"), and if it is determined that the value of the regular map reserve counter is not the upper limit (No), it proceeds to step S6-3, and if it is determined that the value of the regular map reserve counter is the upper limit (Yes), it terminates the series of processes and proceeds to the next process (step S5-3). In step S6-3, the process executes a general map reservation counter update process, and then proceeds to step S6-4. In the general map reservation counter update process, the value set in the general map reservation counter is increased by "1" and set as a new general map reservation counter.

[0239] In step S6-4, the normal random number storage process is executed, and the series of processes is terminated and the process proceeds to the next process (step S5-3). In the normal random number storage process, the winning random number obtained in step S6-1 is stored in the normal game information storage area of ​​RAM 230 as normal game information. RAM 230 is configured to include a memory area 0 in which regular game information during game execution is stored, and a regular game information memory area in which regular game information for which the regular win / loss determination is pending is stored. The regular game information storage area includes storage areas 1 to 4 as storage areas capable of storing regular game information. The priority of each memory area is specified as follows, from highest to lowest (highest to lowest): memory area 1, memory area 2, memory area 3, memory area 4. Then, the normal game information stored in the normal game information memory area is subjected to normal game win / loss judgment in order from the information stored in the memory area with the highest priority. In the normal random number saving process, the winning random number acquired in step S6-1 is stored as normal game information in the normal game information storage area. At this time, the normal game information is stored in the storage area with the highest priority among the available storage areas. That is, if the current value of the regular map reserved number counter is "1", the winning random number obtained in step S6-1 is stored in memory area 1. If the current value of the regular map reserved number counter is "2", the winning random number obtained in step S6-1 is stored in memory area 2. If the current value of the regular map reserved number counter is "3", the winning random number obtained in step S6-1 is stored in memory area 3. If the current value of the regular map reserved number counter is "4", the winning random number obtained in step S6-1 is stored in memory area 4.

[0240] (Special Figure 1 Starting ball detection process) Next, the special chart 1 starting ball detection process in step S5-4 will be explained. Figure 16 is a flowchart showing the special chart 1 starting ball detection process. When the special chart 1 starting ball detection process is executed in step S5-4, it first proceeds to step S7-1 as shown in FIG. In step S7-1, a special symbol identification value setting process is executed, and the process proceeds to step S7-2. In the special symbol identification value setting process, a special symbol identification value corresponding to the first special symbol lottery is set in the special symbol identification value setting area of ​​RAM 230. Also, "1" is added to the value of the external information starting hole ball entry count counter. In addition, in the special symbol identification value setting process, it is determined whether or not it is a right-hit period. If it is determined that it is not a right-hit period (it is a left-hit period), the value of the right-hit error counter is reset (the value of the right-hit error counter is set to "0"). In step S7-2, a reserved number counter address setting process is executed, and the process proceeds to step S7-3. In the reserved number counter address setting process, the address of the reserved number counter for special drawing 1 is set in the reserved number counter address setting area of ​​RAM 230. In step S7-3, a special symbol random number acquisition process is executed, and the series of processes is ended, and the process proceeds to the next process (step S5-5). The special symbol random number acquisition process will be described later.

[0241] (Special Figure 2 Starting Ball Detection Processing) Next, the special chart 2 starting ball detection process in step S5-6 will be explained. Figure 17 is a flowchart showing the special chart 2 starting ball detection process. When the special chart 2 starting ball detection process is executed in step S5-6, it first proceeds to step S8-1 as shown in FIG. In step S8-1, a special symbol identification value setting process is executed, and the process proceeds to step S8-2. In the special symbol identification value setting process, a special symbol identification value corresponding to the second special symbol lottery is set in the special symbol identification value setting area of ​​RAM 230. Also, "1" is added to the value of the external information starting hole ball entry count counter. In addition, in the special symbol identification value setting process, it is determined whether or not it is during the right-hand hit period. If it is determined that it is not during the right-hand hit period (it is during the left-hand hit period), "1" is added to the value of the right-hand hit error counter. In step S8-2, a reserved number counter address setting process is executed, and the process proceeds to step S8-3. In the reserved number counter address setting process, the address of the reserved number counter for special drawing 2 is set in the reserved number counter address area of ​​RAM 230. In step S8-3, a special symbol random number acquisition process is executed, and the series of processes is ended, and the process proceeds to the next process (step S4-13). The special symbol random number acquisition process will be described later.

[0242] (Special pattern random number acquisition process) Next, the special symbol random number acquisition process in steps S7-3 and S8-3 will be described. FIG. 18 is a flowchart showing the special symbol random number acquisition process. When the special symbol random number acquisition process is executed in steps S7-3 and S8-3, as shown in FIG. 18, the process first proceeds to step S9-1. In step S9-1, a special symbol identification value acquisition process is executed, and the process proceeds to step S9-2. In the special symbol identification value acquisition process, the special symbol identification value set in the special symbol identification value setting area of ​​the RAM 230 is acquired (loaded). In step S9-2, a special drawing reservation number acquisition process is executed, and the process proceeds to step S9-3. In the special drawing reservation number acquisition process, the value (special drawing 1 reservation number or special drawing 2 reservation number) of the special drawing reservation number counter (special drawing 1 reservation number counter or special drawing 2 reservation number counter) specified by the address set in the reservation number counter address area is acquired (loaded).

[0243] In step S9-3, a special symbol random number acquisition process is executed, and the process proceeds to step S9-4. In the special symbol random number acquisition process, various random numbers (random value values) such as a jackpot random number, a winning symbol random number, a reach group random number, a reach mode random number, and a variable pattern random number are acquired (loaded) from the loop counters corresponding to each lottery. At this time, the corresponding loop counter is selected based on the special symbol identification value acquired in step S9-1. In step S9-4, it is determined whether the number of reserved special drawings (number of reserved special drawings 1 or number of reserved special drawings 2) obtained in step S9-2 is the upper limit (in this embodiment, "4"), and if it is determined that the number of reserved special drawings is not the upper limit (No), it proceeds to step S9-5, and if it is determined that the number of reserved special drawings is the upper limit (Yes), it terminates the series of processes and proceeds to the next process (step S4-13 or S5-5). In step S9-5, a special drawing reservation number counter update process is executed, and the process proceeds to step S9-6. In the special drawing reservation number counter update process, the value set in the special drawing reservation number counter (special drawing 1 reservation number counter or special drawing 2 reservation number counter) specified by the address set in the reservation number counter address area is added with "1" and the value is set in the special drawing reservation number counter.

[0244] In step S9-6, a special random number saving process is executed, and the process proceeds to step S9-7. In the special random number saving process, the various random numbers acquired in step S9-3 are stored as special game information (special game information 1 or special game information 2) in the special game information storage area (special game information 1 or special game information storage area) of RAM 230. RAM230 is configured to include a memory area 0 in which special game information during game execution is stored, a special game information memory area in which special game information for which start determination is pending is stored, and a special game information memory area in which start determination is pending. The special chart 1 game information storage area is configured to include storage areas 1 to 4 as storage areas capable of storing special chart 1 game information. The priority of each memory area is specified as follows, from highest to lowest: memory area 1, memory area 2, memory area 3, memory area 4 (highest to lowest). The special game information stored in the special game information memory area is subjected to start determination in the order of priority, starting from the information stored in the memory area with the highest priority. The special chart 2 game information storage area is configured to include storage areas 1 to 4 as storage areas capable of storing special chart 2 game information. The priority of each memory area is specified as follows, from highest to lowest: memory area 1, memory area 2, memory area 3, memory area 4 (highest to lowest). The special game information stored in the special game information memory area is subjected to start determination in order from the information stored in the memory area with the highest priority.

[0245] In the special symbol random number saving process, if the special symbol identification value acquired in step S9-1 is a value corresponding to the first special symbol lottery, the various random numbers acquired in step S9-3 are stored in the special symbol 1 game information storage area as special symbol 1 game information. At this time, the various random numbers acquired in step S9-3 are stored in the storage area with the highest priority among the available storage areas. That is, if the current value of the special drawing 1 reserved number counter is "1", the various random numbers obtained in step S9-3 are stored in memory area 1. If the current value of the special drawing 1 reserved number counter is "2", the various random numbers obtained in step S9-3 are stored in memory area 2. If the current value of the special drawing 1 reserved number counter is "3", the various random numbers obtained in step S9-3 are stored in memory area 3. If the current value of the special drawing 1 reserved number counter is "4", the various random numbers obtained in step S9-3 are stored in memory area 4. On the other hand, if the special symbol identification value acquired in step S9-1 is a value corresponding to the second special symbol lottery, the various random numbers acquired in step S9-3 are stored in the special symbol 2 game information storage area as special symbol 2 game information. At this time, the various random numbers acquired in step S9-3 are stored in the storage area with the highest priority among the available storage areas. That is, if the current value of the special drawing 2 reserved number counter is "1", the various random numbers obtained in step S9-3 are stored in memory area 1. If the current value of the special drawing 2 reserved number counter is "2", the various random numbers obtained in step S9-3 are stored in memory area 2. If the current value of the special drawing 2 reserved number counter is "3", the various random numbers obtained in step S9-3 are stored in memory area 3. If the current value of the special drawing 2 reserved number counter is "4", the various random numbers obtained in step S9-3 are stored in memory area ...

Claims

1. a control means for adjusting the volume of the second audio data assigned to the second track based on the volume of the first audio data assigned to the first track; volume data indicating a peak value of the volume of the first audio data at each predetermined time interval is stored; A gaming machine characterized in that the volume of the second audio data can be adjusted based on the volume data.

2. 2. The gaming machine according to claim 1, wherein an adjustment amount for the volume of the second audio data is calculated at each predetermined time interval.

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