Nanoscale-aligned three-dimensional stacked integrated circuit

Abstract

To provide 2D scaling and general top down fabrication at and beyond the 7 nm node.SOLUTION: A method for fabricating a three-dimensional (3D) stacked integrated circuit 208 uses pick-and-place strategies so as to stack source wafers 201 provided with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers are stacked in a sequential or parallel fashion. The stacking is in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in the face-to-back, back-to-face or back-to-back fashion are connected using Through Silicon Vias (TSVs), and source wafers that are stacked in the face-to-face fashion are connected using Inter Layer Vias (ILVs).SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 62 / 609,891, filed December 22, 2017, entitled "Nanoscale-Aligned 3D Stacked Integrated Circuit," which is incorporated herein by reference in its entirety.

[0002] (Technical field) The present invention relates generally to semiconductor manufacturing, and more particularly to nanoscale aligned three-dimensional (3D) stacked integrated circuits. [Background technology]

[0003] Moore's Law is the observation that the number of transistors in high-density integrated circuits doubles approximately every two years. The two-dimensional (2D) scaling of electronic circuits characterized by Moore's Law may have reached a limit in recent times as feature dimensions reach the atomic scale. For example, the thickness of high-K capping layers for the 10-nm technology node is close to 0.5 nm, which is smaller than the width of two silicon atoms. The metrology accuracy requirements for multiple patterning technology (MPT) are close to 0.2 nm, which is smaller than the width of one silicon atom. Summary of the Invention [Problem to be solved by the invention]

[0004] In light of these and other limitations, 2D scaling and top-down manufacturing in general pose significant challenges for continuing to the 7 nm node and beyond. [Means for solving the problem]

[0005] In one embodiment of the present invention, a method for fabricating a three-dimensional (3D) system-on-chip (SoC) includes assembling a layer (k) two-dimensional (2D) die array on a layer (k-1) 2D die array of a layer (k-1) wafer, where the 2D die is disposed on the layer (k-1) wafer, and k is a positive integer greater than 1. The 2D die array includes a single 2D die, a single island of 2D die forming a contiguous group of 2D dies, or multiple islands of 2D die. The method further includes deploying a fluid that enables lubricated relative motion between the layer (k) 2D die array and the layer (k-1) 2D die array, where the fluid enables precise overlay of the layer (k) and layer (k-1) 2D die arrays.

[0006] In another embodiment of the present invention, a method for fabricating a three-dimensional (3D) system-on-chip (SoC) includes assembling a layer (k) two-dimensional (2D) die array on a layer (k-1) 2D die array of a layer (k-1) wafer, where the 2D die is disposed on the layer (k-1) wafer, and k is a positive integer greater than 1. The 2D die array includes a single 2D die, a single island of 2D die forming a contiguous group of 2D die, or multiple islands of 2D die. The method further includes providing an encapsulation layer to protect the 2D die of each of the layer (k) wafer and the layer (k-1) wafer from an etchant used during the pick-and-place process.

[0007] In another embodiment of the present invention, a method for fabricating a three-dimensional (3D) system-on-chip (SoC) includes assembling a layer (k) two-dimensional (2D) die array on a layer (k-1) 2D die array of a layer (k) wafer, where the 2D die is disposed on the layer (k-1) wafer, and k is a positive integer greater than 1. Further, the 2D die array includes a single 2D die, a single island of 2D die forming a contiguous group of 2D die, or multiple islands of 2D die. Further, the 2D die has a thickness of less than 10 micrometers.

[0008] In a further embodiment of the present invention, an electronic design automation (EDA) methodology for designing three-dimensional (3D) application-specific integrated circuit (ASIC) system-on-chip (SoC) logic circuits includes a combination of software integrated with a two-dimensional (2D) EDA solution, where the software includes a netlist partitioning algorithm for partitioning the 3D design netlist into 2D modules. The 2D EDA solution is used to perform one or more of synthesis, 3D placement-aware synthesis, placement, clock tree synthesis (CTS), routing, design verification, and sign-off analysis.

[0009] The foregoing has outlined rather generally the features and technical advantages of one or more embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which may form the subject of the claims of the invention.

[0010] A better understanding of the present invention can be obtained when the following detailed description is considered in conjunction with the following drawings. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 illustrates an exemplary layer-k source wafer showing various 2D die layouts according to one embodiment of the present invention. [Figure 2] FIG. 2 illustrates stacking of a layer-k 2D die array (k>1) onto a layer 1 2D die array according to one embodiment of the present invention. [Figure 3A] FIG. 3A shows a cross section of a layer-k silicon-on-insulator (SOI) wafer having two buried layers, according to one embodiment of the present invention. [Figure 3B] FIG. 3B shows a cross section of a layer-k silicon-on-insulator (SOI) wafer having two buried layers, according to one embodiment of the present invention. [Figure 4A] FIG. 4A illustrates another cross section of a layer-k SOI wafer according to one embodiment of the present invention. [Figure 4B]FIG. 4B illustrates another cross section of a layer-k SOI wafer according to one embodiment of the present invention. [Figure 5A] FIG. 5A shows a further cross section of a layer-k SOI wafer according to one embodiment of the present invention. [Figure 5B] FIG. 5B shows a further cross section of a layer-k SOI wafer according to one embodiment of the present invention. [Figure 6] FIG. 6 is a flow chart of a method for a backgrinding-based approach for inversion and bulk material removal, according to one embodiment of the present invention. [Figure 7A] FIG. 7A shows a cross-sectional view for inversion and bulk material removal using the steps described in FIG. 6 according to one embodiment of the present invention. [Figure 7B] FIG. 7B shows a cross-sectional view for inversion and bulk material removal using the steps described in FIG. 6 according to one embodiment of the present invention. [Figure 7C] FIG. 7C shows a cross-sectional view for inversion and bulk material removal using the steps described in FIG. 6 according to one embodiment of the present invention. [Figure 7D] FIG. 7D shows a cross-sectional view for inversion and bulk material removal using the steps described in FIG. 6 according to one embodiment of the present invention. [Figure 8] FIG. 8 is a flow chart of a method for an ablation-based approach for inversion and bulk material removal, according to one embodiment of the present invention. [Figure 9A] FIG. 9A shows a cross-sectional view for inversion and bulk material removal using the steps described in FIG. 8 according to one embodiment of the present invention. [Figure 9B] FIG. 9B shows a cross-sectional view for inversion and bulk material removal using the steps described in FIG. 8 according to one embodiment of the present invention. [Figure 9C] FIG. 9C shows a cross-sectional view for inversion and bulk material removal using the steps described in FIG. 8 according to one embodiment of the present invention. [Figure 9D]FIG. 9D shows a cross-sectional view for inversion and bulk material removal using the steps described in FIG. 8 according to one embodiment of the present invention. [Figure 9E] FIG. 9E shows a cross-sectional view for inversion and bulk material removal using the steps described in FIG. 8 according to one embodiment of the present invention. [Figure 10] FIG. 10 is a flowchart of a method for overlay and distortion control of multiple packed 2D dies, according to one embodiment of the present invention. [Figure 11A] FIG. 11A illustrates a cross-sectional view for providing overlay and distortion control of multiple packed 2D dies using the steps described in FIG. 10 according to one embodiment of the present invention. [Figure 11B] FIG. 11B illustrates a cross-sectional view for providing overlay and distortion control of multiple packed 2D dies using the steps described in FIG. 10 according to one embodiment of the present invention. [Figure 12A] FIG. 12A is a diagram illustrating overlay and distortion control of a single picked 2D die according to one embodiment of the present invention. [Figure 12B] FIG. 12B is a diagram illustrating overlay and distortion control of a single picked 2D die according to one embodiment of the present invention. [Figure 13] FIG. 13 illustrates that through-silicon vias (TSVs) are formed through access holes that already exist in the picked and placed 2D die, according to one embodiment of the present invention. [Figure 14A] FIG. 14A illustrates an exemplary process for temporary attachment and bonding according to one embodiment of the present invention. [Figure 14B] FIG. 14B illustrates an exemplary process for temporary attachment and bonding according to one embodiment of the present invention. [Figure 14C] FIG. 14C illustrates an exemplary process for temporary attachment and bonding according to one embodiment of the present invention. [Figure 15]FIG. 15 illustrates a conventional 2D application specific integrated circuit (ASIC) electronic design automation (EDA) flow for logic implementation according to one embodiment of the present invention. [Figure 16] FIG. 16 illustrates a 2D single-sided static random access memory (SRAM) configuration according to one embodiment of the present invention. [Figure 17] FIG. 17 illustrates 3D standalone SRAM die stacking according to one embodiment of the present invention. [Figure 18] FIG. 18 illustrates a 3D only bitcell stacked SRAM according to one embodiment of the present invention. [Figure 19] FIG. 19 shows a vertical bitline cross section of a 3D only bitcell stacked SRAM according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] As mentioned in the background section, two-dimensional (2D) scaling and top-down fabrication in general pose significant challenges as they continue to the 7 nm node and beyond.

[0013] The present invention provides a third embodiment, as described below. rd ) dimension to address these challenges.

[0014] In one embodiment, the present invention uses source wafers with device layers fabricated using standard 2D semiconductor manufacturing processes (described below in connection with FIG. 1 ) and stacks them (the source wafers) sequentially or in parallel using a pick-and-place strategy. Such pick-and-place strategies are discussed in Sreenivasan et al. (WO 2018 / 119451 A1) (hereinafter, “Sreenivasan et al.”), which is incorporated herein by reference in its entirety. In one embodiment, stacking is performed in a face-to-face (F2F), face-to-back (F2B), back-to-face (B2F), or back-to-back (B2B) manner. B2F, F2B, and B2B can be connected using, for example, through-silicon vias (TSVs). F2F can be connected using interlayer vias (ILVs).

[0015] At this point, a discussion of standard semiconductor processes is deemed appropriate.

[0016] As used herein, "layer-0 source wafer" refers to a fully populated wafer of transistors and interconnects fabricated using standard 2D manufacturing processes. This layer also contains associated alignment marks and forms the starting layer for the final wafer-scale three-dimensional (3D) integrated circuit (IC) stack.

[0017] As used herein, a "layer-k source wafer" refers to a fully populated wafer of transistors and interconnects fabricated using standard 2D manufacturing processes on a wafer containing at least one sacrificial layer, such as oxide, buried under silicon; this layer also includes associated alignment marks, and is assembled onto a layer "k-1" and is part of a 3D-IC stack. Assembly of this layer can be in one step (all 2D die are picked up at once) or in multiple steps where a single 2D die array or arrays of 2D die are picked up from the layer "k" wafer and precisely placed onto the layer "k-1" wafer.

[0018] In one embodiment, assembly is performed to achieve sub-50 nm, sub-30 nm, sub-20 nm, sub-10 nm, or sub-5 nm overlay between each 2D die of the layer (k) wafer and the corresponding 2D die of the layer (k-1) wafer.

[0019] Referring to FIG. 1, FIG. 1 illustrates an exemplary layer-k source wafer 100 showing various 2D die layouts according to one embodiment of the present invention.

[0020] Referring to FIG. 1, a layer-k source wafer 100 includes 2D die array 101, which is a single 2D die, 2D die array 102, which is a contiguous island of 2D dies, and 2D die array 103, which is a group of islands.

[0021] As used herein, "2D die" refers to a single layer of a three-dimensional (3D) system-on-chip (SoC), where the 3D-SoC includes at least two 2D dies precisely stacked in a three-dimensional configuration. These 2D dies are fabricated using standard 2D semiconductor manufacturing processes. In one embodiment, the thickness of the 2D dies may be less than 10 micrometers. Wafers thinned using standard wafer thinning processes, such as backgrinding, are expected to remain at thicknesses of 15 μm or greater due to defects caused by the grinding process. However, 2D dies fabricated using non-grinding processes can be fabricated at thicknesses significantly smaller than current thickness limits.

[0022] As used herein, a "2D die array" refers to a single 2D die (see 2D die array 101) or a group of 2D dies that are collectively transferred from their source wafer (e.g., layer-k) and collectively and precisely assembled onto a previous wafer (layer-k-1), where k>1. This 2D die array can include a single island of 2D dies that form a contiguous group (see 2D die array 102). Alternatively, the 2D die array can include multiple islands of 2D dies, where each island of 2D dies forms a contiguous group, but the islands are not contiguous (see 2D die array 103).

[0023] "Overlay," as used herein, refers to a vector quantity defined at every point on a wafer. It is the difference between the vector position of a point on the substrate geometry and the vector position of the corresponding point in the overlay pattern. A commonly accepted quantifier of overlay is the (mean + 3 sigma) value of the magnitude of said overlay vector.

[0024] As used herein, "alignment" refers to the set of rigid body errors (translation and rotation) between two overlay bodies.

[0025] Referring to FIG. 2, FIG. 2 illustrates stacking of a layer-k 2D die array (k>1) onto a layer-1 2D die array, according to one embodiment of the present invention.

[0026] As shown in FIG. 2 , in one embodiment, layer-1 of source wafer 201 corresponds to a silicon-on-insulator wafer 202 having three elements 203. In one embodiment, wafer 202 includes a layered silicon 204-insulator (sacrificial layer) 205-silicon 206 substrate. In one embodiment, element 203, in its most general form, is a “feedstock” consisting of transistor, interconnect, and dielectric layers. Furthermore, in one embodiment, element 203, as used herein, may include silicon layer 204 of SOI wafer 202. It may or may not have any functionality of its own, but when assembled with other elements 203 and possibly additional interconnect and dielectric layers, it can be used to fabricate a working ASIC. Furthermore, front-end, high-resolution device layers, which have high mask costs, will reside within element 203. This is to reduce the cost of expensive masks (for the high-resolution device layers) across the fabrication of various ASIC devices.

[0027] In one embodiment, the width of the element 203 corresponds to a 2D die width of tens of millimeters. In one embodiment, the street width or "scribe width" may range from hundreds of nanometers to tens of micrometers. In one embodiment, such a width corresponds to the boundary 207 of the element 203.

[0028] 2, e.g., Layer-2...Layer-n (where n is a positive integer), is configured similarly to Layer-1 201. As a result, each of these layers (referred to simply as "Layer-k," where k is a positive integer) may be referred to generally herein as element 201.

[0029] As shown in FIG. 2, the layers of the source wafer are stacked in an interwoven fashion (flip, face-up, flip, face-up, . . . ) to form a 3D-IC stack 208, which is described in more detail below.

[0030] 2 further illustrates that B2F, F2B, and B2B can be connected using, for example, through-silicon vias (TSVs), and F2F can be connected using inter-layer vias (ILVs). Such features are described in further detail below, including with layer-k wafers.

[0031] In one embodiment, a fluid is deployed to enable lubricated relative motion between a layer (k) two-dimensional (2D) die array (e.g., 2D die array 102) and a layer (k-1) 2D die array (e.g., 2D die array 102), and the fluid enables precise overlay of the layer (k) and layer (k-1) 2D die arrays. In one embodiment, the fluid is a gas, a liquid, or a combination thereof. In one embodiment, such a combination includes heterogeneous gas and liquid portions, or homogeneously mixed gas and liquid portions.

[0032] In one embodiment, the first layer 2D die array can be on any substrate, but subsequent 2D die arrays (which can be picked and placed) require an underlying sacrificial layer, as shown in Figures 3A-3B. As a result, in one embodiment, layer-k 2D die may require an underlying oxide layer for optimal device function (e.g., fully depleted (FD)-SOI and partially depleted (PD)-SOI). This would require another sacrificial layer at a deeper level for pick and place. In one embodiment, these are commercially available through Lapis Semiconductor®.

[0033] In one embodiment, the 2D die width can range from tens of micrometers to tens of millimeters.

[0034] 3A-3B, which illustrate a cross section of a layer-k SOI wafer having two buried layers (e.g., an insulator layer, which may be composed of silicon oxide, and a sacrificial layer) in accordance with one embodiment of the present invention.

[0035] 3B, a cross section of layer-k SOI wafer 201 shows that device 203 may be comprised of transistor 301, interconnect 302, and dielectric 303. In one embodiment, device 203 further includes silicon layer 304. Additionally, as discussed above, layer-k 2D die may require an underlying oxide layer 305 for optimal device performance.

[0036] In one embodiment, the thickness of the 2D die can range from tens of nanometers to tens of micrometers, as shown in FIG. 3A.

[0037] Additionally, in one embodiment, FIG. 3A shows the boundary 207 of the element 203 .

[0038] Alternatively, in one embodiment, the layer-k 2D die may not require an underlying oxide, as shown in Figures 4A-4B, which illustrate another cross section of a layer-k SOI wafer according to one embodiment of the present invention.

[0039] In such embodiments, the sacrificial layer may need to reside at a deeper level than found in standard PD-SOI wafers for mechanical stability. These are commercially available through several sources, e.g., ShinEtsu®.

[0040] Additionally, in one embodiment, the sacrificial oxide (for pick and place) is the same depth as that used for standard PD-SOI wafers, as shown in Figures 5A-5B, which are commercially available through multiple sources, e.g., Soitec®.

[0041] 5A-5B illustrate additional cross sections of a layer-k SOI wafer according to one embodiment of the present invention.

[0042] As shown in Figures 5A-5B, in one embodiment, the thickness of the 2D die is about 100 nanometers or less.

[0043] A discussion of the process and mechanical design concepts of 3D integrated circuits (ICs) is now considered relevant.

[0044] In one embodiment, a generally applicable assembly sequence is substantially the same as that described in Sreenivasan et al. (WO 2018 / 119451 A1) (hereinafter "Sreenivasan et al."), which is incorporated herein by reference in its entirety. For example, the steps are as follows: 1. Etch and encapsulation; 2. Bulk etch process (to facilitate subsequent pick-and-place); 3. 2D die array pickup; 4. Alignment of 2D die array to product substrate; 5. Temporary attachment and bonding; 6. Repeat steps 3 through 5 until the product wafer is fully assembled.

[0045] In one embodiment, the assembly sequence for the 3D-IC may require some modifications to steps 2, 4, and 5, as discussed below.

[0046] The bulk etch process to facilitate subsequent pick-and-place requires some modification to account for the type of stacking being performed (F2F vs. F2B vs. B2F vs. B2B). For B2F and B2B stacking, the bulk etch process described by Sreenivasan et al. would be sufficient because it does not require flipping the layer-k wafer. However, for F2F and F2B stacking approaches, a wafer flipping step must occur in addition to the bulk etch. Furthermore, for F2F stacking, a delamination step is required to selectively remove the encapsulation layer for face-to-face connections. This can be done in various ways, depending on the specific nature of the encapsulation layer used. For example, if the encapsulation layer is composed of Al2O3, a timed buffered oxide etch can be used. Alternatively, if the encapsulation layer is composed of chemical vapor deposition (CVD) amorphous carbon, oxygen plasma can be used for stripping. Alternatively, if the encapsulation layer is composed of multiple layers, such as Al2O3, on top of CVD amorphous carbon, an oxygen plasma step and a buffered oxide etch can be performed sequentially. In one embodiment, the encapsulation layer protects the 2D die in both the layer (k) wafer and the layer (k-1) wafer from the etchants used during the pick-and-place process. In one embodiment, the encapsulation layer is compatible with existing semiconductor manufacturing technologies, such as complementary metal-oxide semiconductor (CMOS) and III-V semiconductors (e.g., gallium nitride, gallium arsenide). Two different techniques for flipping and bulk material removal are described below in connection with Figures 6, 7A-7D, 8, and 9A-9D.

[0047] Figure 6 is a flow chart of a method for a backgrinding-based approach for inversion and bulk material removal, according to one embodiment of the present invention. Figures 7A-7D show cross-sectional views for inversion and bulk material removal using the steps described in Figure 6, according to one embodiment of the present invention.

[0048] 6 along with FIGS. 7A-7D, in step 601, the encapsulation layer (not shown) is stripped as shown in FIG. 7A. Additionally, as illustrated in FIG. 7A, access holes 701 can be used to speed up the etching process. In one embodiment, access holes 701 are used for an etchant, such as hydrofluoric acid, to release the 2D die from the wafer. In one embodiment, access holes 701 are utilized to create conductors that enable through-silicon vias (TSVs).

[0049] In step 602, the layer-k wafer 201 is flipped over and attached to a glass carrier wafer 702 via a laser debonding adhesive 703 (commercially available), as shown in FIG. 7B.

[0050] In step 603, backgrinding of the layer-k wafer 201 is performed, as shown in FIG. 7C.

[0051] In step 604, the sacrificial layer 205 is etched using an acid such as hydrofluoric acid (HF).

[0052] Figure 8 is a flow chart of a method for an ablation-based approach for inversion and bulk material removal, according to one embodiment of the present invention. Figures 9A-9E show cross-sectional views for inversion and bulk material removal using the steps described in Figure 8, according to one embodiment of the present invention.

[0053] 8 in conjunction with FIGS. 9A-9D, in step 801, a timed HF etch is performed on the sacrificial layer 205 in such a way as to form pyramidal pillars (tethers) 901 as shown in FIGS. 9A and 9B. These pyramidal tethers 901 can facilitate pick-and-place steps, as described below. Additionally, access holes 701 may be used to speed up the etching process, as shown in FIG. 9A.

[0054] In step 802, the encapsulation layer (not shown) is stripped, as shown in Figure 9C.

[0055] In step 803, the layer-k wafer 201 is flipped, as shown in Figure 9D.

[0056] In step 804, the inverted layer-k wafer 201 is attached to a glass carrier wafer 902 via laser debonding adhesive 903 (commercially available), and the silicon and sacrificial layers 206, 205 are peeled away, as shown in Figure 9E.

[0057] The principles of the present invention also provide distortion control of the picked 2D die array in alignment with the product substrate, as described below.

[0058] In one embodiment, precise alignment can be achieved based on whether single or multiple 2D dies are assembled simultaneously, different from the method discussed in Sreenivasan et al.

[0059] For multiple 2D dies, moiré metrology must refer to the superstrate rather than the individual 2D dies being picked and placed. This requires alignment marks patterned on the bottom surface of the superstrate. These marks can be patterned on the absolute corners of the superstrate or distributed areally. Corresponding marks would be required on the product wafer. Some distortion control of the 2D dies can be achieved using thermal actuation. In addition, thermal actuation can be performed within the wafer chuck as well, for added degrees of freedom of actuation. If the superstrate material is not transparent to the wavelengths of light used for metrology (typically visible or IR), an observation window can be created within the superstrate. Alternatively, the superstrate can be constructed from commercially available transparent materials such as SiC and / or sapphire (Al2O3). A discussion of precision alignment involving multiple 2D dies is discussed below in connection with Figures 10 and 11A-11B.

[0060] Figure 10 is a flowchart of a method 1000 for overlay and distortion control of multiple packed 2D dies, according to one embodiment of the present invention. Figures 11A-11B show cross-sectional views for providing overlay and distortion control of multiple packed 2D dies using the steps described in Figure 10, according to one embodiment of the present invention.

[0061] 10, in conjunction with FIGS. 11A-11B, in step 1001, as a picked 2D die 1101 (a picked 2D die, such as 2D die array 101, 102, 103) is brought closer to a product wafer 1102, a course alignment is first performed, as shown in FIG. 11A. FIG. 11A shows a superstrate 1103 having alignment marks 1104 and an observation window 1105.

[0062] In step 1002, fine alignment is performed to align alignment marks 1104 and observation window 1105 of superstrate 1103 with alignment marks 1106 in the substrate. In one embodiment, some amount of distortion control of the 2D die can be achieved using thermal actuation via thermal actuator 1107. Additionally, thermal actuation can be implemented in wafer chuck 1108 as well for added degrees of actuation freedom.

[0063] For a single 2D die, in addition to the methods described above, Moiré metrology can be performed using IR-sensitive marks 1201 embedded in the layer-k and layer (k-1) 2D die 1101 and an IR-transparent superstrate, as shown in Figures 12A-12B, which illustrate overlay and distortion control of a single picked 2D die, according to one embodiment of the present invention.

[0064] Referring now to Figure 13, Figure 13 illustrates that through silicon vias (TSVs) are created through access holes already present in the picked and placed 2D die, in accordance with one embodiment of the present invention. As shown in Figure 13, layer-k, layer (k+1), and layer (k+2) are arranged such that layer (k+1) is inverted and layer (k+2) is face up. As further shown in Figure 13, the through silicon vias are fabricated through field access holes 701.

[0065] The required TSV density can be as high as 10,000 / mm for applications such as static random access memory (SRAM) stacking. At this level of TSV density, the TSV diameter can be approximately 20 nm to 80 nm. Some or all of these TSVs can potentially be routed through access holes 701 already present in the 2D die.

[0066] 14A-14C, which illustrate an exemplary process for temporary attachment and bonding according to an embodiment of the present invention.

[0067] In one embodiment, bonding can be performed after temporary attachment. In one embodiment, a dynamic air cushion based on a "slow landing" approach can be used. Such systems have traditionally been used in high-precision air-bearing stages, hard disk drive systems, and have been investigated for drop skating on solid surfaces. In this approach, a thin layer of UV-curable adhesive can be first dispensed onto the edge of the layer-0 2D die. The adhesive can be composed of a combination of volatile and non-volatile components, or in limited cases, the adhesive can be composed solely of non-volatile components. The UV-curable adhesive and / or a liquid containing volatile components provide damping, thereby substantially minimizing vibrational displacement between the layer-0 and layer-1 2D dies. Once the layer-1 2D die is attached near the layer-0 die as a superstrate, air flow can be initiated through pressure holes 1401. This creates a bearing of air or nitrogen (to provide an inert environment) around the 2D die. A combination of the superstrate z-force and the bearing flow rate can be used to control the "soft landing." At the same time, coarse alignment corrections can be made as the superstrate 1103 is pressed down. At the same time, a second air cushion 1402 is created between the stacked 2D dies. This second air cushion 1402 can provide additional lubrication between the 2D dies during fine alignment corrections.

[0068] Furthermore, the outward flow of air from this air cushion ensures that volatile components in the adhesive (located on the edge) do not contaminate the metal-metal contacts 1403 in the bulk of the 2D die. Furthermore, the flow rate of the second air cushion 1402 can be controlled by varying the topography of the 2D die using a superstrate 1103 with a z-directional piezoelectric actuator. Such a system has been previously demonstrated. Once the 2D dies are in contact, a blanket UV exposure 1404 can be performed to cure the adhesive located on the edge. To further secure the 2D dies, surface activation of the metal contacts 1403 can be performed. Such a process has previously been shown for metal-to-metal bonds involving metals such as copper, tungsten, and aluminum. Surface activation of copper can be achieved using argon ion treatment of the copper surface. In one embodiment, it is assumed that all of the air used in the air bearings described above is semiconductor-grade clean, dry air. Alternatively, if the bearings use nitrogen, it is also assumed that it is semiconductor-grade, clean, and dry. In one embodiment, the surface activated copper is maintained in an inert environment after the activation process until the bonding step (including tool-to-tool transfer and all tool handling). In one embodiment, vacuum holes 1405 may be used to enable a vacuum-based pick-up mechanism.

[0069] A discussion of the electronic design automation (EDA) / computer-aided design (CAD) flow required to realize a 3D-IC system-on-chip (SoC) is now appropriate. Typically, a 2D ASIC SoC consists of billions of transistors optimally arranged to meet performance / speed, area, and power specifications. Commercially available EDA CAD tools exist to simplify the design process for efficiently designing 2D ASIC SoCs, i.e., to meet design specifications with a lower turnaround time to market (TAT). However, no such EDA tools exist for 3D-IC ASIC design.

[0070] A typical ASIC SoC can be broadly divided into the following segments: logic (CPU, GPU, modem, etc.), memory / cache (static random access memory (SRAM), embedded dynamic random access memory (eDRAM), etc.), third-party IP blocks, analog IP, IO, etc. 3D SoC design offers the benefits of reduced footprint, reduced memory access time and latency, higher bandwidth, and faster Mbits / mm 2 The goal is to implement an SoC with the same functionality while improving performance in terms of higher capacity in terms of bandwidth, higher frequencies due to shorter interconnect delays, etc.

[0071] A typical 3D SoC, also referred to herein as a "nano-precision aligned 3D stacked integrated circuit (N3SI)," includes n base transistor layers, where N>1. In one embodiment, an application-specific integrated circuit (ASIC) system on a chip with logic and memory circuits is designed and fabricated in three dimensions using a sub-50 nm overlay pick-and-place method, which enables precise overlay of the logic and memory circuits. Each base layer can have m metal layers, where m>1 and can vary from base layer to base layer. The base layers in the 3D stack can be arranged in any of the following configurations relative to each other: face-to-face, face-to-back, back-to-back, etc. Connections between different base layers can be made using interlayer vias (ILVs) when the base layers are in a face-to-face configuration, or nanoscale through-silicon vias (nano-TSVs) when the base layers are in a face-to-face or back-to-back configuration. 3D SoCs can be designed using any combination of the following design approaches: There are several approaches to implementing 3D logic: 2D logic with 3D memory implementation, 3D logic with 2D memory implementation, and 3D logic with 3D memory implementation. 3D logic implementation can be performed at the block / partition level or at the flat level. In 3D block-level logic implementation, partitions are synthesized and routed using 2D tools, but different partitions are placed on different base layers. This approach requires changes only to the top-level SoC design, but the block-level design of a 3D SoC remains the same as a 2D SoC. Therefore, this approach is easier to implement. In flat-level 3D logic implementation, partitions are also implemented in 3D, i.e., cells within a partition are placed on multiple base layers. 3D logic implementation and 3D memory design implementation are discussed below. Area overhead due to TSVs and HF holes can also be optimized using space optimization algorithms.

[0072] Next, an electronic design automation (EDA) design methodology for 3D-IC logic implementation will be described. A conventional 2D ASIC EDA flow for logic implementation is shown in Figure 15 according to an embodiment of the present invention. Synthesis is performed in the front-end design stage, and the back-end design stage performs placement, pre-CTS optimization, clock tree synthesis (CTS), route and post-route optimization, sign-off analysis, and design verification.

[0073] The present invention's EDA methodology for 3D-IC SoCs is also similar to the 2D ASIC flow. This method attempts to reuse a large portion of existing commercial 2D EDA tools, along with using some in-house developed solutions. Such a flow is referred to herein as the "N3SI EDA flow." The following subsections describe the design steps of the N3SI EDA flow.

[0074] 3D-IC SoC Synthesis Synthesis of 3D-IC SoCs utilizes commercially available 2D synthesis tools. In the first pass, the design is synthesized exactly as it would be for a 2D SoC. Once placement is performed, 3D placement-aware synthesis is performed. In this synthesis pass, the tool synthesizes cells more optimally because it has 3D placement information to obtain accurate interconnect loads and delays. This process flow is also similar to 2D placement-aware synthesis, but in this case the placement information is in three dimensions.

[0075] 3D-IC SoC installation This section describes 3D placement of logic / standard cells. In our method, the design netlist is first partitioned into multiple modules, with each module netlist consisting of logic cells placed on a different layer of the 3D-IC SoC stack. Next, a commercially available 2D EDA tool is used to perform 2D placement of each module within its assigned layer of the 3D stack. Netlist partitioning can be performed using an in-house solution utilizing standard partitioning algorithms such as FM Min-Cut and Min-Flow. Modules generated by partitioning consist of input / output ports that can be placed anywhere within the module, not just at the module periphery. Consequently, in-house developed software generates the locations of these ports using standard partitioning algorithms. Multiple modules transfer signals through these ports. These ports can be connected via interlayer vias (ILVs) or nanoscale through-silicon vias (nano-TSVs). The locations of these ports can be constrained based on the thermal and mechanical stability of the ILVs and TSVs. Once port locations are determined, the timing budget and port locations are fed into a 2D placement tool to perform placement of each module independently, ensuring that overall timing and performance metrics are measured simultaneously. To ensure legal cell placement, placement or routing blocks are formed in module areas through which TSV or HF holes pass. In-house developed software generates placement or routing blockages using standard partitioning algorithms to avoid DRC issues (design rule checks) at ILV / TSV locations, etc.

[0076] CTS for 3D-IC SoC Clock tree synthesis (CTS) for 3D SoCs can be performed using existing 2D EDA place-and-route (P&R) tools. Once the design is partitioned and placed into multiple modules, the clock tree can be constructed and optimized separately for each module. However, the challenge with 3D clock trees is ensuring there are no setup, hold, etc. violations while accounting for process variations across multiple wafers on which the 3D clock tree may be constructed. There are several possible ways to solve or prevent this problem. One possible solution is to constrain the placement of launch and capture flops on the same layer, i.e., the launch and capture flops for a data path must be placed on the same layer. This can be achieved with an in-house netlist partitioning tool. Another solution is to include a high margin to ensure there are no violations in the worst-case process variation scenario.

[0077] The 3D-IC SoC Route The routing method for 3D-IC SoCs includes 2D routing within each module and routing across multiple modules using ILVs and nano-TSVs. Resistance and capacitance values ​​can be accurately determined and are discussed next. The 3D-IC routing method remains the same as 2D routing. Routing for each module can be performed using 2D P&R tools separately. To ensure there are no design rule check (DRC) failures, routing blockages are formed in the areas where ILVs and TSV interconnects are placed.

[0078] Parasitic extraction for 3D-IC SoC The design methodology for parasitic extraction of 3D SoCs differs from that of 2D ASICs. Resistance and capacitance values ​​can vary significantly due to TSVs and ILVs. Commercially available EDA tools cannot perform 3D extraction. However, embodiments of the present invention utilize a 3D extraction flow that leverages existing 2D extractors. In this flow, layout information for each module or layer is first streamed out. Then, the layout / route data for all modules is streamed to a layout editor tool such as Virtuoso®. During streaming in, the layout of a specific module can be flipped as needed to make it look similar to the 3D SoC stackup. The extractor is then run on this layout. The resulting resistance and capacitance values ​​are expected to be accurate, considering the 3D layout, taking into account TSVs and ILVs.

[0079] Next, we will describe a 3D design implementation of a static random access memory (SRAM). A typical SRAM includes a bit cell array with word lines and bit lines, sense amplifiers, column and row decoders, timer circuits, IOs, and other peripheral circuits. There are several SRAM configurations for arranging SRAM design elements, such as a butterfly configuration and a single-sided configuration. These configurations differ in implementation complexity, access time, latency, etc. Figure 16 shows a 2D single-sided SRAM configuration according to one embodiment of the present invention. The SRAM configuration includes basic memory design elements such as a bit array of SRAM cells 1601, bit lines 1602, word lines 1603, IO cells 1604, timer circuits 1605, sense amplifiers 1606, and decoders 1607.

[0080] Similar to 2D SRAM configurations, 3D SRAM can be designed in multiple configurations depending on the design needs. 3D eSRAM is also similar to the 3D SRAM methodology, and similar eDRAM configurations can be designed. One possible 3D single-sided SRAM configuration, shown in Figure 17, is a 3D stacked die of stand-alone SRAM arrays. Figure 17 illustrates 3D stand-alone SRAM die stacking according to one embodiment of the present invention.

[0081] In this 3D SRAM configuration, each layer implements a self-sustaining 2D single-sided SRAM. Data input, power, and control signals are supplied to each 2D SRAM stacked in the 3D configuration, and output data signals are obtained from each layer. The complete 3D SRAM output is obtained by combining the data outputs from all layers. For example, as shown in Figure 17, in The data bus signal is split into four 8-bit data bus signals and fed to each of the four layers. out consists of 8 bits, and the data output D out Combining these results in a 32-bit output signal.

[0082] Another possible 3D single-sided SRAM configuration is the 3D only bit cell stacked SRAM shown in FIG. 18 according to one embodiment of the present invention.

[0083] In this type of 3D SRAM configuration, the base layer, or layer-1, includes a bit cell array 1801 with bit lines 1802 and word lines 1803, and control and peripheral circuit elements such as IO cells 1804, timer circuits 1805, sense amplifiers 1806, and decoders 1807. The stacked 3D layers include only the bit cell array, bit lines, and word lines. In one embodiment, the control circuitry in the base layer for a 3D SRAM is expected to have more column decoders compared to a 2D configuration. Similar to single-sided SRAM designs, other 2D SRAM configurations, such as the butterfly, can also be realized in 3D.

[0084] For a 3D-only bitcell style stacked SRAM, there are several ways to design according to the design specifications. In one configuration, each layer contains a bitcell array of the same size as a 2D SRAM. In a 3D SARM, the bitline and wordline lengths, bandwidth, footprint, etc. remain the same as in a 2D SARM, but the memory capacity, i.e., array bitcell density, is increased by n times, where n is the number of layers. A minor modification to this design configuration would be to add more sense amplifiers to increase memory bandwidth. Figure 19 shows a vertical bitline cross section of a 3D-only bitcell stacked SRAM according to one embodiment of the present invention.

[0085] As shown in Figure 19, in this example, a column decoder is not used to select the bit line layer. However, it is expected that memory access time will be reduced due to shorter bit line lengths, which ultimately reduces the time constant RC, where R is resistance and C is capacitance. A decoder can be added to this design to select the bit line for a particular layer.

[0086] Another possible 3D-only bitcell stacked SRAM design configuration reduces the footprint / area while keeping the memory capacity, i.e., array bitcell density, the same. In this configuration, the first base layer contains control circuitry identical to that used in 2D SRAM configurations. The bitcell array footprint is typically 70% of the SRAM area in 2D configurations and can be reduced in 3D configurations. The bitcell array area can be divided by n, where n>1 is the number of bitcell array layers. This configuration reduces the length of the bitlines and wordlines and adds column decoders. However, this type of memory configuration is expected to result in shorter memory access times.

[0087] Using the principles of the present invention, it is now possible to fabricate three-dimensional (3D) stacked integrated circuits. In one embodiment, a pick-and-place strategy is used to stack source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication techniques. Source wafers can be stacked sequentially or in parallel. Stacking can be face-to-face, face-to-back, back-to-face, or back-to-back. Source wafers stacked in a face-to-back, back-to-face, or back-to-back fashion can be connected using through-silicon vias (TSVs). Alternatively, source wafers stacked face-to-face can be connected using interlayer vias (ILVs).

[0088] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications or technical improvements to technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A method for assembling a source wafer onto a product wafer, comprising: picking up the source wafer including a plurality of die areas; placing and bonding the picked-up source wafer onto the product wafer using a precision overlay; Including, the precision overlay is enabled by a fluid disposed between the die areas on the source wafer and the product wafer; The precision overlay includes a difference between vector positions of points in one or more of the plurality of die areas and vector positions of corresponding points on the product wafer. method.

2. The fabrication method is performed to achieve one of an overlay accuracy of 100 nm or less, 25 nm or less, 10 nm or less, and 5 nm or less. The method of claim 1.

3. The precision overlay is achieved using nanometer-precision overlay metrology. The method of claim 1.

4. The precision overlay is achieved using Moire metrology methods. The method of claim 1.

5. The precision overlay is achieved using IR moire metrology. The method of claim 1.

6. performing a coarse alignment; performing a fine alignment; 10. The method of claim 1, comprising:

7. the fluid comprises one of a gas, a liquid, and a combination of a gas and a liquid; The combination may include different gas and liquid portions or homogeneously mixed gas and liquid portions. The method of claim 1.

8. The fluid includes air. The method of claim 1.

9. The fluid comprises a liquid The method of claim 1.

10. The fluid comprises a volatile liquid The method of claim 1.

11. The fluid includes an adhesive. The method of claim 1.

12. During the placing and bonding, the topography of one or more of the die regions is changed. The method of claim 1.

13. The topography change is performed using a piezoelectric actuator. The method of claim 12.

14. Distortion control of one or more of the die regions is used to enable the precision overlay. The method of claim 1.

15. The strain control is enabled by thermal actuators.

15. The method of claim 14.

16. The thickness of the liquid is varied using a pre-calculated droplet volume.

10. The method of claim 9.

17. Prior to assembly, one or more of the die regions are surface activated. The method of claim 1.

18. The bonding includes direct bonding. The method of claim 1.

19. 1. A method for assembling one or more dies on a product substrate, comprising: selectively picking up the one or more dies from a source wafer by a superstrate attached to the one or more dies; placing the selectively picked-up one or more dies onto the product substrate; Including, Alignment metrology between the one or more dies and the product substrate is performed using a metrology scheme that references the superstrate and the product substrate. method.

20. The one or more dies include a plurality of dies.

20. The method of claim 19.

21. The selectively picking and placing are performed in a massively parallel manner.

20. The method of claim 19.

22. The fabrication method is performed to achieve one of an overlay accuracy of 100 nm or less, 25 nm or less, 10 nm or less, and 5 nm or less.

20. The method of claim 19.

23. Precise overlay between the one or more dies and the product substrate is achieved using nanometer-accuracy overlay metrology.

20. The method of claim 19.

24. Precise overlay between the one or more dies and the product substrate is achieved using Moire metrology.

20. The method of claim 19.

25. Precise overlay between the one or more dies and the product substrate is achieved using IR moire metrology.

20. The method of claim 19.

26. performing coarse alignment using a stage actuator as the selectively picked up one or more dies are brought close to the product substrate; performing fine alignment after the one or more dies contact a fluid disposed between the one or more dies and the product substrate; 20. The method of claim 19, comprising:

27. precision overlay is enabled by a fluid disposed between the one or more dies and the product substrate; the fluid comprises one of a gas, a liquid, and a combination of a gas and a liquid; The combination may include different gas and liquid portions or homogeneously mixed gas and liquid portions.

20. The method of claim 19.

28. precision overlay is enabled by a fluid disposed between the one or more dies and the product substrate; The fluid includes air.

20. The method of claim 19.

29. precision overlay is enabled by a fluid disposed between the one or more dies and the product substrate; The fluid comprises a volatile liquid 20. The method of claim 19.

30. precision overlay is enabled by a fluid disposed between the one or more dies and the product substrate; The fluid includes an adhesive.

20. The method of claim 19.

31. The superstrate includes a piezoelectric actuator that enables topographical changes of the one or more dies.

20. The method of claim 19.

32. Precise overlay is possible using distortion control of the one or more dies.

20. The method of claim 19.

33. The strain control is enabled by thermal actuators.

33. The method of claim 32.

34. a scribe width between the one or more dies on the source wafer between 200 nanometers and 10 micrometers 20. The method of claim 19.

35. Prior to assembly, the one or more dies are surface activated to allow for the assembly.

20. The method of claim 19.

36. Assembly includes direct joining 20. The method of claim 19.

Images