Semiconductor device

Abstract

To reduce the parasitic capacitance of a wire of a display device, provide a display device having both high resolution and high frame frequency, and provide a high-definition display device.SOLUTION: A semiconductor device used in a display device includes a first resin layer between a first wire and a transistor, a first insulating layer between the first resin layer and the transistor, a second resin layer between the transistor and a second wire, and a second insulating layer between the second resin layer and the transistor. The first insulating layer and the second insulating layer include an inorganic insulating film containing nitrogen. Compared to the first insulating layer and the second insulating layer, the first resin layer and the second resin layer respectively have lower dielectric constant and have their thickness 5 times or more and 100 times or less.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] In recent years, there has been a demand for high-resolution display devices. For example, while the mainstream of home television sets (also called televisions or television receivers) has a resolution of full high definition (1920 x 1080 pixels), it is expected that television sets will continue to have higher resolutions in the future, such as 4K (3840 x 2160 pixels) or 8K (7680 x 4320 pixels).

[0004] Furthermore, in portable information terminal devices such as mobile phones, smartphones, tablet terminals, and notebook PCs, the resolution of display panels used in the display units of the devices is also increasing.

[0005] Oxide semiconductors using metal oxides have been attracting attention as semiconductor materials applicable to transistors used in display devices. For example, Patent Document 1 discloses a semiconductor device in which a plurality of oxide semiconductor layers are stacked, and an oxide semiconductor layer serving as a channel contains indium and gallium, and the proportion of indium is made higher than the proportion of gallium, thereby increasing field-effect mobility. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-7399 Summary of the Invention [Problem to be solved by the invention]

[0007] For display devices with the same screen size, the higher the resolution, the higher the pixel density, which results in a larger parasitic capacitance between wires. Furthermore, the higher the resolution, the more wires a single wire crosses, which in turn increases the parasitic capacitance. If the parasitic capacitance of a wire is large, the time constant of the wire increases, making it difficult to display images at a high frame frequency.

[0008] An object of one embodiment of the present invention is to provide a display device in which parasitic capacitance of wiring is reduced.An object of one embodiment of the present invention is to provide a display device which achieves both high resolution and a high frame frequency.An object of one embodiment of the present invention is to provide a high-definition display device.An object of one embodiment of the present invention is to provide a highly reliable display device or semiconductor device.

[0009] An object of one embodiment of the present invention is to provide a semiconductor device, a display device, a display module, an electronic device, or the like having a novel structure.An object of one embodiment of the present invention is to provide a method for manufacturing the above-described display device or semiconductor device with high yield.An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device including a first wiring, a second wiring, and a transistor. The semiconductor device includes a first resin layer between the first wiring and the transistor. The semiconductor device includes a first insulating layer between the first resin layer and the transistor. The semiconductor device includes a second resin layer between the transistor and the second wiring. The semiconductor device includes a second insulating layer between the second resin layer and the transistor. The first insulating layer and the second insulating layer include an inorganic insulating film containing nitrogen. The first resin layer and the second resin layer have a lower dielectric constant than the first insulating layer and the second insulating layer, respectively. Furthermore, the first resin layer and the second resin layer are 5 to 100 times thicker than the first insulating layer and the second insulating layer, respectively.

[0012] Preferably, the first and second resin layers contain the same material and have the same thickness. Alternatively, the thickness of the second resin layer is preferably 80% to 120% of the thickness of the first resin layer. Furthermore, the first and second resin layers are preferably formed using the same material and the same film formation method.

[0013] Preferably, the first and second insulating layers contain the same material and have the same thickness. Alternatively, the thickness of the second insulating layer is preferably 80% to 120% of the thickness of the first insulating layer. Furthermore, the first and second insulating layers are preferably formed using the same material and by the same film formation method.

[0014] In the above, the transistor preferably includes a first gate electrode, a second gate electrode, a first gate insulating layer, a second gate insulating layer, and a semiconductor layer. In this case, the first gate insulating layer is located between the semiconductor layer and the first gate electrode. The second gate insulating layer is located between the semiconductor layer and the second gate electrode. The first gate electrode and the second gate electrode have an overlapping region with the semiconductor layer interposed therebetween. The first gate electrode is electrically connected to the first wiring through an opening provided in the first insulating layer and the first resin layer.

[0015] In the above, the second wiring is preferably electrically connected to the semiconductor layer through an opening provided in the second resin layer and the second insulating layer.

[0016] Alternatively, in the above, the transistor preferably has a first electrode between the second resin layer and the second insulating layer. Furthermore, the first electrode is preferably electrically connected to a part of the semiconductor layer through an opening provided in the second insulating layer. Furthermore, the second wiring is preferably electrically connected to the first electrode through an opening provided in the second resin layer.

[0017] In any of the above, the second gate electrode is preferably electrically connected to the first gate electrode through an opening provided in the first gate insulating layer and the second gate insulating layer.

[0018] In any of the above, the semiconductor layer preferably contains either indium or zinc, or both, and oxygen. In this case, the semiconductor layer preferably contains indium, gallium, and zinc, and the atomic ratio of indium in the semiconductor layer is more preferably at least twice that of gallium, and the atomic ratio of zinc in the semiconductor layer is more preferably at least twice that of gallium.

[0019] In any of the above, it is preferable that the first resin layer and the second resin layer each contain acrylic or polyimide.

[0020] Another embodiment of the present invention is a display device including any one of the above semiconductor devices, a pixel electrode, a source driver circuit, and a gate driver circuit. The display device preferably includes a third resin layer between the pixel electrode and the transistor. The first wiring is preferably electrically connected to the source driver circuit, and the second wiring is preferably electrically connected to the gate driver circuit.

[0021] In the above, it is preferable that the display device further comprises an organic EL element, and in this case, the pixel electrode is preferably an electrode of the organic EL element.

[0022] Another embodiment of the present invention is a display module including any one of the display devices described above and a connector or an integrated circuit.

[0023] Another embodiment of the present invention is an electronic device including the above display module and at least one of an antenna, a battery, a housing, a camera, a speaker, a microphone, a touch sensor, and an operation button. [Effects of the Invention]

[0024] According to one embodiment of the present invention, a display device in which parasitic capacitance of wiring is reduced can be provided. Alternatively, a display device which achieves both high resolution and a high frame frequency can be provided. Alternatively, a high-definition display device can be provided. Alternatively, a highly reliable display device or semiconductor device can be provided.

[0025] According to one aspect of the present invention, it is possible to provide a semiconductor device, a display device, a display module, or an electronic device having a novel configuration. Alternatively, it is possible to provide a method for manufacturing the above-described display device or semiconductor device with a high yield. According to one aspect of the present invention, it is possible to at least alleviate at least one of the problems of the prior art.

[0026] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0027] [Figure 1] 1A to 1C are diagrams showing configuration examples of a semiconductor device. [Figure 2] 2A and 2B are diagrams showing an example of the configuration of a semiconductor device. [Figure 3] 3A and 3B are diagrams showing an example of the configuration of a semiconductor device. [Figure 4]4A to 4F are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 5] 5A to 5D are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 6] 6A to 6C are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 7] 7A and 7B are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 8] 8A and 8B are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 9] 9A to 9C are diagrams showing configuration examples of a display device. [Figure 10] 10A to 10C are diagrams showing examples of pixel configurations. [Figure 11] FIG. 11 is a diagram illustrating an example of the configuration of a display device. [Figure 12] FIG. 12 is a diagram illustrating an example of the configuration of a display device. [Figure 13] 13A to 13F are diagrams showing configuration examples of electronic devices. [Figure 14] 14A and 14B are diagrams showing configuration examples of a display module. [Figure 15] 15A and 15B are diagrams showing configuration examples of electronic devices. [Figure 16] 16A to 16E are diagrams showing configuration examples of electronic devices. [Figure 17] 17A to 17G are diagrams showing configuration examples of electronic devices. [Figure 18] 18A to 18D are diagrams showing configuration examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0029] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0030] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0031] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0032] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. In this specification, the term "transistor" includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).

[0033] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0034] Furthermore, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" may be interchangeable with the terms "conductive film" and "insulating film."

[0035] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting) images etc. on a display surface, and therefore the display panel is one aspect of an output device.

[0036] In addition, in this specification, a display panel having a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) attached to the substrate, or having an IC mounted on the substrate using a COG (Chip On Glass) method or the like, may be referred to as a display panel module, display module, or simply a display panel.

[0037] (Embodiment 1) This embodiment will describe a semiconductor device, a manufacturing method thereof, a display device, etc., according to one embodiment of the present invention. In particular, this embodiment will describe a transistor including an oxide semiconductor for a semiconductor layer in which a channel is formed, as an example of a semiconductor device.

[0038] [Configuration example] [Configuration example 1] FIG. 1A shows a schematic top view of a semiconductor device including a transistor 100. FIG. 1B corresponds to a cross-sectional view taken along dashed line A1-A2 in FIG. 1A, and FIG. 1C corresponds to a cross-sectional view taken along dashed line B1-B2 in FIG. 1A. Note that FIG. 1A omits some of the components (such as a gate insulating layer). FIG. 1B is a cross-sectional view of the transistor 100 taken along the channel length direction, and FIG. 1C is a cross-sectional view taken along the channel width direction.

[0039] The transistor 100 is provided over a substrate 102 and includes a conductive layer 106, an insulating layer 103a, an insulating layer 103b, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, a conductive layer 112, and the like. A resin layer 131 is provided between the transistor 100 and the substrate 102. A resin layer 132 is provided over the transistor 100. An insulating layer 104 is provided between the resin layer 131 and the transistor 100. An insulating layer 116 and an insulating layer 118 are stacked between the transistor 100 and the resin layer 132.

[0040] In the transistor 100, part of the conductive layer 106 and part of the conductive layer 112 each function as a gate electrode. Part of the insulating layer 103a, part of the insulating layer 103b, and part of the insulating layer 110 each function as a gate insulating layer.

[0041] A conductive layer 130 functioning as wiring is provided between the substrate 102 and the resin layer 131. Furthermore, a conductive layer 120a and a conductive layer 120b are provided on the resin layer 132. At least one of the conductive layer 120a and the conductive layer 120b functions as wiring.

[0042] Furthermore, a resin layer 133 is provided to cover the resin layer 132, the conductive layer 120a, and the conductive layer 120b. A conductive layer 150 is further provided on the resin layer 133. The conductive layer 150 can be used, for example, as a pixel electrode of a display element. Alternatively, the conductive layer 150 may be used as a wiring. The conductive layer 150 is electrically connected to the conductive layer 120b in an opening 144 provided in the resin layer 133.

[0043] The insulating layer 104 functions as a barrier film that prevents impurities such as water or hydrogen in the resin layer 131 from diffusing into the transistor 100. Similarly, the insulating layer 116 functions as a barrier film that prevents impurities such as water or hydrogen contained in the resin layer 132 from diffusing into the transistor 100. In this way, by enclosing the transistor 100 with the insulating layers 104 and 116, a highly reliable semiconductor device can be realized even with a structure in which the transistor 100 is sandwiched between resin layers above and below.

[0044] For the insulating layer 104 and the insulating layer 116, an inorganic insulating film through which water or hydrogen does not easily diffuse can be used. For example, an insulating film containing a nitride, such as silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, or aluminum nitride oxide, can be preferably used. In particular, silicon nitride has a blocking property against either or both of hydrogen and oxygen, and therefore can prevent both diffusion of hydrogen from the outside to the semiconductor layer 108 and desorption of oxygen from the semiconductor layer 108 to the outside, thereby realizing a highly reliable transistor.

[0045] An organic resin can be used for the resin layer 131 and the resin layer 132. In particular, it is preferable to use acrylic or polyimide. However, the material that can be used for the resin layer 131 is not limited to these, and any chemically or thermally stable material can be used.

[0046] The resin layers 131 and 132 preferably function as planarizing films. For example, they are preferably films formed by a coating method such as spin coating or slit coating. The resin layer 131 functions as a planarizing film, thereby suppressing the influence of steps due to the conductive layer 130 located closer to the substrate 102 than the transistor 100, flattening the surface on which the transistor 100 is to be formed, and reducing variations in the electrical characteristics of the transistor 100. Furthermore, the resin layer 132 functions as a planarizing film, thereby suppressing the influence of steps due to the transistor 100, flattening the surfaces on which the conductive layers 120a and 120b are to be formed, and reducing processing defects. Furthermore, the surface on which the conductive layer 150, which can be used as a pixel electrode, is formed can be flattened, thereby reducing variations in the electrical and optical characteristics of a display element using the conductive layer 150 as a pixel electrode.

[0047] It is preferable that the resin layer 131 and the resin layer 132 each have a low dielectric constant. Specifically, it is preferable to use an organic insulating material having a lower dielectric constant than either or both of the insulating layer 104 and the insulating layer 116. In particular, it is preferable that the resin layer 131 and the resin layer 132 have a lower dielectric constant than both the insulating layer 104 and the insulating layer 116.

[0048] Furthermore, it is preferable that resin layer 131 and resin layer 132 are each formed thick. For example, it is preferable that resin layer 131 and resin layer 132 are each thicker than either or both of insulating layer 104 and insulating layer 116. In particular, it is preferable that resin layer 131 and resin layer 132 are thicker than both insulating layer 104 and insulating layer 116. Specifically, resin layer 131 and resin layer 132 can each be 5 to 100 times, 5 to 50 times, or 5 to 30 times thicker than insulating layer 104 or insulating layer 116. As a more specific example, insulating layer 104 and insulating layer 116 can each be 50 nm to 300 nm thick, and resin layer 131 and resin layer 132 can each be 500 nm to 20 μm thick, preferably 1 μm to 10 μm thick.

[0049] The left side of FIG. 1B shows a cross section at the intersection of conductive layer 130 and conductive layer 120a shown in FIG. 1A.

[0050] At least resin layers 131 and 132 are provided between the conductive layer 130 and the conductive layer 120a. The resin layers 131 and 132 have a low dielectric constant and are formed thick, so that the capacitance generated between the conductive layer 130 and the conductive layer 120a at their intersection can be made extremely small. This makes it possible to realize a display device that can be driven at a high resolution, high definition, and high frame rate.

[0051] Because the parasitic capacitance between wiring can be reduced, the number of pixels connected to one wiring can be increased, enabling display devices with high resolutions equivalent to full high definition (also called "2K resolution," "2K1K," or "2K"), ultra high definition (also called "4K resolution," "4K2K," or "4K"), or super high definition (also called "8K resolution," "8K4K," or "8K").

[0052] Furthermore, because the parasitic capacitance between wiring lines is small, an increase in the time constant of the wiring lines can be suppressed even when the resolution is increased, thereby realizing a high-resolution display device. The resolution can be, for example, 400 ppi or more, or 500 ppi or more, preferably 1000 ppi or more, more preferably 2000 ppi or more, or even 3000 ppi or more, and a high-resolution display device having a resolution of 10000 ppi or less, 7500 ppi or less, or 6000 ppi or less can be realized. Note that the above configuration is also preferable for display devices with a resolution of less than 400 ppi, since applying it can reduce parasitic capacitance. For example, the above configuration can be suitably used in large display devices with a diagonal screen size of 50 inches or more, 60 inches or more, or 70 inches or more.

[0053] Furthermore, since the time constant of the wiring can be reduced, the time required for charging and discharging the wiring (for example, the time required for writing to pixels) can be shortened, making it possible to drive at high frame rates, such as 60 Hz, 120 Hz, 180 Hz, and even 240 Hz.

[0054] Furthermore, it is preferable that the resin layer 131 and the resin layer 132 contain the same material and have the same thickness. Alternatively, it is preferable that the thickness of the resin layer 132 is 80% to 120% of the thickness of the resin layer 131. Furthermore, it is preferable that the resin layer 131 and the resin layer 132 are formed using the same material and by the same film formation method.

[0055] By forming the pair of resin layers 131 and 132 sandwiching the transistor 100 from the same material and making them approximately the same thickness, it is possible to make the stresses approximately the same. This makes it possible to make the stresses approximately the same on the top and bottom of the transistor 100, so that an extreme difference in stress does not occur, and as a result, it is possible to suppress film peeling during processing. Furthermore, since the stresses applied to the transistor 100 from above and below can be made uniform, it is possible to reduce variations in the electrical characteristics of the transistor 100.

[0056] Similarly, the insulating layers 104 and 116 preferably contain the same material and have the same thickness. Alternatively, the thickness of the insulating layer 116 is preferably 80% to 120% of the thickness of the insulating layer 104. Furthermore, the insulating layers 104 and 116 are preferably formed using the same material and by the same film formation method. This not only effectively prevents film peeling during the process but also reduces variations in the electrical characteristics of the transistor 100.

[0057] The conductive layer 106 is provided over the insulating layer 104. The insulating layer 103a is provided to cover the conductive layer 106. The insulating layer 103b is provided over the insulating layer 103a. The island-shaped semiconductor layer 108 is provided over the insulating layer 103b and overlaps with part of the conductive layer 106. The insulating layer 110, the metal oxide layer 114, and the conductive layer 112 are stacked in this order over the semiconductor layer 108 and the insulating layer 103b, and have parts that overlap with the semiconductor layer 108 and the conductive layer 106. The insulating layer 116 is provided to cover the insulating layer 103a, the semiconductor layer 108, the insulating layer 110, the metal oxide layer 114, and the conductive layer 112. The insulating layer 118 is provided over the insulating layer 116.

[0058] The semiconductor layer 108 has a region overlapping with the conductive layer 112 and a pair of low-resistance regions 108n that sandwich the region. The region of the semiconductor layer 108 overlapping with the conductive layer 112 functions as a channel formation region of the transistor 100. On the other hand, the pair of low-resistance regions 108n function as a source region and a drain region of the transistor 100.

[0059] The insulating layer 103a located on the conductive layer 106 side is preferably an insulating film containing nitrogen. On the other hand, the insulating layer 103b in contact with the semiconductor layer 108 is preferably an insulating film containing oxygen. The insulating layers 103a and 103b are preferably formed successively using a plasma CVD apparatus without exposure to air.

[0060] The insulating layer 103a can be an insulating film containing nitrogen, such as a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or a hafnium nitride film.

[0061] The insulating layer 103b in contact with the semiconductor layer 108 is preferably a dense insulating film whose surface is less likely to adsorb impurities such as water. It is also preferable to use an insulating film with as few defects as possible and in which impurities such as water or hydrogen are reduced.

[0062] The insulating layer 103b can be, for example, an insulating layer containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film. In particular, a silicon oxide film or a silicon oxynitride film is preferably used.

[0063] The insulating layer 103b in contact with the semiconductor layer 108 preferably includes an oxide insulating film. The insulating layer 103b more preferably includes a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 103b includes an insulating film capable of releasing oxygen. For example, oxygen can be supplied to the insulating layer 103b by forming the insulating layer 103b in an oxygen atmosphere, performing heat treatment on the formed insulating layer 103b in an oxygen atmosphere, performing plasma treatment or the like in an oxygen atmosphere after the formation of the insulating layer 110, or forming an oxide film (e.g., a metal oxide film to be the semiconductor layer 108) on the insulating layer 103b in an oxygen atmosphere. Note that in each of the above treatments for supplying oxygen, an oxidizing gas (e.g., nitrous oxide, ozone, or the like) may be used instead of or in addition to oxygen.

[0064] The semiconductor layer 108 contains a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor characteristics. The semiconductor layer 108 preferably contains at least indium and oxygen. When the semiconductor layer 108 contains an oxide of indium, carrier mobility can be increased. For example, a transistor that can pass a larger current than a transistor using amorphous silicon can be realized.

[0065] A region of the semiconductor layer 108 that overlaps with the conductive layer 112 functions as a channel formation region. The semiconductor layer 108 preferably has a pair of low-resistance regions 108n sandwiching the channel formation region. The low-resistance regions 108n have a higher carrier concentration than the channel formation region and function as a source region and a drain region.

[0066] The low-resistance region 108n can also be referred to as a region having a lower resistance than the channel formation region, a region having a higher carrier concentration, a region having a larger amount of oxygen vacancy, a region having a higher hydrogen concentration, or a region having a higher impurity concentration.

[0067] Here, the composition of the semiconductor layer 108 will be described. The semiconductor layer 108 preferably contains a metal oxide containing at least indium and oxygen. The semiconductor layer 108 may also contain zinc in addition to these elements. The semiconductor layer 108 may also contain gallium.

[0068] Typically, indium oxide, indium zinc oxide (In-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), or the like can be used for the semiconductor layer 108. Indium tin oxide (In-Sn oxide), indium tin oxide containing silicon, or the like can also be used.

[0069] Here, the composition of the semiconductor layer 108 greatly affects the electrical characteristics, reliability, and the like of the transistor 100. For example, by increasing the indium content in the semiconductor layer 108, carrier mobility can be improved, and a transistor with high field-effect mobility can be realized.

[0070] One of the indicators for evaluating transistor reliability is the gate bias stress test (GBT), in which an electric field is applied to the gate and the test is held at high temperature. Among these tests, a test in which a positive potential is applied to the gate relative to the source and drain potentials and the test is held at high temperature is called a PBTS (Positive Bias Temperature Stress) test, and a test in which a negative potential is applied to the gate and the test is held at high temperature is called an NBTS (Negative Bias Temperature Stress) test. Furthermore, the PBTS and NBTS tests, which are conducted under illumination with light such as white LED light, are called PBTIS (Positive Bias Temperature Illumination Stress) and NBTIS (Negative Bias Temperature Illumination Stress), respectively.

[0071] In particular, in an n-type transistor using an oxide semiconductor, a positive potential is applied to the gate when the transistor is turned on (a state in which current flows), so the amount of change in threshold voltage in the PBTS test is one of the important items to focus on as an index of transistor reliability.

[0072] Here, by using a metal oxide film that does not contain gallium or has a low gallium content as the composition of the semiconductor layer 108, the amount of variation in threshold voltage in the PBTS test can be reduced. Furthermore, when gallium is contained, it is preferable that the gallium content be smaller than the indium content in the composition of the semiconductor layer 108. This makes it possible to realize a highly reliable transistor.

[0073] More specifically, when an In-Ga-Zn oxide is used for the semiconductor layer 108, a metal oxide film in which the atomic ratio of In is higher than the atomic ratio of Ga can be used for the semiconductor layer 108. It is more preferable to use a metal oxide film in which the atomic ratio of Zn is higher than the atomic ratio of Ga. In other words, it is preferable to use a metal oxide film in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga for the semiconductor layer 108.

[0074] For example, the semiconductor layer 108 can be a metal oxide film having an atomic ratio of metal elements of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=6:1:6, In:Ga:Zn=5:2:5, or a ratio close to these.

[0075] Alternatively, the semiconductor layer 108 is preferably a film formed by a sputtering method using a metal oxide target whose atomic ratio of metal elements falls within the above range. In this case, the composition of the semiconductor layer 108 after deposition may differ from the composition of the metal oxide target.

[0076] Alternatively, a metal oxide film containing no gallium may be used for the semiconductor layer 108. For example, In-Zn oxide may be used for the semiconductor layer 108. In this case, increasing the atomic ratio of In to the atomic number of metal elements contained in the metal oxide film can increase the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of Zn to the atomic number of metal elements contained in the metal oxide film results in a metal oxide film with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving reliability. Alternatively, a metal oxide film containing no gallium or zinc, such as indium oxide, may be used for the semiconductor layer 108. Using a metal oxide film containing no gallium at all can significantly reduce fluctuations in threshold voltage, particularly in a PBTS test.

[0077] For example, an oxide film such as indium oxide, indium zinc oxide, or indium tin oxide can be used for the semiconductor layer 108.

[0078] Although gallium has been described as a representative example here, the above description can also be applied to the case where element M (M is one or more elements selected from aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) is used instead of gallium. In particular, it is preferable that M is one or more elements selected from gallium, aluminum, yttrium, and tin.

[0079] It is preferable to use a crystalline metal oxide film for the semiconductor layer 108. For example, a metal oxide film having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a microcrystalline structure, or the like, which will be described later, can be used. By using a crystalline metal oxide film for the semiconductor layer 108, the density of defect states in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0080] The higher the crystallinity of the semiconductor layer 108, the more the density of defect states in the film can be reduced. On the other hand, by using a metal oxide film with low crystallinity, a transistor capable of passing a large current can be realized.

[0081] When a metal oxide film is formed by sputtering, the higher the substrate temperature (stage temperature) during film formation, the higher the crystallinity of the formed metal oxide film.Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film formation gas used during film formation (also referred to as the oxygen flow rate ratio), the higher the crystallinity of the formed metal oxide film.

[0082] The low-resistance region 108n of the semiconductor layer 108 is a region containing an impurity element. Examples of the impurity element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, and rare gases. Typical examples of rare gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable for the low-resistance region 108n to contain boron or phosphorus. Two or more of these elements may also be contained.

[0083] The low resistance region 108n has an impurity concentration of 1×10 19 atoms / cm 3 That's it, 1 x 10 23 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 That's it, 5 x 10 22 atoms / cm 3 Less than 1×10, more preferably 20 atoms / cm 3 That's it, 1 x 10 22 atoms / cm 3 It is preferred to include a region in which:

[0084] The concentration of impurities contained in the low-resistance region 108n can be analyzed by, for example, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), etc. When XPS analysis is used, the concentration distribution in the depth direction can be determined by combining ion sputtering from the front or back side with XPS analysis.

[0085] The conductive layer 112, the metal oxide layer 114, and the insulating layer 110 are processed so that their top surface shapes generally match each other.

[0086] In this specification, the phrase "top surface shapes generally match" means that at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" also applies.

[0087] As for the insulating film that can be used for the insulating layer 110, the description of the insulating layer 103b can be cited.

[0088] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 functions as a barrier film that prevents oxygen contained in the insulating layer 110 from diffusing toward the conductive layer 112. The metal oxide layer 114 also functions as a barrier film that prevents hydrogen or water contained in the conductive layer 112 from diffusing toward the insulating layer 110. For the metal oxide layer 114, it is preferable to use a material that is less permeable to oxygen and hydrogen than, for example, the insulating layer 110.

[0089] The metal oxide layer 114 can prevent oxygen from diffusing from the insulating layer 110 to the conductive layer 112, even when the conductive layer 112 is made of a metal material that easily absorbs oxygen, such as aluminum or copper. Furthermore, even when the conductive layer 112 contains hydrogen, the metal oxide layer 114 can prevent hydrogen from diffusing from the conductive layer 112 to the semiconductor layer 108 through the insulating layer 110. As a result, the carrier density in the channel formation region of the semiconductor layer 108 can be made extremely low.

[0090] An insulating material or a conductive material can be used for the metal oxide layer 114. When the metal oxide layer 114 has insulating properties, the metal oxide layer 114 functions as a part of the gate insulating layer. On the other hand, when the metal oxide layer 114 has conductive properties, the metal oxide layer 114 functions as a part of the gate electrode.

[0091] It is preferable to use an insulating material having a higher dielectric constant than silicon oxide for the metal oxide layer 114. In particular, it is preferable to use an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like, because the driving voltage can be reduced.

[0092] Conductive oxides such as indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can also be used as the metal oxide layer 114. Conductive oxides containing indium are particularly preferred because of their high conductivity.

[0093] It is preferable to use an oxide material containing one or more of the same elements as those of the semiconductor layer 108 for the metal oxide layer 114. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108. In this case, it is preferable to use a metal oxide film formed using the same sputtering target as that for the semiconductor layer 108 for the metal oxide layer 114, because this allows the use of common equipment.

[0094] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering apparatus, oxygen can be suitably added to the insulating layer 110 or the semiconductor layer 108 by forming the oxide film in an atmosphere containing oxygen gas.

[0095] The insulating layer 116 is provided in contact with the upper surface of the low-resistance region 108n. The insulating layer 116 preferably has a function of reducing the resistance of the low-resistance region 108n. As such an insulating layer 116, an insulating film that can supply impurities into the low-resistance region 108n by heating during or after the formation of the insulating layer 116 can be used. Alternatively, an insulating film that can cause oxygen vacancies in the low-resistance region 108n by heating during or after the formation of the insulating layer 116 can be used. Alternatively, an insulating film that can impart strain to the low-resistance region 108n by heating during or after the formation of the insulating layer 116 can be used.

[0096] For example, an insulating film that functions as a supply source for supplying impurities to the low-resistance region 108n can be used as the insulating layer 116. In this case, the insulating layer 116 is preferably a film that releases hydrogen when heated. By forming such an insulating layer 116 in contact with the semiconductor layer 108, impurities such as hydrogen can be supplied to the low-resistance region 108n, thereby reducing the resistance of the low-resistance region 108n.

[0097] The insulating layer 116 is preferably formed using a gas containing an impurity element such as a hydrogen element as a deposition gas. The lower the deposition temperature of the insulating layer 116, the more impurity elements can be effectively supplied to the semiconductor layer 108. The deposition temperature of the insulating layer 116 can be, for example, 200° C. or higher and 500° C. or lower, preferably 220° C. or higher and 450° C. or lower, more preferably 230° C. or higher and 400° C. or lower.

[0098] Furthermore, forming the insulating layer 116 under reduced pressure and by heating can promote desorption of oxygen from the region that will become the low-resistance region 108n in the semiconductor layer 108. Supplying impurities such as hydrogen to the semiconductor layer 108 in which many oxygen vacancies have been formed increases the carrier density in the low-resistance region 108n, and can more effectively reduce the resistance of the low-resistance region 108n.

[0099] For example, an insulating film containing a nitride, such as silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, or aluminum nitride oxide, can be preferably used as the insulating layer 116. Silicon nitride in particular has a blocking property against hydrogen, oxygen, or the like, and can therefore prevent both diffusion of hydrogen from the outside to the semiconductor layer and desorption of oxygen from the semiconductor layer to the outside, thereby realizing a highly reliable transistor. Alternatively, an insulating film containing an oxide, such as silicon oxide, aluminum oxide, or hafnium oxide, can also be used.

[0100] The insulating layer 118 functions as a protective layer to protect the transistor 100. For example, an inorganic insulating material such as an oxide or a nitride can be used for the insulating layer 110. More specifically, an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, or hafnium aluminate can be used.

[0101] Note that either the insulating layer 116 or the insulating layer 118 does not necessarily have to be provided, or the stacking order of the insulating layer 116 and the insulating layer 118 may be changed.

[0102] It can also be said that parts of the conductive layer 120a and the conductive layer 120b provided over the resin layer 132 are electrically connected to the low-resistance region 108n of the transistor 100 and function as a source electrode or a drain electrode. The conductive layer 120a and the conductive layer 120b are electrically connected to the low-resistance region 108n through an opening 141a or an opening 141b provided in the resin layer 132, the insulating layer 118, and the insulating layer 116, respectively.

[0103] Here, an example is shown in which the conductive layer 112, the conductive layer 106, and the conductive layer 130 are electrically connected to each other. The conductive layer 112 is electrically connected to the conductive layer 106 at an opening 142 provided in the metal oxide layer 114, the insulating layer 110, the insulating layer 103b, and the insulating layer 103a. The conductive layer 106 is electrically connected to the conductive layer 130 at an opening 143 provided in the insulating layer 104 and the resin layer 131.

[0104] Although an example in which both of the pair of gate electrodes are electrically connected to the conductive layer 130 has been described here, a structure in which either one of the pair of gate electrodes is electrically connected to the conductive layer 130 may be used. For example, when the conductive layer 130 and the conductive layer 112 are electrically connected without the conductive layer 106, the conductive layer 130 and the conductive layer 106 may be electrically connected to each other through a relay electrode formed by processing the same conductive film as the conductive layer 106. Alternatively, an opening that reaches the upper surface of the conductive layer 130 from the metal oxide layer 114 may be formed, and the conductive layer 112 and the conductive layer 130 may be directly connected to each other.

[0105] Furthermore, by not providing the conductive layer 106 under the semiconductor layer 108, a transistor having only one gate (also referred to as a single-gate transistor) may be formed. In this case, the transistor can be a so-called top-gate transistor having a gate above the semiconductor layer 108 where a channel is formed. For example, in FIG. 1C, a single-gate transistor can be realized by forming the right end of the conductive layer 106 to be located between the opening 142 and the semiconductor layer 108.

[0106] [Configuration example 2] 2A and 2B show an example in which the configuration is partially different from that of Configuration Example 1. The configurations shown in Figures 2A and 2B differ mainly in that the shape of the insulating layer 110 is different.

[0107] The insulating layer 110 is provided to cover the upper surface of the insulating layer 103b and the upper and side surfaces of the semiconductor layer 108. The insulating layer 110 is provided in contact with not only the channel formation region of the semiconductor layer 108 but also the upper surface of the low-resistance region 108n.

[0108] The low-resistance region 108n can be formed by forming the insulating layer 110, the metal oxide layer 114, and the conductive layer 112, and then using the conductive layer 112 as a mask to supply an impurity or the like through the insulating layer 110. For example, the impurity element can be supplied to the semiconductor layer 108 through the insulating layer 110 by plasma treatment, plasma ion doping, ion implantation, or the like.

[0109] By forming the insulating layer 110 in this manner, the coverage of the insulating layer 116 in the vicinity of the end of the conductive layer 112 can be improved, thereby increasing reliability and manufacturing yield.

[0110] [Configuration Example 3] The configuration shown in FIG. 3A differs from Structural Example 1 above mainly in that it includes conductive layers 121a and 121b.

[0111] The conductive layer 120a is electrically connected to the low-resistance region 108n via the conductive layer 121a. The conductive layer 120b is electrically connected to the low-resistance region 108n via the conductive layer 121b. Therefore, the conductive layers 121a and 121b can also be called relay wirings.

[0112] The conductive layer 121a and the conductive layer 121b are provided between the insulating layer 118 and the resin layer 132. The conductive layer 121a and the conductive layer 121b are electrically connected to the low-resistance region 108n through openings provided in the insulating layer 118 and the insulating layer 116, respectively.

[0113] The conductive layer 120a and the conductive layer 120b are electrically connected to the conductive layer 121a and the conductive layer 121b, respectively, through openings provided in the resin layer 132.

[0114] In this way, by disposing the conductive layer 121a and the conductive layer 121b, which function as relay wiring, between the insulating layer 118 and the resin layer 132, it is not necessary to form deep contact holes, and therefore it is possible to improve the manufacturing yield. For example, when opening the resin layer 132 containing a resin and the insulating layer 118 and the insulating layer 116 containing an inorganic insulating film in a series of steps, not only do the processing conditions become more restrictive, but problems such as the disappearance of the semiconductor layer 108 located at the bottom of the opening or the opening diameter becoming larger may occur.

[0115] 3A shows an example in which the opening provided in the resin layer 132 and the openings provided in the insulating layer 118 and the insulating layer 116 overlap with each other at the connection portion between the conductive layer 120a and the conductive layer 121a. Alternatively, the two openings may be offset from each other so as not to overlap, as in the connection portion between the conductive layer 120b and the conductive layer 121b.

[0116] 3B shows an example in which the conductive layer 121a and the conductive layer 121b are applied to the structure illustrated in Structural Example 2. The conductive layer 121a and the conductive layer 121b are electrically connected to the low-resistance region 108n through openings provided in the insulating layer 118, the insulating layer 116, and the insulating layer 110, respectively.

[0117] [Example of manufacturing method] Hereinafter, an example of a method for manufacturing the semiconductor device exemplified above will be described with reference to the drawings. Here, the semiconductor device exemplified in Configuration Example 2, FIGS. 2A and 2B will be described as an example.

[0118] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and atomic layer deposition (ALD). CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD).

[0119] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0120] Furthermore, when processing a thin film that constitutes a semiconductor device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0121] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0122] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed using immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. Instead of light used for exposure, an electron beam can also be used. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0123] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0124] 4A to 8B show cross sections in the channel length direction and the channel width direction at each stage of the manufacturing process of the semiconductor device exemplified in Configuration Example 2. FIG.

[0125] [Formation of Conductive Layer 130] A conductive film is formed on the substrate 102 and then processed by etching to form a conductive layer 130 that functions as wiring (FIG. 4A).

[0126] In this case, the resin layer 131 formed later functions as a planarizing film and has extremely high coverage, so there is no need to tape the conductive layer 130. In addition, since the conductive layer 130 can be made thicker, the wiring resistance of the wiring to which the conductive layer 130 is applied can be reduced.

[0127] Furthermore, by using a conductive film containing copper as the conductive film to be the conductive layer 106, wiring resistance can be reduced. For example, when the conductive film is applied to a large display device or a display device with high resolution, it is preferable to use a conductive film containing copper. Even when a conductive film containing copper is used for the conductive layer 106, the insulating layer 103a prevents copper from diffusing toward the semiconductor layer 108, so that a highly reliable transistor can be realized.

[0128] [Formation of Resin Layer 131] Next, a resin layer 131 is formed to cover the substrate 102 and the conductive layer 130 (FIG. 4B).

[0129] The resin layer 131 is formed by forming a mixed material of a resin precursor and a solvent on a support substrate by a method such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife printing, slit coating, roll coating, curtain coating, knife coating, etc. Then, by performing a heat treatment, the material is cured while removing the solvent, etc., and the resin layer 131 containing an organic resin can be formed.

[0130] Polyimide is a typical organic resin that can be used for the resin layer 131. Polyimide is preferable because of its excellent heat resistance. Other examples that can be used include acrylic, epoxy, polyamide, polyimideamide, siloxane, benzocyclobutene-based resin, and phenolic resin.

[0131] For example, when polyimide is used, a resin precursor that generates imide bonds upon dehydration can be used, or a material containing soluble polyimide can be used.

[0132] The organic resin used for the resin layer 131 may be either photosensitive or non-photosensitive. Photosensitive polyimide is a material that is suitable for use as a planarization film for a display panel, and therefore the same forming equipment and materials can be used. Therefore, new equipment and materials are not required to realize one embodiment of the present invention. Furthermore, by using a photosensitive resin material, exposure and development processes can be performed to form openings or remove unnecessary portions, for example. Furthermore, optimizing the exposure method and exposure conditions can also form a textured surface. For example, multiple exposure techniques, or exposure techniques using a half-tone mask or gray-tone mask, can be used.

[0133] [Formation of insulating layer 104] Subsequently, the insulating layer 104 is formed on the resin layer 131 (FIG. 4C). The insulating layer 104 can be formed using a PECVD method, an ALD method, a sputtering method, or the like.

[0134] [Formation of opening 143] Next, a resist mask is formed on the insulating layer 104, and a portion of the insulating layer 104 is removed by etching to form an opening in the insulating layer 104. Next, using the insulating layer 104 as a hard mask, an opening is formed in a portion of the resin layer 131 that reaches the conductive layer 130, thereby forming an opening 143 (FIG. 4D).

[0135] In this manner, by using the insulating layer 104 as a hard mask, the diameter of the opening 143 can be reduced. At this time, the resist mask used for processing the insulating layer 104 is preferably removed after etching the insulating layer 104. In addition, the resin layer 131 is preferably etched by dry etching. For example, the resin layer 131 can be etched by ashing treatment using plasma.

[0136] Alternatively, the opening 143 may be formed using the following method, which is different from the above. First, a photosensitive material is used for the resin layer 131, and exposure and development are performed to form the resin layer 131 having an opening that overlaps with the conductive layer 130. Next, the insulating layer 104 is formed, and then the portion of the resin layer 131 that overlaps with the opening is removed by etching, thereby forming the opening 143. With this method, the step of etching the thick resin layer 131 can be omitted.

[0137] [Formation of Conductive Layer 106] Subsequently, a conductive film is formed to cover the insulating layer 104 and the opening 143, and is then processed by etching to form a conductive layer 106 that functions as a gate electrode (FIG. 4E).

[0138] At this time, it is preferable to process the conductive layer 106 so that the end portion thereof has a tapered shape, as shown in Fig. 4E, which can improve the step coverage of the insulating layer 103a to be formed next.

[0139] Furthermore, by using a conductive film containing copper as the conductive film to be the conductive layer 106, wiring resistance can be reduced.

[0140] [Formation of insulating layers 103a and 103b] Subsequently, insulating layers 103a and 103b are formed to cover the insulating layer 104 and the conductive layer 106 (FIG. 4F). The insulating layers 103a and 103b can be formed by a PECVD method, an ALD method, a sputtering method, or the like.

[0141] Here, the insulating layer 103a and the insulating layer 103b are stacked. In particular, the insulating layer 103a and the insulating layer 103b are preferably formed by PECVD.

[0142] After the insulating layer 103b is formed, treatment for supplying oxygen to the insulating layer 103b may be performed. For example, plasma treatment or heat treatment in an oxygen atmosphere may be performed. Alternatively, oxygen may be supplied to the insulating layer 103b by plasma ion doping, ion implantation, or the like.

[0143] [Formation of Semiconductor Layer 108] Subsequently, a metal oxide film is formed on the insulating layer 103b, and a portion of the metal oxide film is etched to form island-shaped semiconductor layers 108 (FIG. 5A).

[0144] The metal oxide film is preferably formed by a sputtering method using a metal oxide target.

[0145] The metal oxide film is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film is preferably a high-purity film with as little impurities as possible, such as hydrogen or water, as reduced as possible. In particular, it is preferable to use a crystalline metal oxide film.

[0146] Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with a higher on-state current can be obtained.

[0147] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the metal oxide film, whereas the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film.

[0148] The conditions for forming the metal oxide film are that the substrate temperature is from room temperature to 250° C., preferably from room temperature to 200° C., and more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to less than 140° C. is preferred because it increases productivity. Furthermore, by forming the metal oxide film at room temperature or without intentional heating, the crystallinity can be reduced.

[0149] Before forming the metal oxide film, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 103b and a treatment for supplying oxygen into the insulating layer 103b. For example, heat treatment can be performed at a temperature of 70°C or higher and 200°C or lower in a reduced-pressure atmosphere. Alternatively, plasma treatment can be performed in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer 103b by plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO). Plasma treatment containing nitrous oxide gas can supply oxygen while suitably removing organic substances on the surface of the insulating layer 103b. After such treatment, it is preferable to continuously form a metal oxide film without exposing the surface of the insulating layer 103b to the air.

[0150] In addition, when the semiconductor layer 108 has a stacked structure in which a plurality of metal oxide films are stacked, it is preferable to deposit a metal oxide film first and then deposit a subsequent metal oxide film without exposing the surface of the first metal oxide film to the air.

[0151] The metal oxide film may be processed by wet etching, dry etching, or both. At this time, a part of the insulating layer 103b that does not overlap with the semiconductor layer 108 may be etched and thinned. For example, the insulating layer 103b may be removed by etching, and the surface of the insulating layer 103a may be exposed.

[0152] Here, heat treatment is preferably performed after the metal oxide film is formed or after the metal oxide film is processed into the semiconductor layer 108. The heat treatment can remove hydrogen or water contained in or adsorbed on the surface of the metal oxide film or the semiconductor layer 108. Furthermore, the heat treatment may improve the film quality of the metal oxide film or the semiconductor layer 108 (for example, reduce defects or improve crystallinity).

[0153] Further, heat treatment can supply oxygen from the insulating layer 103b to the metal oxide film or the semiconductor layer 108. In this case, heat treatment is preferably performed before processing into the semiconductor layer 108.

[0154] The temperature of the heat treatment can typically be 150°C or higher and lower than the strain point of the substrate, or 200°C or higher and 500°C or lower, or 250°C or higher and 450°C or lower, or 300°C or higher and 450°C or lower.

[0155] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. Alternatively, after heating in the atmosphere, heating can be performed in an atmosphere containing oxygen. Alternatively, heating can be performed in a dry air atmosphere. Note that it is preferable that the atmosphere for the heat treatment contains as little hydrogen, water, or the like as possible. The heat treatment can be performed using an electric furnace, an RTA (Rapid Thermal Anneal) device, or the like. Using an RTA device can shorten the heat treatment time.

[0156] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, there are cases where a high-temperature treatment in a later step (e.g., a film formation step) can also serve as the heat treatment.

[0157] [Formation of insulating layer 110] Subsequently, the insulating layer 110 is formed to cover the insulating layer 103b and the semiconductor layer .

[0158] The insulating layer 110 is preferably formed by the PECVD method.

[0159] Furthermore, before the insulating layer 110 is formed, it is preferable to perform plasma treatment on the surface of the semiconductor layer 108. The plasma treatment can reduce impurities such as water adsorbed to the surface of the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 110 can be reduced, thereby realizing a highly reliable transistor. This is particularly suitable when the surface of the semiconductor layer 108 is exposed to the air during the period from the formation of the semiconductor layer 108 to the formation of the insulating layer 110. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. It is preferable to perform the plasma treatment and the formation of the insulating layer 110 successively without exposure to the air.

[0160] Here, heat treatment is preferably performed after the insulating layer 110 is formed. The heat treatment can remove hydrogen or water contained in or adsorbed to the surface of the insulating layer 110. Furthermore, defects in the insulating layer 110 can be reduced.

[0161] The conditions for the heat treatment may be as described above.

[0162] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, there are cases where a high-temperature treatment in a later step (e.g., a film formation step) can also serve as the heat treatment.

[0163] [Formation of Metal Oxide Film 114f] Subsequently, a metal oxide film 114f is formed on the insulating layer 110 (FIG. 5B).

[0164] The metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferably formed by a sputtering method in an atmosphere containing oxygen. This allows oxygen to be supplied to the insulating layer 110 during the formation of the metal oxide film 114f. Note that oxygen may be supplied to the semiconductor layer 108 during the formation of the metal oxide film 114f.

[0165] When the metal oxide film 114f is formed by a sputtering method using an oxide target containing a metal oxide similar to that used for the semiconductor layer 108, the description of the semiconductor layer 108 can be used.

[0166] For example, the metal oxide film 114f may be formed by reactive sputtering using oxygen as a deposition gas and a metal target. When aluminum is used as the metal target, an aluminum oxide film can be formed.

[0167] During deposition of the metal oxide film 114f, the higher the ratio of the oxygen flow rate to the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus (oxygen flow rate ratio) or the higher the oxygen partial pressure in the deposition chamber, the more oxygen can be supplied to the insulating layer 110. The oxygen flow rate ratio or oxygen partial pressure is, for example, 50% to 100%, preferably 65% ​​to 100%, more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate ratio to 100% and to set the oxygen partial pressure in the deposition chamber as close to 100% as possible.

[0168] In this way, by forming the metal oxide film 114f by a sputtering method in an atmosphere containing oxygen, oxygen can be supplied to the insulating layer 110 during the formation of the metal oxide film 114f, and oxygen can be prevented from being released from the insulating layer 110. As a result, an extremely large amount of oxygen can be trapped in the insulating layer 110.

[0169] After the metal oxide film 114f is formed, heat treatment is preferably performed. By the heat treatment, oxygen contained in the insulating layer 110 can be supplied to the semiconductor layer 108. By performing heat treatment while the insulating layer 110 is covered with the metal oxide film 114f, oxygen is prevented from being released from the insulating layer 110 to the outside, and a large amount of oxygen can be supplied to the semiconductor layer 108. As a result, oxygen vacancies in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be realized.

[0170] The conditions for the heat treatment may be as described above.

[0171] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, there are cases where a high-temperature treatment in a later step (e.g., a film formation step) can also serve as the heat treatment.

[0172] After the metal oxide film 114f is formed or after the heat treatment, the metal oxide film 114f may be removed.

[0173] [Formation of opening 142] Next, the metal oxide film 114f, the insulating layer 110, the insulating layer 103b, and a portion of the insulating layer 103a are etched to form an opening 142 that reaches the conductive layer 106 (FIG. 5C). This allows the conductive layer 106 to be electrically connected to the conductive layer 112, which will be formed later, through the opening 142.

[0174] [Formation of Conductive Layer 112 and Metal Oxide Layer 114] Subsequently, a conductive film 112f that will become the conductive layer 112 is formed on the metal oxide film 114f (FIG. 5D).

[0175] The conductive film 112f is preferably made of a low-resistance metal or alloy material, a material that does not easily release hydrogen and from which hydrogen does not easily diffuse, and a material that does not easily oxidize.

[0176] For example, the conductive film 112f is preferably formed by a sputtering method using a sputtering target containing a metal or an alloy.

[0177] For example, the conductive film 112f is preferably a stacked film in which a conductive film that is resistant to oxidation and hydrogen diffusion and a conductive film with low resistance are stacked.

[0178] Subsequently, the conductive film 112f and the metal oxide film 114f are partly etched to form the conductive layer 112 and the metal oxide layer 114. The conductive film 112f and the metal oxide film 114f are preferably processed using the same resist mask. Alternatively, the metal oxide film 114f may be etched using the etched conductive layer 112 as a hard mask.

[0179] It is particularly preferable to use a wet etching method for etching the conductive film 112f and the metal oxide film 114f.

[0180] This allows the formation of the conductive layer 112 and the metal oxide layer 114 whose top surface shapes are roughly the same.

[0181] In this way, by forming a structure in which the top surface and side surface of the semiconductor layer 108 and the insulating layer 103b are covered without etching the insulating layer 110, it is possible to prevent the semiconductor layer 108, the insulating layer 103b, and the like from being etched and thinned when the conductive film 112f and the like are etched.

[0182] [Fueling of impurity elements] Next, a process of supplying (also referred to as adding or injecting) the impurity element 140 to the semiconductor layer 108 through the insulating layer 110 is performed using the conductive layer 112 as a mask (FIG. 6A). As a result, a low-resistance region 108n can be formed in a region of the semiconductor layer 108 that is not covered with the conductive layer 112. At this time, it is preferable to determine conditions for the process of supplying the impurity element 140 in consideration of the material, thickness, and the like of the conductive layer 112 that serves as a mask so that the impurity element 140 is not supplied to a region of the semiconductor layer 108 that overlaps with the conductive layer 112 as much as possible. As a result, a channel formation region with a sufficiently reduced impurity concentration can be formed in the region of the semiconductor layer 108 that overlaps with the conductive layer 112.

[0183] The impurity element 140 can be preferably supplied by plasma ion doping or ion implantation. These methods allow the concentration profile in the depth direction to be controlled with high precision by adjusting the ion acceleration voltage, dose, etc. The use of plasma ion doping can increase productivity. Furthermore, the use of ion implantation using mass separation can increase the purity of the supplied impurity element.

[0184] In the supplying process of the impurity element 140, it is preferable to control the processing conditions so that the concentration is highest at the interface between the semiconductor layer 108 and the insulating layer 110, or in a portion close to the interface in the semiconductor layer 108, or in a portion close to the interface in the insulating layer 110. This allows the impurity element 140 to be supplied at an optimum concentration to both the semiconductor layer 108 and the insulating layer 110 in a single process.

[0185] Examples of the impurity element 140 include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and rare gases. Typical examples of rare gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable to use boron, phosphorus, aluminum, magnesium, or silicon.

[0186] As a source gas for the impurity element 140, a gas containing the above impurity element can be used. When supplying boron, B2H6 gas or BF3 gas can be typically used. When supplying phosphorus, PH3 gas can be typically used. Alternatively, a mixed gas in which these source gases are diluted with a rare gas can be used.

[0187] Other usable source gases include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and rare gases. The ion source is not limited to gas, and a solid or liquid vaporized by heating may also be used.

[0188] The addition of the impurity element 140 can be controlled by setting conditions such as acceleration voltage or dose amount in consideration of the composition, density, thickness, and the like of the insulating layer 110 and the semiconductor layer 108 .

[0189] For example, when adding boron or phosphorus by ion implantation or plasma ion doping, the dose is, for example, 1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Less than 1 × 10 14 ions / cm 2 5x10 or more 16 ions / cm 2 Less than 1×10, more preferably 15 ions / cm 2 3x10 or more 16 ions / cm 2 The range can be as follows:

[0190] The method for supplying the impurity element 140 is not limited to this, and may be, for example, a treatment using thermal diffusion by heating, a plasma treatment, or the like. In the case of the plasma treatment, the impurity element can be added by generating plasma in a gas atmosphere containing the impurity element to be added and performing the plasma treatment. The apparatus for generating the plasma may be a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like.

[0191] In one embodiment of the present invention, the impurity element 140 can be supplied to the semiconductor layer 108 through the insulating layer 110. Therefore, even when the semiconductor layer 108 has crystallinity, damage to the semiconductor layer 108 when the impurity element 140 is supplied can be reduced, and loss of crystallinity can be suppressed. Therefore, this is preferable in cases where electrical resistance increases due to a decrease in crystallinity.

[0192] [Formation of Insulating Layer 116 and Insulating Layer 118] Subsequently, insulating layer 116 and insulating layer 118 are formed covering insulating layer 110, metal oxide layer 114, and conductive layer 112 (FIG. 6B).

[0193] When the insulating layer 116 and the insulating layer 118 are formed by the plasma CVD method, if the film formation temperature is too high, impurities contained in the low-resistance region 108n and the like may diffuse into the peripheral portion including the channel formation region of the semiconductor layer 108. In addition, the electrical resistance of the low-resistance region 108n may increase. Therefore, the film formation temperature for the insulating layer 116 and the insulating layer 118 may be determined taking these factors into consideration.

[0194] For example, the deposition temperature of the insulating layers 116 and 118 is preferably 150° C. or higher and 400° C. or lower, preferably 180° C. or higher and 360° C. or lower, more preferably 200° C. or higher and 250° C. By depositing the insulating layers 116 and 118 at low temperatures, good electrical characteristics can be imparted even to transistors with short channel lengths.

[0195] After the insulating layers 116 and 118 are formed, heat treatment may be performed. The heat treatment may make the low-resistance region 108n more stable and low-resistance. For example, the heat treatment may cause the impurity element 140 to diffuse appropriately and become locally uniform, thereby forming the low-resistance region 108n having an ideal impurity element concentration gradient. Note that if the temperature of the heat treatment is too high (for example, 500° C. or higher), the impurity element 140 may diffuse into the channel formation region, which may result in deterioration of the electrical characteristics and reliability of the transistor.

[0196] The conditions for the heat treatment may be as described above.

[0197] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, if there is a high-temperature treatment (e.g., a film formation step) in a later step, this heat treatment may be combined with the heat treatment.

[0198] [Formation of Resin Layer 132] Subsequently, a resin layer 132 having an opening is formed on the insulating layer 118 (FIG. 6C).

[0199] The same description as for the resin layer 131 can be applied to materials that can be used for the resin layer 132. Here, a photosensitive material is used, and the resin layer 132 having openings is formed by exposure and development.

[0200] [Formation of Openings 141a and 141b] Next, portions of the insulating layer 118, the insulating layer 116, and the insulating layer 110 in the regions overlapping with the openings of the resin layer 132 are etched to form openings 141a and 141b that reach the low-resistance region 108n (FIG. 7A).

[0201] Here, the resin layer 132 is used as an etching mask to etch the portions of the insulating layer 118, the insulating layer 116, and the insulating layer 110 that are located within the openings of the resin layer 132.

[0202] Alternatively, the openings 141a and 141b may be formed using the following method, which is different from the above. First, before forming the resin layer 132, a resist mask is formed on the insulating layer 118, and openings are formed in advance in the insulating layer 118, the insulating layer 116, and the insulating layer 110. Next, a photosensitive material is used, and exposure and development are performed to form the resin layer 132 having openings. In this way, the openings 141a and 141b can be formed.

[0203] [Formation of Conductive Layer 120a and Conductive Layer 120b] Subsequently, a conductive film is formed on the resin layer 132 so as to cover the openings 141a and 141b, and the conductive film is processed into a desired shape to form the conductive layers 120a and 120b (FIG. 7B).

[0204] Through the above steps, a semiconductor device including a transistor can be manufactured.

[0205] [Formation of Resin Layer 133] Subsequently, a resin layer 133 having an opening 144 is formed to cover the conductive layer 120a, the conductive layer 120b, and the resin layer 132 (FIG. 8A).

[0206] For details of the resin layer 133, the descriptions of the resin layer 131 and the resin layer 132 can be cited.

[0207] [Formation of Conductive Layer 150] Subsequently, a conductive film is formed on the resin layer 133 so as to cover the opening 144, and the conductive film is processed into a desired shape to form a conductive layer 150 (FIG. 8B).

[0208] The above is a description of an example of the manufacturing method.

[0209] [Components of semiconductor device] The components included in the semiconductor device of this embodiment will be described below.

[0210] 〔substrate〕 Although there are no significant limitations on the material of the substrate 102, it is necessary that the substrate 102 has at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. Furthermore, any of these substrates on which semiconductor elements are provided may also be used as the substrate 102.

[0211] Alternatively, a flexible substrate may be used as the substrate 102, and the semiconductor device may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the semiconductor device. The peeling layer can be used to separate a semiconductor device, after a part or all of the semiconductor device is completed thereon, from the substrate 102 and transfer the semiconductor device to another substrate. In this case, the semiconductor device can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0212] [Conductive Layer] The conductive layer 112, the conductive layer 106, the conductive layer 120a, the conductive layer 120b, the conductive layer 121a, the conductive layer 121b, the conductive layer 130, the conductive layer 150, and the like can each be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt, or an alloy containing any of the above-mentioned metal elements, or an alloy combining any of the above-mentioned metal elements.

[0213] The conductive layer may also be made of an oxide conductor or a metal oxide film such as In-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide, or In-Ga-Zn oxide.

[0214] [Semiconductor layer] When the semiconductor layer 108 is an In-M-Zn oxide, examples of the atomic ratio of metal elements in a sputtering target used to deposit the In-M-Zn oxide include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=2:2:1, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, and In:M:Zn=5:2:5.

[0215] Furthermore, it is preferable to use a target containing a polycrystalline oxide as the sputtering target, since this facilitates the formation of a crystalline semiconductor layer 108. The atomic ratio of the semiconductor layer 108 to be formed can vary within a range of ±40% of the atomic ratio of the metal elements contained in the sputtering target. For example, if the composition of the sputtering target used for the semiconductor layer 108 is In:Ga:Zn=4:2:4.1 [atomic ratio], the composition of the semiconductor layer 108 to be formed may be close to In:Ga:Zn=4:2:3 [atomic ratio].

[0216] When describing an atomic ratio of In:Ga:Zn=4:2:3 or thereabout, this includes a case where, when In is taken as 4, Ga is 1 to 3 and Zn is 2 to 4. When describing an atomic ratio of In:Ga:Zn=5:1:6 or thereabout, this includes a case where, when In is taken as 5, Ga is more than 0.1 and 2 or less and Zn is 5 to 7. When describing an atomic ratio of In:Ga:Zn=1:1:1 or thereabout, this includes a case where, when In is taken as 1, Ga is more than 0.1 and 2 or less and Zn is more than 0.1 and 2 or less.

[0217] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide having a wider energy gap than silicon, the off-state current of the transistor can be reduced.

[0218] The semiconductor layer 108 preferably has a non-single-crystal structure. Examples of the non-single-crystal structure include a CAAC structure, a polycrystalline structure, a microcrystalline structure, and an amorphous structure, which will be described later. Among the non-single-crystal structures, the amorphous structure has the highest density of defect states, and the CAAC structure has the lowest density of defect states.

[0219] Below, we explain about CAAC (c-axis aligned crystal), which is an example of a crystal structure.

[0220] The CAAC structure is a type of crystalline structure, such as in thin films, that contains multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm), characterized by the c-axis of each nanocrystal oriented in a specific direction, the a-axis and b-axis not being oriented, and the nanocrystals being continuously connected without forming grain boundaries. In particular, thin films with the CAAC structure are characterized by the c-axis of each nanocrystal tending to be oriented in the thickness direction of the thin film, the normal direction to the surface on which it is formed, or the normal direction to the surface of the thin film.

[0221] CAAC-OS (oxide semiconductor) is an oxide semiconductor with high crystallinity. On the other hand, because no clear crystal grain boundaries are observed in CAAC-OS, it can be said that a decrease in electron mobility due to crystal grain boundaries is unlikely to occur. Furthermore, since the crystallinity of oxide semiconductors can be reduced by the inclusion of impurities or the generation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable.

[0222] In crystallography, it is common to define a unit cell with a specific axis as the c-axis, out of the three axes (crystal axes) that make up the unit cell: the a-axis, the b-axis, and the c-axis. In particular, for crystals with a layered structure, it is common to define the two axes parallel to the plane of the layers as the a-axis and the b-axis, and the axis intersecting the layers as the c-axis. A typical example of a crystal with such a layered structure is graphite, which is classified as a hexagonal crystal system. The a-axis and b-axis of the unit cell are parallel to the cleavage plane, and the c-axis is perpendicular to the cleavage plane. For example, InGaZnO4 crystals, which have a layered YbFe2O4-type crystal structure, can be classified as a hexagonal crystal system. The a-axis and b-axis of the unit cell are parallel to the plane of the layers, and the c-axis is perpendicular to the layers (i.e., the a-axis and b-axis).

[0223] In an oxide semiconductor film having a microcrystalline structure (microcrystalline oxide semiconductor film), crystal parts may not be clearly visible in a TEM image. The crystal parts contained in a microcrystalline oxide semiconductor film often have a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film having nanocrystals (nc), which are microcrystals with a size of 1 nm to 10 nm, or 1 nm to 3 nm, is called an nc-OS (nanocrystalline oxide semiconductor) film. Furthermore, in an nc-OS film, for example, crystal grain boundaries may not be clearly visible in a TEM image.

[0224] The nc-OS film has periodic atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Furthermore, the nc-OS film does not exhibit regularity in the crystal orientation between different crystalline regions. Therefore, the film as a whole lacks orientation. Therefore, depending on the analytical method, the nc-OS film may be indistinguishable from an amorphous oxide semiconductor film. For example, when the nc-OS film is subjected to structural analysis using an XRD apparatus that uses X-rays with a diameter larger than that of the crystalline region, peaks indicating crystal planes are not detected by the out-of-plane analysis. Furthermore, when the nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of the crystalline region (for example, 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also known as nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) close to or smaller than the size of the crystalline portion, a circular (ring-shaped) region of high brightness is observed, and multiple spots may be observed within the ring-shaped region.

[0225] The nc-OS film has a lower density of defect states than an amorphous oxide semiconductor film. However, the nc-OS film lacks regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film. Therefore, the nc-OS film may have a higher carrier density and electron mobility than the CAAC-OS film. Therefore, a transistor using the nc-OS film may exhibit high field-effect mobility.

[0226] The nc-OS film can be formed by lowering the oxygen flow rate during film formation compared to the CAAC-OS film. The nc-OS film can also be formed by lowering the substrate temperature during film formation compared to the CAAC-OS film. For example, the nc-OS film can be formed at a relatively low substrate temperature (e.g., 130°C or lower) or without heating the substrate. This makes the nc-OS film suitable for use on large glass or resin substrates, thereby improving productivity.

[0227] An example of the crystal structure of a metal oxide will be described. A metal oxide formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) at a substrate temperature of 100°C to 130°C tends to have either an nc (nano crystal) structure or a CAAC structure, or a mixture of these. On the other hand, a metal oxide formed at a substrate temperature of room temperature (RT) tends to have an nc crystal structure. Note that room temperature (RT) here includes the temperature when the substrate is not intentionally heated.

[0228] [Metal oxide composition] The structure of a cloud-aligned composite (CAC)-OS that can be used for the transistor disclosed in one embodiment of the present invention will be described below.

[0229] Note that CAAC (c-axis aligned crystal) represents an example of a crystal structure, and CAC (Cloud-Aligned Composite) represents an example of a function or material configuration.

[0230] CAC-OS or CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and functions as a semiconductor as a whole. When CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is a function of allowing electrons (or holes) to flow as carriers, and the insulating function is a function of preventing the flow of electrons as carriers. By making the conductive function and the insulating function act complementarily, a switching function (on / off function) can be imparted to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0231] Furthermore, CAC-OS or CAC-metal oxide has conductive regions and insulating regions. The conductive regions have the above-mentioned conductive function, and the insulating regions have the above-mentioned insulating function. In addition, the conductive regions and the insulating regions may be separated at the nanoparticle level in the material. In addition, the conductive regions and the insulating regions may be unevenly distributed in the material. In addition, the conductive regions may be observed as connected in a cloud-like shape with the periphery blurred.

[0232] In addition, in CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may be dispersed in the material with sizes of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0233] Furthermore, the CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, the CAC-OS or CAC-metal oxide is composed of a component with a wide gap due to an insulating region and a component with a narrow gap due to a conductive region. In this configuration, when carriers flow, the carriers mainly flow in the component with the narrow gap. Furthermore, the component with the narrow gap acts complementarily with the component with the wide gap, and carriers also flow in the component with the wide gap in conjunction with the component with the narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, the transistor can achieve high current driving power in the on state, i.e., a large on-state current, and high field-effect mobility.

[0234] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0235] The above is the explanation of the configuration of the metal oxide.

[0236] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0237] (Embodiment 2) In this embodiment, an example of a display device including the semiconductor device described in the above embodiment will be described.

[0238] 9A shows a schematic top view of a display device 10, which will be described below. The display device 10 includes a pixel portion 11, a circuit 12, a circuit 13, a terminal portion 15a, a terminal portion 15b, a wiring 16a, a wiring 16b, and a wiring 16c. Also, FIG. 9A shows an example in which an IC 17 is mounted on the display device 10.

[0239] The pixel section 11 has a plurality of pixels and has the function of displaying an image.

[0240] The circuit 12 and IC 17 have the function of outputting a signal for driving each pixel in the pixel unit 11. For example, the circuit 12 is a circuit that functions as a gate drive circuit. Also, for example, the IC 17 is a circuit that functions as a source drive circuit. FIG. 9A shows an example in which two circuits 12 are provided on either side of the pixel unit 11 and six ICs 17 are mounted. Note that a configuration may be adopted in which an IC that functions as a gate drive circuit is mounted, but no circuit 12 is mounted. Alternatively, a configuration may be adopted in which a source drive circuit is mounted, but no IC 17 is mounted.

[0241] Note that a display module can be a device that has an integrated circuit such as an IC or a connector such as an FPC (Flexible Printed Circuit), while a display panel can be a device that does not have a connector or integrated circuit.

[0242] Circuit 13 is a circuit (e.g., a demultiplexer circuit) that has the function of distributing one of the signals input from IC 17 to two or more wirings. By providing circuit 13, the number of signals output by IC 17 can be reduced, and the number of terminals of IC 17 can be reduced. Alternatively, the number of components can be reduced. In particular, providing circuit 13 is particularly effective when realizing a display device with extremely high resolution such as 4K or 8K. Circuit 13 does not have to be provided if it is not necessary.

[0243] Terminal portion 15a and terminal portion 15b are provided with a plurality of terminals, which can be connected to a connector such as an FPC or an integrated circuit such as another IC. Each terminal of terminal portion 15a is electrically connected to circuit 12 via one of a plurality of wirings 16a. Each terminal of terminal portion 15b is electrically connected to IC 17 via one of a plurality of wirings 16b. Furthermore, each of a plurality of output terminals of IC 17 is electrically connected to circuit 13 via one of a plurality of wirings 16c.

[0244] FIG. 9B is a schematic top view showing an example of a method for arranging pixel electrodes in the pixel section 11. The pixel section 11 has a plurality of pixel units 20. FIG. 9B shows four pixel units 20. The pixel unit 20 is configured to include a pixel 21a and a pixel 21b. The pixel 21a has a pixel electrode 31a, a pixel electrode 32a, and a pixel electrode 33a. The pixel 21b has a pixel electrode 31b, a pixel electrode 32b, and a pixel electrode 33b. Each pixel electrode functions as an electrode of a display element, which will be described later. The display region 22 of one subpixel is located inside the pixel electrode of that subpixel.

[0245] The six pixel electrodes of the pixel unit 20 are arranged in a matrix of two vertical rows and three horizontal rows. Here, pixel electrode 31a, pixel electrode 32a, and pixel electrode 33a can be electrodes of display elements that exhibit different colors. Also, pixel electrode 31b can be electrodes of display elements that exhibit the same color as pixel electrode 31a, pixel electrode 32b can be electrodes of display elements that exhibit the same color as pixel electrode 32a, and pixel electrode 33b can be electrodes of display elements that exhibit the same color as pixel electrode 33a. While the three types of pixel electrodes are shown here as having the same size, they may be different sizes. Alternatively, the size of the display area 22 on each pixel electrode may be different.

[0246] For ease of explanation, pixel electrode 31a is an electrode of a display element that exhibits red (R) and is assigned the symbol R. Similarly, pixel electrode 32a is an electrode of a display element that exhibits green (G) and is assigned the symbol G, and pixel electrode 33a is an electrode of a display element that exhibits blue (B) and is assigned the symbol B. Note that the pixel arrangement shown in FIG. 9B etc. is an example and is not limited to this. Furthermore, R, G, and B can be interchanged with each other. Furthermore, a pixel arrangement in which the pixel arrangement shown in FIG. 9B etc. is horizontally or vertically inverted may be used.

[0247] The arrangement of the display elements is not limited to the above, and may be, for example, a so-called stripe arrangement in which three rectangular display elements are arranged in one square, or a so-called delta arrangement in which any of three display elements is arranged at the vertices of a grid of identical triangles.

[0248] [Pixel circuit configuration example] An example of a pixel circuit included in the pixel unit 20 will be described below. Fig. 9C shows an example of a circuit diagram of the pixel unit 20. Wirings 51a and 51b, wirings 52a to 52d, and wirings 53a to 53c are connected to the pixel unit 20. Fig. 9C shows an example in which four wirings (such as wiring 52a) that function as signal lines are connected to one pixel unit 20.

[0249] Pixel 21a has subpixels 71a, 72a, and 73a. Pixel 21b has subpixels 71b, 72b, and 73b. Each subpixel has a pixel circuit (pixel circuit 41a, pixel circuit 41b, pixel circuit 42a, pixel circuit 42b, pixel circuit 43a, or pixel circuit 43b) and a display element 60. For example, subpixel 71a has pixel circuit 41a and display element 60. Here, a case is shown in which a light-emitting element such as an organic EL element is used as display element 60.

[0250] Each pixel circuit includes a transistor 61, a transistor 62, and a capacitor 63. For example, in the pixel circuit 41a, the gate of the transistor 61 is electrically connected to a wiring 51a, one of the source and drain of the transistor 61 is electrically connected to a wiring 52a, and the other of the source and drain is electrically connected to the gate of the transistor 62 and one electrode of the capacitor 63. One of the source and drain of the transistor 62 is electrically connected to one electrode of the display element 60, and the other of the source and drain of the transistor 62 is electrically connected to the other electrode of the capacitor 63 and the wiring 53a. The other electrode of the display element 60 is electrically connected to a wiring to which a potential V1 is applied. Note that the other pixel circuits have the same configuration as the pixel circuit 41a, except that the wiring to which the gate of the transistor 61 is connected, the wiring to which one of the source and drain of the transistor 61 is connected, and the wiring to which the other electrode of the capacitor 63 is connected are different, as shown in FIG. 9C .

[0251] 9C, the transistor 61 functions as a selection transistor. The transistor 62 is connected in series to the display element 60 and has a function of controlling a current flowing through the display element 60. In FIG. 9C, the transistor 61 functioning as a selection transistor is electrically connected to one electrode (pixel electrode) of the display element 60 through the transistor 62. The capacitor 63 has a function of holding the potential of a node to which the gate of the transistor 62 is connected. Note that if the leakage current in the off state of the transistor 61 and the leakage current through the gate of the transistor 62 are extremely small, the capacitor 63 is not necessarily provided.

[0252] 9C, the transistor 62 preferably has a first gate and a second gate that are electrically connected to each other. Such a configuration having two gates can increase the current that can flow through the transistor 62. This is particularly preferable for high-resolution display devices, because it can increase the current without increasing the size of the transistor 62, particularly its channel width.

[0253] Of the pair of electrodes of the display element 60, the electrode electrically connected to the transistor 62 corresponds to the pixel electrode (for example, the pixel electrode 31a). Here, FIG. 9C illustrates a configuration in which the electrode electrically connected to the transistor 62 of the display element 60 serves as a cathode, and the opposite electrode serves as an anode. This configuration is particularly effective when the transistor 62 is an n-channel transistor. That is, when the transistor 62 is on, the potential applied by the wiring 53a serves as the source potential. Therefore, the current flowing through the transistor 62 can be kept constant regardless of variations in the electrical resistance of the display element 60 and fluctuations in the electrical resistance.

[0254] Note that the electrode of the display element 60 on the transistor 62 side may be an anode, and the electrode on the opposite side may be a cathode. With this configuration, a fixed potential lower than the potential applied to the wiring 53a or the like can be used as the potential V1 applied to the other electrode of the display element 60. It is also preferable to use a potential common to other circuits, such as a common potential or a ground potential, as the potential V1, because this simplifies the circuit configuration.

[0255] Note that although an example in which an n-channel transistor is used as a transistor included in a pixel circuit is shown here, a p-channel transistor may also be used.

[0256] [Pixel layout example] An example of the layout of the pixel unit 20 will be described below.

[0257] 10A and 10B show an example of the layout of one subpixel. For clarity, an example before forming a pixel electrode is shown. In addition, in FIG. 10B, the wiring 52 and the like in FIG. 10A are indicated by dashed lines. The subpixel shown in FIG. 10A includes a transistor 61, a transistor 62, and a capacitor 63. The transistor 62 is a transistor having two gates sandwiching a semiconductor layer.

[0258] The transistors described in Embodiment 1 can be used as the transistors 61 and 62.

[0259] In Figure 10A and other figures, patterns formed by processing the same conductive film are indicated by the same hatching pattern. The lowest conductive layer (conductive layer 130) forms the wiring 51. Conductive layers formed later (conductive layers 106a, 106b, etc.) form relay wiring, one gate of the transistor 62, etc. The gate of the transistor 61 and the other gate of the transistor 62 are formed later (conductive layers 112a, 112b, etc.). The source and drain electrodes of each transistor and one electrode of the capacitor 63 are formed later (conductive layers 121a, 121b, 121c, 121d, etc.). The wiring 52, wiring 53, relay wiring, etc. are formed later (conductive layers 120a, 120b, 120c, etc.). Part of the wiring 53 functions as the other electrode of the capacitor 63. The conductive layer 120c functions as a relay wiring that connects the transistor 62 to the pixel electrode 31 and the like. The transistor 61 includes a semiconductor layer 108a, and the transistor 62 includes a semiconductor layer 108b.

[0260] Fig. 10C shows an example of the layout of a pixel unit 20 using the sub-pixels illustrated in Fig. 10A. Fig. 10C also clearly shows each pixel electrode and a display area 22.

[0261] Here, an example is shown in which the three sub-pixels electrically connected to the wiring 51a and the three sub-pixels electrically connected to the wiring 51b are symmetrical to each other. As a result, when sub-pixels of the same color are arranged in a zigzag pattern in the extension direction of the wiring 52a, etc., and these sub-pixels are connected to one wiring that functions as a signal line, the lengths of the wiring within the sub-pixels can be made uniform, thereby suppressing variations in brightness between the sub-pixels.

[0262] The display regions 22 of three sub-pixels electrically connected to the wiring 51a and the display regions 22 of three sub-pixels electrically connected to the wiring 51b may be arranged so as to be offset by a distance of half the arrangement pitch in the extension direction of the wiring 51a, thereby realizing a so-called delta arrangement.

[0263] The above is a description of an example of a pixel layout.

[0264] The display device exemplified in this embodiment can realize an extremely high-definition display device. Furthermore, a display device with improved display quality can be provided. Furthermore, a display device with improved viewing angle characteristics can be provided. Furthermore, a display device with an increased aperture ratio can be provided.

[0265] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0266] (Embodiment 3) In this embodiment, a cross-sectional structure example of a display device according to one embodiment of the present invention will be described.

[0267] [Cross-section example 1] 11 is a schematic cross-sectional view of a display panel 700. FIG. 11 shows a cross section including a pixel portion 702, a gate driver circuit portion 706, and an FPC terminal portion 708. The pixel portion 702 includes a transistor 750, a transistor 754, and a capacitor 790. The gate driver circuit portion 706 includes a transistor 752.

[0268] The transistors described in Embodiment 1 can be used as the transistors 750, 752, and 754.

[0269] The transistor 750, the transistor 752, and the transistor 754 are transistors in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed. Note that the present invention is not limited to this, and a transistor in which silicon (amorphous silicon, polycrystalline silicon, or single crystal silicon) or an organic semiconductor is used for the semiconductor layer can also be used.

[0270] The transistor used in this embodiment includes a highly purified oxide semiconductor film in which the formation of oxygen vacancies is suppressed. The off-state current of the transistor can be significantly reduced. Therefore, a pixel including such a transistor can hold an electric signal such as an image signal for a long time and can set a long interval between writing of the image signal or the like. Therefore, the frequency of a refresh operation can be reduced, leading to reduced power consumption.

[0271] Furthermore, the transistor used in this embodiment can achieve relatively high field-effect mobility and thus can be driven at high speed. For example, by using such a transistor capable of high-speed driving in a display panel, a switching transistor in a pixel portion and a driver transistor used in a driver circuit portion can be formed over the same substrate. That is, a configuration without using a driver circuit formed using a silicon wafer or the like is possible, and the number of components in a display device can be reduced. Furthermore, by using a transistor capable of high-speed driving in the pixel portion, a high-quality image can be provided.

[0272] The capacitor 790 has a lower electrode formed by processing the same film as the first gate electrode of the transistor 750, and an upper electrode formed by processing the same metal oxide film as the semiconductor layer. The upper electrode has low resistance, similar to the source and drain regions of the transistor 750. A part of an insulating film functioning as the first gate insulating layer of the transistor 750 is provided between the lower and upper electrodes. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes. The upper electrode is connected to wiring obtained by processing the same film as the source and drain electrodes of the transistor 750.

[0273] The display panel 700 includes a supporting substrate 745 and a supporting substrate 740. As the supporting substrate 745 and the supporting substrate 740, for example, a flexible substrate such as a glass substrate or a plastic substrate can be used.

[0274] The transistor 750, the transistor 752, the transistor 754, the capacitor 790, and the like are provided over an insulating layer 744. The supporting substrate 745 and the insulating layer 744 are attached to each other with an adhesive layer 742.

[0275] The conductive layer 720 is provided over the insulating layer 744. The resin layer 722 is provided to cover the insulating layer 744 and the conductive layer 720. The insulating layer 723 is provided to cover the resin layer 722.

[0276] The transistor 750 , the transistor 752 , the transistor 754 , the capacitor 790 , and the like are provided over the insulating layer 723 .

[0277] The transistor 750, the transistor 752, and the transistor 754 each include a conductive layer 791 functioning as a first gate electrode, an insulating layer 792 functioning as a first gate insulating layer, a semiconductor layer 793, an insulating layer 794 functioning as a second gate insulating layer, a conductive layer 795 functioning as a second gate electrode, etc. An insulating layer 726 is provided to cover the transistor 750, the transistor 752, and the transistor 754.

[0278] A resin layer 724 is provided on the insulating layer 726, and a conductive layer 725 and the like are provided on the resin layer 724.

[0279] A conductive layer 721 formed by processing the same conductive film as the conductive layer 791 is electrically connected to the conductive layer 720 in an opening provided in the insulating layer 723 and the resin layer 722 .

[0280] Part of the conductive layer 720 functions as a gate line. Part of the conductive layer 725 functions as a source line. Part of the conductive layer 720 overlaps with part of the conductive layer 725 with at least the resin layer 722 and the resin layer 724 interposed therebetween.

[0281] An insulating layer 770 functioning as a planarization film is provided over the transistor 750, the transistor 752, the transistor 754, and the capacitor 790.

[0282] The transistors 750 and 754 in the pixel portion 702 and the transistor 752 in the gate driver circuit portion 706 may have different structures. For example, a top-gate transistor may be used for one of them, and a bottom-gate transistor may be used for the other.

[0283] The FPC terminal portion 708 includes a wiring 760, a part of which functions as a connection electrode, an anisotropic conductive film 780, and an FPC 716. The wiring 760 is electrically connected to a terminal of the FPC 716 via the anisotropic conductive film 780. Here, the wiring 760 is formed using the same conductive film as the source and drain electrodes of the transistor 750 and the like.

[0284] The display panel 700 also includes a light-emitting element 782, a coloring layer 736, a light-shielding layer 738, and the like.

[0285] The light-emitting element 782 includes a conductive layer 772, an EL layer 786, and a conductive layer 788. The conductive layer 772 is electrically connected to a source electrode or a drain electrode of the transistor 750. The conductive layer 772 is provided over the insulating layer 770 and functions as a pixel electrode. An insulating layer 730 is provided to cover an end portion of the conductive layer 772, and the EL layer 786 and the conductive layer 788 are stacked over the insulating layer 730 and the conductive layer 772.

[0286] The conductive layer 772 can be formed using a material that reflects visible light. For example, a material containing aluminum, silver, or the like can be used. The conductive layer 788 can be formed using a material that transmits visible light. For example, an oxide material containing indium, zinc, tin, or the like can be used. Therefore, the light-emitting element 782 is a top-emission light-emitting element that emits light to the opposite side to the surface where it is formed (the supporting substrate 740 side).

[0287] The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots, etc. The EL layer 786 includes a light-emitting material that emits white light when a current flows through it.

[0288] Examples of luminescent materials include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, inorganic compounds (quantum dot materials, etc.), etc. Examples of materials that can be used for quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell-type quantum dot materials, and core-type quantum dot materials.

[0289] The light-shielding layer 738 and the coloring layer 736 are provided on one surface of the insulating layer 746. The coloring layer 736 is provided at a position overlapping with the light-emitting element 782. The light-shielding layer 738 is provided in a region of the pixel portion 702 that does not overlap with the light-emitting element 782. The light-shielding layer 738 may also be provided to overlap with the gate driver circuit portion 706, etc.

[0290] The support substrate 740 is bonded to the other surface of the insulating layer 746 by an adhesive layer 747. The support substrate 740 and the support substrate 745 are bonded to each other by a sealing layer 732.

[0291] Here, a light-emitting material that emits white light is used for the EL layer 786 of the light-emitting element 782. The white light emitted by the light-emitting element 782 is colored by the coloring layer 736 and emitted to the outside. The EL layer 786 is provided across pixels that exhibit different colors. By arranging pixels in a matrix in the pixel portion 702, each of which is provided with a coloring layer 736 that transmits any of red (R), green (G), and blue (B), the display panel 700 can display full colors.

[0292] Alternatively, a conductive film having transparency and reflectivity may be used as the conductive layer 788. In this case, a microresonator (microcavity) structure may be realized between the conductive layer 772 and the conductive layer 788, so that light of a specific wavelength can be intensified and emitted. In this case, an optical adjustment layer for adjusting the optical distance may be disposed between the conductive layer 772 and the conductive layer 788, and the thickness of the optical adjustment layer may be made different between pixels of different colors, thereby increasing the color purity of the light emitted from each pixel.

[0293] In addition, when the EL layer 786 is formed in an island shape for each pixel or in a striped shape for each pixel column, that is, when it is formed by separate coating, at least one of the colored layer 736 and the optical adjustment layer described above may be omitted. In this case, the EL layer 786 may be separately formed by a vacuum deposition method using a shadow mask such as a metal mask, or the EL layer 786 may be processed into an island shape or a striped shape by a photolithography method.

[0294] Here, an inorganic insulating film functioning as a barrier film with low moisture permeability is preferably used for each of the insulating layers 744 and 746. By sandwiching the light-emitting element 782, the transistor 750, and the like between the insulating layers 744 and 746, deterioration of the light-emitting element 782, the transistor 750, and the like can be suppressed, thereby realizing a highly reliable display panel.

[0295] A display panel 700A shown in FIG. 12 has a protective layer 749 instead of the support substrate 740.

[0296] The protective layer 749 is attached to the sealing layer 732. A glass substrate, a resin film, or the like can be used as the protective layer 749. Alternatively, the protective layer 749 may be an optical member such as a polarizing plate (including a circular polarizing plate) or a scattering plate, an input device such as a touch sensor panel, or a configuration in which two or more of these are stacked.

[0297] The EL layer 786 of the light-emitting element 782 is provided in an island shape over the insulating layer 730 and the conductive layer 772. By forming the EL layer 786 so that each subpixel emits a different light color, color display can be achieved without using the coloring layer 736.

[0298] A protective layer 741 is provided to cover the light-emitting element 782. The protective layer 741 has a function of preventing impurities such as water from diffusing into the light-emitting element 782. The protective layer 741 has a layered structure in which an insulating layer 741a, an insulating layer 741b, and an insulating layer 741c are stacked in this order from the conductive layer 788 side. In this case, it is preferable to use an inorganic insulating film that has a high barrier property against impurities such as water for the insulating layer 741a and the insulating layer 741c, and an organic insulating film that functions as a planarization film for the insulating layer 741b. It is also preferable that the protective layer 741 be provided so as to extend to the gate driver circuit portion 706.

[0299] 12, a conductive layer 761 is provided over the protective layer 741. The conductive layer 761 can be used as a wiring, an electrode, or the like.

[0300] Furthermore, when a touch sensor is provided over the display panel 700A, the conductive layer 761 can function as an electrostatic shielding film for preventing electrical noise generated when a pixel is driven from being transmitted to the touch sensor. In this case, a predetermined constant potential may be applied to the conductive layer 761.

[0301] Alternatively, the conductive layer 761 can be used as, for example, an electrode of a touch sensor. This allows the display panel 700A to function as a touch panel. For example, the conductive layer 761 can be used as an electrode or wiring of a capacitive touch sensor. In this case, the conductive layer 761 can be used as a wiring or electrode to which a detection circuit is connected, or a wiring or electrode to which a sensor signal is input. In this way, by forming a touch sensor over the light-emitting element 782, the number of components can be reduced, and the manufacturing costs of electronic devices and the like can be reduced.

[0302] The conductive layer 761 is preferably provided in a portion that does not overlap with the light-emitting element 782. For example, the conductive layer 761 can be provided in a portion that overlaps with the insulating layer 730. This eliminates the need to use a transparent conductive film with relatively low conductivity as the conductive layer 761, and allows the use of a metal or alloy with high conductivity, thereby improving the sensitivity of the sensor.

[0303] Note that the type of the touch sensor that can be configured using the conductive layer 761 is not limited to a capacitance type, and various types such as a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type can be used. Alternatively, two or more of these types may be used in combination.

[0304] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0305] (Fourth embodiment) In this embodiment, an example of a head-mounted display to which a display device is applied will be described as an example of an electronic device of one embodiment of the present invention.

[0306] 13A and 13B show the appearance of the head mounted display 8300.

[0307] The head mounted display 8300 includes a housing 8301, a display portion 8302, operation buttons 8303, and a band-shaped fixture 8304.

[0308] The operation button 8303 has a function of a power button, etc. In addition to the operation button 8303, other buttons may be provided.

[0309] 13C, a lens 8305 may be provided between the display unit 8302 and the user's eyes. The lens 8305 allows the user to view an enlarged image of the display unit 8302, enhancing the sense of realism. In this case, as shown in FIG. 13C, a dial 8306 may be provided to change the position of the lens for diopter adjustment.

[0310] The display device of one embodiment of the present invention can be applied to the display portion 8302. The display device of one embodiment of the present invention has extremely high resolution; therefore, even when an image is enlarged using the lens 8305 as in FIG. 13C , pixels are not visible to a user, and more realistic images can be displayed.

[0311] 13A to 13C show an example in which one display portion 8302 is included. With such a configuration, the number of components can be reduced.

[0312] The display portion 8302 can display two images, one for the right eye and one for the left eye, side by side in two regions, left and right, respectively, thereby enabling display of a stereoscopic image using binocular parallax.

[0313] Alternatively, a single image that can be viewed with both eyes may be displayed across the entire area of ​​the display unit 8302. This allows a panoramic image to be displayed across both ends of the field of view, thereby enhancing the sense of reality.

[0314] Here, the head mounted display 8300 preferably has a mechanism for changing the curvature of the display portion 8302 to an appropriate value depending on the size of the user's head, the position of the user's eyes, etc. For example, the user may adjust the curvature of the display portion 8302 by operating a dial 8307 for adjusting the curvature of the display portion 8302. Alternatively, the housing 8301 may be provided with a sensor (for example, a camera, a contact sensor, a non-contact sensor, etc.) that detects the size of the user's head, the position of the user's eyes, etc., and the head mounted display 8300 may have a mechanism for adjusting the curvature of the display portion 8302 based on the detection data of the sensor.

[0315] When the lens 8305 is used, it is preferable to provide a mechanism for adjusting the position and angle of the lens 8305 in synchronization with the curvature of the display portion 8302. Alternatively, the dial 8306 may have a function for adjusting the angle of the lens.

[0316] 13E and 13F show an example including a driver 8308 that controls the curvature of the display unit 8302. The driver 8308 is fixed to at least a part of the display unit 8302. The driver 8308 has a function of deforming the display unit 8302 by deforming or moving a part fixed to the display unit 8302.

[0317] 13E is a schematic diagram showing a case where a user 8310 with a relatively large head size is wearing housing 8301. At this time, the shape of display unit 8302 is adjusted by drive unit 8308 so that the curvature is relatively small (the radius of curvature is large).

[0318] On the other hand, Fig. 13F shows a case where a user 8311, whose head is smaller than that of the user 8310, is wearing the housing 8301. Furthermore, the distance between the eyes of the user 8311 is narrower than that of the user 8310. In this case, the shape of the display unit 8302 is adjusted by the driving unit 8308 so that the curvature of the display unit 8302 is large (the radius of curvature is small). In Fig. 13F, the position and shape of the display unit 8302 in Fig. 13E are indicated by dashed lines.

[0319] In this way, the head mounted display 8300 has a mechanism for adjusting the curvature of the display portion 8302, and can provide an optimal display to various users, regardless of age or gender.

[0320] Furthermore, by changing the curvature of the display portion 8302 depending on the content displayed on the display portion 8302, a high sense of realism can be given to the user. For example, by vibrating the curvature of the display portion 8302, it is possible to express shaking. In this way, various effects can be produced according to the scene in the content, and a new experience can be provided to the user. Furthermore, by linking this with a vibration module provided in the housing 8301, a more realistic display can be achieved.

[0321] Note that the head mounted display 8300 may have two display units 8302 as shown in FIG. 13D.

[0322] By having two display units 8302, the user can view one display unit per eye. This allows high-resolution images to be displayed even when performing 3D display using parallax. Furthermore, the display unit 8302 is curved in an arc shape roughly centered on the user's eye. This allows the distance from the user's eye to the display surface of the display unit to be constant, allowing the user to view more natural images. Furthermore, even if the brightness and chromaticity of light from the display unit change depending on the viewing angle, this effect can be substantially ignored because the user's eyes are positioned in the normal direction to the display surface of the display unit, allowing for the display of more realistic images.

[0323] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0324] (Embodiment 5) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described.

[0325] A display module 6000 shown in FIG. 14A has a display device 6006 connected by an FPC 6005, a frame 6009, a printed circuit board 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.

[0326] For example, a display device manufactured using one embodiment of the present invention can be used as the display device 6006. The display device 6006 can provide a display module with extremely low power consumption.

[0327] The shape and dimensions of the upper cover 6001 and the lower cover 6002 can be changed appropriately to match the size of the display device 6006.

[0328] The display device 6006 may have a function as a touch panel.

[0329] The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, and the like.

[0330] The printed circuit board 6010 has a power supply circuit, a signal processing circuit for outputting video signals and clock signals, a battery control circuit, and the like.

[0331] FIG. 14B is a cross-sectional schematic diagram of a display module 6000 with an optical touch sensor.

[0332] The display module 6000 has a light emitting section 6015 and a light receiving section 6016 provided on a printed circuit board 6010. The display module 6000 also has a pair of light guiding sections (light guiding section 6017a, light guiding section 6017b) in an area surrounded by an upper cover 6001 and a lower cover 6002.

[0333] The display device 6006 is provided so as to overlap the printed circuit board 6010 and the battery 6011 with the frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to the light guide portions 6017a and 6017b.

[0334] Light 6018 emitted from light-emitting unit 6015 passes through light-guiding unit 6017a, passes through the upper part of display device 6006, and reaches light-receiving unit 6016 through light-guiding unit 6017b. When light 6018 is blocked by a detectable object such as a finger or a stylus, a touch operation can be detected.

[0335] A plurality of light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light-receiving units 6016 are provided at positions facing the light-emitting units 6015. This makes it possible to obtain information about the position where a touch operation is performed.

[0336] The light-emitting unit 6015 may be a light source such as an LED element, and it is particularly preferable to use a light source that emits infrared light. The light-receiving unit 6016 may be a photoelectric element that receives the light emitted by the light-emitting unit 6015 and converts it into an electrical signal. Preferably, a photodiode that can receive infrared light may be used.

[0337] The light guiding portions 6017a and 6017b that transmit light 6018 allow the light emitting portion 6015 and the light receiving portion 6016 to be disposed below the display device 6006, thereby preventing external light from reaching the light receiving portion 6016 and causing the touch sensor to malfunction. In particular, using a resin that absorbs visible light and transmits infrared light can more effectively prevent the touch sensor from malfunctioning.

[0338] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0339] (Embodiment 6) In this embodiment, examples of electronic devices to which the display device of one embodiment of the present invention can be applied will be described.

[0340] Electronic device 6500 shown in FIG. 15A is a portable information terminal that can be used as a smartphone.

[0341] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0342] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0343] FIG. 15B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0344] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0345] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0346] A part of the display panel 6511 is folded back in an area outside the display unit 6502. An FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is also connected to a terminal provided on a printed circuit board 6517.

[0347] The flexible display panel of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0348] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0349] (Embodiment 7) In this embodiment, electronic devices including a display device manufactured using one embodiment of the present invention will be described.

[0350] The electronic devices exemplified below each include a display device according to one embodiment of the present invention in a display portion. Therefore, the electronic devices can achieve high resolution. Furthermore, the electronic devices can also have both high resolution and a large screen.

[0351] One embodiment of the present invention includes a display device and at least one of an antenna, a battery, a housing, a camera, a speaker, a microphone, a touch sensor, and an operation button.

[0352] The electronic device of one embodiment of the present invention may include a secondary battery, and it is preferable that the secondary battery can be charged using contactless power transmission.

[0353] Examples of secondary batteries include lithium ion secondary batteries such as lithium polymer batteries (lithium ion polymer batteries) that use a gel electrolyte, nickel-metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead-acid batteries, air secondary batteries, nickel-zinc batteries, and silver-zinc batteries.

[0354] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0355] The display portion of the electronic device of one embodiment of the present invention can display images with a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher.

[0356] Examples of electronic devices include electronic devices with relatively large screens such as television devices, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0357] An electronic device to which one embodiment of the present invention is applied can be incorporated along a flat or curved surface of an inner or outer wall of a building such as a house or a building, or the interior or exterior of a car or the like.

[0358] FIG. 16A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0359] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, etc. The camera 8000 also has a detachable lens 8006 attached thereto.

[0360] The camera 8000 may have the lens 8006 and the housing integrated together.

[0361] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display unit 8002 that functions as a touch panel.

[0362] The housing 8001 has a mount with electrodes, and can be connected to a finder 8100 as well as a strobe device and the like.

[0363] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0364] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display unit 8102.

[0365] The button 8103 has a function such as a power button.

[0366] The display device of one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a finder 8100. Note that the camera 8000 may have a built-in finder.

[0367] FIG. 16B is a diagram showing the appearance of the head mounted display 8200.

[0368] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 has a built-in battery 8206.

[0369] A cable 8205 supplies power from a battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver or the like, and can display received video information on a display portion 8204. The main body 8203 also includes a camera, and can use information on the movement of the user's eyeballs or eyelids as an input means.

[0370] The wearing unit 8201 may have a function of recognizing the line of sight by providing a plurality of electrodes at positions that come into contact with the user and capable of detecting a current that flows in accordance with the movement of the user's eyeballs. The wearing unit 8201 may also have a function of monitoring the user's pulse rate based on the current that flows through the electrodes. The wearing unit 8201 may also have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may also have a function of displaying the user's biological information on the display unit 8204 and a function of changing the image displayed on the display unit 8204 in accordance with the movement of the user's head.

[0371] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0372] 16C, 16D, and 16E are diagrams showing the appearance of a head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0373] A user can view the display on the display portion 8302 through the lens 8305. Note that it is preferable to arrange the display portion 8302 in a curved manner because the user can feel a high sense of presence. In addition, by viewing different images displayed in different regions of the display portion 8302 through the lens 8305, it is possible to perform 3D display using parallax. Note that the present invention is not limited to a configuration in which one display portion 8302 is provided, and two display portions 8302 may be provided, with one display portion being provided for each eye of the user.

[0374] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. The display device including the semiconductor device of one embodiment of the present invention has extremely high definition; therefore, even when an image is enlarged using the lens 8305 as in FIG. 16E, pixels are not visible to a user, and more realistic images can be displayed.

[0375] The electronic device shown in Figures 17A to 17G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to measure force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, etc.

[0376] 17A to 17G have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing using various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic device are not limited to these, and the electronic device may have various other functions. The electronic device may have multiple display units. Furthermore, the electronic device may have a function to include a camera or the like to capture still images or videos and store them on a recording medium (external or built-in to the camera), a function to display the captured images on the display unit, etc.

[0377] The electronic device shown in FIGS. 17A to 17G will be described in detail below.

[0378] 17A is a perspective view showing a television device 9100. The television device 9100 can incorporate a display unit 9001 with a large screen, for example, 50 inches or more, or 100 inches or more.

[0379] FIG. 17B is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. The mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text, image information, and the like on multiple surfaces thereof. FIG. 17B shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, and the strength of antenna reception. Alternatively, the icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

[0380] 17C is a perspective view showing mobile information terminal 9102. Mobile information terminal 9102 has a function of displaying information on three or more sides of display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, while carrying mobile information terminal 9102 in a breast pocket of clothes, the user can check information 9053 displayed in a position that can be observed from above mobile information terminal 9102. The user can check the display without taking mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.

[0381] 17D is a perspective view showing a wristwatch-type mobile information terminal 9200. The display surface of the display unit 9001 is curved, and a display can be displayed along the curved display surface. The mobile information terminal 9200 can also perform hands-free conversations by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also perform data transmission and reception with other information terminals or charge itself via a connection terminal 9006. Charging may be performed by wireless power supply.

[0382] 17E, 17F, and 17G are perspective views showing a foldable mobile information terminal 9201. FIG. 17E shows the mobile information terminal 9201 in an unfolded state, FIG. 17G shows it in a folded state, and FIG. 17F is a perspective view showing a state in the process of changing from one of FIG. 17E and FIG. 17G to the other. The mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, providing excellent viewability of the display. A display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

[0383] 18A shows an example of a television device. A television device 7100 has a display unit 7500 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0384] 18A can be operated using operation switches provided on the housing 7101 or a separate remote control 7111. Alternatively, a touch panel may be applied to the display portion 7500, and the television 7100 may be operated by touching the touch panel. The remote control 7111 may have a display portion in addition to operation buttons.

[0385] The television device 7100 may also include a television broadcast receiver or a communication device for network connection.

[0386] 18B shows a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display portion 7500 is incorporated in the housing 7211.

[0387] 18C and 18D show an example of a digital signage.

[0388] 18C includes a housing 7301, a display unit 7500, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0389] 18D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7500 provided along the curved surface of the pillar 7401.

[0390] The larger the display unit 7500, the more information can be provided at one time, and the larger the display unit 7500 is, the more easily it will catch people's attention, which will have the effect of increasing the advertising effectiveness of advertisements, for example.

[0391] It is preferable that a touch panel be applied to the display unit 7500 so that the user can operate it. This allows the display unit 7500 to be used not only for advertising purposes but also for providing information desired by the user, such as route information, traffic information, or guidance information for commercial facilities.

[0392] 18C and 18D, the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311. Furthermore, the display on the display unit 7500 can be switched by operating the information terminal 7311.

[0393] Furthermore, a game using the information terminal device 7311 as an operation means (controller) can be executed on the digital signage 7300 or the digital signage 7400. This allows an unspecified number of users to simultaneously participate in and enjoy the game.

[0394] The display device of one embodiment of the present invention can be applied to the display portion 7500 in FIGS. 18A to 18D.

[0395] Although the electronic devices in this embodiment have a display portion, one embodiment of the present invention can also be applied to electronic devices that do not have a display portion.

[0396] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification. [Explanation of symbols]

[0397] 10: Display device 11: Pixel section 12: Circuit 13: Circuit 15a, 15b: Terminal section 16a-16c: Wiring 17: IC 20: Pixel unit 21a-21b: Pixel 22: Display area 31-33: Pixel electrode 41-43: Pixel circuit 51-53: Wiring 60: Display element 61-62: Transistor 63: Capacitor element 71-73: Subpixel 100: Transistor 102: Substrate 103a-103b: Insulating layer 104: Insulating layer 106, 106a, 106b: Conductive layer 108, 108a, 108b: Semiconductor layer 108n: Low resistance region 110: Insulating layer 112, 112a, 112b: Conductive layer 112f: Conductive film 114: Metal oxide layer 114f: Metal oxide film 116, 118: Insulating layers 120a-120c: Conductive layers 121-121d: Conductive layers 130: Conductive layers 131-133: Resin layers 140: Impurity elements 141a-141b: Openings 142-144: Openings 150: Conductive layers

Claims

1. a first wiring, a second wiring, and a transistor; the transistor has a channel formation region in an oxide semiconductor layer, a first resin layer is provided between the first wiring and the transistor; a first insulating layer between the first resin layer and the transistor; a second resin layer is provided between the transistor and the second wiring; a second insulating layer between the second resin layer and the transistor; the first insulating layer and the second insulating layer each have an inorganic insulating film containing nitrogen, the first wiring is electrically connected to a gate electrode of the transistor; the second wiring is electrically connected to one of the source and the drain of the transistor, In a plan view, the first wiring is arranged to extend in a first direction, In a plan view, the second wiring is arranged to extend in a second direction intersecting the first direction, In a plan view, the first wiring has a region where it intersects with the second wiring, The region overlaps with the second wiring with the first resin layer, the first insulating layer, the second insulating layer, and the second resin layer sandwiched therebetween.

2. In claim 1, The semiconductor device, wherein the oxide semiconductor layer contains indium oxide.

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