Semiconductor device

Abstract

To provide a semiconductor device which can improve arithmetic capacity such as AI learning and processing efficiency.SOLUTION: A flash memory 100 includes a NAND type or NOR type memory cell array 110, and an arithmetic processing unit 190. The arithmetic processing unit 190 includes a bit line current detection unit 200, a voltage holding unit 210 which holds voltage corresponding to detected current, an addition unit 220 which adds the voltage held in the voltage holding unit 210, and an A / D conversion unit 230 which performs A / D conversion on an addition result of the addition unit 220. The arithmetic processing unit 190 can calculate the sum of currents which flow through a bit line in a line direction and / or a column direction at reading of the memory cell array.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including a NOR or NAND memory cell array, and more particularly to a semiconductor device that can be used as a neuromorphic device. [Background technology]

[0002] Crossbar arrays using variable resistance elements are being put into practical use as AI (artificial intelligence) hardware that structurally simulates synapses and neurons (see, for example, Patent Document 1). Crossbar arrays include variable resistance elements at the intersections of row and column lines, and the variable resistance elements store different resistance values ​​(conductance) when a voltage or current is applied. By writing a desired resistance value into the variable resistance element, for example, an input signal applied to a row line is weighted by the resistance value of the variable resistance element and output from a column line. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6818116 Summary of the Invention [Problem to be solved by the invention]

[0004] 1 is a block diagram showing the configuration of a conventional synapse array device with a learning function. The synapse array device 10 includes a flash memory 20 that stores learning data, a crossbar array 30, and a controller 40. The controller 40 reads the learning data from the flash memory 20, writes the read learning data to the crossbar array 30, modulates the resistance of the variable resistance elements, and performs data learning. The controller 40 also reads the learned data from the crossbar array 30 and writes the read data to the flash memory 20.

[0005] In the conventional synapse array device 10, the flash memory 20 does not have a data calculation function, so it is not possible to perform matrix calculations required for AI learning, etc. This results in low data transfer efficiency, which results in the problem of AI learning processing taking a long time.

[0006] The present invention aims to solve such conventional problems and provide a semiconductor device that can improve the computing power and processing efficiency of AI learning and the like. [Means for solving the problem]

[0007] The calculation method for a semiconductor device according to the present invention includes a NOR or NAND type memory cell array, and when reading multiple rows of the memory cell array, calculates the sum of column-wise currents flowing through bit lines when reading each row.

[0008] In one embodiment, the calculation method further calculates a row-wise sum of column-wise currents of a plurality of bit lines. In one embodiment, the calculation method calculates a row-wise sum of currents corresponding to data stored in memory cells arranged in a plurality of rows and a plurality of columns. In one embodiment, the calculation method includes A / D converting the column-wise sum of currents or the row-wise sum of currents to generate multi-bit data. In one embodiment, the calculation method further includes writing the multi-bit data to memory cells of the memory cell array. In one embodiment, the memory cell array includes first and second memory planes, and calculates a row-wise sum of currents flowing in bit lines during reading of the first memory plane, and writes the multi-bit data to the second memory plane. In one embodiment, the calculation method calculates a first sum of column-wise currents flowing through a first group of bit lines and a second sum of column-wise currents flowing through a second group of bit lines, and calculates a difference between the first sum and the second sum of currents. In one embodiment, the sum of the first currents represents a positive coefficient and the sum of the second currents represents a negative coefficient.

[0009] The semiconductor device of the present invention includes a NOR or NAND type memory cell array including a plurality of row lines, a plurality of bit lines, and a plurality of memory cells, read means for reading from the memory cell array, write means for writing to the memory cell array, and calculation means for calculating the sum of column-wise currents flowing in the bit lines when reading from each row by the read means.

[0010] In one embodiment, the calculation means further calculates a row-wise sum of the column-wise sums of currents flowing through a plurality of bit lines. In another embodiment, the calculation means calculates a row-wise sum of currents flowing through a plurality of rows and a plurality of columns corresponding to data stored in memory cells. In another embodiment, the calculation means includes A / D conversion means that performs A / D conversion on the column-wise sum or the row-wise sum of currents to generate multi-bit data. In another embodiment, the writing means writes the multi-bit data to memory cells of the memory cell array. In another embodiment, the memory cell array includes first and second memory planes, and the calculation means calculates a row-wise sum of currents flowing through bit lines when reading from the first memory plane, and the writing means writes the multi-bit data to the second memory plane. In one embodiment, the calculation means calculates a sum of first currents flowing in the column direction through the bit lines of the first group and a sum of second currents flowing in the column direction through the bit lines of the second group, and calculates the difference between the sum of the first currents and the sum of the second currents. [Effects of the Invention]

[0011] According to the present invention, in a semiconductor device having a NOR or NAND memory cell array, by providing a calculation function for calculating the sum of currents flowing through bit lines, it is possible to improve the calculation capacity and processing efficiency of AI learning, etc. This makes it possible to provide a semiconductor device suitable for neuromorphic devices. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram showing the configuration of a conventional synapse array device. [Figure 2] 1 is a block diagram showing a configuration of a NAND flash memory according to an embodiment of the present invention; [Figure 3] FIG. 2 is a diagram showing a configuration of a block of a memory cell array. [Figure 4] FIG. 2 is a diagram illustrating a configuration example of a page buffer / sense circuit. [Figure 5] FIG. 2 is a block diagram showing the configuration of an arithmetic processing unit of a flash memory according to the present embodiment. [Figure 6] FIG. 6 is a diagram illustrating a functional configuration of a processing unit shown in FIG. 5. [Figure 7] FIG. 10 is a diagram showing a flow of a matrix calculation according to the present embodiment. [Figure 8] FIG. 2 is a schematic diagram illustrating a matrix operation according to the present embodiment. [Figure 9] FIG. 10 is a diagram showing the flow of row-direction calculations in this embodiment. [Figure 10] 10A and 10B are schematic diagrams illustrating row-direction calculations in this embodiment. [Figure 11] FIG. 10 is a diagram showing a flow of calculation in the column direction in this embodiment. [Figure 12] FIG. 10 is a schematic diagram illustrating a column-direction calculation according to the present embodiment. [Figure 13] 10A and 10B are diagrams illustrating writing of matrix calculation results in the present embodiment. [Figure 14] FIG. 10 is a diagram illustrating an example of read / write operations between planes in the present embodiment. [Figure 15] FIG. 10 is a diagram illustrating an example in which the flash memory of the present embodiment is applied to an optical encoder. [Figure 16] FIG. 10 is a block diagram showing the configuration of a processing unit according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] The semiconductor device according to the present invention relates to a flash memory including a NOR or NAND memory cell array. In one embodiment, the flash memory includes a function for detecting currents flowing through bit lines, enabling calculation of the sum of currents corresponding to data in multiple memory cells arranged in a column direction on multiple bit lines when reading multiple rows. In another embodiment, the flash memory includes multiple memory planes, enabling the results of matrix operations on data read from one memory plane to be written to another memory plane. The flash memory can function as an AI memory or neuromorphic device with learning capabilities by performing matrix operations on data read from the memory cell array. The following description will exemplify a NAND flash memory with matrix operations. [Example]

[0014] Next, an embodiment of the present invention will be described with reference to the drawings. Fig. 2 is a diagram showing the configuration of a NAND flash memory according to this embodiment, and the flash memory 100 comprises a NAND memory array 110 in which a plurality of memory cells are arranged in a matrix, an input / output circuit 120 connected to an external input / output terminal and outputting read data to the outside or taking in data input from the outside, an ECC circuit 130 generating an error correction code for data to be programmed and detecting and correcting errors in the read data based on the error correction code, an address register 140 receiving address data via the input / output circuit 120, and an instruction (command) or control signal received via the input / output circuit 120. The flash memory 100 includes a controller 150 that controls each component based on a control signal applied to a control terminal, a word line selection circuit 160 that selects a block or a word line based on the result of decoding row address information Ax from the address register 140, a page buffer / sense circuit 170 that holds data read from a selected page of the memory cell array 110 or data to be programmed to the selected page, a column selection circuit 180 that selects a column based on the result of decoding column address information Ay from the address register 140, and an arithmetic processing unit 190 that performs arithmetic processing in the row and / or column directions of the memory cell array 110. Although not shown here, the flash memory 100 also includes an internal voltage generation circuit that generates voltages (such as a program voltage Vpgm, a pass voltage Vpass, a read voltage Vread, and an erase voltage Vers) required for data reading, programming (writing), and erasing. The NAND flash memory 100 may also be equipped with an SPI to ensure compatibility with NOR flash memories.

[0015] In one embodiment, memory cell array 110 includes, but is not limited to, two memory planes P0 and P1. Memory planes P0 and P1 are formed, for example, in separate P-wells. For example, memory plane P0 includes 1024 even-numbered blocks (BLK0, 2, . . . , 2044, 2046), and memory plane P1 includes 1024 odd-numbered blocks (BLK1, 3, . . . , 2045, 2047).

[0016] As shown in FIG. 3, multiple NAND strings are formed in one block. One NAND string includes multiple memory cells (64 memory cells in this example), bit line side select transistors, and source line side select transistors. The NAND strings may be formed in a two-dimensional array on the surface of a substrate, or in a three-dimensional array on the substrate. The memory cells may be of an SLC type that stores one bit, or may be of a type that stores multiple bits.

[0017] The word line selection drive circuit 160 selects a block in plane P0 and / or a block in plane P1 based on the row address Ax, and then selects a word line of the selected block. It should be noted here that when simultaneously operating planes P0 and P1, the word line selection drive circuit 160 selects the blocks in plane P0 and plane P1 individually; that is, it selects the block in plane P0 based on the address for plane P0, and selects the block in plane P1 based on the address for plane P1. Furthermore, when simultaneously operating planes P0 and P1, the word line selection drive circuit 160 outputs select signals SGS / SGD corresponding to the operation of plane P0 to the bit line side select transistors / source line side select transistors, and outputs select signals SGS / SGD corresponding to the operation of plane P1 to the bit line side select transistors / source line side select transistors.

[0018] The ECC circuit 130 detects and corrects errors in data to be programmed or read. ECC calculations are performed using known techniques such as Hamming code or Reed-Solomon algorithms, and convert k bits or k bytes of input data Di into p = k + q, where "q" is the error correction code or parity bit required for detecting and correcting errors in the data.

[0019] Each of the memory planes P0 and P1 is provided with a page buffer / sense circuit 170, a column selection circuit 180, and an arithmetic processing unit 190. Fig. 4 shows one page buffer / sense circuit and a bit line selection circuit connected thereto. The page buffer / sense circuit 170_0 includes a sense circuit 172_0 that senses data read onto a bit line or sets a voltage corresponding to data to be programmed, a latch circuit 174_0 that holds the sensed data or holds data to be programmed, and a bit line selection circuit 176_0.

[0020] The sense circuit 172_0 includes a precharge transistor BLPRE connected between a voltage supply node V1 and a sense node SNS, a transistor BLCLAMP for generating a clamp voltage at a node TOBL, and a transistor BLCN connected between the node TOBL and a node BLS of the bit line selection circuit 176_0. The sense node SNS is connected to the latch circuit 174_0 via a charge transfer transistor (not shown).

[0021] The bit line selection circuit 176_0 includes a transistor BLSe for selecting the even bit line BLe, a transistor BLSo for selecting the odd bit line BLo, a transistor YBLe for connecting the virtual power supply VIRPWR to the even bit line BLe, and a transistor YBLo for connecting the virtual power supply VIRPWR to the odd bit line BLo.

[0022] In one embodiment, the page buffer 170 includes a first latch L1 capable of holding one page of data and a second latch L2 capable of transferring data to and from the first latch L1. The latch L2 of the page buffer / sense circuit 170 is connected to the input / output buffer 110, the ECC circuit 130, etc. via an internal bus. In another embodiment, the latches L1 and L2 each include a first cache C0 and a second cache C1 that hold data in half-page units, and the first cache C0 is configured to be able to transfer data independently from the second cache C1.

[0023] In a read operation for each memory plane, a positive voltage is applied to the bit line, a read voltage (e.g., 0V) is applied to the selected word line, a read pass voltage Vpass is applied to unselected word lines, the bit line side select transistors and source line side select transistors are turned on by the select signals SGD / SGS, and 0V is applied to the common source line. In a program operation, a high program voltage Vpg is applied to the selected word line, an intermediate potential is applied to unselected word lines, the bit line side select transistors are turned on, the source line side select transistors are turned off, and a voltage corresponding to the program data is applied to the bit line. In an erase operation, 0V is applied to the selected word line within the block, and an erase voltage Vers is applied to the P-well to erase data on a block-by-block basis.

[0024] The arithmetic processing unit 190 has a function of performing matrix operations on data read from the memory cell array 110. More specifically, when reading multiple rows of the memory cell array 110, it detects the currents flowing through the bit lines when reading each row (page), calculates the sum of the detected currents, and A / D converts the calculated sum of currents. The A / D converted data is written back into the memory cell array.

[0025] As shown in FIG. 5, the arithmetic processing unit 190 includes a bit line current detection unit 200, a voltage holding unit 210, an adder unit 220, and an A / D converter unit 230. When reading a selected page, if the selected memory cell stores data "1," the selected memory cell turns on, and the charge precharged on the bit line BL is discharged to the source line SL via the NAND string. On the other hand, if the selected memory cell stores data "0," the selected memory cell turns off, and the charge precharged on the bit line BL is hardly discharged to the source line SL. The bit line current detection unit 200 detects the current flowing from the bit line BL to the source line SL during reading. The bit line current detection unit 200 is not particularly limited in its configuration, but it may be, for example, a unit that connects a shunt resistor in series to the bit line and detects the voltage drop across the shunt resistor, or a current sense amplifier that combines a shunt resistor and an operational amplifier.

[0026] 6 is a diagram showing the connection relationship between the page buffer / sense circuit 170 and the arithmetic processing unit 190. The bit line current detection units 200_0 to 200_q are connected to the page buffer / sense circuits 170_0 to 170_q, respectively, and detect the current flowing through the even bit line BLe or odd bit line BLo selected by the bit line selection circuit. The detection results of the bit line current detection units 200_0 to 200_q are held by the voltage holding units 210_0 to 210_q, respectively. The configuration of the voltage holding unit 210 is not particularly limited, but may include, for example, a charging circuit that charges a capacitor using a diode or a switch and a capacitor, and a reset circuit that discharges the charge stored in the capacitor.

[0027] When multiple pages are read, voltage holding unit 210 may charge a capacitor for each page and provide the charged voltage for each page to adder unit 220 (in this case, the capacitor is reset for each page), or may charge a capacitor with a voltage for each page and provide the charged voltage after the multiple pages have been read to adder unit 220 (in this case, the capacitor is reset after the multiple pages have been read). For example, when eight pages are read consecutively, voltage holding unit 210 may output the voltage charged in the capacitor to adder unit 220 each time the reading of one page is completed, or may output the voltage charged in the capacitor by reading eight pages to adder unit 220 when the reading of eight pages is completed.

[0028] The adder 220 includes column adders 220_0 to 220_q that add voltages of bit lines in the column direction, and a row adder 222 that adds voltages of multiple bit lines in the row direction. The adder 222 is not particularly limited in configuration, but may be configured, for example, using an operational amplifier that adds multiple input voltages. As shown in FIG. 6 , the column adder 220_0 to 220_q is connected to the voltage hold units 210_0 to 210_q, receives the voltages held by the voltage hold units 210_0 to 210_q, and adds these input voltages. The row adder 222 receives the voltages output from the column adder 220_0 to 220_q and adds these input voltages.

[0029] The A / D conversion unit 230 receives the analog voltage output from the addition unit 220 and converts the analog voltage into digital data of a predetermined number of bits. The digital data converted by the A / D conversion unit 230 is again written (programmed) into a selected page in a selected block of the memory cell array.

[0030] The controller 150 is configured, for example, by a microcontroller including ROM / RAM or a state machine. In this embodiment, the controller 150 controls the arithmetic processing unit 190 during read and write operations, for example, using new commands. In one aspect, the controller 150 detects currents flowing through bit lines during read operations from the memory plane P0 or P1, performs a matrix operation on the detected currents, converts the matrix-operated analog data into digital data using the A / D conversion unit 230, and controls writing of the converted digital data to another memory plane P1 or P0.

[0031] Next, a description will be given of the matrix operation of the flash memory 100 of this embodiment. Fig. 7 is a flow showing an example of the matrix operation, and Fig. 8 is a schematic diagram for explaining the matrix operation shown in Fig. 7. The matrix operation here is performed, for example, when consecutive reading is performed from the kth page to the nth page (multiple pages) in the selected block of memory plane P0.

[0032] When the controller 150 receives a command and address for matrix calculation from the host system, it starts continuous reading of multiple pages according to the command. When the kth page (row) of the memory plane P0 is read (S100), current precharged in each bit line flows to the source line according to the data stored in the selected memory cell of the selected page. If the selected memory cell is turned on, the charge on the bit line is discharged to the source line, and if the selected memory cell is off, the charge on the bit line remains almost unchanged. The bit line current detection unit 200 detects currents iBL0, iBL1, . . . , iBLm flowing through the bit lines BL0, BL1, . . . , BLm (S110). Referring to FIG. 8, when the word line WLk is selected, currents iBL0_k to iBLm_k flowing through the bit lines BL0 to BLm are detected, and the detection result is held in the voltage holding unit 210 (S120).

[0033] During successive reads from the kth page to the nth page, currents flowing through the bit lines BL0 to BLm are detected during each read, and voltages corresponding to these currents are held in the voltage holding unit 210. Referring to Fig. 8, when word line WLk+1 is selected, currents iBL0_k+1 to iBLm_k+1 flowing through each of the bit lines BL0 to BLm are detected, and similar detection is performed thereafter, and when word line WLn is selected, currents iBL0_n to iBLm_n flowing through each of the bit lines BL0 to BLm are detected.

[0034] Next, the column summation units 220_0 to 220_q calculate total sums ΣiBL0 to ΣiBLm of the currents of the bit lines BL0 to BLm (S140). When the voltage holding unit 210 holds the total sum of the currents of the bit lines from page k to page n, the column summation units 220_0 to 220_q calculate voltages equal to the voltages held by the voltage holding unit 210. On the other hand, when the voltage holding unit 210 holds the currents of the bit lines when each page is read, the column summation units 220_0 to 220_q sequentially add up the voltages held by the voltage holding unit 210 for each page read.

[0035] Next, the row summation unit 222 inputs the voltages summed by the column summation units 220_0 to 220_q and sums these input voltages (S140). In this way, the sum of voltages corresponding to the currents flowing through the bit lines when reading pages k to n is calculated. Thereafter, the sum of voltages is converted into multi-bit digital data by the A / D conversion unit 230 and written to the selected page of the selected block in the memory plane P1. This writing will be described later.

[0036] In one aspect, in response to a new command, controller 150 enables row-wise calculation by calculation processing unit 190. Fig. 9 is a flow showing an example of row-wise calculation, and Fig. 10 is a schematic diagram for explaining the row-wise calculation shown in Fig. 9.

[0037] When the controller 150 receives a command and address for row-direction calculation from the host system, it starts reading the k-th page in accordance with the command. When the k-th page (row) of the memory plane P0 is read (S200), currents corresponding to the data of the selected memory cells flow from the bit lines BL0 to BLm to the source lines, as shown in Figure 10, and these currents iBL0, iBL1, ..., iBLm are detected by the bit line current detection unit 200 (S210).

[0038] The voltage holding unit 210 holds a voltage corresponding to the bit line current detected by the bit line current detection unit 210 (S220), and then the row addition unit 222 calculates the sum of the row-direction currents iBL0_k+iBL1_k, ... iBLm_k for m bits (230).

[0039] In another aspect, in response to a new command, the controller 150 enables column-wise calculation by the calculation processing unit 190. Fig. 11 is a flow showing an example of column-wise calculation, and Fig. 12 is a schematic diagram for explaining the column-wise calculation shown in Fig. 11.

[0040] When the controller 150 receives a command and an address for matrix calculation from the host system, it starts continuous reading of multiple pages according to the command. When the kth page (row) of the memory plane P0 is read (S300), for example, the bit line current detection unit 210 detects a current iBL2_k flowing through the bit line BL2 (S310), and the voltage corresponding to the detected current iBL2 is held by the voltage holding unit 220 (S320).

[0041] During successive reads from the kth page to the nth page, the current flowing through the bit line BL2 is detected during each read, and a voltage corresponding to the detected current is held in the voltage holding unit 210 (S330). Next, the column addition unit 220_2 calculates a voltage corresponding to the sum of the column-direction currents iBL2_k to iBL2_n (S340).

[0042] In the above embodiment, the bit line current detection units 200_0 to 200_q detect the currents flowing through each bit line, respectively. However, this is merely an example, and the sum of currents flowing through multiple bit lines may be detected. In this case, multiple bit lines are treated as one unit, and the bit line current detection unit 200 detects the sum of currents flowing through multiple bit lines in each unit. For example, if one unit consists of 16 bit lines, the bit line current detection unit 200 detects the sum of currents flowing through the 16 bit lines. For example, the bit line current detection unit 200 detects the sum of currents flowing through shunt resistors connected to the 16 bit lines, and the detected voltage is provided to the voltage holding unit 210. Detecting the sum of currents flowing through multiple bit lines read from the same row is equivalent to the process of adding up the currents flowing through the bit lines in the row direction described in the previous embodiment (FIGS. 9 and 10).

[0043] In another embodiment, a plurality of bit lines in each unit may be commonly connected to a source line, and the bit line current detection unit 200 may detect the current flowing in the common source line in each unit by the bit line current detection unit 200. In other words, the sum of the currents flowing in the plurality of bit lines in each unit flows in the common source line in each unit, and this sum of the currents is detected by the bit line current detection unit 200.

[0044] In yet another embodiment, in a configuration in which a read voltage is applied to a bit line from a voltage supply unit of a sense circuit and the voltage or current of a source line is sensed, as in a NOR flash memory, the bit line current detection unit 200 may be configured to detect a current supplied to multiple bit lines (units) from the current supply unit. A read voltage is supplied from the voltage supply unit to each of the multiple bit lines constituting a unit, and a current corresponding to the data stored in the memory cell flows from the bit line to the source line. The current supplied from the voltage supply unit to the multiple bit lines constituting a unit is equal to the sum of the currents flowing from each bit line to the source line.

[0045] In this way, by using the bit line current detection unit 200 to detect the sum of the currents flowing through the multiple bit lines that make up the unit, the number of circuits in the bit line current detection unit 200, voltage holding unit 210, and addition unit 220 can be reduced, thereby reducing the space required for the circuit.

[0046] Next, an example of writing the result of a matrix operation to another block will be described. In one aspect, the controller 150 writes the result of the matrix operation obtained when reading from the memory plane P0 to the memory plane P1. However, this is just an example, and the operation result can also be written within the same memory plane.

[0047] FIG. 13(A) shows the result of a matrix operation when page reading is performed on word lines WL0 to WL16 in block A, and FIG. 13(B) shows an example of writing the operation result to a selected page on word line WL0 in block B. The matrix operation is data that reflects data stored in memory cells arranged in 16 rows and m columns. If the memory cells store binary data and the A / D conversion unit 230 converts the result of the matrix operation into m-bit digital data, the data in the memory cells arranged in 16 rows and m columns will be compressed to 1 / 16. In other words, the resolution (number of bits) of the A / D conversion unit 230 is determined by the degree to which the result of the matrix operation is compressed.

[0048] The above example shows an example in which the results of a matrix operation are compressed and written, but it is also possible to compress the results of operation in the row direction as shown in Figures 9 and 10 and write them to other blocks, or to compress the results of operation in the column direction as shown in Figures 11 and 12 and write them to other blocks. In these cases, the compression ratio is also determined by the A / D conversion unit 230.

[0049] 14 shows a schematic example of writing the results of a matrix operation between memory planes. First, a matrix operation is performed when block BLK0 of memory plane P0 is read, and the compressed data of the operation result is written to block BLK1 of memory plane P1 (indicated by arrow A). Through this process, the results of the matrix operation performed when memory plane P0 was read are accumulated in block BLK1 of memory plane P1.

[0050] When data is accumulated in block BLK1 of memory plane P1, a matrix operation is performed when block BLK1 is read, and the compressed data of the operation result is written to block BLK0 of memory plane P0 (indicated by arrow B). By repeatedly alternating between read and write operations between memory planes P0 and P1, matrix operations of data stored in multiple memory cells can be realized in the flash memory. Furthermore, since the matrix operation and the result can be written in the internal processing of the flash memory without reading and outputting the operation result from the flash memory to the outside or inputting and writing the operation result from the outside, the efficiency of the matrix operation processing can be improved and the processing time can be reduced.

[0051] A flash memory having a matrix operation function as in this embodiment can be applied to a neuromorphic device, similar to a crossbar array having a resistance change type memory.

[0052] An example of an autoencoder using a neural network is shown in Figure 15. The autoencoder includes multiple encoder layers and multiple decoder layers between the input and output, and the weights or codes of the encoders and decoders are adjusted by learning. The flash memory 100 processes each of the encoder and decoder layers between the input and output.

[0053] Each memory cell of flash memory 100 stores weights or codes for AI learning, and for example, performs matrix operations on data read from the i-th layer, writes the results to the next i+1-th layer, performs matrix operations on data read from the i+1-th layer, and writes the results to the next i+2-th layer, repeating this process in sequence.

[0054] For example, nodes d1, d3, d3, d4, and d5 in the i-th layer correspond to each page when read, and node e1 in the (i+1)-th layer corresponds to data obtained by A / D converting the sum of currents id1_WL1, id2_WL2, id3_WL3, id4_WL4, and id5_WL5 flowing through the bit lines when nodes d1, d2, d3, d4, and d5 are read. Node e2 corresponds to data obtained by A / D converting the sum of currents id1_WL6, id2_WL7, id3_WL8, id4_WL9, and id5_WL10 flowing through the bit lines when nodes d1, d2, d3, d4, and d5 are read. It should be noted here that the pages of nodes d1 to d5 read when writing data to node e1 are different from the pages of nodes d1 to d5 read when writing data to node e2. The A / D converted data is disguised as a WL voltage and transferred to the next hidden layer i+2, and the readout is repeated for the number of nodes in the hidden layer.

[0055] In this way, the flash memory 100 stores learning data whose features have been compressed by matrix calculation processing, and an external controller can perform various processes (e.g., image processing, prediction processing, natural language processing, etc.) using the learning data in the flash memory 100.

[0056] As described above, according to this embodiment, by configuring a flash memory with a matrix operation function, it becomes possible to use the flash memory as a neuromorphic chip with an AI learning function.

[0057] Next, another embodiment of the present invention will be described. In matrix operations in AI learning, weighting coefficients or signs are increased or decreased in either a positive or negative direction. That is, when the connection strength of a synapse increases, the weighting coefficient increases in a positive direction, and when the connection strength decreases, the weighting coefficient decreases in a negative direction.

[0058] In this embodiment, to increase or decrease the weighting coefficient, half of the m-bit memory cells store positive data, and the remaining half store negative data. For example, data from memory cells connected to even bit lines is assigned a positive weighting coefficient, and data from memory cells connected to odd bit lines is assigned a negative coefficient. When the coupling strength between synapses is strong, the data represented by the memory cells on the even bit lines becomes large, and when the coupling strength is low, the data represented by the memory cells on the odd bit lines becomes large.

[0059] 16 is a block diagram showing the configuration of the arithmetic processing unit of this embodiment. The arithmetic processing unit 190A of this embodiment includes a bit line current detection unit 200, a voltage holding unit 210, a positive adder 300, a negative adder 310, a difference calculation unit 320, and an A / D conversion unit 230. Of these, the bit line current detection unit 200, the voltage holding unit 210, and the A / D conversion unit 230 are configured in the same way as in the previous embodiment, so their description will be omitted.

[0060] The positive adder 300 adds the sum of currents flowing through bit lines assigned positive weighting coefficients, e.g., even bit lines, and the negative adder 310 adds the sum of currents flowing through bit lines assigned negative weighting coefficients, e.g., odd bit lines. The difference calculation unit 320 compares the addition result of the positive adder 300 with the addition result of the negative adder 310, calculates the difference, and provides this difference to the A / D conversion unit 230. The A / D conversion unit 230 converts the difference into multi-bit data.

[0061] It should be noted here that difference calculation unit 320 identifies which is larger, the result of positive adder 300 or the result of negative adder 310. If the addition result of positive adder 300 is larger than the addition result of negative adder 310, controller 150 controls so that the A / D converted data is written to a memory cell assigned a positive weighting coefficient, and if the addition result of negative adder 310 is larger than the addition result of positive adder 300, controller 150 controls so that the A / D converted data is written to a memory cell assigned a negative weighting coefficient.

[0062] Thus, according to this embodiment, the difference between the sum of the currents flowing through the bit lines assigned a positive weighting coefficient and the sum of the currents flowing through the bit lines assigned a negative weighting coefficient is calculated, so that modulation by increasing or decreasing the weighting coefficient in AI learning can be easily performed.

[0063] Although the above embodiment illustrates a NAND-type flash memory, the present invention may also be applied to a NOR-type flash memory. A NOR-type flash memory does not have a circuit for sensing one page of data, as in a NAND-type flash memory. However, it is possible to, for example, sequentially switch the connection between a sense circuit equipped with an arithmetic processing unit and the bit lines to detect the currents flowing through the multiple bit lines.

[0064] Although the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the specific embodiment, and various modifications and variations are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0065] 100: Flash memory 110: Memory cell array 120: Address buffer 130: Input / output circuit 140: ECC circuit 150: Controller 160: Word line selection circuit 170: Page buffer / sense circuit 180: column selection circuit 190: arithmetic processing unit

Claims

1. A computing method for a semiconductor device including a NOR or NAND type memory cell array, comprising: A calculation method for calculating a sum of column-direction currents flowing through bit lines when reading each row of the memory cell array.

2. The calculation method according to claim 1 , further comprising calculating a row-wise sum of column-wise current sums of a plurality of bit lines.

3. 3. The calculation method according to claim 2, wherein the calculation method calculates a sum of currents in rows and columns corresponding to data stored in memory cells of a plurality of rows and a plurality of columns.

4. 2. The calculation method according to claim 1, comprising: A / D converting a sum of currents in a column direction or a sum of currents in a row and column direction to generate multi-bit data.

5. 5. The method according to claim 4, further comprising writing said multi-bit data into memory cells of said memory cell array.

6. the memory cell array includes first and second memory planes; 6. The method according to claim 5, further comprising calculating a sum of currents flowing in rows and columns in bit lines when reading from the first memory plane, and writing the plurality of bits of data to the second memory plane.

7. 2. The method of claim 1, wherein the calculation method calculates a sum of first currents flowing in a column direction through the bit lines of the first group and a sum of second currents flowing in a column direction through the bit lines of the second group, and calculates a difference between the sum of the first currents and the sum of the second currents.

8. 8. The method of claim 7, wherein the sum of the first currents represents a positive coefficient and the sum of the second currents represents a negative coefficient.

9. a NOR or NAND type memory cell array including a plurality of row lines, a plurality of bit lines, and a plurality of memory cells; reading means for reading the memory cell array; a write means for writing data to the memory cell array; a calculation means for calculating a sum of column-direction currents flowing through bit lines when reading out a plurality of rows by the reading means; A semiconductor device comprising:

10. 10. The semiconductor device according to claim 9, wherein said calculation means further calculates a row-wise sum of the column-wise current sums of a plurality of bit lines.

11. 11. The semiconductor device according to claim 10, wherein said calculation means calculates a sum of currents in rows and columns corresponding to data stored in memory cells of a plurality of rows and a plurality of columns.

12. 10. The semiconductor device according to claim 9, wherein said calculation means includes A / D conversion means for A / D converting the sum of currents in the column direction or the sum of currents in the row and column directions to generate multi-bit data.

13. 13. The semiconductor device according to claim 12, wherein said writing means writes said multi-bit data into memory cells of said memory cell array.

14. the memory cell array includes first and second memory planes; 14. The semiconductor device according to claim 13, wherein said calculation means calculates a sum of row and column currents flowing through bit lines in a read operation from a first memory plane, and said writing means writes said plurality of bits of data to a second memory plane.

15. 11. The semiconductor device according to claim 10, wherein the calculation means calculates a sum of first currents flowing in the column direction through the bit lines of the first group and a sum of second currents flowing in the column direction through the bit lines of the second group, and calculates a difference between the sum of the first currents and the sum of the second currents.

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