Semiconductor device and semiconductor chip

Abstract

To realize means of fixing an input value of a plurality of pads corresponding to a function to be disabled in a relatively small area.SOLUTION: A semiconductor device includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a plurality of first pads for inputting and outputting a function signal corresponding to a part of the plurality of functions, and a control signal generation circuit for generating a control signal indicating that another part of the plurality of functions is invalid. The second semiconductor chip includes a plurality of second pads for inputting and outputting a function signal corresponding to each of the plurality of functions, and an input fixing circuit for fixing an input value of a pad corresponding to the function to be disabled among the plurality of second pads based on the control signal. The first pad and the second pad are connected to each other.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The disclosed technology relates to a semiconductor device and a semiconductor chip. [Background technology]

[0002] The following technologies are known as technologies related to semiconductor devices. For example, Patent Document 1 describes a semiconductor device that includes a plurality of pads electrically connected to external terminals on a semiconductor chip including a functional part, and at least one of the plurality of pads is an unnecessary pad that is not involved in signal input / output between the functional part and the external terminal, and that includes an I / O buffer circuit near each of the pads that are involved in relaying electrical signals, and that does not include an I / O buffer circuit but instead provides a leak path with a smaller area than the I / O buffer circuit near the unnecessary pad.

[0003] Patent document 2 describes a semiconductor integrated circuit configured by combining multiple pre-prepared functional blocks on a semiconductor substrate, characterized in that it has a first control means for controlling the execution of the original operation of at least one of the multiple functional blocks, and a second control means for controlling the execution of the operation of other functional blocks based on a signal provided from outside the semiconductor integrated circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 03-014265 [Patent Document 2] Japanese Patent Application Publication No. 01-146349 Summary of the Invention [Problem to be solved by the invention]

[0005] Semiconductor devices with a multi-chip configuration are known, in which a general-purpose core chip having general-purpose functional units such as a CPU (Central Processing Unit) and memory and a custom chip having functional units for realizing specific functions are packaged together. To ensure versatility, the general-purpose core chip has all the functions of multiple types of custom chips and has multiple pads for inputting and outputting signals corresponding to each function to and from the custom chip. When a custom chip that does not have some of the functions of the general-purpose core chip is combined with the general-purpose core chip, those functions are disabled in the general-purpose core chip. Input values ​​of multiple pads corresponding to the disabled functions in the general-purpose core chip must be fixed. To fix the input values ​​of the multiple pads corresponding to the disabled functions, it is possible to provide multiple pads on the custom chip that output fixed values ​​to be input to each of these pads. However, the area required for providing the multiple pads is relatively large, making it difficult to miniaturize the custom chip. Furthermore, reserving a large area for functions that the custom chip does not have is wasteful.

[0006] The disclosed technology has been made in consideration of the above points, and aims to realize a means for fixing input values ​​of multiple pads corresponding to disabled functions in a relatively small area. [Means for solving the problem]

[0007] The semiconductor device according to the disclosed technology includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a plurality of first pads for inputting and outputting function signals corresponding to some of a plurality of functions, and a control signal generation circuit that generates a control signal indicating that some of the other functions are disabled. The second semiconductor chip includes a plurality of second pads for inputting and outputting function signals corresponding to each of the plurality of functions, and an input fixing circuit that fixes an input value of a pad of the plurality of second pads corresponding to a function to be disabled based on the control signal. The first pads and the second pads are connected.

[0008] The semiconductor chip according to the disclosed technology includes a plurality of first pads for inputting and outputting function signals corresponding to some of the plurality of functions, and a control signal generating circuit for generating a control signal indicating that some of the other functions of the plurality of functions are disabled.

[0009] The semiconductor chip according to the disclosed technology includes a plurality of second pads for inputting and outputting function signals corresponding to each of a plurality of functions, and an input fixing circuit that fixes the input value of a pad among the plurality of second pads corresponding to a function to be disabled based on the control signal. [Effects of the Invention]

[0010] According to the present invention, it is possible to realize means for fixing input values ​​of a plurality of pads corresponding to functions to be disabled in a relatively small area. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view showing an example of a configuration of a semiconductor device according to an embodiment of the disclosed technique; [Figure 2] 1 is a conceptual diagram illustrating an example of a functional configuration of a general-purpose core chip and a custom chip according to an embodiment of the disclosed technology. [Figure 3] 1 is a plan view showing an example of the configuration of pads formed on the chip surfaces of a general-purpose core chip and a custom chip according to an embodiment of the disclosed technique; [Figure 4] 1 illustrates an example of a configuration of an input fixing circuit according to an embodiment of the disclosed technique. [Figure 5] 1 is a diagram illustrating an example of the configuration of a general-purpose core chip and a custom chip according to an embodiment of the disclosed technology; [Figure 6] 1 is a diagram illustrating an example of the configuration of a general-purpose core chip and a custom chip according to an embodiment of the disclosed technology; [Figure 7] FIG. 10 is a plan view showing an example of the configuration of pads formed on the surface of a custom chip according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the disclosed technology will be described with reference to the drawings. In each drawing, substantially the same or equivalent components or parts are denoted by the same reference numerals.

[0013] FIG. 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to an embodiment of the disclosed technology. The semiconductor device 1 has a multi-chip configuration including a custom chip 10 and a general-purpose core chip 20. The general-purpose core chip 20 has general-purpose functional units such as a CPU and memory. The custom chip 10 has functional units for realizing specific functions according to the application. The custom chip 10 is an example of a "first semiconductor chip" in the disclosed technology, and the general-purpose core chip 20 is an example of a "second semiconductor chip" in the disclosed technology.

[0014] The custom chip 10 and the generic core chip 20 each have a flip-chip structure and include a plurality of pads 11, 21 arranged in a grid pattern on the surface of a semiconductor substrate, and bumps 12, 22 connected to the pads 11, 211, respectively. The generic core chip 20 and the custom chip 10 are electrically and mechanically connected to each other by bonding the bumps 12 and 22. In this embodiment, the area of ​​the custom chip 10 is larger than that of the generic core chip 20, and the generic core chip 20 is stacked on top of the custom chip 10. The custom chip 10 is bonded to the top surface of a package substrate 30. The custom chip 10 is electrically connected to wiring (not shown) formed on the package substrate 30 via wires 31. The generic core chip 20 and the custom chip 10 are sealed on the package substrate 30 by a sealing member 32. The bottom surface of the package substrate 30 has a plurality of bumps 33 arranged in a grid pattern. In other words, the semiconductor device 1 has a BGA (Ball Grid Array) package configuration. The package form of the semiconductor device 1 is not limited to BGA, and may be other package forms such as QFP (Quad Flat Package) or WL-CSP (Wafer Level Chip Size Package).

[0015] 2 is a conceptual diagram showing an example of the functional configuration of the general-purpose core chip 20 and the custom chip 10. The general-purpose core chip 20 has all of the functions of multiple types of custom chips to enable combination with multiple types of custom chips with different functional configurations. FIG. 2 illustrates an example in which the general-purpose core chip 20 has [Function 1], [Function 2], [Function 3], and [Function 4], and the custom chip 10 has [Function 1], [Function 2], and [Function 3], but does not have [Function 4].

[0016] [Function 1] is realized by a processing unit 201 that executes processing related to [Function 1] of the general-purpose core chip 20 and a processing unit 101 that executes processing related to [Function 1] of the custom chip 10 transmitting and receiving a function signal S1 to each other.

[0017] Similarly, [Function 2] is realized by a processing unit 202 that executes processing related to [Function 2] of the general-purpose core chip 20 and a processing unit 102 that executes processing related to [Function 2] of the custom chip 10 transmitting and receiving a function signal S2 to each other.

[0018] Similarly, [Function 3] is realized by processing unit 203, which executes processing related to [Function 3] of the general-purpose core chip 20, and processing unit 103, which executes processing related to [Function 3] of the custom chip 10, sending and receiving function signal S3 to each other.

[0019] Since the custom chip 10 does not have [Function 4], the processing unit 204 that executes the processing related to [Function 4] of the general-purpose core chip 20 is disabled. The processing unit 204 is disabled by inputting a fixed value to the processing unit 204 by the input fixing circuit 210, which will be described later.

[0020] The left side of FIG. 3 is a plan view showing an example of the configuration of pads formed on the chip surface of generic core chip 20, and the right side of FIG. 3 is a plan view showing an example of the configuration of pads formed on the chip surface of custom chip 10. Generic core chip 20 has pad group G1a consisting of multiple pads 21 for inputting and outputting function signal S1 corresponding to [function 1]. The multiple pads 21 belonging to pad group G1a are arranged together in a predetermined area. Similarly, custom chip 10 has pad group G1b consisting of multiple pads 11 for inputting and outputting function signal S1 corresponding to [function 1]. The multiple pads 11 belonging to pad group G1b are arranged together in a predetermined area. The multiple pads 21 belonging to pad group G1a and the multiple pads 11 belonging to pad group G1b are connected to each other via bumps 12 and 22. Pad 11 is an example of a "first pad" in the disclosed technology. Pad 21 is an example of a "second pad" in the disclosed technology.

[0021] The general-purpose core chip 20 has a pad group G2a consisting of a plurality of pads 21 for inputting and outputting a function signal S2 corresponding to [function 2]. The plurality of pads 21 belonging to pad group G2a are arranged together in a predetermined area. Similarly, the custom chip 10 has a pad group G2b consisting of a plurality of pads 11 for inputting and outputting a function signal S2 corresponding to [function 2]. The plurality of pads 11 belonging to pad group G2b are arranged together in a predetermined area. The plurality of pads 21 belonging to pad group G2a and the plurality of pads 11 belonging to pad group G2b are connected to each other via bumps 12 and 22.

[0022] The general-purpose core chip 20 has a pad group G3a consisting of a plurality of pads 21 for inputting and outputting a function signal S3 corresponding to [function 3]. The plurality of pads 21 belonging to pad group G3a are arranged together in a predetermined area. Similarly, the custom chip 10 has a pad group G3b consisting of a plurality of pads 11 for inputting and outputting a function signal S3 corresponding to [function 3]. The plurality of pads 11 belonging to pad group G3b are arranged together in a predetermined area. The plurality of pads 21 belonging to pad group G3a and the plurality of pads 11 belonging to pad group G3b are connected to each other via bumps 12 and 22.

[0023] The generic core chip 20 has a pad group G4a consisting of a plurality of pads 21 for inputting and outputting a function signal S4 corresponding to [Function 4]. The pads 21 belonging to the pad group G4a are arranged together in a predetermined area. The custom chip 10 does not have [Function 4], and does not have a plurality of pads for inputting and outputting a function signal corresponding to [Function 4]. Therefore, input values ​​are not provided from the custom chip 10 to the pads 21 belonging to the pad group G4a corresponding to [Function 4] in the generic core chip 20.

[0024] If the input values ​​of each of the pads 21 belonging to pad group G4a corresponding to [function 4] disabled in the general-purpose core chip 20 are indefinite (floating), a malfunction such as an inrush current may occur when the general-purpose core chip 20 is started up. Therefore, a means is required to fix the input values ​​of each of the pads 21 belonging to pad group G4a corresponding to [function 4] disabled in the general-purpose core chip 20. In the semiconductor device 1 according to this embodiment, the above means is realized by a control signal generation circuit 110 included in the custom chip 10 and an input fixing circuit 210 included in the general-purpose core chip 20.

[0025] The control signal generation circuit 110 generates a control signal S indicating that [function 4] is disabled among [function 1] to [function 4] included in the general-purpose core chip 20. C The control signal S generated by the control signal generating circuit 110 is C is output from pad 13 of custom chip 10.

[0026] Control signal S C is input to pad 23 of general-purpose core chip 20. Pad 13 of custom chip 10 and pad 23 of general-purpose core chip 20 are connected via bumps. Input fixing circuit 210 outputs control signal S C Based on this, the input values ​​of the pads belonging to the pad group G4a corresponding to [function 4] (input values ​​of the processing unit 204 that executes the process related to [function 4]) are fixed.

[0027] 4 shows an example of the configuration of the input fixing circuit 210. The input fixing circuit 210 has a plurality of AND circuits 211 and a plurality of OR circuits 212. One input terminal of each of the AND circuits 211 is connected to some of the pads 21 belonging to the pad group G4a, and the other input terminal of each of the AND circuits 211 is connected to a control signal S COne input terminal of each of the OR circuits 212 is connected to another part of the pads 21 belonging to the pad group G4a, and the other input terminal of each of the OR circuits 211 is connected to the pad 23 to which the control signal S C is connected to a pad 23 to which the

[0028] The custom chip 10 outputs a control signal S with a logic value of "0" indicating that [function 4] is disabled. C In this case, each AND circuit 211 outputs a logical value of "0" regardless of the state of the pad 21, and supplies this value to the processing unit 204 that executes the process related to [function 4]. This means that the input value of the pad 21 connected to the AND circuit 211, among the multiple pads 21 belonging to the pad group G4a corresponding to [function 4], is fixed to "0".

[0029] On the other hand, the control signal S having a logical value of "0" input to the OR circuit 212 C is logically inverted and input to the OR circuit 212. In this case, the OR circuit 212 outputs a logical value of "1" regardless of the state of the pad 21, and supplies this value to the processing unit 204 that executes the process related to [function 4]. This means that the input value of the pad 21 connected to the OR circuit 212, among the multiple pads 21 belonging to the pad group G4a corresponding to [function 4], is fixed to "1".

[0030] By fixing the input value of the pad 21 corresponding to [function 4] disabled in the general-purpose core chip 20 to "0" or "1," it is possible to prevent malfunctions such as an inrush current from flowing when the general-purpose core chip 20 is started up. The input fixing circuit 210 can be configured by arranging an AND circuit 211 on a signal line to which a logical value "0" should be input as a fixed value, and an OR circuit 212 on a signal line to which a logical value "1" should be input as a fixed value. When the input values ​​of all signal lines are fixed to the logical value "0," the input fixing circuit 210 can be configured only by a plurality of AND circuits 211, and when the input values ​​of all signal lines are fixed to the logical value "1," the input fixing circuit 210 can be configured only by a plurality of OR circuits 212.

[0031] 5, a pair of an input fixing circuit 210 and a control signal generating circuit 110 may be provided for each function. When the corresponding [function X] is disabled, the control signal generating circuit 110 outputs a control signal S with a logic value of "0". C If the corresponding [function X] is enabled, the control signal S C Output.

[0032] The input fixing circuit 210 corresponding to the [function X] outputs a control signal S with a logic value of "0" indicating that the [function X] is disabled. C are input, the AND circuit 211 and the OR circuit 212 output the fixed values ​​"0" and "1", respectively, and supply these to the processing unit related to [function X]. On the other hand, the AND circuit 211 and the OR circuit 212 output the control signal S of the logical value "1" indicating that [function X] is enabled. C are input, the logical value of the function signal SX input to the corresponding pad group GXa is output as is.

[0033] As shown in FIG. 6, the control signal generating circuit 110 and the control signal S C In this case, the control signal generation circuit 110 transmits additional information indicating which of the [function 1] to [function 4] is disabled to the control signal S. C The control signal S containing additional information C may be transmitted in the form of a serial signal using, for example, one or two signal lines.

[0034] Input fixing circuits 210 corresponding to each of [Function 1] to [Function 4] determine, based on the additional information, whether to output a fixed value as the input value of pad 21 corresponding to that function, or to output a corresponding function signal supplied from custom chip 10. Input fixing circuits 210 corresponding to the disabled function indicated by the additional information output a fixed value as the input value of pad 21 corresponding to that function, and input fixing circuits 210 corresponding to the other functions output the corresponding function signal supplied from custom chip 10.

[0035] FIG. 7 is a plan view showing an example of the configuration of pads formed on the surface of a custom chip 10X according to a comparative example that does not have [Function 4]. The custom chip 10X according to the comparative example has a pad group G4c including multiple pads 14 as a means for fixing the input values ​​of each of the multiple pads 21 belonging to the pad group G4a corresponding to [Function 4] that is disabled in the generic core chip 20. The multiple pads 21 belonging to the pad group G4a of the generic core chip 20 and the multiple pads 14 belonging to the pad group G4c of the custom chip 10X are connected to each other via bumps. A fixed value is output from each of the multiple pads 14. This fixes the input values ​​of each of the multiple pads 21 belonging to the pad group G4a corresponding to [Function 4] that is disabled in the generic core chip 20. The custom chip 10X according to the comparative example requires the pad group G4c, which requires a relatively large area, making it difficult to miniaturize the custom chip 10X. Furthermore, it is wasteful to reserve a large area for [Function 4] that the custom chip 10X does not have.

[0036] On the other hand, according to the semiconductor device 1 relating to the embodiment of the disclosed technology, the means for fixing the input values ​​of each of the multiple pads corresponding to the functions to be disabled in the general-purpose core chip 20 is composed of the control signal generation circuit 110 and the input fixing circuit 210, so there is no need to provide the pad group G4c relating to the comparative example in the custom chip 10.

[0037] According to the semiconductor device 1 of this embodiment, the control signal generating circuit 110, the input fixing circuit 210 and the control signal S CHowever, the area of ​​each of these elements is much smaller than the area of ​​the region for providing pad group G4c according to the comparative example, so these elements do not pose a disadvantage. If the general-purpose core chip 20 has an input fixing circuit used in a wafer probing test, this input fixing circuit can be used to fix the input values ​​of each of the multiple pads corresponding to the disabled functions, and in this case, the input fixing circuit 210 does not incur additional costs.

[0038] As described above, the semiconductor device 1 according to the embodiment of the disclosed technique can realize a means for fixing input values ​​of multiple pads corresponding to disabled functions in a relatively small area, which makes it possible to reduce the size of the custom chip 10 or to implement other functions on the custom chip 10 without increasing the area.

[0039] Furthermore, since a plurality of pads 11 are arranged in groups by function in the custom chip 10, if there are functions that are not used in the custom chip 10, it is possible to secure a large amount of free space in the custom chip 10.

[0040] Although the above description exemplifies the use of a combination of the general-purpose core chip 20 and the custom chip 10, the disclosed technology is not limited to this example. The disclosed technology can be applied to semiconductor devices including semiconductor chips with any function or purpose. Furthermore, although the above description exemplifies the use of a semiconductor device including two semiconductor chips, the disclosed technology can also be applied to cases where the semiconductor device includes three or more semiconductor chips.

[0041] Furthermore, the above explanation has exemplified a case where one of the four functions possessed by the general-purpose core chip 20 is disabled, but the number of functions possessed by the general-purpose core chip 20 may be two, three, or five or more, and two or more of these functions may be disabled.

[0042] The following additional notes are provided regarding the above-described embodiments. (Appendix 1) A semiconductor device including a first semiconductor chip and a second semiconductor chip, The first semiconductor chip comprises: a plurality of first pads for inputting and outputting function signals corresponding to some of the plurality of functions; a control signal generation circuit that generates a control signal indicating that some other functions of the plurality of functions are disabled; Including, The second semiconductor chip comprises: a plurality of second pads for inputting and outputting function signals corresponding to the plurality of functions; an input fixing circuit that fixes an input value of a pad corresponding to a function to be disabled among the plurality of second pads based on the control signal; Including, The first pad and the second pad are connected Semiconductor device.

[0043] (Appendix 2) In the first semiconductor chip, the plurality of first pads are arranged in groups according to function, In the second semiconductor chip, the second pads are arranged in groups according to their functions. 2. The semiconductor device according to claim 1.

[0044] (Appendix 3) The input fixing circuit includes a logic circuit that selectively outputs the value of the function signal and a fixed value based on the control signal. 10. The semiconductor device according to claim 1 or 2.

[0045] (Appendix 4) a plurality of first pads for inputting and outputting function signals corresponding to some of the plurality of functions; a control signal generation circuit that generates a control signal indicating that some other functions of the plurality of functions are disabled; 1. A semiconductor chip comprising:

[0046] (Appendix 5) a plurality of second pads for inputting and outputting function signals corresponding to the plurality of functions; an input fixing circuit that fixes an input value of a pad corresponding to a function to be disabled among the plurality of second pads based on a control signal indicating that some of the plurality of functions are disabled; 1. A semiconductor chip comprising: [Explanation of symbols]

[0047] 1. Semiconductor device 10 Custom Chips Pads 11, 13, and 14 20 General-purpose core chips 21, 23 Pads 110 Control signal generation circuit 210 Input fixed circuit

Claims

1. A semiconductor device including a first semiconductor chip and a second semiconductor chip, The first semiconductor chip includes: a plurality of first pads for inputting and outputting function signals corresponding to some of the plurality of functions; a control signal generation circuit that generates a control signal indicating that some other functions of the plurality of functions are disabled; Including, The second semiconductor chip includes: a plurality of second pads for inputting and outputting function signals corresponding to the plurality of functions; an input fixing circuit that fixes an input value of a pad corresponding to a function to be disabled among the plurality of second pads based on the control signal; Including, The first pad and the second pad are connected Semiconductor device.

2. In the first semiconductor chip, the plurality of first pads are arranged in groups according to their functions, In the second semiconductor chip, the second pads are arranged in groups according to their functions. The semiconductor device according to claim 1 .

3. The input fixing circuit includes a logic circuit that selectively outputs the value of the function signal and a fixed value based on the control signal. The semiconductor device according to claim 1 .

4. a plurality of first pads for inputting and outputting function signals corresponding to some of the plurality of functions; a control signal generation circuit that generates a control signal indicating that some other functions of the plurality of functions are disabled; 1. A semiconductor chip comprising:

5. a plurality of second pads for inputting and outputting function signals corresponding to the plurality of functions; an input fixing circuit that fixes an input value of a pad corresponding to a function to be disabled among the plurality of second pads based on a control signal indicating that some of the plurality of functions are disabled; 1. A semiconductor chip comprising:

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