Cache device and method for controlling the same

Abstract

To suppress increase in a mounting area while improving access efficiency in a cache device.SOLUTION: A cache device includes: a plurality of caches having a different number of ports that can be used in parallel and each capable of holding data to be used for execution of an instruction by an operation execution unit; and a control unit that controls an input and an output of data to and from the plurality of caches. The control unit determines in which of the plurality of caches data transferred from a memory is to be stored based on identification information held in an identification information holding unit when an access request from the operation execution unit results in cache miss, and stores the data in the determined cache.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a cache device and a method for controlling a cache device. [Background technology]

[0002] A processor such as a CPU (Central Processing Unit) has a cache that holds part of the data stored in the main memory. When the cache holds the target data of a memory access request issued from a processor core (a cache hit), the cache outputs the data to the core without issuing a memory access request to the main memory. This improves data access efficiency and the processing performance of the processor.

[0003] A program executed by a processor is converted into code executable by a compiler. This type of compiler generates code for operating on data that is transferred to a non-cacheable area rather than to a cache, for example, when the boundaries of data used in a task included in the program do not match the memory management unit (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-128803 Summary of the Invention [Problem to be solved by the invention]

[0005] Incidentally, the more ports a cache has for inputting and outputting data, the greater the parallelism of data and the better its access efficiency. This improves execution efficiency, for example, when a core executes instructions in multithreaded mode. On the other hand, the more ports there are, the greater the number of control circuits and signal lines within the cache, which increases the implementation area and cost of the cache. For this reason, there is a demand for a cache that can improve access efficiency while suppressing increases in implementation area.

[0006] In one aspect, the present invention aims to improve access efficiency in a cache device while suppressing an increase in packaging area. [Means for solving the problem]

[0007] According to one aspect, a cache device has a plurality of caches each having a different number of ports that can be used in parallel and each capable of holding data used in the execution of instructions by an execution unit, and a control unit that controls the input and output of data to and from the plurality of caches, and when an access request from the execution unit results in a cache miss, the control unit determines in which of the plurality of caches data transferred from memory should be stored, based on identification information held in an identification information holding unit, and controls the storage of the data in the determined cache. [Effects of the Invention]

[0008] In the cache device, it is possible to improve access efficiency while suppressing an increase in the mounting area. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram illustrating an example of a computer including a cache device according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating an outline of instruction analysis by the compiler in FIG. 1 and data allocation by the control unit. [Figure 3]3 is a diagram showing an example of an execution cycle when the execution unit of FIG. 1 executes the program of FIG. 2. FIG. [Figure 4] 2 is a flow diagram illustrating an example of the operation of the control unit and cache of FIG. 1. [Figure 5] 1. FIG. 4 is a flow diagram illustrating another example of the operation of the control unit and cache of FIG. [Figure 6] FIG. 10 is a block diagram illustrating an example of a computer including a cache device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings.

[0011] Fig. 1 shows an example of a computer including a cache device according to an embodiment. For example, the computer 100 shown in Fig. 1 includes a memory 110, a cache 120, a core 130, and an identification information storage unit 140. The cache 120 includes two types of caches 121 and 122, and a control unit 123 that controls input and output of data to and from the caches 121 and 122. The cache 121 is an example of a first cache, and the cache 122 is an example of a second cache.

[0012] For example, the cache 120 is a data cache that operates as an L3 cache. The cache 120 is an example of a cache device. The computer 100 may also have an instruction cache (not shown) separate from the data cache.

[0013] The core 130 has an execution unit 131 including multiple types of arithmetic units 132 such as an adder, a multiplier, a multiply-and-accumulate unit, and an address generation unit, as well as an instruction decoder, a load-store unit, a register file, etc. (not shown). The core 130 may have an L1 cache and an L2 cache.

[0014] The cache 120 is connected to the memory 110 via a memory bus MBUS. The caches 121 and 122 have asymmetric structures and differ from each other in the number of ports that can be used in parallel. The cache 122 has a larger number of read ports than the cache 121 and has high data read performance (high functionality). The caches 121 and 122 can each hold data used by the execution unit 131 to execute instructions.

[0015] For example, cache 121 has one read port and one write port that can be used in parallel, allowing one read access and one write access to be performed simultaneously (1R1W type), while cache 122 has two read ports and one write port that can be used in parallel, allowing two read accesses and one write access to be performed simultaneously (2R1W type).

[0016] The cache 120 may include caches 121 and 122, each having one read port and one write port that can be used exclusively and another having one read port and one write port that can be used in parallel. The cache 120 may also include cache 121, having one read port and one write port that can be used exclusively, and cache 122, having two read ports and one write port that can be used in parallel. In a cache having one read port and one write port that can be used exclusively, the read port and the write port cannot be used simultaneously.

[0017] For example, if cache 120 is equipped with only cache 122, it is possible to realize a computer 100 with higher computational performance than when cache 120 is equipped with only cache 121, but the mounting area of ​​cache 120 increases, resulting in increased costs. Therefore, in this embodiment, by installing two types of caches 121 and 122 with different read performance in cache 120, it is possible to suppress increases in costs and realize a computer 100 with higher computational performance than when only cache 121 is installed. Computational performance will be described with reference to FIG. 3.

[0018] For example, the memory 110 may be a main storage device. When the core 130 is equipped with a cache such as an L1 cache or an L2 cache, the cache 120 is an LLC (Last Level Cache) such as an L3 cache.

[0019] For example, each of the caches 121 and 122 has a tag area and a data area. The tag area holds information indicating the memory address of the data held in the cache 121 (or 122) and information indicating the coherency of the data held in the cache 121 (or 122). The memory address is an address assigned to an area in the memory 110 that holds the data to be accessed.

[0020] The data area may have multiple areas for storing data for each data input / output to / from the core 130, or may have multiple areas (i.e., cache lines) for storing multiple pieces of data with consecutive memory addresses. Note that the tag area may be provided in common to the caches 121 and 122.

[0021] When data is to be stored in cache 120, control unit 123 uses the identification information held in identification information holding unit 140 to determine whether the data should be stored in cache 121 or 122. Control unit 123 connects one of the determined caches 121 or 122 to memory bus MBUS. Data read from memory 110 is then stored in cache 121 or 122 determined by control unit 123. For example, data is stored from memory 110 to cache 120 in the event of a cache miss, in which data used by execution unit 131 is not held in cache 120.

[0022] For example, the identification information holding unit 140 has a memory that holds identification information transferred from the memory 110. The identification information includes information on whether data is to be stored in the cache 121 or 122, corresponding to an address (memory address) of the memory 110 that holds data used in the execution of an instruction by the execution unit 131. For example, in this embodiment, the identification information includes a memory address of data to be stored in the high-performance cache 122. However, the identification information may also include a memory address of data to be stored in the low-performance cache 121, or may include addresses of data to be stored in the caches 121 and 122 corresponding to the caches 121 and 122, respectively.

[0023] The identification information may also include information indicating whether the data is to be stored in cache 121 or 122, corresponding to an address range including an address of memory 110 that holds the data used in executing the instruction. The identification information holding unit 140 may be provided within cache 120.

[0024] For example, a program executed by the computer 100 (instructions executed by the execution unit 131) is compiled by a compiler 220 installed in an information processing device 200 such as a server. The compiler 220 compiles the program 210 to generate object code 230 (binary code) that can be executed by the execution unit 131. The object code 230 is an example of instruction code.

[0025] Furthermore, the compiler 220 analyzes the instructions included in the program 210 when compiling the program 210, thereby generating identification information 240 along with the object code 230. For example, in order to improve the calculation performance of the calculation execution unit 131, the compiler 220 analyzes which data among the data used in the program 210 should be stored in the high-performance cache 122, and outputs the analysis result as the identification information 240.

[0026] The object code 230 and identification information 240 output by the compiler 220 are transferred to the memory 110 by the OS (Operating System) executed by the computer 100. The identification information 240 transferred to the memory 110 is further transferred to the identification information holding unit 140 before the execution of instructions by the execution unit 131 begins. The dashed arrows in the figure indicate the transfer paths of the object code and identification information by the OS. The transfer of the object code and identification information by the OS is performed before the computer 100 executes an application program for computation.

[0027] For example, the compiler 220 may output, as the identification information 240, the address of the memory 110 that holds the data to be stored in the cache 122. Alternatively, the compiler 220 may output, as the identification information 240, a range of addresses of the memory 110 that holds multiple data to be stored in the cache 122.

[0028] As described above, the control unit 123 performs control to store data read from the memory 110 in either of the caches 121 and 122, which have different performance, based on the identification information stored in the identification information storage unit 140. This improves the data access efficiency when the execution unit 131 executes an instruction. As a result, the instruction execution cycle can be shortened, and the processing performance of the computer 100 can be improved.

[0029] Note that a cache with a configuration similar to that of the cache 120 may be installed in the core 130 as either or both of an L1 cache and an L2 cache. In this case, the computer 100 may have a normal L3 cache instead of the cache 120. In other words, two types of caches 121 and 122 with different read performance may be installed in one or more of the multiple tiers of cache.

[0030] 2 shows an overview of instruction analysis by the compiler 220 in FIG. 1 and data allocation by the control unit 123. In the example shown in FIG. 2, each of the four processes executed by the program includes one of threads 0 to 3. For example, each thread performs a multiply-and-accumulate operation to multiply two data (data A and B, data A and D, data A and F, or data A and H) and add the multiplication result to data (data C, data E, data G, or data I).

[0031] For example, the compiler 220 analyzes the dependency of data used in instructions included in the program 210. Then, in order to minimize the average read access time from the cache 120 for data used by the execution unit 131, the compiler 220 decides whether to store the data in the low-performance cache 121 or the high-performance cache 122. In other words, the compiler 220 analyzes whether the calculation time by the execution unit 131 can be reduced by allocating the storage destination of the data used by each instruction to the caches 121 and 122. Then, the compiler 220 outputs the analysis result as identification information.

[0032] 2, the compiler 220 determines in the analysis process that data A is included in each thread of four processes and therefore has a dependency between the processes, but that data other than data A does not have a dependency between the processes. Furthermore, in the analysis process, the compiler 220 determines that it is preferable to store data F and G in a cache separate from the cache that stores data other than data A, in order to optimize the number of instructions executed simultaneously. Then, as a result of the analysis, the compiler 220 outputs identification information indicating that data A, F, and G should be allocated to cache 122 (2R1W type) and the other data should be allocated to cache 121 (1R1W type).

[0033] 2, the compiler 220 may determine that data B and C are to be stored in a cache separate from the cache that stores data other than data A. Alternatively, the compiler 220 may determine that data D and E are to be stored in a cache separate from the cache that stores data other than data A, or may determine that data H and I are to be stored in a cache separate from the cache that stores data other than data A.

[0034] 4 and 5, when a cache miss occurs during execution of program 210 (i.e., object code 230) by operation execution unit 131, control unit 123 refers to identification information holding unit 140. Then, control unit 123 determines whether data read from memory 110 should be stored in cache 120 as cache 121 or 122.

[0035] When all the data AG has been used by the program executed by the execution unit 131, the state of the cache 120 holding the data AG will be as shown in Figure 2. The symbols R and W shown in the caches 121 and 122 indicate the read port and write port, respectively.

[0036] Figure 3 shows an example of an execution cycle when the program 210 in Figure 2 is executed by the execution unit 131 in Figure 1. The upper part of Figure 3 shows an example of operation when it is assumed that the cache 120 includes two caches 121 (1R1W type). The lower part of Figure 3 shows an example of operation when the cache 120 includes one cache 121 (1R1W type) and one cache 122 (2R1W type), as shown in Figure 1. Hereinafter, the 1R1W type cache 121 and the 2R1W type cache 122 may be referred to as the 1R1W cache and the 2R1W cache, respectively.

[0037] The symbol RD indicates a read cycle that executes a read operation (load command), and the letter after the hyphen indicates the data read from the cache. The symbol WR indicates a write cycle that executes a write operation (store command), and the letter after the hyphen indicates the data written to the cache.

[0038] 3, it is assumed that all data used in the operation is held in the cache 120 and that all accesses result in a cache hit. It is assumed that the execution cycles for each of the read operation, write operation, and multiply-accumulate operation are eight cycles. It is also assumed that access to the cache 120 is performed using three load-store units. It is assumed that the multiply-accumulate operation is performed by the operation execution unit 131, and therefore can be executed overlapping with the read cycle and write cycle.

[0039] If the cache 120 includes two 1R1W type caches 121, the execution unit 131 can execute a maximum of two read cycles every eight cycles. In this case, the number of cycles required for each of threads 0 to 3 to execute one multiply-accumulate operation is 80 cycles.

[0040] If the cache includes one 1R1W cache and one 2R1W cache, the execution unit 131 can execute up to three read cycles every eight cycles. In this case, the number of cycles required for threads 0 to 3 to execute one multiply-and-accumulate operation is 72. Therefore, by replacing part of the cache 120 with a high-performance 2R1W type cache, the operation speed can be increased by 1.11 times (=80 / 72), for example.

[0041] As a result, it is possible to realize a computer 100 with higher computing performance than when only cache 121 is installed in cache 120. In this case, it is possible to reduce the mounting area of ​​cache 120 compared to when all caches 120 are high-performance 2R1W type caches. Therefore, cache 120 shown in FIG. 1 can suppress an increase in mounting area while improving access efficiency.

[0042] Fig. 4 shows an example of the operation of the cache 120 in Fig. 1. The operation shown in Fig. 4 is started when the cache 120 receives a read access request from the execution unit 131. The operation of the cache 120 is controlled by the control unit 123.

[0043] When the cache 120 receives a read access request from the execution unit 131, in step S110, the control unit 123 determines whether there is a hit in the 1R1W cache or the 2R1W cache. If there is a hit in either the 1R1W cache or the 2R1W cache, step S160 is performed. If there is a miss in both the 1R1W cache and the 2R1W cache, step S120 is performed.

[0044] In step S120, the control unit 123 issues a read access request to the memory 110. Next, in step S130, the control unit 123 reads from the identification information holding unit 140 the identification information corresponding to the access address included in the read access request.

[0045] Next, in step S140, the control unit 123 selects either the 1R1W cache or the 2R1W cache that stores the data to be read, based on the read identification information, and connects it to the memory 110. For example, the 1R1W cache or the 2R1W cache and the memory 110 are connected via a multiplexer controlled by the control unit 123.

[0046] Next, in step S150, the control unit 123 stores the data output from the memory 110 in the 1R1W cache or 2R1W cache connected to the memory 110. After step S150, step S160 is performed.

[0047] In step S160, the cache 120 outputs the data to be read to the operation execution unit 131, and the operation shown in FIG. 4 ends.

[0048] If a miss occurs in the 1R1W cache or the 2R1W cache, data may be flushed from the 1R1W cache or the 2R1W cache that caused the miss to memory 110 to secure an area to store the data to be read. However, in FIG. 4, it is assumed that there is free space in the 1R1W cache and the 2R1W cache, and no data flushing will occur. If data flushing occurs, the data flushing process is performed between steps S140 and S150.

[0049] Figure 5 shows another example of the operation of the control unit 123 and cache 120 of Figure 1. Detailed description of the same operations as those in Figure 4 will be omitted. The operations of steps S210, S220, S230, S240, and S250 are the same as the operations of steps S110, S120, S130, S140, and S150 of Figure 4, respectively. That is, when a miss occurs in the 1R1W cache and the 2R1W cache, data corresponding to the data to be written is read from the memory 110, and the read data is stored in the 1R1W cache or the 2R1W cache selected based on the identification information.

[0050] If the 1R1W cache or the 2R1W cache is hit, or after step S250 is executed due to a cache miss, step S260 is performed. In step S260, the cache 120 writes the write-target data to the write-target 1R1W cache or 2R1W cache indicated by the identification information. Then, the operation shown in FIG. 5 ends.

[0051] If a miss occurs in the 1R1W cache or the 2R1W cache, in step S260 the cache 120 overwrites the data to be written in the 1R1W cache or the 2R1W cache in which the data from the memory 110 is stored.

[0052] For example, the unit size of data input / output between the cache 120 and the memory 110 (cache line size) is assumed to be larger than the unit size of data read / written between the cache 120 and the execution unit 131 (register file size). In this case, upon a cache miss, data of the cache line size is stored from the memory 110 in the 1R1W cache or 2R1W cache, and then the data to be written output from the execution unit is overwritten.

[0053] As described above, in this embodiment, the control unit 123 stores data read from the memory 110 in either of the caches 121 and 122, which have different performance, based on the identification information stored in the identification information storage unit 140. This improves the data access efficiency when the execution unit 131 executes an instruction, and shortens the instruction execution cycle. As a result, the processing performance of the computer 100 can be improved.

[0054] In this case, it is possible to realize a computer 100 with higher computing performance than, for example, when the cache 120 is equipped with only the low-performance cache 121. Also, it is possible to reduce the mounting area of ​​the cache 120 compared to, for example, when all of the caches 120 are high-performance 2R1W type caches. As a result, it is possible to improve the access efficiency of the cache 120 while suppressing an increase in the mounting area.

[0055] The identification information includes information on whether data is to be stored in cache 121 or 122, corresponding to the memory address of the data used in executing the instruction. This allows control unit 123 to determine cache 121 or 122 in which to store data based on the address, thereby simplifying the control of allocating data to caches 121 and 122. For example, by setting the identification information to an address range, the control of allocating data to caches 121 and 122 can be made simpler.

[0056] The identification information is generated together with the object code 230 by the compiler 220 analyzing the instructions included in the program 210 when compiling the program 210. Therefore, the control unit 123 can select the caches 121, 122 in which to store data based on the identification information appropriately generated to shorten the instruction execution cycle.

[0057] 6 shows an example of a computer including a cache device according to another embodiment. The same elements as those in FIG. 1 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted. In this embodiment, a compiler 220 embeds identification information generated by analyzing a program 210 during compilation into an object code 230.

[0058] For example, the compiler 220 adds a flag to instruction codes (e.g., load instructions) that use data to be stored in the intelligent cache 122. For this reason, the identification information is transferred by the OS to the memory 110 together with the object code 230. Hereinafter, the flag added to the instruction code to identify the data to be stored in the cache 122 will be referred to as an identification flag.

[0059] 6 has a configuration and functions similar to those of the cache 100 in FIG. 1, except that it has a cache 120A and an execution unit 131A instead of the cache 120 and the execution unit 131 in FIG. 1, and does not have the identification information holding unit 140 in FIG. 1. Note that object code (instruction code with identification information) held in memory 110 is fetched by the execution unit 131A via an instruction cache (not shown). Cache 120A has a configuration and functions similar to those of cache 120 in FIG. 1, except that it has a control unit 123A instead of the control unit 123 in FIG. 1.

[0060] When an identification flag is added to an instruction code decoded by an instruction decoder (not shown), the execution unit 131A outputs an access request with the identification flag to the cache 120A. For example, the access request with the identification flag is a read access request corresponding to a load instruction or a write access request corresponding to a store instruction.

[0061] When a read access request or a write access request with an identification flag received from the core 130A results in a cache miss, the control unit 123A selects the 2R1W cache and connects it to the memory 110. On the other hand, when a read access request or a write access request without an identification flag received from the core 130A results in a cache miss, the control unit 123A selects the 1R1W cache and connects it to the memory 110.

[0062] When a read access request or write access request received from the core 130A results in a cache hit, the cache 120A outputs the data from the hit cache 121 (or 122) to the execution unit 131A regardless of the presence or absence of an identification flag.

[0063] As a result, the computer 100A can achieve the same functions as the computer 100 shown in Figures 1 to 5. If the read access request results in a cache miss, the control unit 123A uses the identification flag added to the read access request as identification information instead of step S130 in Figure 4. Similarly, if the cache 120A determines that the write access request results in a cache miss, the control unit 123A uses the identification flag added to the write access request as identification information instead of step S230 in Figure 5.

[0064] As described above, the embodiment shown in FIG. 6 can also achieve the same effects as the embodiments shown in FIGS. 1 to 5. For example, the control unit 123A stores data read from the memory 110 in one of the caches 121 and 122, which have different performance, based on an access request with an identification flag received from the core 130A. This improves the data access efficiency when the execution unit 131A executes an instruction, and shortens the instruction execution cycle. As a result, the processing performance of the computer 100A can be improved. Therefore, it is possible to prevent an increase in the mounting area while improving the access efficiency of the cache 120A.

[0065] The compiler 220 analyzes the instructions included in the program 210 when compiling the program 210, and adds the identification information as an identification flag to the instruction code in the object code 230. Therefore, the control unit 123A can select the cache 121, 122 in which to store data based on the identification flag that has been appropriately added to shorten the instruction execution cycle.

[0066] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims encompass the features and advantages of the above-described embodiments without departing from the spirit and scope of the claims. Furthermore, any improvements and modifications will be readily apparent to those skilled in the art. Therefore, it is not intended that the scope of the inventive embodiments be limited to the above-described embodiments, and appropriate improvements and equivalents within the scope of the disclosed embodiments may be utilized. [Explanation of symbols]

[0067] 100, 100A calculator 110 memory 120, 120A Cache 121 1R1W type cache 122 2R1W type cache 123, 123A control unit 130, 130A core 131, 131A Calculation execution unit 132 Arithmetic unit 140 Identification information storage unit 200 Information processing device 210 Programs 220 Compiler 230 Object Code 240 Identification Information MBUS Memory Bus

Claims

1. a plurality of caches each having a different number of ports that can be used in parallel and each capable of holding data used in the execution of instructions by an execution unit; a control unit that controls input and output of data to and from the plurality of caches; When an access request from the execution unit results in a cache miss, the control unit determines in which of the plurality of caches data transferred from the memory should be stored, based on the identification information held in the identification information holding unit, and performs control to store the data in the determined cache. Cache device.

2. The identification information includes information indicating in which of the plurality of caches data is to be stored, corresponding to an address of the memory that holds data used in the execution of the instruction by the execution unit. The cache device according to claim 1 .

3. The identification information includes information indicating in which of the plurality of caches data is to be stored, corresponding to an address range including an address of the memory that holds data used in the execution of the instruction by the execution unit. The cache device according to claim 1 .

4. The identification information is information that is generated together with an instruction code by analyzing the instruction by a compiler that compiles the instruction executable by the execution unit, and is transferred to the identification information holding unit before the execution of the instruction by the execution unit begins. The cache device according to claim 1 .

5. a plurality of caches each having a different number of ports that can be used in parallel and each capable of holding data used in the execution of instructions by an execution unit; a control unit that controls input and output of data to and from the plurality of caches; When an access request from the execution unit results in a cache miss, the control unit determines in which of the plurality of caches data from the memory should be stored based on identification information received from the execution unit, and performs control to store the data in the determined cache. Cache device.

6. The identification information is added to the instruction code executed by the execution unit.

6. The cache device according to claim 5.

7. The identification information is information that is generated by a compiler that compiles instructions executable by the execution unit by analyzing the instructions, and is added to the instruction code generated by the compiler.

7. The cache device according to claim 6.

8. the plurality of caches are a first cache and a second cache; the first cache has one read port and one write port that can be used in parallel, or one read port and one write port that can be used exclusively; The second cache has two of the read ports and one write port that can be used in parallel.

8. The cache device according to claim 1.

9. the plurality of caches are a first cache and a second cache; the first cache has one read port and one write port that can be used exclusively; The second cache has one read port and one write port that can be used in parallel.

8. The cache device according to claim 1.

10. 1. A method for controlling a cache device having a plurality of caches each having a different number of ports that can be used in parallel and each capable of holding data used in execution of an instruction by an execution unit, comprising: The control unit of the cache device Controlling input and output of data to and from the plurality of caches; When an access request from the execution unit results in a cache miss, the control unit determines which of the plurality of caches to store data transferred from the memory based on the identification information stored in the identification information storage unit, and performs control to store the data in the determined cache. A method for controlling a cache device.

11. 1. A method for controlling a cache device having a plurality of caches each having a different number of ports that can be used in parallel and each capable of holding data used in execution of an instruction by an execution unit, comprising: The control unit of the cache device Controlling input and output of data to and from the plurality of caches; When an access request from the execution unit results in a cache miss, the execution unit determines which of the plurality of caches to store data from the memory based on identification information received from the execution unit, and performs control to store the data in the determined cache. A method for controlling a cache device.

Images