Semiconductor device and control method for semiconductor device

Abstract

To provide a semiconductor device capable of improving inverter efficiency and a control method for the semiconductor device.SOLUTION: According to one embodiment, a semiconductor device 1 comprises a first gate of IGBT10, which is a gate of an element connecting a collector of IGBT10 to a drain of MOSFET30 and a cathode of a diode, and connecting an emitter of IGBT10 to a source of MOSFET30 and an anode of the diode, and a control unit 500 for controlling a second gate, which is a gate of MOSFET 30, and the control unit 500 controls the first gate while keeping the second gate turned on.SELECTED DRAWING: Figure 12

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for controlling the semiconductor device, for example, a semiconductor device including a metal-oxide-semiconductor field-effect transistor (MOSFET) and an insulated gate bipolar transistor (IGBT), and a method for controlling the semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a method for controlling a semiconductor device including an inverter. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-102923 Summary of the Invention [Problem to be solved by the invention]

[0004] It is desirable to reduce power losses in semiconductor devices that include inverters and to improve the efficiency of the inverters.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, a semiconductor device includes a control unit that connects a collector of an IGBT, a drain of a MOSFET, and a cathode of a diode, and controls a first gate that is a gate of the IGBT and a second gate that is a gate of the MOSFET in an element that connects an emitter of the IGBT, a source of the MOSFET, and an anode of the diode, and the control unit controls the first gate while keeping the second gate on.

[0007] According to one embodiment, a method for controlling a semiconductor device includes a control unit that connects the collector of an IGBT, the drain of a MOSFET, and the cathode of a diode, and controls a first gate that is the gate of the IGBT and a second gate that is the gate of the MOSFET in an element that connects the emitter of the IGBT, the source of the MOSFET, and the anode of the diode, and includes a step of controlling the first gate with the second gate turned on. [Effects of the Invention]

[0008] According to the embodiment, it is possible to provide a semiconductor device and a method for controlling the semiconductor device that can improve the efficiency of the inverter. [Brief explanation of the drawings]

[0009] [Figure 1] 10 is a circuit diagram illustrating an inverter in a semiconductor device according to Comparative Example 1. FIG. [Figure 2] 10 is a circuit diagram illustrating an inverter in a semiconductor device according to Comparative Example 2. FIG. [Figure 3] 11 is a circuit diagram illustrating an inverter in a semiconductor device according to Comparative Example 3. FIG. [Figure 4] 1 is a graph illustrating the conduction loss of an inverter in semiconductor devices according to Comparative Examples 1 to 3, in which the horizontal axis represents the voltage between the collector terminal and the emitter terminal of an IGBT or the voltage between the drain terminal and the source terminal of a MOSFET, and the vertical axis represents the current between the collector terminal and the emitter terminal of an IGBT or the current between the drain terminal and the source terminal of a MOSFET. [Figure 5] 1 is a graph illustrating a tail current at turn-off in a semiconductor device according to Comparative Example 1, where the horizontal axis represents time and the vertical axis represents current or voltage. [Figure 6] 10 is a graph illustrating the current at the time of turn-off in the semiconductor device according to Comparative Example 2, where the horizontal axis represents time and the vertical axis represents current or voltage. [Figure 7] 1 is a graph illustrating the reverse recovery current of an FRD in a semiconductor device according to Comparative Example 1, where the horizontal axis represents time and the vertical axis represents the current flowing through the FRD. [Figure 8] 10 is a graph illustrating the reverse recovery current of an SBD in a semiconductor device according to Comparative Example 3, where the horizontal axis represents time and the vertical axis represents the current flowing through the SBD. [Figure 9] 2 is a circuit diagram illustrating an inverter in the semiconductor device according to the first embodiment. FIG. [Figure 10] 1 is a graph illustrating the conduction loss of an inverter in the semiconductor device according to the first embodiment, in which the horizontal axis represents the voltage between the collector terminal and the emitter terminal of an IGBT or the voltage between the drain terminal and the source terminal of a MOSFET, and the vertical axis represents the current between the collector terminal and the emitter terminal of an IGBT or the current between the drain terminal and the source terminal of a MOSFET. [Figure 11] 2 is a circuit diagram illustrating an example of an outline of exclusive control of an inverter in the semiconductor device according to the first embodiment. FIG. [Figure 12] 2 is a circuit diagram illustrating an outline of individual control of inverters in the semiconductor device according to the first embodiment. FIG. [Figure 13] 2 is a circuit diagram illustrating an outline of simultaneous control of inverters in the semiconductor device according to the first embodiment. FIG. [Figure 14] 2 is a block diagram illustrating a control unit in the semiconductor device according to the first embodiment. FIG. [Figure 15] 2 is a block diagram illustrating an MCU in the semiconductor device according to the first embodiment. FIG. [Figure 16] 2 is a block diagram illustrating a GDU in the semiconductor device according to the first embodiment. FIG. [Figure 17] 4 is a flowchart illustrating a control method of a control unit in the semiconductor device according to the first embodiment. FIG. [Figure 18]1 is a graph illustrating changes in the gate voltage VG1, voltage VCE, and current ICE of an IGBT, and the gate voltage VG2, voltage VDS, and current IDS of a MOSFET in a semiconductor device according to embodiment 1, where the horizontal axis represents time and the vertical axis represents each voltage and each current. [Figure 19] 4 is a flowchart illustrating a control method of a control unit in the semiconductor device according to the first embodiment. FIG. [Figure 20] 1 is a graph illustrating changes in the gate voltage VG1, voltage VCE, and current ICE of an IGBT, and the gate voltage VG2, voltage VDS, and current IDS of a MOSFET in a semiconductor device according to embodiment 1, where the horizontal axis represents time and the vertical axis represents each voltage and each current. [Figure 21] 2 is a circuit diagram illustrating a GDU and an MCU that perform individual control in the semiconductor device according to the first embodiment. FIG. [Figure 22] 10 is a circuit diagram illustrating a GDU and an MCU that perform individual control in a semiconductor device according to a modified example of the first embodiment. FIG. [Figure 23] 2 is a circuit diagram illustrating a GDU and an MCU that perform simultaneous control in the semiconductor device according to the first embodiment. FIG. [Figure 24] 10 is a circuit diagram illustrating another GDU and MCU that perform simultaneous control in a semiconductor device according to Modification 1 of Embodiment 1. FIG. [Figure 25] 10 is a circuit diagram illustrating another GDU and MCU that perform simultaneous control in a semiconductor device according to Modification 2 of Embodiment 1. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. Note that in each drawing, the same elements are given the same reference numerals, and duplicate explanations are omitted as necessary. Furthermore, reference numerals have been omitted as appropriate to avoid cluttering the drawings.

[0011] First, in <Comparative Example 1> to <Comparative Example 3>, semiconductor devices and methods for controlling the semiconductor devices according to Comparative Examples 1 to 3 will be described. Then, in <Problems Newly Discovered by the Inventors>, problems newly discovered by the inventors with respect to Comparative Examples 1 to 3 will be described. Then, in <Embodiment 1>, semiconductor devices and methods for controlling the semiconductor devices according to the embodiments will be described. This will make the semiconductor devices and methods for controlling the semiconductor devices of the embodiments clearer. Note that the semiconductor devices and methods for controlling the semiconductor devices according to Comparative Examples 1 to 3, as well as the problems newly discovered by the inventors, are also within the technical scope of the embodiments.

[0012] <Comparative Example 1> Comparative Example 1 is an example in which an inverter includes an IGBT and an FRD (Fast Recovery Diode). FIG. 1 is a circuit diagram illustrating an inverter INV1 in a semiconductor device 101 according to Comparative Example 1. In FIG. 1, some reference numerals are omitted to avoid cluttering the diagram. Similarly, some reference numerals may be omitted in subsequent drawings. As shown in FIG. 1, the semiconductor device 101 according to Comparative Example 1 includes an inverter INV1. The semiconductor device 101 includes, for example, a power module and controls the driving of a motor or the like. The inverter INV1 has a function of switching-controlling the voltage applied to the motor. The inverter INV1 applies, for example, six-channel driving voltages to the motor to pass current through the motor and drive the motor. The motor may be a three-phase motor including, for example, a u-phase terminal 50u, a v-phase terminal 50v, and a w-phase terminal 50w. The inverter INV1 may include multiple semiconductor elements 100a to 100f corresponding to the number of channels.

[0013] The semiconductor element 100a is arranged between a wiring VBUS to which a power supply voltage is applied and a terminal 50u. The semiconductor element 100b is arranged between the wiring VBUS and a terminal 50v. The semiconductor element 100c is arranged between the wiring VBUS and a terminal 50w. On the other hand, the semiconductor element 100d is arranged between a wiring GND to which a ground power supply voltage is applied and the terminal 50u. The semiconductor element 100e is arranged between the wiring GND and the terminal 50v. The semiconductor element 100f is arranged between the wiring GND and the terminal 50w.

[0014] The plurality of semiconductor elements 100a to 100f are collectively referred to as semiconductor element 100. The semiconductor element 100 includes an IGBT 10 and an FRD 20. In the semiconductor element 100, a collector terminal 11 of the IGBT 10 is connected to a cathode terminal 21 of the FRD 20. An emitter terminal 12 of the IGBT 110 is connected to an anode terminal 22 of the FRD 120. The semiconductor element 100 includes an FRD 20 that includes silicon (Si). The FRD 20 described below may include Si.

[0015] In the semiconductor elements 100a to 100c, the collector terminal 11 of the IGBT 10 and the cathode terminal 21 of the FRD 20 are connected to the wiring VBUS. In the semiconductor elements 100a to 100c, the emitter terminal 12 of the IGBT 10 and the anode terminal 22 of the FRD 20 are connected to the terminals 50u to 50w, respectively. In the semiconductor elements 100d to 100f, the collector terminal 11 of the IGBT 10 and the cathode terminal 21 of the FRD 20 are connected to the terminals 50u to 50w, respectively. In the semiconductor elements 100d to 100f, the emitter terminal 12 of the IGBT 10 and the anode terminal 22 of the FRD 20 are connected to the wiring GND.

[0016] The gate terminal 13 of the IGBT 10 is connected to, for example, a gate driver. The semiconductor device 100 may include a diode such as a free wheeling diode (FWD) instead of the FRD 20.

[0017] <Comparative Example 2> Comparative Example 2 is an example in which the inverter includes a MOSFET. The MOSFET may be formed using silicon carbide (SiC). FIG. 2 is a circuit diagram illustrating an inverter INV2 in a semiconductor device 102 according to Comparative Example 2. As shown in FIG. 2, the semiconductor device 102 according to Comparative Example 2 includes an inverter INV2. The inverter INV2 has the same function as the inverter INV1. The inverter INV2 may include a plurality of semiconductor elements 200a to 200f.

[0018] The semiconductor element 200a is arranged between the wiring VBUS and the terminal 50u. The semiconductor element 200b is arranged between the wiring VBUS and the terminal 50v. The semiconductor element 200c is arranged between the wiring VBUS and the terminal 50w. On the other hand, the semiconductor element 200d is arranged between the wiring GND and the terminal 50u. The semiconductor element 200e is arranged between the wiring GND and the terminal 50v. The semiconductor element 200f is arranged between the wiring GND and the terminal 50w.

[0019] The plurality of semiconductor elements 200a to 200f are collectively referred to as semiconductor elements 200. The semiconductor elements 200 include, for example, MOSFETs 30 containing SiC. The MOSFETs 30 described below may contain SiC.

[0020] The drain terminals 31 of the MOSFETs 30 in the semiconductor elements 200a to 200c are connected to the wiring VBUS. The source terminals 32 of the MOSFETs 30 in the semiconductor elements 200a to 200c are connected to the terminals 50u to 50w, respectively. The drain terminals 31 of the MOSFETs 30 in the semiconductor elements 200d to 200f are connected to the terminals 50u to 50w, respectively. The source terminals 32 of the MOSFETs 30 in the semiconductor elements 200d to 200f are connected to the wiring GND.

[0021] A gate terminal 33 of the MOSFET 30 is connected to, for example, a gate driver. In the semiconductor element 200, an impurity region formed in the MOSFET 30 functions as a diode, i.e., an FWD. That is, in the semiconductor device 102, the body diode of the MOSFET 30 is an FWD.

[0022] <Comparative Example 3> Comparative Example 3 is an example in which the inverter includes a MOSFET and an SBD (Schottky Barrier Diode). The SBD may be configured as an external device. FIG. 3 is a circuit diagram illustrating an inverter INV3 in a semiconductor device 103 according to Comparative Example 3. As shown in FIG. 3, the semiconductor device 103 according to Comparative Example 3 includes an inverter INV3. The inverter INV3 has the same function as the inverter INV1. The inverter INV3 may include a plurality of semiconductor elements 300a to 300f.

[0023] The semiconductor element 300a is arranged between the wiring VBUS and the terminal 50u. The semiconductor element 300b is arranged between the wiring VBUS and the terminal 50v. The semiconductor element 300c is arranged between the wiring VBUS and the terminal 50w. On the other hand, the semiconductor element 300d is arranged between the wiring GND and the terminal 50u. The semiconductor element 300e is arranged between the wiring GND and the terminal 50v. The semiconductor element 300f is arranged between the wiring GND and the terminal 50w.

[0024] The plurality of semiconductor elements 300a to 300f are collectively referred to as semiconductor element 300. The semiconductor element 300 may include a MOSFET 30 and an SBD 40. In the semiconductor element 300, a drain terminal 31 of the MOSFET 30 is connected to a cathode terminal 41 of the SBD 40. A source terminal 32 of the MOSFET 30 is connected to an anode terminal 42 of the SBD 40.

[0025] In the semiconductor elements 300a to 300c, the drain terminal 31 of the MOSFET 30 and the cathode terminal 41 of the SBD 40 are connected to the wiring VBUS. In the semiconductor elements 300a to 300c, the source terminal 32 of the MOSFET 30 and the anode terminal 42 of the SBD 40 are connected to the terminals 50u to 50w, respectively. In the semiconductor elements 300d to 300f, the drain terminal 31 of the MOSFET 30 and the cathode terminal 41 of the SBD 40 are connected to the terminals 50u to 50w, respectively. In the semiconductor elements 300d to 300f, the source terminal 32 of the MOSFET 30 and the anode terminal 42 of the SBD 40 are connected to the wiring GND.

[0026] The gate terminal 33 of the MOSFET 30 is connected to, for example, a gate driver.

[0027] <New problem discovered by the inventor> 4 is a graph illustrating the conduction loss of the inverters INV1 to INV3 in the semiconductor devices 101 to 103 according to the comparative examples 1 to 3. The horizontal axis represents the voltage V between the collector terminal 11 and the emitter terminal 12 of the IGBT 10. CE or the voltage V between the drain terminal 31 and the source terminal 32 of the MOSFET 30 DS The vertical axis represents the current I between the collector terminal 11 and the emitter terminal 12 of the IGBT 10. CE or the current I between the drain terminal 31 and the source terminal 32 in the MOSFET 30 DS Shows.

[0028] As shown in Figure 4, the conduction loss of the IGBT 10 is represented by the magnitude indicated by y in the figure. The IGBT 10 operates at a constant voltage V CE This is inevitably caused by the structure of the IGBT 10. Specifically, the conduction loss LossIGBT of the IGBT 10 is expressed by the following formula (1). The conduction loss LossIGBT of the IGBT 10 is CE Losses related to this will occur.

[0029] LossIGBT=VCE ×I CE (1)

[0030] On the other hand, the conduction loss of the MOSFET 30 is represented by the magnitude shown by x in the figure. The conduction loss of the MOSFET 30, LossMOSFET, is expressed by the following equation (2). The conduction loss of the MOSFET 30 at low load, LossMOSFET, is smaller than the conduction loss of the IGBT 10, LossIGBT. Here, Ron includes the on-resistance.

[0031] LossMOSFET=I DS ×I DS ×Ron (2)

[0032] FIG. 5 is a graph illustrating the tail current at turn-off in the semiconductor device 101 according to Comparative Example 1, where the horizontal axis represents time and the vertical axis represents the current I CE or voltage V CE As shown in FIG. 5, in the case of the IGBT 10, a tail current occurs when the IGBT 10 is turned off. Therefore, the switching loss when the IGBT 10 is turned off is larger than that of the MOSFET 30. This is an inevitable result of the structure of the IGBT 10.

[0033] FIG. 6 is a graph illustrating the current at the time of turn-off in the semiconductor device 102 according to Comparative Example 2, where the horizontal axis represents time and the vertical axis represents the current I DS or voltage V DS 6, in the case of the MOSFET 30, no tail current occurs when the MOSFET 30 is turned off, or if any, it is only a small amount. Therefore, the switching loss of the MOSFET 30 when the MOSFET 30 is turned off is smaller than that of the IGBT 10.

[0034] 7 is a graph illustrating the reverse recovery current of the FRD 20 in the semiconductor device 101 according to Comparative Example 1, where the horizontal axis represents time and the vertical axis represents the current I F flowing through the FRD 20. As shown in FIG. 7, for example, the FRD 20 containing silicon (Si) has large ringing of the reverse recovery current, resulting in large switching loss.

[0035] 8 is a graph illustrating the reverse recovery current of the SBD 40 in the semiconductor device 103 according to Comparative Example 3, where the horizontal axis represents time and the vertical axis represents the current I F flowing through the SBD 40. As shown in FIG. 8, the SBD 40 has small ringing in the reverse recovery current, and therefore small switching loss.

[0036] Based on the characteristics of the IGBT 10 and FRD 20 described above, the inverter INV1 including the IGBT 10 and FRD 20 of Comparative Example 1 is characterized by low inverter efficiency in the actual vehicle load range (e.g., light load conditions = 30 kW, 50 N m, etc.) such as in the WLTC (Worldwide-harmonized Light vehicles Test Cycle) mode. This reduces the actual driving distance, and a large-capacity battery is required to ensure the driving distance on a single charge.

[0037] In contrast, the conduction loss of the inverters INV2 and INV3 using the MOSFET 30 of Comparative Examples 2 and 3 is given by the above-mentioned formula (2). Therefore, the conduction loss of the inverters INV2 and INV3 in the low load region is small. Therefore, the inverters INV2 and INV3 can achieve high efficiency in the actual vehicle load region such as the WLTC mode. This increases the actual driving distance, and a long driving distance can be ensured with a smaller battery capacity.

[0038] On the other hand, in the high load range, conduction loss increases with the square of the load current. For this reason, the efficiency of inverters INV2 and INV3 decreases in the high load range. Furthermore, the cost of bare dies containing SiC is high. Therefore, when outputting sufficient acceleration performance (150 kW, 400 N·m, etc.) as a traction motor, configuring it solely with MOSFETs 30 containing SiC results in extremely high costs and poor cost performance. While high output such as 150 kW is not necessary for driving in WLTC mode, sufficient acceleration performance is also required to improve the drivability of the vehicle.

[0039] Toward achieving carbon neutrality, there is a demand for traction motor systems that offer higher efficiency. Achieving higher efficiency will increase the driving distance per charge and improve the convenience of xEVs, especially EVs (Electric Vehicles) and PHEVs (Plug-in Hybrid Electric Vehicles). Furthermore, to improve inverter efficiency, semiconductor elements made of low-loss IGBT10 and SiC are increasingly being adopted. However, inverters made of IGBT10 have high losses in the low-load range and are not highly efficient in the actual vehicle operating range, such as the WLTC mode.

[0040] On the other hand, inverters configured with MOSFETs 30 containing SiC are characterized by small losses in the low load range but large losses in the high load range. Therefore, expectations are rising for hybrid power modules that use both IGBTs 10 and MOSFETs 30. The hybrid method eliminates the disadvantages of both the IGBTs 10 and MOSFETs 30 by driving the MOSFETs 30 at low loads and the IGBTs 10 at high loads. Furthermore, the hybrid method can reduce the amount of MOSFET 30 chips used, including SiC, relative to the inverter and motor output expected in a vehicle. For this reason, the hybrid method enables cost reduction.

[0041] This disclosure proposes a method for reducing switching loss by soft switching in a hybrid power module using an IGBT 10 and a MOSFET 30. Note that soft switching is called ZVS (Zero Voltage Switching).

[0042] <Embodiment 1> This embodiment is an example of a hybrid system in which the inverter includes both the IGBT 10 and the MOSFET 30. FIG. 9 is a circuit diagram illustrating an inverter INV4 in the semiconductor device 1 according to the first embodiment. As shown in FIG. 9, the semiconductor device 1 according to the first embodiment includes an inverter INV4. The inverter INV4 has the same function as the inverter INV1. The inverter INV4 includes a plurality of semiconductor elements 400a to 400f.

[0043] The semiconductor element 400a is arranged between the wiring VBUS and the terminal 50u. The semiconductor element 400b is arranged between the wiring VBUS and the terminal 50v. The semiconductor element 400c is arranged between the wiring VBUS and the terminal 50w. On the other hand, the semiconductor element 400d is arranged between the wiring GND and the terminal 50u. The semiconductor element 400e is arranged between the wiring GND and the terminal 50v. The semiconductor element 400f is arranged between the wiring GND and the terminal 50w.

[0044] The plurality of semiconductor elements 400a to 400f are collectively referred to as semiconductor element 400. The semiconductor element 400 includes an IGBT 10, an FRD 20, and a MOSFET 30. In the semiconductor element 400, the collector terminal 11 of the IGBT 10 is connected to the cathode terminal 21 of the FRD 20 and the drain terminal 31 of the MOSFET 30. The emitter terminal 12 of the IGBT 10 is connected to the anode terminal 22 of the FRD 120 and the source terminal 32 of the MOSFET 30. In this manner, the semiconductor element 400 connects the collector of the IGBT 10, the drain of the MOSFET 30, and the cathode of the diode, and connects the emitter of the IGBT 10, the source of the MOSFET 30, and the anode of the diode. The semiconductor element 400 may also be simply referred to as an element.

[0045] In the semiconductor elements 400a to 400c, the collector terminal 11 of the IGBT 10, the cathode terminal 21 of the FRD 20, and the drain terminal 31 of the MOSFET 30 are connected to the wiring VBUS. In the semiconductor elements 400a to 400c, the emitter terminal 12 of the IGBT 10, the anode terminal 22 of the FRD 20, and the source terminal 32 of the MOSFET 30 are connected to the terminals 50u to 50w, respectively. In the semiconductor elements 400d to 400f, the collector terminal 11 of the IGBT 10, the cathode terminal 21 of the FRD 20, and the drain terminal 31 of the MOSFET 30 are connected to the terminals 50u to 50w, respectively. In the semiconductor elements 400d to 400f, the emitter terminal 12 of the IGBT 10, the anode terminal 22 of the FRD 20, and the source terminal 32 of the MOSFET 30 are connected to the wiring GND.

[0046] The gate terminal 13 of the IGBT 10 is connected to, for example, a gate driver. The gate terminal 33 of the MOSFET 30 is similarly connected to the gate driver. The semiconductor device 400 may include an FWD instead of the FRD 20.

[0047] 10 is a graph illustrating the conduction loss of the inverter INV4 in the semiconductor device 1 according to the first embodiment. The horizontal axis represents the voltage V between the collector terminal 11 and the emitter terminal 12 of the IGBT 10. CE or the voltage V between the drain terminal 31 and the source terminal 32 of the MOSFET 30 DS The vertical axis represents the current I between the collector terminal 11 and the emitter terminal 12 of the IGBT 10. CE or the current I between the drain terminal 31 and the source terminal 32 in the MOSFET 30 DS 10, the conduction loss of the hybrid inverter INV4 is smaller than that of the MOSFET 30 in the low load range, and smaller than that of the IGBT 10 in the high load range.

[0048] As described above, in the semiconductor device 1 of this embodiment, the inverter INV4 includes the IGBT 10 and the MOSFET 30 connected in parallel. The inverter INV4 passes current through the MOSFET 30 under low load conditions and through the IGBT 10 under high load conditions. As a result, the conduction loss of the inverter INV4 has intermediate characteristics between those of the inverter INV1 of Comparative Example 1, the inverter INV2 of Comparative Example 2, and the inverter INV3 of Comparative Example 3. Therefore, the inverter INV4 of this embodiment can achieve high efficiency from low load conditions to high load conditions. Furthermore, the inverter INV4 of this embodiment can reduce the amount of MOSFET 30 containing expensive SiC, thereby achieving cost reductions for the power module.

[0049] Next, a method for driving the hybrid inverter INV4 will be described. The methods for driving the hybrid inverter INV4 include exclusive control, individual control, and simultaneous control. The outline of each control will be explained below in (i) Overview of exclusive control, (ii) Overview of individual control, and (iii) Overview of simultaneous control.

[0050] (i) Overview of exclusive control 11 is a circuit diagram illustrating an outline of exclusive control of the inverter INV4 in the semiconductor device 1a according to the first embodiment. As shown in FIG. 11, the semiconductor device 1a includes an inverter INV4 including a plurality of semiconductor elements 400 and a control unit 500. Note that FIG. 11 shows one semiconductor element 400. In this embodiment, the semiconductor devices 1 that perform exclusive control are collectively referred to as the semiconductor device 1a. The control unit 500 includes a GDU (Gate Driver Unit) 60 and an MCU (Microcontroller Unit) 70.

[0051] The GDU 60 functions as a gate driver and has terminals 61a, 61b, 62a, and 62b. The terminals 61a and 61b are connected to a terminal 71 of the MCU 70 via a switch 79. The terminal 62a is connected to a gate terminal 13 of the IGBT 10. The terminal 62b is connected to a gate terminal 33 of the MOSFET 30. A signal PWM1 input to the terminal 61a is output from the terminal 62a to the gate terminal 13 of the IGBT 10 after being level-shifted. A signal PWM1 input to the terminal 61b is output from the terminal 62b to the gate terminal 33 of the MOSFET 30 after being level-shifted. The signal PWM1 includes, for example, a pulse signal such as PWM (Pulse Width Modulation).

[0052] The MCU 70 has one terminal 71. The MCU 70 has a switch 79 that switches the terminal 71 to either the terminal 61a or the terminal 61b. The MCU 70 outputs a signal PWM1 to the GDU 60 via the terminal 71, which turns on the gate of the IGBT 10 or the gate of the MOSFET 30. The MCU 70 outputs the signal PWM1 to the terminal 61a or the terminal 61b by switching the switch 79.

[0053] The MCU 70 outputs a signal PWM1 to the terminal 61a to turn on the gate of the IGBT 10. The MCU 70 also outputs a signal PWM1 to the terminal 61b to turn on the gate of the MOSFET 30. In this way, the exclusive control switches one signal PWM1 between the gate of the IGBT 10 and the gate of the MOSFET 30.

[0054] For exclusive control, a single-channel drive circuit may be provided in the MCU 70. The MCU 70 can then exclusively control the IGBT 10 and the MOSFET 30 by switching the switch 79. In the low-load region, the gate of the MOSFET 30 is turned on to drive the MOSFET 30. In the high-load region, the gate of the IGBT 10 is turned on to drive the IGBT 10. However, this exclusive control method does not allow the IGBT 10 and the MOSFET 30 to be driven simultaneously. Therefore, the maximum output of the exclusive control is not the sum of the outputs of the IGBT 10 and the MOSFET 30. For example, even if the output of the MOSFET 30 is configured to be 50 kW and the output of the IGBT 10 is configured to be 100 kW, the maximum output is still 100 kW. Therefore, to achieve an output of 150 kW, the number of IGBTs 10 or MOSFETs 30 must be increased, which increases costs.

[0055] (ii) Overview of individual control 12 is a circuit diagram illustrating an outline of individual control of the inverter INV4 in the semiconductor device 1b according to the first embodiment. As shown in FIG. 12, the semiconductor device 1b includes an inverter INV4 including a plurality of semiconductor elements 400 and a control unit 500. In this embodiment, the semiconductor devices 1 that perform individual control are collectively referred to as semiconductor device 1b. In the case of individual control, the MCU 70 has two terminals, 71a and 71b. The terminal 71a is connected to the terminal 61a, and the terminal 71b is connected to the terminal 61b.

[0056] The MCU 70 outputs a signal PWM1 to the GDU 60 via terminals 71a and 61a, which turns on or off the gate of the IGBT 10. The MCU 70 outputs a signal PWM2 to the GDU 60 via terminals 71b and 61b, which turns on or off the gate of the MOSFET 30. The MCU 70 turns on or off the gate of the IGBT 10 by outputting the signal PWM1 to the terminal 61a. The MCU 70 also turns on or off the gate of the MOSFET 30 by outputting the signal PWM2 to the terminal 61b. In this way, individual control switches between the individual signals PWM1 and PWM2 for the IGBT 10 and the MOSFET 30. The signal PWM2 includes, for example, a pulse signal such as PWM (Pulse Width Modulation).

[0057] Individual control can be achieved by providing the MCU 70 with a two-channel drive circuit. This allows the MCU 70 to individually control the IGBT 10 and the MOSFET 30 by appropriately outputting signals PWM1 and PWM2. In the low-load region, the gate of the MOSFET 30 is turned on to drive the MOSFET 30. In the high-load region, the gate of the IGBT 10 is turned on to drive the IGBT 10. In the high-load region, the gate of the MOSFET 30 can be turned on to drive the MOSFET 30 in addition to the IGBT 10. Therefore, the maximum output of individual control is the sum of the outputs of the IGBT 10 and the MOSFET 30. For example, if the output of the MOSFET 30 is configured to be 50 kW and the output of the IGBT 10 is configured to be 50 kW, the maximum output is 100 kW. The disadvantage is that the control by the MCU 70 becomes more complex, requiring a high-performance microcontroller as the MCU 70.

[0058] (iii) Overview of simultaneous control FIG. 13 is a circuit diagram illustrating an outline of simultaneous control of inverters INV4 in a semiconductor device 1c according to the first embodiment. As shown in FIG. 13, the semiconductor device 1c includes an inverter INV4 including multiple semiconductor elements 400 and a control unit 500. In this embodiment, semiconductor devices 1 that perform simultaneous control are collectively referred to as semiconductor device 1c. In the case of simultaneous control, the GDU 60 has terminals 61, 62a, and 62b. The terminal 61 is connected to a terminal 71 of the MCU 70. The terminal 62a is connected to the gate terminal 13 of the IGBT 10. The terminal 62b is connected to the gate terminal 33 of the MOSFET 30. The signal PWM1 input to the terminal 61 branches within the GDU 60. One of the branched signals PWM1 is output from the terminal 62a to the gate terminal 13 of the IGBT 10 via a level shifter. The other branched signal PWM1 is output from the terminal 62b to the gate terminal 33 of the MOSFET 30 via a level shifter.

[0059] The MCU 70 has one terminal 71. The terminal 71 is connected to the terminal 61. The MCU 70 outputs a signal PWM1 to the GDU 60 via the terminals 71 and 61 to turn on or off the gate of the IGBT 10, and also outputs a signal PWM1 to the GDU 60 via the terminals 71 and 61 to turn on or off the gate of the MOSFET 30. The MCU 70 turns on or off the gate of the IGBT 10 by outputting the signal PWM1 to the terminal 61, and turns on or off the gate of the MOSFET 30 by outputting the signal PWM1 to the terminal 61. In this way, simultaneous control turns on or off the IGBT 10 and MOSFET 30 simultaneously with the same signal PWM1.

[0060] Simultaneous control can be achieved by providing a one-channel drive circuit in the MCU 70. This allows the MCU 70 to simultaneously control the IGBT 10 and the MOSFET 30 to be turned on or off by outputting the signal PWM1. CE The voltage V of the MOSFET 30 is DSIn the region where the voltage drop of the component is small, the current flows predominantly to the MOSFET 30 side. On the other hand, in the high load region, the voltage V DS The voltage drop of the component is the voltage V of IGBT10 CE If the component exceeds this, the current automatically becomes dominant in the IGBT 10. Because MOSFET 30 and IGBT 10 can be controlled simultaneously, the maximum output of simultaneous control is the sum of the outputs of IGBT 10 and MOSFET 30. For example, if the MOSFET 30 and IGBT 10 are configured to output 50 kW and 50 kW, respectively, the maximum output is 100 kW. A disadvantage is that the turn-on and turn-off timing must be adjusted using an external circuit such as the GDU 60. Furthermore, because the output of the PWM1 signal from the MCU 70 is common to both the IGBT 10 and MOSFET 30, switching losses on the IGBT 10 side can increase when operating at a high carrier frequency (e.g., 20 kHz), a characteristic of SiC.

[0061] FIG. 14 is a block diagram illustrating a control unit 500 in the semiconductor device 1 according to the first embodiment. As shown in FIG. 14, the control unit 500 includes an MCU 70 and a GDU 60. The control unit 500 controls the gate of the IGBT 10 and the gate of the MOSFET 30. The control unit 500 outputs a first ON signal that turns on the gate of the IGBT 10 in the semiconductor element 400, and outputs a second ON signal that turns on the gate of the MOSFET 30. The control unit 500 also outputs a first OFF signal that turns off the gate of the IGBT 10 in the semiconductor element 400, and outputs a second OFF signal that turns off the gate of the MOSFET 30. In this embodiment, the gate of the IGBT 10 may be referred to as a first gate, and the gate of the MOSFET 30 may be referred to as a second gate.

[0062] FIG. 15 is a block diagram illustrating an MCU 70 in the semiconductor device 1 according to the first embodiment. FIG. 16 is a block diagram illustrating a GDU 60 in the semiconductor device 1 according to the first embodiment. As shown in FIGS. 15 and 16, at least one of the MCU 70 and the GDU 60 may be an information processing device such as a microcomputer. Such an information processing device may further include a processor PRC, a memory MMR, a storage device STR, and a user interface UI. The storage device STR stores programs that represent processes to be executed by each component of the information processing device. The processor PRC also loads the programs from the storage device STR into the memory MMR and executes the programs. In this way, the processor PRC realizes the functions of each component of the information processing device. The user interface UI may include input devices such as a keyboard and a mouse, and output devices such as a display, a printer, and a speaker.

[0063] Each component of the information processing device may be realized by dedicated hardware. Furthermore, some or all of the components may be realized by general-purpose or dedicated circuits, processor PRCs, etc., or a combination of these. These may be configured by a single chip, or by multiple chips connected via a bus. Some or all of the components may be realized by a combination of the above-mentioned circuits, etc., and a program. Furthermore, the processor PRC may be a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an FPGA (Field-Programmable Gate Array), a quantum processor (quantum computer control chip), etc.

[0064] Furthermore, when some or all of the components of an information processing device are realized by multiple information processing devices, circuits, etc., the multiple information processing devices, circuits, etc. may be centrally or decentralized.

[0065] In the following, the timings of turning on and off the IGBT 10 and the MOSFET 30 are adjusted using individual control and simultaneous control in the semiconductor device 1 including the hybrid inverter INV4. This allows ZVS to be performed when turning on and off the IGBT 10, which has a relatively large switching loss. In other words, the control unit 500 controls the gate of the IGBT 10 while keeping the gate of the MOSFET 30 on.

[0066] The operation of the control unit 500 will be described below in the following cases (I) when the device is turned on and (II) when the device is turned off.

[0067] (I) At turn-on The control unit 500 first turns on the MOSFET 30 and controls the voltage V of the MOSFET 30 using the individual control and the simultaneous control. DS (and the voltage V of IGBT10 CE ) has decreased, the control unit 500 turns on the IGBT 10. Specifically, when the control unit 500 turns on the gate (first gate) of the IGBT 10 and the gate (second gate) of the MOSFET 30, the control unit 500 outputs a second on signal to turn on the second gate, thereby decreasing the voltage V between the drain and the source. DC After the voltage V drops, the control unit 500 outputs a first ON signal to turn on the first gate. DC becomes 0, the first gate is turned on by outputting a first on signal.

[0068] In this way, ZVS is performed to reduce switching loss. Note that the control unit 500 controls the voltage V between the collector and the emitter. CE After the voltage V has decreased, the control unit 500 may output a first ON signal to turn on the first gate. CE After becomes 0, the first gate may be turned on by outputting a first on signal.

[0069] 17 is a flowchart illustrating a control method of the control unit 500 in the semiconductor device 1 according to the first embodiment. As shown in FIG. 17, the control method of the semiconductor device 1 includes steps S11 to turn on the second gate when turning on the gate (first gate) of the IGBT 10 and the gate (second gate) of the MOSFET 30, and S21 to turn on the voltage V of the MOSFET 30. DS and step S12 of turning on the first gate after the voltage drops.

[0070] FIG. 18 shows the gate voltage V of the IGBT 10 in the semiconductor device 1 according to the first embodiment. G1 , voltage V CE and current I CE , and the gate voltage V of the MOSFET 30 G2 , voltage V DS and current I DS 18 is a graph illustrating an example of a change in the voltage and current, where the horizontal axis represents time and the vertical axis represents each voltage and each current. As shown in FIG. 18, when the gate of the MOSFET 30 and the gate of the IGBT 10 are turned on, at time t1, the control unit 500 outputs a second on signal that turns on the gate of the MOSFET 30, thereby first turning on the gate of the MOSFET 30. Then, the current I flowing through the MOSFET 30 DS This increases the voltage V of the MOSFET 30. DS Also, the voltage V of IGBT10 CE For example, the voltage V of the MOSFET 30 DS At time t2 when the voltage Vcc reaches 0V, the control unit 500 outputs a first ON signal to turn on the gate of the IGBT 10, thereby turning on the gate of the IGBT 10. Then, the current I CE At time t3, a predetermined current I CE is playing.

[0071] IGBT10 turns on when the voltage V DS (and voltage V CE ) is low (for example, 0 V), the switching loss of the IGBT 10 can be suppressed.

[0072] (II) At turn-off The control unit 500 performs ZVS by first turning off the IGBT 10. Specifically, when turning off the gate (first gate) of the IGBT 10 and the gate (second gate) of the MOSFET 30, the control unit 500 outputs a first off signal to turn off the first gate, and then outputs a second off signal to turn off the second gate. This allows the semiconductor device 1 to improve the switching loss of the IGBT 10 and increase the efficiency of the inverter. In particular, in simultaneous control, even when the carrier frequency is set high to drive the MOSFET 30 including SiC, the switching loss on the IGBT 10 side can be suppressed.

[0073] When turning off, the gate of the IGBT 10 is turned off first while the gate of the MOSFET 30 is turned on. Since the gate of the MOSFET 30 is in the on state, the voltage V DS (and voltage V CE ) has dropped, the gate of the IGBT 10 can be turned off. This allows ZVS to be performed. The IGBT 10 inherently has a tail current, but when the voltage V CE Since the power supply can be turned off at a low voltage, switching loss can be reduced.

[0074] 19 is a flowchart illustrating a control method of the control unit 500 in the semiconductor device 1 according to embodiment 1. As shown in Fig. 19, the control method of the semiconductor device 1 includes step S21 of turning off the gate of the IGBT 10 while keeping the gate of the MOSFET 30 on, and step S22 of turning off the gate of the MOSFET 30 after the gate of the IGBT 10 is turned off.

[0075] FIG. 20 shows the gate voltage V of the IGBT 10 in the semiconductor device 1 according to the first embodiment. G1 , voltage V CE and current I CE , and the gate voltage V of the MOSFET 30 G2 , voltage V DSand current I DS 20 is a graph illustrating an example of a change in the voltage and current, where the horizontal axis represents time and the vertical axis represents each voltage and each current. As shown in FIG. 20, when turning off the gate of MOSFET 30 and the gate of IGBT 10, at time t4, the control unit 500 outputs a first off signal that turns off the gate of IGBT 10 while keeping the gate of MOSFET 30 on. As a result, the control unit 500 turns off the gate of IGBT 10 first. Thereafter, the current I flowing through the IGBT 10 CE After turning off the gate of the IGBT 10, the control unit 500 outputs a second off signal that turns off the gate of the MOSFET 30. This turns off the gate of the MOSFET 30.

[0076] IGBT10 turns off when the voltage V CE is lower than a predetermined value (for example, 0 V), the switching loss due to the tail current of the IGBT 10 can be suppressed by ZVS.

[0077] In the following "Semiconductor device performing individual control" and "Semiconductor device performing simultaneous control", examples of the semiconductor device 1b and the semiconductor device 1c will be described.

[0078] <Semiconductor device with individual control> 21 is a circuit diagram illustrating a GDU 60 and an MCU 70 that perform individual control in the semiconductor device 1b according to the first embodiment. As shown in FIG. 21, the control unit 500 has the GDU 60 and the MCU 70. The GDU 60 outputs a first ON signal to the gate of the IGBT 10. The GDU 60 also outputs a second ON signal to the gate of the MOSFET 30. The GDU 60 also outputs a first OFF signal to the gate of the IGBT 10. The GDU 60 also outputs a second OFF signal to the gate of the MOSFET 30.

[0079] The MCU 70 outputs a signal PWM1 to the GDU 60, causing the GDU 60 to output a first ON signal. The MCU 70 also outputs a signal PWM2 to the GDU 60, causing the GDU 60 to output a second ON signal. The MCU 70 also outputs a signal PWM1 to the GDU 60, causing the GDU 60 to output a first OFF signal. The MCU 70 also outputs a signal PWM2 to the GDU 60, causing the GDU 60 to output a second OFF signal.

[0080] The signal PWM1 that causes the GDU 60 to output the first ON signal may be called the first pulse signal, and the signal PWM2 that causes the GDU 60 to output the second ON signal may be called the second pulse signal. The signal PWM1 that causes the GDU 60 to output the first OFF signal may be called the third pulse signal, and the signal PWM2 that causes the GDU 60 to output the second OFF signal may be called the fourth pulse signal.

[0081] When the gate of the IGBT 10 and the gate of the MOSFET 30 are controlled separately, the MCU 70 outputs a second pulse signal P to the GDU 60, causing the GDU 60 to output a second ON signal. This turns on the gate of the MOSFET 30. Then, the control unit 500 controls the voltage V of the MOSFET 30. DS After the voltage Vcc drops, the MCU 70 outputs a first pulse signal to the GDU 60, causing the GDU 60 to output a first ON signal. This turns on the gate of the IGBT 10. The MCU 70 also outputs a third pulse signal P to the GDU 60, causing the GDU 60 to output a first OFF signal. This turns off the gate of the IGBT 10. After the gate of the IGBT 10 turns off, the control unit 500 outputs a fourth pulse signal to the GDU 60, causing the GDU 60 to output a second OFF signal. This turns off the gate of the MOSFET 30.

[0082] In addition to terminals 61a, 61b, 62a, and 62b, the GDU 60 also includes transmitters 63a, 63b, isolators 64a, 64b, and receivers 65a and 65b. In the case of individual control, the GDU 60 has two-channel isolators 64a and 64b for driving the IGBT 10 and the MOSFET 30, respectively. In the case of individual control, the MCU 70 adjusts the on-timing and off-timing of the IGBT 10 and the MOSFET 30 by outputting signals PWM1 and PWM2.

[0083] The transmitter 63a is connected to the terminal 61a. The receiver 65a is connected to a level shifter connected to the terminal 62a. The isolator 64a is disposed between the transmitter 63a and the receiver 65a, and indirectly transmits signals between the transmitter 63a and the receiver 65a without being directly connected to each other. For example, the isolator 64a includes a primary-side inductor and a secondary-side inductor. The transmitter 63a transmits a signal PWM1 (first pulse signal) output from the MCU 70 to the isolator 64a. The receiver 65a outputs a first on signal to the gate of the IGBT 10 based on the isolator 64a receiving the signal PWM1 (first pulse signal). The transmitter 63a also transmits a signal PWM1 (third pulse signal) output from the MCU 70 to the isolator 64a. The receiving unit 65a outputs a first off signal to the gate of the IGBT 10 based on the isolator 64a receiving the signal PWM1 (third pulse signal).

[0084] The transmitter 63b is connected to the terminal 61b. The receiver 65b is connected to the level shifter connected to the terminal 62b. The isolator 64b is disposed between the transmitter 63b and the receiver 65b, and indirectly transmits signals between the transmitter 63b and the receiver 65b without being directly connected to each other. The transmitter 63b transmits a signal PWM2 (second pulse signal) output from the MCU 70 to the isolator 64b. The receiver 65b outputs a second ON signal to the gate of the MOSFET 30 based on the isolator 64b receiving the signal PWM2 (second pulse signal). The transmitter 63b also transmits a signal PWM2 (fourth pulse signal) output from the MCU 70 to the isolator 64b. The receiver 65b outputs a second OFF signal to the gate of the MOSFET 30 based on the isolator 64b receiving the signal PWM2 (fourth pulse signal).

[0085] In the semiconductor device 1b, the IGBT 10 and the MOSFET 30 can be controlled individually, and therefore the MCU 70 can output signals to turn on and off the gates of the IGBT 10 and the MOSFET 30 at any timing. In this way, in the case of individual control, the MCU 70 adjusts the on timing and off timing of the IGBT 10 and the MOSFET 30.

[0086] Fig. 22 is a circuit diagram illustrating a GDU 60 and an MCU 70 that perform individual control in a semiconductor device 1b according to a modification of embodiment 1. As shown in Fig. 22, the GDU 60 of the modification includes a terminal 61a, a terminal 61b, a terminal 62a, and a terminal 62b, as well as a transmitter 63, an isolator 64, a receiver 65, and a state machine 66. The MCU 70 includes a terminal 71a and a terminal 71b.

[0087] Terminals 71a and 71b of the MCU 70 are connected to a state machine 66 via terminals 61a and 61b of the GDU 60, respectively. The state machine 66 is connected to a transmitter 63. A receiver 65 is connected to a level shifter connected to a terminal 62a and a level shifter connected to a terminal 62b. An isolator 64 is disposed between the transmitter 63 and receiver 65, and transmits signals indirectly without being directly connected to the transmitter 63 and receiver 65.

[0088] The state machine 66 transmits a 2-bit status signal indicating the following three states to the transmitter 63 based on the signals PWM1 and PWM2 received from the MCU 70. The transmitter 63 outputs the status signal to the isolator 64. The receiver 65 outputs signals to the terminals 62a and 62b based on the status signal received by the isolator 64.

[0089] 00 (third state): IGBT 10 gate off, MOSFET 30 gate off 01 (second state): Gate of IGBT 10 is off, and gate of MOSFET 30 is on 11 (first state): Gate of IGBT 10 is on, and gate of MOSFET 30 is on

[0090] The state machine 66 outputs a first state signal that outputs a first on signal and a second on signal, a second state signal that outputs a first off signal and a second on signal, and a third state signal that outputs a first off signal and a second off signal, based on the signal PWM1 (first pulse signal and third pulse signal) and the signal PWM2 (second pulse signal and fourth pulse signal).

[0091] The transmitter 63 transmits the first state signal, the second state signal, and the third state signal output from the state machine 66 to the isolator 64. The receiver 65 outputs a first on signal, a first off signal, a second on signal, and a second off signal based on the isolator 64 receiving the first state signal, the second state signal, and the third state signal.

[0092] For example, when the state machine 66 outputs the second state signal and then outputs the first state signal, the receiving unit 65 outputs the second ON signal based on the isolator 64 receiving the second state signal and the first state signal, and the voltage V of the MOSFET 30 is DS When the second state signal is output from the state machine 66 and then the third state signal is output, the receiving unit 65 outputs the first off signal and then the second off signal based on the isolator 64 receiving the second state signal and the third state signal.

[0093] <Semiconductor device with simultaneous control> 23 is a circuit diagram illustrating a GDU 60 and an MCU 70 performing simultaneous control in the semiconductor device 1c according to the first embodiment. As shown in FIG. 23, the GDU 60 includes a terminal 61, a terminal 62a, and a terminal 62b, as well as a transmitter 63, an isolator 64, a receiver 65, and a state machine 66. When performing simultaneous control, the MCU 70 outputs a signal PWM1 (sometimes referred to as a fifth pulse signal) to the GDU 60, causing the GDU 60 to output at least one of a first ON signal that turns on the gate of the IGBT 10 and a second ON signal that turns on the gate of the MOSFET 30. The MCU 70 also outputs a signal PWM1 (sometimes referred to as a sixth pulse signal) to the GDU 60, causing the GDU 60 to output at least one of a first OFF signal that turns off the gate of the IGBT 10 and a second OFF signal that turns off the gate of the MOSFET 30.

[0094] When the gate of the IGBT 10 and the gate of the MOSFET 30 are controlled simultaneously, the MCU 70 drives the GDU 60 by outputting a fifth pulse signal to the GDU. This causes the GDU 60 to output a second ON signal, and the voltage V of the MOSFET 30 DS After the voltage Vcc drops, the MCU 70 outputs the first ON signal. The MCU 70 also drives the GDU 60 by outputting a sixth pulse signal to the GDU. As a result, the GDU 60 outputs the first OFF signal and then the second OFF signal.

[0095] The transmitter 63 is connected to the terminal 61, and the receiver 65 is connected to the state machine 66. The isolator 64 is disposed between the transmitter 63 and the receiver 65. The transmitter 63 transmits a fifth pulse signal output from the MCU 70 to the isolator 64. The receiver 65 outputs a first control signal to the state machine 66 based on the isolator 64 receiving the fifth pulse signal. The first control signal causes the state machine 66 to output a second on signal, thereby increasing the voltage V of the MOSFET 30. DS Therefore, the state machine 66 outputs the second ON signal upon receiving the first control signal from the receiving unit 65, and outputs the first ON signal after the voltage VDS of the MOSFET 30 has dropped. This causes the control unit 500 to turn on the gate of the MOSFET 30 and DS After the voltage drops, the gate of IGBT 10 is turned on.

[0096] The transmitter 63 transmits the sixth pulse signal output from the MCU 70 to the isolator 64. The receiver 65 outputs a second control signal to the state machine 66 based on the isolator 64 receiving the sixth pulse signal. The second control signal causes the state machine 66 to output a first off signal and then a second off signal. Therefore, upon receiving the second control signal from the receiver 65, the state machine 66 outputs the first off signal and then outputs the second off signal. As a result, the control unit 500 turns off the gate of the IGBT 10 and then turns off the gate of the MOSFET 30. In this way, in the case of simultaneous control, the GDU 60 adjusts the on-timing and off-timing of the IGBT 10 and the MOSFET 30.

[0097] 24 is a circuit diagram illustrating a GDU 60 and an MCU 70 that perform simultaneous control in a semiconductor device 1c according to Modification 1 of Embodiment 1. As shown in Fig. 24, the GDU 60 of Modification 1 includes a terminal 61, a terminal 62a, and a terminal 62b, as well as a transmitter 63, an isolator 64, a receiver 65, a state machine 66, a register 67, a terminal 61c, a transmitter 63c, an isolator 64c, and a receiver 65c.

[0098] The MCU 70 includes a terminal 71c in addition to the terminal 71. The MCU 70 outputs a signal (sometimes referred to as a seventh pulse signal) indicating the timing to turn on the gates of the IGBT 10 and the MOSFET 30 to the serial terminal 71c, such as an SPI (Serial Peripheral Interface) or an I2C (Inter-Integrated Circuit). The MCU 70 also outputs a signal (sometimes referred to as an eighth pulse signal) indicating the timing to turn off the gates of the IGBT 10 and the MOSFET 30 to the terminal 71c. The terminal 71c is connected to the terminal 61c.

[0099] The configurations of the transmitter 63, the isolator 64, the receiver 65, and the state machine 66 are the same as those of the semiconductor device 1c described above. However, the state machine 66 of the first modification uses the register 67 to adjust the timing of outputting the first ON signal and the second ON signal when the first control signal is received. Furthermore, the state machine 66 of the first modification uses the register 67 to adjust the timing of outputting the first OFF signal and the second OFF signal when the second control signal is received.

[0100] The transmitter 63c is connected to the terminal 61c, and the receiver 65c is connected to the resistor 67. The isolator 64c is disposed between the transmitter 63c and the receiver 65c. In this manner, in addition to the one-channel isolator 64 for controlling the gates of the IGBT 10 and the MOSFET 30, the modified example includes the isolator 64c for turn-on and turn-off settings.

[0101] The transmitter 63c transmits the seventh pulse signal output from the MCU 70 to the isolator 64c. The receiver 65c outputs a first adjustment signal based on the isolator 64c receiving the seventh pulse signal. The first adjustment signal is a signal that causes the register 67 to adjust the timing at which the state machine 66 outputs the first ON signal and the second ON signal when the state machine 66 receives the first control signal. Therefore, upon receiving the first adjustment signal, the register 67 adjusts the timing at which the state machine 66 outputs the second ON signal and the voltage V of the MOSFET 30. DS After the voltage drops, the timing for outputting the first ON signal is adjusted.

[0102] Furthermore, the transmitter 63c transmits the eighth pulse signal output from the MCU 70 to the isolator 64c. The receiver 65c outputs a second adjustment signal based on the isolator 64c receiving the eighth pulse signal. The second adjustment signal is a signal that causes the register 67 to adjust the timing at which the state machine 66 outputs the first OFF signal and the second OFF signal when the state machine 66 receives the second control signal. Therefore, by receiving the second adjustment signal, the register 67 adjusts the timing at which the state machine 66 outputs the second OFF signal after outputting the first OFF signal.

[0103] The register 67 may store in advance the timings for turning on and off the gate of the IGBT 10 and the gate of the MOSFET 30. When the register 67 receives the first adjustment signal and the second adjustment signal from the receiving unit 65c, the register 67 outputs the timings for turning on and off the gate of the IGBT 10 and the gate of the MOSFET 30 to the state machine 66 based on the stored timings. The state machine 66 outputs the first ON signal and the second ON signal, etc. to the terminals 62a and 62b based on the timings input from the register 67. In this way, in the case of simultaneous control, the GDU 60 adjusts the ON timings and OFF timings of the IGBT 10 and the MOSFET 30.

[0104] FIG. 25 is a circuit diagram illustrating a GDU 60 and an MCU 70 that perform simultaneous control in a semiconductor device 1c according to Modification 2 of Embodiment 1. As shown in FIG. 25, the GDU 60 includes a transmitter 63, an isolator 64, a receiver 65, a state machine 66, an analog-to-digital converter (ADC) 68, and terminals 61d and 61e in addition to terminals 61, 62a, and 62b. In this modification, instead of the register 67 in Modification 1, the timing of outputting the first ON signal, the second ON signal, etc., is adjusted based on an externally input voltage value. That is, in Modification 2, in addition to the one-channel isolator 64 for controlling the gates of the IGBT 10 and the MOSFET 30, a secondary-side setting pin 2 input is configured using terminals 61d and 61e for turn-on and turn-off. This controls the turn-on and turn-off timing.

[0105] A first voltage value is input to terminal 61d from the outside. The first voltage value adjusts the timing at which the state machine 66 outputs the second ON signal and the timing at which the state machine 66 outputs the first ON signal. A second voltage value is input to terminal 61e from the outside. The second voltage value adjusts the timing at which the state machine 66 outputs the first OFF signal and the timing at which the state machine 66 outputs the second OFF signal.

[0106] The configurations of the transmitter 63, the isolator 64, the receiver 65, and the state machine 66 are the same as those of the semiconductor device 1c described above. However, the state machine 66 of the second modification adjusts the timing of outputting the first ON signal and the second ON signal when the first control signal is received, based on a voltage value input from the outside. Specifically, the ADC 68 receives the first voltage value from the outside, and thereby the state machine 66 outputs the second ON signal, and the voltage V of the MOSFET 30 is adjusted. DSThe ADC 68 outputs a first digital value to the state machine 66, which adjusts the timing to output the first ON signal after the voltage Vout drops. The ADC 68 also receives a second voltage value from the outside, and outputs a second digital value to the state machine 66, which adjusts the timing to output the second OFF signal after the state machine 66 outputs the first OFF signal.

[0107] In this way, in the case of simultaneous control, the GDU 60 adjusts the on-timing and off-timing of the IGBT 10 and the MOSFET 30.

[0108] Next, the effects of this embodiment will be described. The semiconductor device 1 of this embodiment controls the gate of the IGBT 10 while keeping the gate of the MOSFET 30 in the inverter INV4 on. This reduces switching loss. Therefore, it is possible to reduce power loss in the semiconductor device 1 including the inverter INV4 and improve the efficiency of the inverter INV4. For example, when using individual control and simultaneous control, the control unit 500 first turns on the MOSFET 30 and controls the voltage V of the MOSFET 30. DS After the voltage drops, the control unit 500 turns on the IGBT 10. After turning off the IGBT 10, the control unit 500 turns on the MOSFET 30. This allows ZVS to be performed, and the switching loss can be further reduced.

[0109] When performing control using individual control and simultaneous control, the timing of turning on and off can be made regular by using the state machine 66. Furthermore, by adjusting the timing by the state machine 66 using the register 67, the ADC 68, etc., the regularity of the timing can be further improved.

[0110] The inverter INV4 includes a semiconductor element 400 including an IGBT 10 and a MOSFET 30. This allows high efficiency to be achieved under a wide range of load conditions, from low to high. Furthermore, the inverter INV4 can reduce the amount of MOSFET 30 including high-cost SiC used, thereby achieving a low-cost power module.

[0111] The disclosure made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present disclosure is not limited to the above embodiments and modifications, and various modifications are possible without departing from the spirit of the disclosure. For example, appropriate combinations of the configurations of Comparative Examples 1 to 3, Embodiment 1, and the modifications are also within the scope of the technical concept of the embodiments. In addition, the following configurations are also within the scope of the technical concept of the embodiments.

[0112] (Appendix A1) a control unit that connects a collector of an IGBT, a drain of a MOSFET, and a cathode of a diode, and controls a first gate that is a gate of the IGBT and a second gate that is a gate of the MOSFET in an element that connects an emitter of the IGBT, a source of the MOSFET, and an anode of the diode, The control unit controls the first gate while keeping the second gate on. Semiconductor device. (Appendix A2) The control unit outputting a first off signal to turn off the first gate and a second off signal to turn off the second gate; When the first gate and the second gate are turned off, After turning off the first gate by outputting the first off signal, By outputting the second off signal, the second gate is controlled to be turned off. The semiconductor device according to Appendix A1. (Appendix A3) The control unit outputting a first ON signal to turn on the first gate and a second ON signal to turn on the second gate; When the first gate and the second gate are turned on, outputting the second on signal to turn on the second gate; After the voltage between the drain and the source drops, the first gate is controlled to be turned on by outputting the first on signal. The semiconductor device according to Appendix A2. (Appendix A4) the control unit outputs the first on signal to turn on the first gate after the voltage between the drain and the source has decreased; 1. The semiconductor device according to claim 1, (Appendix A5) The control unit a GDU that outputs the first off signal to the first gate and the second off signal to the second gate; an MCU that outputs a third pulse signal to the GDU to cause the GDU to output the first off signal, and outputs a fourth pulse signal to the GDU to cause the GDU to output the second off signal; Includes When the first gate and the second gate are controlled individually, The MCU After outputting the third pulse signal to the GDU, causing the GDU to output the fourth pulse signal to the GDU; The semiconductor device according to Appendix A2. (Appendix A6) The GDU outputs a first ON signal to the first gate to turn on the first gate, and outputs a second ON signal to the second gate to turn on the second gate; The MCU outputting a second pulse signal to the GDU to cause the GDU to output the second ON signal; After the voltage between the drain and the source drops, a first pulse signal is output to the GDU, causing the GDU to output the first on signal. The semiconductor device according to Appendix A5. (Appendix A7) The GDU is a first transmitting unit that transmits the third pulse signal output from the MCU to a first isolator; a first receiving unit that outputs the first off signal based on the first isolator receiving the third pulse signal; a second transmitting unit that transmits the fourth pulse signal output from the MCU to a second isolator; a second receiving unit that outputs the second off signal based on the second isolator receiving the fourth pulse signal; having The semiconductor device according to Appendix A6. (Appendix A8) the first transmission unit transmits the first pulse signal output from the MCU to the first isolator; the first receiving unit outputs the first on signal based on the first isolator receiving the first pulse signal; the second transmission unit transmits the second pulse signal output from the MCU to the second isolator; the second receiving unit outputs the second on signal based on the second isolator receiving the second pulse signal. The semiconductor device according to Appendix A7. (Appendix A9) The GDU is a first state machine that outputs a second state signal that outputs the first OFF signal and the second ON signal based on the first pulse signal, the second pulse signal, the third pulse signal, and the fourth pulse signal, and outputs a third state signal that outputs the first OFF signal and the second OFF signal; a third transmitting unit that transmits the second state signal and the third state signal output from the first state machine to a third isolator; a third receiving unit that outputs the first off signal and then the second off signal based on the third isolator receiving the second state signal and the third state signal; Including, The semiconductor device according to Appendix A6. (Appendix A10) the first state machine outputs a first state signal that outputs the first ON signal and the second ON signal based on the first pulse signal, the second pulse signal, the third pulse signal, and the fourth pulse signal; the third transmitting unit transmits the first state signal and the second state signal output from the first state machine to the third isolator; the third receiving unit outputs the second ON signal based on the third isolator receiving the first state signal and the second state signal, and outputs the first ON signal after a voltage between the drain and the source drops. The semiconductor device according to Appendix A9. (Appendix A11) The control unit a GDU that outputs the first off signal to the first gate and the second off signal to the second gate; an MCU that outputs a sixth pulse signal to the GDU, causing the GDU to output at least one of the first off signal and the second off signal; Including, When the first gate and the second gate are controlled simultaneously, the MCU drives the GDU by outputting the sixth pulse signal to the GDU; The GDU outputs the second off signal after outputting the first off signal. The semiconductor device according to Appendix A2. (Appendix A12) The GDU outputs a first ON signal to the first gate to turn on the first gate, and outputs a second ON signal to the second gate to turn on the second gate; The MCU driving the GDU by outputting a fifth pulse signal to the GDU, the fifth pulse signal causing the GDU to output at least one of the first on signal and the second on signal; The GDU outputs the second ON signal, and after the voltage between the drain and the source decreases, outputs the first ON signal. The semiconductor device according to Appendix A11. (Appendix A13) The GDU is a fourth transmitter that transmits the sixth pulse signal output from the MCU to a fourth isolator; a fourth receiving unit that outputs a second control signal based on the fourth isolator receiving the sixth pulse signal; a second state machine that receives the second control signal, outputs the first off signal, and then outputs the second off signal; Including, The semiconductor device according to Appendix A12. (Appendix A14) the fourth transmission unit transmits the fifth pulse signal output from the MCU to the fourth isolator; the fourth receiving unit outputs a first control signal based on the fourth isolator receiving the fifth pulse signal; the second state machine outputs the second ON signal in response to receiving the first control signal, and outputs the first ON signal after the voltage between the drain and the source has decreased; The semiconductor device according to Appendix A13. (Appendix A15) The MCU outputs an eighth pulse signal; The GDU is a fifth transmitting unit that transmits the eighth pulse signal output from the MCU to a fifth isolator; a fifth receiving unit that outputs a second adjustment signal based on the fifth isolator receiving the eighth pulse signal; a register that receives the second adjustment signal and adjusts the timing at which the second state machine outputs the second off signal after the second state machine outputs the first off signal; having The semiconductor device according to Appendix A14. (Appendix A16) The MCU outputs a seventh pulse signal; the fifth transmission unit transmits the seventh pulse signal output from the MCU to the fifth isolator; the fifth receiving unit outputs a first adjustment signal based on the fifth isolator receiving the seventh pulse signal; the register receives the first adjustment signal, and adjusts the timing at which the second state machine outputs the second ON signal and outputs the first ON signal after the voltage between the drain and the source has decreased. The semiconductor device according to Appendix A15. (Appendix A17) The GDU has an ADC that receives a second voltage value from an external device and outputs a second digital value that adjusts the timing at which the second state machine outputs the second off signal after outputting the first off signal. The semiconductor device according to Appendix A14. (Appendix A18) the ADC receives a first voltage value from the outside, causing the second state machine to output the second ON signal, and outputs a first digital value that adjusts the timing of outputting the first ON signal after the voltage between the drain and the source drops. The semiconductor device according to Appendix A17. (Appendix B1) A control method for a semiconductor device including a control unit that controls a first gate that is a gate of the IGBT and a second gate that is a gate of the MOSFET in an element that connects a collector of an IGBT, a drain of a MOSFET, and a cathode of a diode, and connects an emitter of the IGBT, a source of the MOSFET, and an anode of the diode, the control unit comprising: and controlling the first gate while the second gate is turned on. A method for controlling a semiconductor device. (Appendix B2) The step of controlling the first gate while the second gate is turned on includes: When the first gate and the second gate are turned on, the control unit outputs the second on signal to turn on the second gate; After the voltage between the drain and the source decreases, the control unit outputs the first ON signal to turn on the first gate; Including, A method for controlling a semiconductor device according to Appendix B1. (Appendix B3) In the step of turning on the first gate, The control unit, after the voltage between the drain and the source is reduced, outputting the first on signal to turn on the first gate; A method for controlling a semiconductor device according to Appendix B2. (Appendix B4) The step of controlling the first gate while the second gate is turned on includes: When turning off the first gate and the second gate, the control unit outputs a first off signal that turns off the first gate, thereby turning off the first gate; After turning off the first gate, the control unit outputs a second off signal to turn off the second gate, thereby turning off the second gate; further comprising: A method for controlling a semiconductor device according to Appendix B2. (Appendix B5) The control unit a GDU that outputs the first ON signal to the first gate and the second ON signal to the second gate; an MCU that outputs a first pulse signal to the GDU to cause the GDU to output the first ON signal, and outputs a second pulse signal to the GDU to cause the GDU to output the second ON signal; and When the first gate and the second gate are controlled individually, In the step of turning on the second gate, the MCU outputs the second pulse signal to the GDU, thereby causing the GDU to output the second ON signal; In the step of turning on the first gate, the MCU outputs the first pulse signal to the GDU after the voltage between the drain and the source drops, thereby causing the GDU to output the first ON signal; A method for controlling a semiconductor device according to Appendix B2. (Appendix B6) The step of controlling the first gate while the second gate is turned on includes: the MCU outputs a third pulse signal to the GDU, causing the GDU to output a first off signal for turning off the first gate, thereby causing the GDU to output the first off signal, thereby turning off the first gate; After turning off the first gate, the MCU outputs a fourth pulse signal to the GDU, causing the GDU to output a second off signal that turns off the second gate, thereby causing the GDU to output the second off signal, thereby turning off the second gate; further comprising: A method for controlling a semiconductor device according to Appendix B5. (Appendix B7) The GDU is a first transmitting unit that transmits the first pulse signal output from the MCU to a first isolator; a first receiving unit that outputs the first on signal based on the first pulse signal received by the first isolator; a second transmitting unit that transmits the second pulse signal output from the MCU to a second isolator; a second receiving unit that outputs the second ON signal based on the second pulse signal received by the second isolator; Including, A method for controlling a semiconductor device according to Appendix B6. (Appendix B8) the first transmission unit transmits the third pulse signal output from the MCU to the first isolator; the first receiving unit outputs the first off signal based on the first isolator receiving the third pulse signal; the second transmission unit transmits the fourth pulse signal output from the MCU to the second isolator; the second receiving unit outputs the second off signal based on the second isolator receiving the fourth pulse signal. A method for controlling a semiconductor device according to Appendix B7. (Appendix B9) The GDU is a first state machine that outputs a first state signal that outputs the first ON signal and the second ON signal and outputs a second state signal that outputs the first OFF signal and the second ON signal based on the first pulse signal, the second pulse signal, the third pulse signal, and the fourth pulse signal; a third transmitting unit that transmits the first state signal and the second state signal output from the first state machine to a third isolator; a third receiving unit that outputs the second ON signal based on the third isolator receiving the first state signal and the second state signal, and outputs the first ON signal after a voltage between the drain and the source drops; Including, A method for controlling a semiconductor device according to Appendix B6. (Appendix B10) the first state machine outputs a third state signal that outputs the first off signal and the second off signal based on the first pulse signal, the second pulse signal, the third pulse signal, and the fourth pulse signal; the third transmitting unit transmits the second state signal and the third state signal output from the first state machine to the third isolator; the third receiving unit outputs the first off signal and then the second off signal based on the third isolator receiving the second state signal and the third state signal. A method for controlling a semiconductor device according to Appendix B9. (Appendix B11) The control unit a GDU that outputs the first ON signal to the first gate and the second ON signal to the second gate; an MCU that outputs a fifth pulse signal to the GDU, causing the GDU to output at least one of the first on signal and the second on signal; Including, When the first gate and the second gate are controlled simultaneously, In the step of turning on the second gate, the MCU outputs the fifth pulse signal to the GDU to drive the GDU and cause the GDU to output the second ON signal; In the step of turning on the first gate, the MCU outputs the fifth pulse signal to the GDU after the voltage between the drain and the source has decreased, thereby causing the GDU to output the first ON signal; A method for controlling a semiconductor device according to Appendix B2. (Appendix B12) the MCU outputs a sixth pulse signal to the GDU, causing the GDU to output at least one of a first off signal for turning off the first gate and a second off signal for turning off the second gate, thereby causing the GDU to turn off the first gate; After turning off the first gate, the MCU outputs the sixth pulse signal to the GDU, thereby causing the GDU to output the second off signal, thereby turning off the second gate; further comprising: A method for controlling a semiconductor device according to Appendix B11. (Appendix B13) The GDU is a fourth transmitter that transmits the fifth pulse signal output from the MCU to a fourth isolator; a fourth receiving unit that outputs a first control signal based on the fourth isolator receiving the fifth pulse signal; a second state machine that receives the first control signal, outputs the second ON signal, and outputs the first ON signal after a voltage between the drain and the source drops; Including, A method for controlling a semiconductor device according to Appendix B12. (Appendix B14) the fourth transmitter transmits the sixth pulse signal output from the MCU to the fourth isolator; the fourth receiving unit outputs a second control signal based on the fourth isolator receiving the sixth pulse signal; the second state machine receives the second control signal, and then outputs the first off signal and then the second off signal. A method for controlling a semiconductor device according to Appendix B13. (Appendix B15) The MCU outputs a seventh pulse signal; The GDU is a fifth transmitting unit that transmits the seventh pulse signal output from the MCU to a fifth isolator; a fifth receiving unit that outputs a first adjustment signal based on the fifth isolator receiving the seventh pulse signal; a register that adjusts a timing at which the second state machine outputs the second ON signal by receiving the first adjustment signal and outputs the first ON signal after the voltage between the drain and the source has decreased; having A method for controlling a semiconductor device according to Appendix B14. (Appendix B16) The MCU outputs an eighth pulse signal; the fifth transmission unit transmits the eighth pulse signal output from the MCU to the fifth isolator; the fifth receiving unit outputs a second adjustment signal based on the fifth isolator receiving the eighth pulse signal; the register receives the second adjustment signal and adjusts the timing at which the second state machine outputs the second off signal after outputting the first off signal. A method for controlling a semiconductor device according to Appendix B15. (Appendix B17) The GDU receives a first voltage value from an external device, and outputs a first digital value that adjusts the timing at which the second state machine outputs the second ON signal and the first ON signal after the voltage between the drain and the source drops. A method for controlling a semiconductor device according to Appendix B14. (Appendix B18) the ADC receives a second voltage value from the outside and outputs a second digital value that adjusts the timing of outputting the second off signal after the second state machine outputs the first off signal. A method for controlling a semiconductor device according to Appendix B17. [Explanation of symbols]

[0113] 1, 1a, 1b, 1c Semiconductor device 10 IGBT 11 Collector terminal 12 Emitter terminal 13 Gate terminal 20 FRD 21 Cathode terminal 22 Anode terminal 30 MOSFET 31 Drain terminal 32 Source terminal 33 Gate terminal 40 SBD 41 Cathode terminal 42 Anode terminal 50u, 50v, 50w terminals 60 GDU 61, 61a, 61b, 61c, 61d, 61e, 62a, 62b terminals 63, 63a, 63b, 63c Transmitting section 64, 64a, 64b, 64c Isolators 65, 65a, 65b, 65c Receiver 66 State Machine 67 Registers 68 ADC 70 MCU 71, 71a, 71b, 71c terminals 79 Switch 100, 100a, 100b, 100c, 100d, 100e, 100f semiconductor elements 101, 102, 103 Semiconductor device 200, 200a, 200b, 200c, 200d, 200e, 200f semiconductor elements 300, 300a, 300b, 300c, 300d, 300e, 300f semiconductor elements 400, 400a, 400b, 400c, 400d, 400e, 400f semiconductor elements 500 control section GND wiring INV1, INV2, INV3, INV4 inverters VBUS wiring

Claims

1. a control unit that controls a first gate that is a gate of the IGBT and a second gate that is a gate of the MOSFET in an element that connects a collector of an IGBT, a drain of a MOSFET, and a cathode of a diode, and that connects an emitter of the IGBT, a source of the MOSFET, and an anode of the diode, The control unit controls the first gate while keeping the second gate on. Semiconductor device.

2. The control unit outputting a first ON signal to turn on the first gate and a second ON signal to turn on the second gate; When the first gate and the second gate are turned on, outputting the second on signal to turn on the second gate; After the voltage between the drain and the source has decreased, the first gate is controlled to be turned on by outputting the first on signal. The semiconductor device according to claim 1 .

3. the control unit outputs the first on signal to turn on the first gate after the voltage between the drain and the source has decreased; The semiconductor device according to claim 2 .

4. The control unit outputting a first off signal for turning off the first gate and a second off signal for turning off the second gate; When the first gate and the second gate are turned off, After turning off the first gate by outputting the first off signal, By outputting the second off signal, the second gate is controlled to be turned off. The semiconductor device according to claim 2 .

5. The control unit a GDU that outputs the first ON signal to the first gate and the second ON signal to the second gate; an MCU that outputs a first pulse signal to the GDU, causing the GDU to output the first ON signal, and outputs a second pulse signal to the GDU, causing the GDU to output the second ON signal; Including, When the first gate and the second gate are controlled individually, The MCU comprises: outputting the second pulse signal to the GDU, thereby causing the GDU to output the second ON signal; After the voltage between the drain and the source drops, outputting the first pulse signal to the GDU, thereby causing the GDU to output the first ON signal. The semiconductor device according to claim 2 .

6. The GDU outputs a first off signal to the first gate to turn off the first gate, and outputs a second off signal to the second gate to turn off the second gate; The MCU comprises: After outputting a third pulse signal to the GDU to cause the GDU to output the first off signal, outputting a fourth pulse signal to the GDU, causing the GDU to output the second off signal; The semiconductor device according to claim 5 .

7. The GDU comprises: a first transmitting unit that transmits the first pulse signal output from the MCU to a first isolator; a first receiving unit that outputs the first on signal based on the first pulse signal received by the first isolator; a second transmitting unit that transmits the second pulse signal output from the MCU to a second isolator; a second receiving unit that outputs the second on signal based on the second pulse signal received by the second isolator; Including, The semiconductor device according to claim 6.

8. the first transmitting unit transmits the third pulse signal output from the MCU to the first isolator; the first receiving unit outputs the first off signal based on the first isolator receiving the third pulse signal; the second transmitting unit transmits the fourth pulse signal output from the MCU to the second isolator; the second receiving unit outputs the second off signal based on the second isolator receiving the fourth pulse signal. The semiconductor device according to claim 7 .

9. The GDU comprises: a first state machine that outputs a first state signal that outputs the first ON signal and the second ON signal and outputs a second state signal that outputs the first OFF signal and the second ON signal based on the first pulse signal, the second pulse signal, the third pulse signal, and the fourth pulse signal; a third transmitting unit that transmits the first state signal and the second state signal output from the first state machine to a third isolator; a third receiving unit that outputs the second ON signal based on the third isolator receiving the first state signal and the second state signal, and outputs the first ON signal after a voltage between the drain and the source drops; Including, The semiconductor device according to claim 6.

10. the first state machine outputs a third state signal that outputs the first off signal and the second off signal based on the first pulse signal, the second pulse signal, the third pulse signal, and the fourth pulse signal; the third transmitting unit transmits the second state signal and the third state signal output from the first state machine to the third isolator; the third receiving unit outputs the first off signal and then the second off signal based on the third isolator receiving the second state signal and the third state signal. The semiconductor device according to claim 9 .

11. The control unit a GDU that outputs the first ON signal to the first gate and the second ON signal to the second gate; an MCU that outputs a fifth pulse signal to the GDU, causing the GDU to output at least one of the first on signal and the second on signal; and When the first gate and the second gate are controlled simultaneously, the MCU drives the GDU by outputting the fifth pulse signal to the GDU; The GDU outputs the second ON signal, and after the voltage between the drain and the source decreases, outputs the first ON signal. The semiconductor device according to claim 2 .

12. The GDU outputs a first off signal to the first gate to turn off the first gate, and outputs a second off signal to the second gate to turn off the second gate; The MCU comprises: driving the GDU by outputting a sixth pulse signal to the GDU, the sixth pulse signal causing the GDU to output at least one of the first off signal and the second off signal; the GDU outputs the second off signal after outputting the first off signal; The semiconductor device according to claim 11.

13. The GDU comprises: a fourth transmitter that transmits the fifth pulse signal output from the MCU to a fourth isolator; a fourth receiving unit that outputs a first control signal based on the fourth isolator receiving the fifth pulse signal; a second state machine that receives the first control signal, outputs the second ON signal, and outputs the first ON signal after a voltage between the drain and the source drops; Including, The semiconductor device according to claim 12.

14. the fourth transmitter transmits the sixth pulse signal output from the MCU to the fourth isolator; the fourth receiving unit outputs a second control signal based on the fourth isolator receiving the sixth pulse signal; the second state machine receives the second control signal, and then outputs the first off signal and then the second off signal. The semiconductor device according to claim 13.

15. The MCU outputs a seventh pulse signal; The GDU comprises: a fifth transmitting unit that transmits the seventh pulse signal output from the MCU to a fifth isolator; a fifth receiving unit that outputs a first adjustment signal based on the fifth isolator receiving the seventh pulse signal; a register that adjusts a timing at which the second state machine outputs the second ON signal by receiving the first adjustment signal and outputs the first ON signal after the voltage between the drain and the source has decreased; having The semiconductor device according to claim 14.

16. The MCU outputs an eighth pulse signal; the fifth transmitting unit transmits the eighth pulse signal output from the MCU to the fifth isolator, the fifth receiving unit outputs a second adjustment signal based on the fifth isolator receiving the eighth pulse signal; the register receives the second adjustment signal and adjusts the timing at which the second state machine outputs the second off signal after outputting the first off signal. The semiconductor device according to claim 15.

17. The GDU receives a first voltage value from an external device, and the second state machine outputs the second ON signal. The GDU has an ADC that outputs a first digital value that adjusts the timing of outputting the first ON signal after the voltage between the drain and the source drops. The semiconductor device according to claim 14.

18. the ADC receives a second voltage value from the outside and outputs a second digital value that adjusts the timing of outputting the second off signal after the second state machine outputs the first off signal; The semiconductor device according to claim 17.

19. The control unit outputting a first off signal for turning off the first gate and a second off signal for turning off the second gate; When the first gate and the second gate are turned off, After turning off the first gate by outputting the first off signal, By outputting the second off signal, the second gate is controlled to be turned off. The semiconductor device according to claim 1 .

20. A control method for a semiconductor device including a control unit that controls a first gate that is a gate of the IGBT and a second gate that is a gate of the MOSFET in an element in which a collector of an IGBT, a drain of a MOSFET, and a cathode of a diode are connected, and an emitter of the IGBT, a source of the MOSFET, and an anode of the diode are connected, the method comprising: a step of controlling the first gate while the second gate is turned on; A method for controlling a semiconductor device.

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