Superconducting quantum circuit device

Abstract

To ensure the strength of the magnetic field coupling between the SQUID loop of a first chip and the wiring of a second chip, making it possible to ensure a desired internal Q value, which is a performance index of the quantum bit.SOLUTION: A superconducting quantum circuit device includes a first chip including a quantum bit circuit including a SQUID (superconducting quantum interference device) in an interconnection layer, and a second chip having an interconnection layer on a first surface, the interconnection layer on the first surface arranged opposite the interconnection layer of the first chip. The interconnection layer of the first chip has an opening adjacent to the SQUID of the quantum bit circuit. The interconnection layer on the first surface of the second chip has wiring having one end connected to a terminal and the other end connected to ground. The wiring extends along the quantum bit circuit of the first chip in at least a region of the first chip facing the opening, and the other end is connected to a ground pattern.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to superconducting quantum circuit devices. [Background technology]

[0002] A quantum bit consisting of a superconducting quantum circuit generally comprises a planar circuit of a superconducting material formed by deposition or the like on the surface of a semiconductor substrate, and a nonlinear inductor such as a SQUID (superconducting quantum interference device) with multiple Josephson junctions in its loop, and the state of the quantum bit is controlled by applying a magnetic field to the SQUID loop. For example, Patent Document 1 discloses a quantum device with a three-dimensional wiring structure, which comprises a first chip having a quantum bit on a first surface of a substrate, and a second chip having coil wiring (a current path for applying a magnetic field) that generates a magnetic field on the first surface of the substrate, and the first surface of the first chip is bonded to face the first surface of the second chip, with the central axis of the coil wiring of the second chip aligned with the central axis of the SQUID loop of the quantum bit on the first chip. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,950,654 Summary of the Invention [Problem to be solved by the invention]

[0004] As in Patent Document 1, if the central axis of the coil wiring of the second chip is aligned with the central axis of the SQUID loop of the quantum bit circuit of the first chip, and the distance between the first and second chips is narrow, the capacitance between the central axis of the coil wiring of the second chip and the SQUID loop of the quantum bit circuit of the first chip is likely to increase. As a result, there is a trade-off between the strength of the magnetic field coupling between the SQUID loop of the first chip and the coil wiring of the second chip and the magnitude of the internal Q value, which is a performance index of the quantum bit circuit, and it is difficult to achieve both.

[0005] The present disclosure has been devised in view of the above-mentioned problems, and aims to provide a superconducting quantum circuit device that ensures the strength of the magnetic field coupling between the SQUID loop of the quantum bit circuit of the first chip and the wiring of the second chip, and that can ensure a desired internal Q value, which is a performance index of the quantum bit circuit of the first chip. [Means for solving the problem]

[0006] According to the present disclosure, a superconducting quantum circuit device includes a first chip including a quantum bit circuit including a SQUID (superconducting quantum interference device) in an interconnect layer, and a second chip having an interconnect layer on a first surface thereof, the interconnect layer on the first surface being disposed opposite the interconnect layer of the first chip. The interconnect layer of the first chip has an opening adjacent to the SQUID of the quantum bit circuit. The interconnect layer on the first surface of the second chip has wiring having one end connected to a terminal and the other end connected to ground, the wiring extending along the quantum bit circuit of the first chip in at least a region of the first chip facing the opening, and the other end connected to a ground pattern. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to ensure the strength of the magnetic field coupling between the SQUID loop of the quantum bit circuit of the first chip and the wiring of the second chip, thereby ensuring the desired internal Q value, which is a performance index of the quantum bit circuit of the first chip. [Brief explanation of the drawings]

[0008] [Figure 1] 10A and 10B are diagrams illustrating a comparative example. [Figure 2] 10A and 10B are diagrams illustrating a comparative example. [Figure 3] 10A and 10B are diagrams illustrating a comparative example. [Figure 4] 1A and 1B are diagrams illustrating an example of the present disclosure. [Figure 5] 1A and 1B are diagrams illustrating an example of the present disclosure. [Figure 6] FIG. 1 is a diagram illustrating an example of the present disclosure. [Figure 7] FIG. 1 is a diagram illustrating an example of the present disclosure. [Figure 8] FIG. 1 is a diagram illustrating an example of the present disclosure. [Figure 9] 1A to 1C are diagrams illustrating an example of the present disclosure. [Figure 10] 1A to 1C are diagrams illustrating an example of the present disclosure. [Figure 11] 1A to 1C are diagrams illustrating an example of the present disclosure. [Figure 12] FIG. 1 is a diagram illustrating an example of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] Several embodiments of the present disclosure will be described. First, to facilitate understanding of the present disclosure, an analysis by the present inventors of the quantum device disclosed in Patent Document 1 will be presented as a comparative example. FIGS. 1(A) and 1(B) are redrawn versions of the quantum device disclosed in Figures 5A and 5B of Patent Document 1. FIG. 1(A) is a plan view schematically showing the wiring layout of the second chip 311, and FIG. 1(B) is a plan view schematically showing the wiring layout of the first chip 301. In FIGS. 1(A) and 1(B), white areas correspond to areas where a layer of superconducting material is present, and gray areas correspond to areas where no superconducting material is present and the chip substrate may be exposed.

[0010] Referring to FIG. 1A, in the second chip 311, the coil wiring (bias coil) formed from the superconductor layer includes a first portion 504 coupled to the ground plane 501 of the superconductor, a second portion 506 coupled to a signal source that provides control signals during device operation, and a loop portion 508. The loop portion 508 of the coil wiring includes an inner loop edge 503 and an outer loop edge 505. The outer loop edge 505 faces the edge of the ground plane 501 of the superconductor (separated from the ground plane 501) via a gap 507. As shown in FIG. 1A, in the second chip 311, the width 509 of the superconductor material in the first portion 504 and the second portion 506 is set to be much narrower than the width 511 of the superconductor material in the loop portion 508. To ensure an appropriate path for the return current, a ground connection is made where the bias line is shorted. For example, bumps (ground bumps, not shown) are used on both sides of the coil wiring.

[0011] FIG. 1B is a schematic diagram showing a top view of an example SQUID region 510 of a superconducting qubit in the first chip 301. In the example shown in FIG. 1B, the SQUIDs in the SQUID region 510 are physically coupled to a central region of the superconducting qubit (not shown), with wires 517 extending from there between the superconducting qubits. The SQUID region 510 includes a layer of superconductor material arranged in a generally ring shape, interrupted at multiple locations to provide Josephson junctions 514 in the interrupted gaps. The superconducting wires of the Josephson junctions 514 are depicted in black. A portion of the SQUID region 510 may be formed by a superconductor ground plane 513. The SQUID region 510 has an inner ring region 512 that is free of superconductor material.

[0012] The area / perimeter of inner ring region 512 is defined by an edge 516 of superconductor material. During device operation, the coil wiring of second chip 311 is electromagnetically coupled (inductively coupled) to the SQUID in SQUID region 510. Applying a control current to the coil wiring of second chip 311 allows the operating frequency of the qubit to be tuned via inductive coupling.

[0013] As shown in the schematic cross-sectional view of FIG. 2A, the first chip 301 is disposed on the second chip 311 and electrically and / or mechanically connected to it using bumps 304. The bumps 304 may contain a superconductor material. FIG. 2A corresponds to FIG. 3A of Patent Document 1. FIG. 2B is a diagram illustrating the overlapping of the wiring layers of the first chip 301 and the second chip 311 stacked as shown in FIG. 2A. FIG. 2B corresponds to FIG. 5A of Patent Document 1. Referring to FIG. 2B, the inner loop edge 503 and the outer loop edge 505 of the second chip 311 are formed on the second chip 311 such that the inner loop edge 503 is included within the inner ring region 512 of the SQUID region 510 of the superconducting quantum bit on the first chip 301 when the first chip 301 and the second chip 311 are aligned and bump-bonded. The outer loop edge 505 is formed so that, when the first chip 301 and the second chip 311 are aligned, the inner ring region 512 of the SQUID region 510 of the superconducting quantum bit on the first chip 301 is completely encompassed by the outer loop edge 505 of the loop portion 508 on the second chip 311. In Fig. 2(B) , the centers of the inner loop edge 503 of the second chip 311 and the inner ring region 512 of the SQUID region 510 of the superconducting quantum bit on the first chip 301 are joined together so as to overlap.

[0014] As described above, when the center of the coil wiring (center of the inner loop edge 503) of the loop portion 508 surrounded by the inner loop edge 503 and outer loop edge 505 of the second chip 311 is aligned with the center of the inner ring region 512 of the quantum bit circuit of the first chip 301, as shown schematically in Figure 3(A), the magnetic field (magnetic field) generated by the current (loop current) flowing in the loop portion 508 of the second chip 311 penetrates the inner ring region 512A of the quantum bit circuit of the first chip 301, and a magnetic field (magnetic field lines) 521 is generated in the first chip 301, penetrating the substrate from the area where there is no superconducting material and the substrate is exposed, forming a closed circuit. In this case, if the height of bump 304 becomes equal to or smaller than gap (gap) 507, the closest conductor seen from loop portion 508 of second chip 311 becomes wiring (superconductor) 517 of first chip 301, and the capacitance between wiring (superconductor) 517 of first chip 301 and loop portion 508 of second chip 311 becomes non-negligible, resulting in unintended operation. One problem is that the signal frequency of the quantum bit becomes more easily transmitted between second portion 506, which is coupled to the quantum bit and a signal source that supplies a control signal, resulting in a decrease in the internal Q value of the superconducting quantum bit.

[0015] FIG. 3(B) is a diagram illustrating the vector potential A created by the current flowing in the loop portion 508 surrounded by the inner loop edge 503 and outer loop edge 505 of the second chip 311. If the long and short sides of the rectangular inner loop edge 503 of the second chip 311 are a and b, and the current flowing in the loop portion 508 is I, the magnitude of the vector potential A is proportional to the value μ=Iab obtained by multiplying the current I by the area of ​​the inner loop edge 503 (area of ​​a rectangle with width: a, height: b). This μ is called the magnetic moment. The inner loop edge 503 may be a circle or a triangle, etc. If the distance from the position P(x, y, z) (the center of the loop portion 508) to R(=√(x 2 +y 2 *z 2 ) the vector potential A at a distance (ε0 is the dielectric constant of vacuum and c is the speed of light) is given by: TIFF2025152417000002.tif11150…(1) TIFF2025152417000003.tif6150…(2) Therefore, the magnetic field B = (Bx, By, Bz) is given by: TIFF2025152417000004.tif10150…(3) TIFF2025152417000005.tif10150…(4) TIFF2025152417000006.tif11150…(5)

[0016] 3(B), the inner ring region 512 of the SQUID region 510 of the first chip 301 is wider than the inner loop edge 503 of the second chip 311. It can be seen that the magnetic field generated by the current (loop current) flowing in the loop portion 508 surrounded by the inner loop edge 503 and outer loop edge 505 of the second chip 311 spreads widely in all directions of the inner ring region 512 depending on the distance between the second chip 311 and the first chip 301, the size of the rectangular inner loop edge 503 of the second chip 311, and the size of the inner ring region 512 of the SQUID region 510 of the first chip 301. Note that the magnetic fields Bx and By in the x and y directions are (1 / R) 3 Here, the value z on the z axis is the distance between the opposing surfaces of the first tip 301 and the second tip 311, and if the value z is small compared to R, Bz in the z axis direction is proportional to (1 / R) 3 The magnitude of the magnetic field B at point P decreases as the cube of the distance R from the center of the loop current. For example, the magnetic field at a point twice the distance P from the center of the loop current decreases by a factor of eight.

[0017] The above problem is just one example, but according to the present disclosure, the above problem is not limited to the above, and a magnetic field application structure is proposed that ensures the strength of the magnetic field coupling between the SQUID loop of the first chip and the wiring of the second chip when applying a magnetic field to a quantum bit in various situations, thereby making it possible to ensure the desired internal Q value, which is a performance indicator of the quantum bit.

[0018] FIG. 4A is a schematic plan view of the wiring pattern of the wiring layer of the first chip 101 of the present disclosure, viewed from above. In FIG. 4A, the white areas correspond to areas where a wiring layer made of superconducting material is present. The gray areas indicated by reference numeral 110 correspond to areas where no superconducting material is present (such as gaps in the wiring layer) and the substrate of the first chip 101 is exposed. The first chip 101 has at least two Josephson junctions 104a and 104b that connect the wiring 103 of the quantum bit circuit 105 to ground in parallel. The wiring 103 is made of a superconducting material and also serves as an electrode to which one end of each of the Josephson junctions 104a and 104b is connected. The quantum bit circuit 105 is connected to input / output lines (readout lines) not shown. The ground-side electrode to which the other ends of the Josephson junctions 104a and 104b are connected consists of a wiring 107 and a semi-rectangular (open end at the top of the figure) ground electrode 108 (ground surface surrounded by a dashed line). The ground electrode 108 may be integrated with the ground surface 102, and may be formed by patterning the ground surface 102 as shown in the figure. Although not particularly limited, the Josephson junctions 104a and 104b may be formed by forming a first aluminum film by oblique deposition on the surface of the substrate of the first chip and oxidizing it to form a tunnel oxide film (AlO x ) and then a second aluminum film is formed by oblique evaporation from the opposite direction to the previous one, forming a Josephson junction (Al / AlO x / Al) may be formed.

[0019] In the present disclosure, the semi-rectangular ground electrode 108 is disposed at the furthest position in the SQUID loop, facing the wiring 103 of the quantum bit circuit. The wiring 103 of the quantum bit circuit 105, Josephson junctions 104a and 104b, superconducting member (wiring) 107, and semi-rectangular ground electrode 108 constitute a SQUID loop. An opening 106 is provided in the ground surface 102 of the wiring layer of the first chip 101, adjacent to the semi-rectangular ground electrode 108 of the SQUID loop. This opening 106 is formed by removing the wiring layer formed on the substrate by etching or the like, so that the surface of the substrate directly below the wiring layer is exposed. Note that the first chip 101 is also referred to as a quantum chip because it includes the quantum bit circuit 105.

[0020] Fig. 4(B) is a schematic plan view of the first wiring layer of second chip 201 of the present disclosure as viewed from above. First chip 101 in Fig. 4(A) is mounted face-down with its wiring layer facing the first wiring layer of second chip 201. Fig. 4(B) shows the area of ​​the first wiring layer of second chip 201 that corresponds to the area of ​​first chip 101 in Fig. 4(A). Second chip 201 is also called a wiring chip or an interposer.

[0021] The first wiring layer of the second chip 201 is provided with wiring 203 that partially overlaps with a region on one side (the right side of the figure) of the opening 106 (shown by the dashed line) of the first chip 101. The other end of the wiring 203 is connected to a signal source. The wiring 203 extends downward in the figure and is connected to a signal terminal (pad) to which a signal is supplied from a signal source (not shown). The wiring 203 bends 90 degrees in the region corresponding to the opening 106 of the first chip 101, crosses the opening 106, and is connected to ground 202 at the point where it passes over the other side of the opening 106 (the left side of the figure). The ground 202 of the wiring layer is also referred to as a ground plane or a ground pattern. The substrate surface is exposed in a region 204 between the wiring 203 and the ground 202.

[0022] 4(B), the ground pattern 202 to which one end of the wiring 203 is connected is connected to the ground pattern 202 on the right side of the figure in a downward U-shaped pattern so as to surround the opening 106 of the first chip 101 in Fig. 4(A) and the SQUID connected to the quantum bit circuit, and the right ground pattern 202 extends downward along the wiring 203 to a signal terminal (not shown) to which the wiring 203 is connected, surrounds the signal terminal (not shown), and reaches the ground pattern 202 on the left side of the figure. It is worth noting that the area 204A surrounded by the wiring 203 and the ground pattern 202 is laid out so that the SQUID loop of the first chip 101 is located within the range of the area 204A (the area from which the first wiring layer is removed) when the first chip 101 in Fig. 4(A) is mounted face-down.

[0023] FIG. 5(A) is a diagram schematically illustrating an example of a cross section in which the wiring layer of the first chip 101 in FIG. 4(A) is flip-chip mounted facing the wiring layer of the second chip 201 in FIG. 4(B). FIG. 5(B) is a schematic perspective view illustrating a case in which the wiring layer of the first chip 101 in FIG. 4(A) is flip-chip mounted facing the wiring layer of the second chip 201 in FIG. 4(B). FIG. 5(B) schematically illustrates the wiring layer 113 of the first chip 101 and the first wiring layer 213 of the second chip 201, separated from the substrates 112 and 212, respectively. Note that only a portion of the bumps is shown. FIG. 5(A) corresponds to a cross section taken along line AA (parallel to the x-axis) in FIG. 5(B) as viewed from the y-axis direction. Wiring 203 of first wiring layer 213 of second chip 201 traverses rectangular opening 106 (a region where no wiring pattern is provided) of wiring layer 113 of first chip 101 from one end to the other end directly below opening 106 of first chip 101. Fig. 5(B) does not show second wiring layer 215 of second chip 201 or via 216 penetrating substrate 212 of second chip 201 in Fig. 5(A).

[0024] The substrate 112 of the first chip 101 is made of, for example, a silicon substrate. The wiring layer 113 is formed by a wiring pattern formation process (superconducting thin film formation, resist application, exposure / development, etching, etc.) in a semiconductor process. The second chip (interposer) 201 has a first wiring layer 213 and a second wiring layer 215 on a first surface and a second surface of the substrate 212, respectively. The substrate 212 is made of, for example, a silicon substrate. As a non-limiting example, the substrate 112 of the first chip 101 and the substrate 212 of the second chip 201 may be made of not only silicon but also other electronic materials such as sapphire or compound semiconductor materials (Group IV (GeSn, etc.), Group III-V (GaAs, GaN, GaP, GaSb, InAs, InP, InS, etc.), Group II-VI (ZnS, ZnSe)). A single crystal is preferable, but polycrystalline or amorphous materials are also acceptable.

[0025] The wiring layer 113 of the first chip 101 is made of a superconducting material such as niobium (Nb), niobium nitride, aluminum (Al), indium (In), lead (Pb), tin (Sn), rhenium (Re), palladium (Pd), titanium (Ti), tantalum (Ta), tantalum nitride, or a niobium (Nb) alloy containing at least one of these. The superconducting material is not limited to niobium (Nb), but may be niobium nitride, aluminum (Al), indium (In), lead (Pb), tin (Sn), rhenium (Re), palladium (Pd), titanium (Ti), titanium nitride, tantalum (Ta), tantalum nitride, or an alloy containing at least one of these. The wiring layer 113 may be made of the same superconducting material as the first and second wiring layers 213 and 215 of the second chip 201, or may include wiring made of a normal-conducting material. As shown in the figure, the bump 214 is a protrusion suitable for controlling the height of the gap between the substrates to be joined, and any shape can be selected, such as a columnar shape (cylindrical column, polygonal column, etc.), a conical shape (including truncated cones and pyramids as well as truncated cones and pyramids), a spherical shape, a rectangular shape, etc. Here, the top of the bump 214 may be molded to have a partially flat shape. The bump 214 is made of, for example, a normal conducting material such as copper or silicon dioxide (S i O2) or the like, and the surface thereof may be covered with a film of a superconducting material.

[0026] 5(A), a configuration may be adopted in which the second wiring layer 215 side of the second chip 201 is connected to a wiring layer of a printed circuit board (not shown), and the terminal 217 of the first wiring layer 213 of the second chip 201 is connected to a terminal (not shown) on the second wiring layer 215 side through the through via 216, and the connector of the printed circuit board is connected to a signal source (not shown) through a coaxial cable (not shown) or the like. Alternatively, a configuration may be adopted in which the second wiring layer 215 of the second chip 201 is used as a ground pattern, and the terminal 217 of the first wiring layer 213 of the second chip 201 is connected to a peripheral terminal (pad) of the second chip 201 by wiring and then connected to a terminal on the printed circuit board (not shown) by wire bonding or the like.

[0027] 6 is a schematic exploded perspective view showing the wiring 203 of the first wiring layer 213 of the second chip 201 in FIG. 5B overlapping with the opening 106 and Josephson junctions 104a and 104b of the wiring layer 213 of the first chip 101. The area surrounded by a dashed dotted line 120 in FIG. 6 corresponds to the wiring pattern of the first wiring layer of the second chip 201 shown in FIG. 4B and the wiring pattern of the first chip 101 (including the SQUID loop including the Josephson junctions 104a and 104b) that is flip-chip mounted opposite the first wiring layer of the second chip 201. As shown in FIG. 6, one end of the wiring 203 of the first wiring layer of the second chip 201 is connected to a terminal (pad) 217, bent at a right angle on one side of the opening 106 provided in the wiring layer of the first chip 101, and connected to the ground plane 202 across the opening 106. A gap (air gap) 204 is provided between the wiring 203 and the ground 202, and the surface of the substrate of the second chip 201 is exposed. The ground (ground surface) 202 to which one end of the wiring 203 is connected surrounds the quantum bit circuit (SQUID) and the opening 106 of the first chip 101, extends along the wiring 203 to a terminal 217 to which the wiring 203 is connected, surrounds the periphery of the terminal 217, and reaches a connection point with one end of the wiring 203. Reference numeral 218 denotes a bump 214 ( FIG. 5 ) that connects the ground surface 102 of the first chip 101 and the ground surface 202 of the second chip 201. Although not particularly limited, in the example of FIG. 6 , the first wiring layer 213 (ground surface 202, wiring 203, etc.) of the second chip 201 is made of a superconducting material.

[0028] 7 is a diagram showing the wiring pattern of second chip 201 in the area surrounded by dashed line 120 in FIG. 6 superimposed on the wiring layer of first chip 101 flip-chip mounted opposite to it. In FIG. 7, wiring 203 and the like of the first wiring layer of second chip 201 below the wiring layer of first chip 101 are shown by virtual lines (dashed lines). As shown in FIG. 7, when a control current flows from terminal 217 (FIG. 6) to wiring 203 of the first wiring layer of second chip 201 in the direction of the arrow in the figure, a magnetic field H (magnetic field B=μH, where μ is magnetic permeability) is generated according to the following Ampere's law (expressed in integral form in equation (6)): TIFF2025152417000007.tif12150…(6) H is the magnetic field strength, j is the current density, dl is the line element vector, dS is the surface element vector, and ∂S is the boundary of the surface S. A part of the magnetic field H passes through the opening 106 of the first chip 101 and spreads into the inside of the substrate 112 of the first chip 101. The part of the magnetic field that spreads to the substrate 112 of the first chip 101 becomes a component that penetrates the SQUID loop of the first chip 101 (Josephson junctions 104a and 104b, wiring (electrode) 103, and semi-rectangular ground electrode 108). The magnetic field that penetrates the SQUID loop of the first chip 101 returns to the periphery of the wiring 203, one end of which is grounded on the second chip 201, and forms a closed loop.

[0029] 7, when a current (supplied to terminal 217 from a signal source, not shown) flows in the direction of the arrow in wiring 203, one end of which is grounded, in second chip 201 during device operation, the magnetic field (magnetic field) penetrating from the bottom to the top of the page through opening 106 in the wiring layer of first chip 101 passes through substrate 112 of first chip 101, passes around above wiring 203 of second chip 201, passes from the top to the bottom of the page through the SQUID loop including Josephson junctions 104a and 104b of first chip 101, passes under wiring 203 of second chip 201, and forms a closed loop returning from the bottom to the top of the page through opening 106 in the wiring layer of first chip 101. Because the closed loop of the magnetic field related to coupling with the SQUID loop all has components oriented in the same direction, it is possible to increase the magnetic field coupling by superposing the magnetic fields.

[0030] Generally, as the distance between the wiring (coil) that passes current and generates a magnetic field and the SQUID loop increases, the magnetic field coupling between the wiring (coil) and the SQUID loop decreases. According to the present disclosure, even if the distance between the wiring 203 of the second chip 201 and the SQUID loop is increased, it is possible to maintain the same magnetic field coupling or suppress a decrease in magnetic field coupling depending on the magnitude of the applied current, etc. Alternatively, it is possible to increase the magnetic field coupling and reduce the applied current. Furthermore, by increasing the distance between the wiring 203 of the second chip 201 and the SQUID loop, it is possible to suppress the influence of unintended capacitance.

[0031] 8 is a diagram showing the results of simulating, using an electromagnetic field simulator, the magnetic field distribution around the opening 106 in the wiring layer 113 of the first chip 101. Note that since the magnetic field is an AC magnetic field, the direction of the arrow changes depending on the phase of the control current.

[0032] Generally, as the distance between the coil that applies the magnetic field and the quantum bit decreases, the internal Q value of the quantum bit deteriorates. According to the present disclosure, it is possible to increase the distance between the wiring 203 of the second chip 201 and the SQUID loop of the first chip 101 while maintaining the same magnetic field coupling, thereby increasing the distance between the wiring 203 and the quantum bit circuit 105 and improving the internal Q value of the quantum bit circuit 105 of the first chip 101.

[0033] 9A and 9B are diagrams illustrating the relationship between the distance between the wiring 203 of the second chip 201 and the SQUID of the first chip 101. FIG. 9A shows the distance d1 between the wiring 203 of the second chip 201 and the SQUID of the first chip 101. As shown in FIG. 9B, as the distance d1 increases, the magnetic field coupling decreases. As shown in FIG. 9C, as the distance d1 increases, the internal Q value of the quantum bit circuit 105 increases.

[0034] 10A and 10B are diagrams illustrating the relationship between the size (e.g., area) of the opening 106 in the wiring layer 113 of the first chip 101, the magnetic field coupling, and the internal Q value. The size of the opening 106 in FIG. 10A may be the area. As shown in FIG. 10B, as the size of the opening 106 increases, the magnetic field coupling increases and reaches a maximum at a certain size (e.g., area). After this, the magnetic field coupling decreases as the size of the opening 106 increases. As shown in FIG. 10C, as the size of the opening 106 increases, the internal Q value of the quantum bit circuit 105 decreases and reaches a minimum at a certain size (e.g., area). After this, the internal Q value of the quantum bit circuit 105 increases as the size of the opening 106 increases.

[0035] FIG. 11 illustrates the relationship between the overlap size between the opening 106 in the wiring layer 113 of the first chip 101 and the wiring 203 of the second chip, the magnetic coupling, and the internal Q value. The overlap size between the opening 106 in the wiring layer 113 of the first chip 101 and the wiring 203 of the second chip is represented by distance d2 in FIG. 11(A). As shown in FIG. 11(B), as distance d2 increases, the magnetic coupling increases (note that the rate of increase (slope) of the magnetic coupling changes at a certain value of distance d2). As shown in FIG. 11(C), as distance d2 increases, the internal Q value of the quantum bit circuit 105 decreases (note that the rate of decrease of the internal Q value changes at a certain value of distance d2). With respect to distance d2, there is a trade-off between the magnetic coupling and the internal Q value; as one increases, the other decreases.

[0036] Although the shape of opening 106 in wiring layer 113 of first chip 101 is exemplified as a rectangle whose long sides are parallel to the longitudinal direction of wiring 203, it may be a square or an approximately rectangular shape, or may be a rectangle whose short sides are parallel to the longitudinal direction of wiring 203 of second chip 201. Alternatively, it may be a circle, an ellipse, a triangle, a polygon, or the like. In the case of a triangular opening 106, the side parallel to the longitudinal direction of wiring 203 may be the base.

[0037] 12 is a diagram schematically showing the layout of wires 203 of first wiring layer 213 of second chip 201, ground pattern 202 to which one end of wire 203 is connected, and terminal 217 to which the other end of wire 203 is connected. There are no restrictions on the shape of area 204A (area from which the wiring layer (metal layer) has been removed) surrounded by wire 203 and ground pattern 202, as long as it overlaps with the SQUID loop of first chip 101 when wiring layer 113 of first chip 101 is mounted opposite. There are also no restrictions on the shape (pattern) below the dashed dotted line in FIG. 12 and it is arbitrary.

[0038] The above-described embodiment is subject to the following additional notes (but is not limited to the following):

[0039] (Supplementary Note 1) A superconducting quantum circuit device comprises: a first chip including a quantum bit circuit including a SQUID (superconducting quantum interference device) in an interconnection layer; and a second chip having an interconnection layer on a first surface thereof, the interconnection layer on the first surface being arranged opposite the interconnection layer of the first chip, the interconnection layer of the first chip having an opening adjacent to the SQUID of the quantum bit circuit, the interconnection layer on the first surface of the second chip having wiring having one end connected to a terminal and the other end connected to ground, the wiring extending along the quantum bit circuit of the first chip in at least a region of the first chip facing the opening, and having the other end connected to a ground pattern.

[0040] (Supplementary Note 2) In the superconducting quantum circuit device of Supplementary Note 1, in the first chip, the SQUID includes a Josephson junction having one end connected to the superconducting wiring of the quantum bit circuit and the other end connected to a ground electrode.

[0041] (Supplementary Note 3) In the superconducting quantum circuit device of Supplementary Note 1 or 2, in the first chip, the superconducting wiring of the quantum bit circuit, the ground electrode, and two Josephson junctions connected in parallel between the superconducting wiring and the ground electrode form the SQUID loop, and the ground electrode is positioned furthest from the quantum bit circuit.

[0042] (Supplementary Note 4) In the superconducting quantum circuit device of any one of Supplementary Notes 1 to 3, in the first chip, the opening is disposed adjacent to the ground electrode.

[0043] (Appendix 5) In the superconducting quantum circuit device of any one of Appendices 1 to 4, in the second chip, the area surrounded by the wiring and the ground pattern to which the other end of the wiring is connected includes or partially overlaps with the area in which the SQUID of the first chip is arranged.

[0044] (Supplementary Note 6) In the superconducting quantum circuit device of any one of Supplements 1 to 5, in the second chip, the wiring is bent at a position overlapping the opening of the first chip, crosses the opening parallel to the SQUID of the quantum bit circuit of the first chip, and is connected to the ground pattern disposed on the opening end side.

[0045] (Appendix 7) In the superconducting quantum circuit device of any one of Appendices 1 to 6, in the second chip, the ground pattern to which the other end of the wiring is connected surrounds at least the region of the first chip where the SQUID is located, extends beyond the bend in the wiring, and is installed alongside the wiring toward the terminal to which the wiring is connected.

[0046] (Appendix 8) In the superconducting quantum circuit device of any one of Appendices 1 to 7, in the second chip, the ground pattern to which the other end of the wiring is connected has a connection portion with the other end of the wiring that partially overlaps with the region of the opening in the wiring layer of the first chip.

[0047] (Appendix 9) In operation of the superconducting quantum circuit device of any of Appendices 1 to 8, a signal from a signal source is supplied to the terminal of the second chip, and a magnetic field generated by a current flowing in the wiring passes through the opening of the first chip and penetrates the SQUID loop of the quantum bit circuit.

[0048] The disclosure of Patent Document 1 is incorporated herein by reference. Modifications and adjustments of the embodiments and examples are possible within the scope of the entire disclosure of the present invention (including the scope of the claims), and further based on the basic technical concept thereof. Furthermore, various combinations and selections of the various disclosed elements (including each element of each claim, each element of each example, each element of each drawing, etc.) are possible within the scope of the claims of the present invention. In other words, the present invention naturally includes various modifications and alterations that would be possible for a person skilled in the art based on the entire disclosure, including the scope of the claims, and the technical concept thereof. [Explanation of symbols]

[0049] 101 First Chip 102 Ground Plane 103 Wiring (electrode) 104a, 104b Josephson junction 105 qubit circuits 106 Aperture 107 Wiring 108 Ground electrode 112 PCB 113 Wiring layer 201 Second Chip 202 Grand Pattern 203 Wiring Areas 204 and 204A (areas where wiring metal has been removed) 212 Substrate 213 First wiring layer 214 Bump 215 Second wiring layer 216 Through Via 217 terminals (pads) 218 terminals (pads) 301 First Chip 302 Substrate 303 Wiring layer 304 Bump 311 Second Chip 312 Substrate 313 Wiring layer 501, 501A, 501B Ground plane 503, 503A, 503B Inner Loop Edge 504, 504A, 504B Part 1 505 outer loop edge 506 Part 2 507 Gap 508, 508A, 508B Loop section 509, 511 width 510, 510A, 510B SQUID area 512, 512A, 512B inner ring area 513 Ground Plane 514 Josephson junction 516 Edge 517 Wiring (Superconductor) 521 Magnetic Field (Magnetic Lines of Force)

Claims

1. a first chip including a quantum bit circuit including a SQUID (superconducting quantum interference device) in a wiring layer; a second chip having a wiring layer on a first surface, the wiring layer on the first surface being disposed opposite the wiring layer of the first chip; Equipped with the wiring layer of the first chip has an opening adjacent to the SQUID of the quantum bit circuit; the wiring layer on the first surface of the second chip includes wiring having one end connected to a terminal and the other end connected to ground; the wiring extends along the quantum bit circuit of the first chip in at least a region of the first chip facing the opening, and is connected to a ground pattern at the other end.

2. 2. The superconducting quantum circuit device according to claim 1, wherein in the first chip, the SQUID includes a Josephson junction having one end connected to the superconducting wiring of the quantum bit circuit and the other end connected to a ground electrode.

3. In the first chip, the superconducting wiring of the quantum bit circuit, the ground electrode, and two Josephson junctions connected in parallel between the superconducting wiring and the ground electrode form a loop of the SQUID; The superconducting quantum circuit device according to claim 2 , wherein the ground electrode is disposed farthest from the quantum bit circuit.

4. 4. The superconducting quantum circuit device according to claim 3, wherein in the first chip, the opening is disposed adjacent to the ground electrode.

5. 2. The superconducting quantum circuit device according to claim 1, wherein in the second chip, an area surrounded by the wiring and the ground pattern to which the other end of the wiring is connected includes or partially overlaps with an area in which the SQUID of the first chip is arranged.

6. 2. The superconducting quantum circuit device according to claim 1, wherein in the second chip, the wiring is bent at a position overlapping with the opening of the first chip, crosses the opening parallel to the SQUID of the quantum bit circuit of the first chip, and is connected to the ground pattern disposed on the opening end side.

7. 7. The superconducting quantum circuit device according to claim 6, wherein in the second chip, the ground pattern to which the other end of the wiring is connected surrounds at least an area of ​​the first chip in which the SQUID is arranged, extends beyond the bent position of the wiring, and is arranged alongside the wiring toward the terminal to which the wiring is connected.

8. 7. The superconducting quantum circuit device according to claim 6, wherein in the second chip, the ground pattern to which the other end of the wiring is connected has a connection portion with the other end of the wiring that partially overlaps with a region of the opening in the wiring layer of the first chip.

9. 2. The superconducting quantum circuit device according to claim 1, wherein, during operation, a signal from a signal source is supplied to the terminal of the second chip, and a magnetic field generated by a current flowing in the wiring passes through the opening of the first chip and penetrates the loop of the SQUID of the quantum bit circuit.

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