Level voltage generation circuit, display driver, and display device

Abstract

To provide a level voltage generation circuit, a display driver, and a display device with which it is possible to suppress a circuit area and generate a plurality of highly accurate level voltages.SOLUTION: The level voltage generation circuit comprises: a resistor string for outputting a plurality of level voltages having different voltage levels from each of a plurality of taps; a reference voltage generation circuit for generating m reference voltages having different voltage values respectively along a gamma characteristic; and a first to an m-th gamma buffers for individually amplifying the m reference voltages to generate m gamma voltages and outputting these to m taps. At least one gamma buffer has an offset cancellation amplifier including an offset cancellation circuit for removing an offset having occurred to the gamma voltage that it outputted itself, and a control signal output circuit for generating the control signal with two voltages as the binary, and outputs the control signal to the offset cancellation circuit. The two voltages are selected from among the m gamma voltages and the power supply voltages, and have a voltage difference lower than the power supply voltages.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a voltage generating circuit that generates a plurality of voltages with different voltage levels, a display driver, and a display device. [Background technology]

[0002] A liquid crystal or organic EL display device includes a display panel on which a plurality of gate lines extending in the horizontal direction of a two-dimensional screen and a plurality of source lines extending in the vertical direction of the two-dimensional screen are arranged, a gate driver that drives the gate lines, and a source driver that drives the source lines.

[0003] The source driver includes a decoder that receives pixel data pieces representing the luminance level of each pixel based on a video signal and converts each of the pixel data pieces into a gradation voltage having a voltage value corresponding to the luminance level indicated by the pixel data piece. The decoder selects one of the gradation voltages generated by the gradation voltage generator that corresponds to the luminance level indicated by the pixel data piece and supplies the selected gradation voltage to a source line of the display panel.

[0004] As the above-mentioned grayscale voltage generating unit, one including first and second ladder resistors each formed by connecting a plurality of resistors in series, a selector, and a group of gamma amplifiers has been proposed (see, for example, FIG. 3 of Patent Document 1). The selector shown in FIG. 3 of Patent Document 1 selects six voltages (V2 to V7) having voltage values ​​according to desired gamma characteristics from among the plurality of voltages generated by the first ladder resistor 107, and supplies each of the voltages to each of the gamma amplifiers (A1 to A6). Here, the group of voltages amplified by each gamma amplifier is applied to each of the desired taps of the second ladder resistor 153, and at this time, the voltages generated at each tap of the second ladder resistor are output as the above-mentioned plurality of grayscale voltages. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-8958 Summary of the Invention [Problem to be solved by the invention]

[0006] Incidentally, with the recent trend toward larger screens and higher definition display panels, source drivers are constructed by dividing them into multiple IC chips, each of which is arranged side by side along the horizontal direction of the two-dimensional screen of the display panel.

[0007] Here, the amount of error relative to the desired voltage value for each gradation voltage generated within each IC chip may differ for each IC chip due to manufacturing variations, etc., so if the difference in the amount of error is large, it may be perceived as unevenness in the image display.

[0008] Therefore, it is desirable for the grayscale voltage generating section to generate highly accurate grayscale voltages with a small amount of error relative to the desired voltage value.

[0009] In order to improve the accuracy of the gradation voltage, it is conceivable to increase the size of the transistors that make up the gamma amplifiers described above. However, this would result in a corresponding increase in the circuit area required to construct multiple gamma amplifiers.

[0010] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a level voltage generating circuit, a display driver, and a display device that are capable of generating a plurality of desired high-precision level voltages while minimizing the circuit area. [Means for solving the problem]

[0011] The level voltage generating circuit according to the present invention includes a resistor string including a plurality of resistors connected in series with each other via a plurality of taps, and outputs a plurality of level voltages having different voltage levels from each of the taps; a reference voltage generating unit that generates m (m is an integer of 2 or more) reference voltages each having a different voltage value according to a desired gamma characteristic; and first to mth gamma voltage generating units that receive the m reference voltages individually and operate by receiving the supply of two power supply voltages to amplify the m reference voltages individually, generate the m voltages obtained as m gamma voltages, and output the m voltages to m taps out of the plurality of taps. and a buffer, wherein at least one of the first to mth gamma buffers has an offset cancellation amplifier including an offset cancellation circuit that removes an offset voltage occurring in the gamma voltage output by the gamma buffer itself in accordance with a binary control signal, and a control signal output circuit that receives the m gamma voltages output by the first to mth gamma buffers including the gamma buffer itself and two voltages selected from the two power supply voltages, the voltage difference between which is lower than the difference between the two power supply voltages, generates the control signal in which the two voltages are binary-valued, and outputs the control signal to the offset cancellation circuit.

[0012] A display driver according to the present invention is a display driver including the above-described level voltage generation circuit as a grayscale voltage generation circuit, wherein the offset cancellation circuit includes a first capacitive element, and the offset cancellation amplifier sequentially executes a first step of storing the offset voltage or the gamma voltage generating the offset voltage in the first capacitive element based on the control signal, and a second step of holding the voltage stored in the first capacitive element and supplying a gamma voltage obtained by removing the offset voltage from the gamma voltage output by the first gamma buffer to the tap of the resistor string, and wherein a control signal output circuit generates the control signal having one of the two voltages in the first step and generates the control signal having the other of the two voltages in the second step, and wherein the first step is performed within a vertical blanking period of a frame period of a video signal.

[0013] The display device according to the present invention comprises a display panel including a plurality of data lines on which a plurality of display cells are arranged, and a display driver including the above-described level voltage generation circuit as a gradation voltage generation circuit, the plurality of level voltages output from the level voltage generation circuit being a plurality of gradation voltages, and for each pixel based on a video signal, selecting a gradation voltage from the plurality of gradation voltages corresponding to the luminance level indicated by the pixel, and outputting a drive signal having the selected gradation voltage to the data line. [Effects of the Invention]

[0014] In the present invention, a gamma buffer equipped with an offset cancellation circuit is employed as the gamma buffer used in a level voltage generation circuit that generates a plurality of level voltages by applying a plurality of gamma voltages output from a plurality of gamma buffers to a resistor string.

[0015] Furthermore, in the present invention, a low-amplitude control signal is generated as a binary control signal for controlling the operation of the offset cancellation circuit, taking two voltages, of the multiple gamma voltages output by the multiple gamma buffers including the offset cancellation circuit itself and two power supply voltages, whose voltage difference is lower than the difference between the two power supply voltages. By controlling the on / off of the transistor that controls the offset cancellation circuit using this low-amplitude control signal, the amount of feedthrough due to coupling of the parasitic capacitance of the transistor can be suppressed, and the offset voltage associated with that feedthrough can be reduced. This makes it possible to generate multiple highly accurate level voltages that match the desired gamma characteristics without increasing the capacitance of the capacitive elements that make up the offset cancellation circuit in order to achieve high accuracy.

[0016] Therefore, according to the present invention, it is possible to suppress an increase in the circuit scale and to output a plurality of desired voltage levels with high precision. [Brief explanation of the drawings]

[0017] [Figure 1]1 is a block diagram showing a schematic configuration of a display device 100 equipped with a display driver including a level voltage generating circuit according to the present invention. [Figure 2] 2 is a block diagram schematically showing the internal configuration of a data driver 103. FIG. [Figure 3] 3 is a circuit diagram showing an example of the internal configuration of a grayscale voltage generating circuit 122. FIG. [Figure 4A] FIG. 10 is a block diagram showing a gamma buffer unit GAG_1 as an example of the internal configuration of the gamma buffer unit GAG. [Figure 4B] FIG. 10 is a block diagram showing a gamma buffer unit GAG_2 as another internal configuration of the gamma buffer unit GAG. [Figure 5] FIG. 2 is a circuit diagram showing the internal configuration of a gamma buffer GBk. [Figure 6] 10 is a time chart showing the waveforms of the switch signals S1, XS1, S2, and XS2, and the low-amplitude control signal SCk, and the transition of the state of the transistor 16. [Figure 7A] FIG. 1 is a schematic circuit diagram in which the on / off states of transistors 16 to 18, 21, and 22 of the gamma buffer GBk and the current paths are indicated by thick solid lines in the first step. [Figure 7B] FIG. 10 is a schematic circuit diagram in which the on / off states of transistors 16 to 18, 21, and 22 of the gamma buffer GBk and the current paths are indicated by thick solid lines in the second step. [Figure 8] FIG. 10 is a circuit diagram showing the configuration of a gamma buffer GBk_1 as a first modified example of the gamma buffer GBk. [Figure 9] FIG. 10 is a circuit diagram showing the configuration of a gamma buffer GBk_2 as a second modified example of the gamma buffer GBk. [Figure 10A] 10 is a cross-sectional view that schematically illustrates the cross-sectional structure of each of the transistors 16a to 16c, their mutual connection, and their respective states in a first step using the gamma buffer GBk_2. [Figure 10B] 10 is a cross-sectional view that schematically illustrates the cross-sectional structure of each of the transistors 16a to 16c, their mutual connection, and their respective states in a first step using the gamma buffer GBk_2. [Figure 11] FIG. 10 is a circuit diagram showing the configuration of a gamma buffer GBk_3 as a third modified example of the gamma buffer GBk. [Figure 12] FIG. 10 is a circuit diagram showing the configuration of a gamma buffer GBk_4 as a fourth modified example of the gamma buffer GBk. [Figure 13A] FIG. 10 is a schematic circuit diagram in which the on / off states of each transistor of the gamma buffer GBk_4 and the current paths are indicated by thick solid lines in the first step. [Figure 13B] FIG. 10 is a schematic circuit diagram in which the on / off states of each transistor of the gamma buffer GBk_4 and the current paths are indicated by thick solid lines during the transition from the first step to the second step. [Figure 14] 3 is a circuit diagram showing an example of the internal configuration of a grayscale voltage generating circuit 122. FIG. [Figure 15] 10 is a time chart showing waveforms of switch signals S1, XS1, S2, XS2, S1q, XS1q, S2q, and XS2q. [Figure 16] FIG. 10 is a block diagram showing another example of the internal configuration of the gamma buffer unit GAG_1. DETAILED DESCRIPTION OF THE INVENTION

[0018] The present invention will be described in detail below with reference to the drawings. [Example]

[0019] FIG. 1 is a block diagram showing a schematic configuration of a display device 100 equipped with a display driver including a level voltage generating circuit according to the present invention.

[0020] The display device 100 includes a display controller 101 , a gate driver 102 , a data driver 103 , and a display panel 200 .

[0021] The display panel 200 is made of, for example, a liquid crystal or organic EL display panel, and has gate lines GL1 to GLr (r is an integer of 2 or more) extending in the horizontal direction of the two-dimensional screen, and data lines DL1 to DLw (w is an integer of 2 or more) extending in the vertical direction of the two-dimensional screen. At each intersection of the gate lines GL1 to GLr and the data lines DL1 to DLw, a display cell (area surrounded by a dashed line) that displays red, green, or blue is formed.

[0022] The display controller 101 receives a video signal VD and supplies, to the gate driver 102, a gate timing signal indicating the timing at which to apply a gate selection signal to each of the gate lines GL1 to GLr, based on the video signal VD.

[0023] In addition, based on the video signal VD, the display controller 101 generates a video data signal DVS that includes various control signals including a clock signal, a load signal, etc., and a series of pixel data pieces that represent the brightness level of each pixel as a digital value, and supplies this to the data driver 103.

[0024] The gate driver 102 sequentially generates gate selection signals including at least one pulse for selecting a gate line in response to the gate timing signal supplied from the display controller 101, and supplies the gate selection signals to each of the gate lines GL1 to GLr of the display panel 200.

[0025] The data driver 103 takes in each of the pixel data pieces included in the video data signal DVS in units of lines (w / S pieces) divided by the number (S) of data drivers driving one horizontal scan line (w pieces), and converts each pixel data piece into a drive signal having a voltage value corresponding to the brightness level represented by each pixel data piece.The data driver 103 then supplies the generated (w / S) drive signals as drive signals G1 to Gw to data lines DL1 to DLw of the display panel 200, respectively.Note that FIG. 1 shows an example configuration of a display device 100 including one data driver (S=1).

[0026] 2 is a block diagram showing a schematic internal configuration of the data driver 103. The following will also be explained using an example in which the number of data drivers is 1 (S=1).

[0027] As shown in FIG. 2, the data driver 103 includes a control circuit 120, a data latch unit 121, a grayscale voltage generating circuit 122 as a level voltage generating circuit according to the present invention, a decoder unit 123, and an amplifier unit .

[0028] The control circuit 120 receives the video data signal DVS and extracts from the video data signal DVS various control signals including a horizontal synchronization signal, a vertical synchronization signal, a clock signal, a load signal, etc., and a series of pixel data fragments. The control circuit 120 supplies the extracted clock signal, load signal, and series of pixel data fragments to a data latch unit 121, and also supplies the extracted vertical synchronization signal to a grayscale voltage generation circuit 122 as a vertical synchronization signal Vsyn.

[0029] The data latch unit 121 sequentially captures each pixel data piece in the sequence of pixel data pieces at the timing of the clock signal in response to the load signal. Every time the data latch unit 121 captures w pixel data pieces, it outputs the w pixel data pieces to the decoder unit 123 as pixel data P1 to Pw.

[0030] The grayscale voltage generation circuit 122 generates grayscale voltages VR0 to VR(n-1) (n is an integer of 2 or more), each having a voltage value according to a specified gamma characteristic, and supplies the generated grayscale voltages VR0 to VR(n-1) to the decoder unit 123. In generating the grayscale voltages VR0 to VR(n-1), the grayscale voltage generation circuit 122 cancels the offset of an operational amplifier (described later) included therein for each frame period in accordance with the vertical synchronization signal Vsy.

[0031] The decoder unit 123 includes w decoders DEC that individually receive the pixel data P1 to Pw output from the data latch unit 121. Each of the decoders DEC receives the above-mentioned gradation voltages VR0 to VR(n-1) and selects, from the gradation voltages VR0 to VR(n-1), a gradation voltage having a voltage value corresponding to the luminance level indicated by the pixel data piece that it received. The decoder unit 123 receives the w gradation voltages selected by each decoder DEC and supplies gradation signals V1 to Vw having the respective voltage values ​​to the amplifier unit 124.

[0032] The amplifier section 124 amplifies the grayscale signals V1 to Vw individually and outputs the amplified signals to the data lines DL1 to DLw of the display panel 200 as the above-mentioned drive signals G1 to Gw.

[0033] The grayscale voltage generating circuit 122 will be described in detail below.

[0034] FIG. 3 is a circuit diagram showing an example of the internal configuration of the grayscale voltage generating circuit 122. As shown in FIG.

[0035] As shown in FIG. 3, the grayscale voltage generating circuit 122 includes amplifiers GA0 and GA1, first and second resistor strings LD1 and LD2, a gamma selector GSL, a gamma buffer unit GAG, and a control circuit CNT.

[0036] The amplifiers GA0 and GA1 are input gamma amplifiers, each consisting of, for example, a voltage follower operational amplifier whose inverting input terminal and output terminal are connected. The amplifier GA0 receives a first DC voltage VGMA0 at its non-inverting input terminal and applies a voltage having the same voltage value as the voltage VGMA0 to the node nda0. The amplifier GA1 receives a second DC voltage VGMA1, which has a voltage value lower than the voltage VGMA0, at its non-inverting input terminal and applies a voltage having the same voltage value as the voltage VGMA1 to the node nda1.

[0037] The resistor string LD1 consists of first to xth (x is an integer greater than or equal to 2) resistors connected in series between nodes nda0 and nda1, and supplies the voltages at each of the (x+1) connection points (called taps) of the first to xth resistors to the gamma selector GSL as reference voltages Rf0 to Rfx.

[0038] The control circuit CNT supplies a gamma characteristic designation signal de, which designates the desired gamma characteristic, to the gamma selector GSL. Furthermore, the control circuit CNT generates binary (logical level 0 or 1) switch signals S1, XS1, S2, and XS2 that control the offset cancellation operation in response to the vertical synchronization signal Vsyn, and supplies each of these to the gamma buffer unit GAG. The switch signal XS1 is the logical inversion signal of S1, and the switch signal XS2 is the logical inversion signal of S2.

[0039] The gamma selector GSL receives the reference voltages Rf0-Rfx and selects m (m is an integer equal to or greater than 2) reference voltages from among the reference voltages Rf0-Rfx, each having a voltage value in accordance with the gamma characteristics specified by the gamma characteristics specification signal de. The gamma selector GSL then outputs the selected m reference voltages as reference voltages VI0-VI(m-1), respectively. The reference voltages VI0-VI(m-1) have the following magnitude relationships:

[0040] VI0>VI1>VI2>,...,>VI(m-2)>VI(m-1) The gamma buffer unit GAG receives the reference voltages VI0 to VI(m-1), amplifies them individually, and generates the resulting voltages as gamma voltages VG0 to VG(m-1). The gamma voltages VG0 to VG(m-1) have the following magnitude relationships:

[0041] VG0>VG1>VG2>,..., >VG(m-2)>VG(m-1) The gamma buffer unit GAG applies the gamma voltages VG0 to VG(m-1) to each tap including one end and the other end of the resistor string LD2, as shown in FIG.

[0042] The second resistor string LD2 is composed of a series resistor group in which a plurality of resistors are connected in series. The resistor string LD2 outputs n voltages generated at n taps by gamma voltages VG0 and VG(m-1) applied to one end and the other end of the series resistor group, respectively, and gamma voltages VG1 to VG(m-2) applied to connection points (called taps) of the resistors, as the above-mentioned grayscale voltages VR0 to VR(n-1).

[0043] 4A and 4B are block diagrams showing GAG_1 and GAG_2 as an example of the internal configuration of the gamma buffer unit GAG.

[0044] As shown in FIGS. 4A and 4B, the gamma buffer units GAG_1 and GAG_2 include gamma buffers GB0 to GB(m-1) that individually receive reference voltages VI0 to VI(m-1). Each of the gamma buffers GB0 to GB(m-1) is a voltage follower consisting of an operational amplifier equipped with an offset cancellation circuit controlled by the above-mentioned switch signals S1, XS1, S2, and XS2, and operates by receiving a first power supply voltage VDD and a second power supply voltage VSS. Note that the first power supply voltage VDD is higher than the gamma voltage VG0, and the second power supply voltage VSS is lower than the gamma voltage VG(m-1). In FIGS. 4A and 4B, the first power supply voltage VDD and the second power supply voltage VSS supplied to each of the gamma buffers GB0 to GB(m-1) are omitted to avoid cluttering the drawings.

[0045] The gamma buffers GB0 to GB(m-1) individually amplify the reference voltages VI0 to VI(m-1), and apply the resulting voltages as gamma voltages VG0 to VG(m-1) to the respective taps of the resistor string LD2.

[0046] Each of the gamma buffers GB0 to GB(m-1) receives the gamma voltage VG output by itself and two gamma voltages VG from the group of gamma voltages output by each of the other gamma buffers GB in order to generate a binary control signal used to control the offset cancellation circuit by the switch signals S1 and XS1.

[0047] For example, in FIG. 4A , gamma buffers GB1 to GB(m-2) among gamma buffers GB0 to GB(m-1), excluding the gamma buffers at both ends, receive a gamma voltage higher than the gamma voltage they themselves output and a gamma voltage lower than the gamma voltage they themselves output. Among gamma buffers GB0 to GB(m-1), the gamma buffer that outputs the higher-voltage gamma voltage includes a P-channel transistor as a switching element for offset cancellation, while the gamma buffer that outputs the lower-voltage gamma voltage includes an N-channel transistor as a switching element for offset cancellation. In the example shown in FIG. 4 , gamma buffer GB1 receives a gamma voltage VG0 that is one step higher than the gamma voltage VG1 it outputs and a gamma voltage VG2 that is one step lower than the gamma voltage VG1. Furthermore, gamma buffer GB2 receives a gamma voltage VG1 that is one step higher than the gamma voltage VG2 it outputs and a gamma voltage VG3 that is one step lower than the gamma voltage VG2. Furthermore, the gamma buffer GB(m-2) receives a gamma voltage VG(m-3) that is one step higher than the gamma voltage VG(m-2) that it outputs, and a gamma voltage VG(m-1) that is one step lower than the gamma voltage VG(m-2). If the voltage difference between the gamma voltages by one step is small, the gamma buffer may receive a gamma voltage that is two steps away from the gamma voltage that it outputs. For convenience, the following embodiment shows a configuration example in which a gamma voltage that is one step away is received.

[0048] At this time, the gamma buffer GB0 receives a gamma voltage VG1 that is one level lower than the gamma voltage VG0 that it outputs. However, since there is no gamma voltage VG higher than this gamma voltage VG0, the gamma buffer GB0 uses the first power supply voltage VDD as a voltage that is one level higher than the gamma voltage VG0.

[0049] Furthermore, the gamma buffer GB(m-1) receives a gamma voltage VG(m-2) higher than the gamma voltage VG0(m-1) that it outputs. However, since there is no gamma voltage VG lower than this gamma voltage VG(m-1), the gamma buffer GB(m-1) uses the second power supply voltage VSS as a voltage lower than the gamma voltage VG(m-1).

[0050] Meanwhile, FIG. 4B shows a configuration example of a gamma buffer unit GAG_2 different from that shown in FIG. 4A. In FIG. 4B, among the gamma buffers GB0 to GB(m-1), each of the high-voltage gamma buffers GB0 to GBj (j is an integer from 0 to m-2) receives a gamma voltage output by itself and a gamma voltage lower than the gamma voltage output by itself. Each of the gamma buffers GB0 to GBj includes a P-channel transistor as a switching element related to the offset cancellation operation. In the example shown in FIG. 4B, the gamma buffer GB0 receives a gamma voltage VG0 output by itself and a gamma voltage VG1 that is one level lower than the gamma voltage VG0. Furthermore, the gamma buffer GB1 receives a gamma voltage VG1 output by itself and a gamma voltage VG2 that is one level lower than the gamma voltage VG1. Furthermore, among the gamma buffers GB0 to GB(m-1), the gamma buffers GB(j+1) to GB(m-1) on the lower voltage side each receive a gamma voltage that it outputs and a gamma voltage higher than the gamma voltage that it outputs. Each of the gamma buffers GB(j+1) to GB(m-1) includes an N-channel transistor as a switching element related to the offset cancellation operation. In the example shown in FIG. 4B, the gamma buffer GB(m-1) receives a gamma voltage VG(m-1) that it outputs and a gamma voltage VG(m-2) that is one level higher than the gamma voltage VG(m-1).

[0051] FIG. 5 is a circuit diagram showing an example of the internal configuration of the k-th (k is an integer from 1 to m-2) gamma buffer GBk selected from among the gamma buffers GB0 to GB(m-1) in FIG. 4A.

[0052] As shown in FIG. 5, the gamma buffer GBk includes an offset cancellation amplifier A1_k_1 including an offset cancellation circuit, and a control signal output circuit A2_k_1.

[0053] The offset cancellation amplifier A1_k_1 includes an amplifier stage 10, N-channel transistors 11 and 12, P-channel transistors 16 to 18 which are of the opposite conductivity type to the transistors 11 and 12, a capacitor Ca as a capacitive element, and a current source Id.

[0054] The transistor 11 receives at its gate a reference voltage VIk (k is an integer between 1 and m-2) supplied from the gamma selector GSL via a node nd1. The source of the transistor 11 is connected to a current source Id, and the drain of the transistor 11 is connected to the amplifier stage 10 via a node nd11.

[0055] The transistor 12 receives at its gate a gamma voltage VGk (k is an integer between 1 and m-2) output from the gamma buffer GBk via the transistor 16 and a node nd2. The source of the transistor 12 is connected to a current source Id, and the drain of the transistor 12 is connected to the amplifier stage 10 via a node nd12. The current source Id receives a power supply voltage VSS and draws a predetermined constant current (tail current) from the sources of the transistors 11 and 12.

[0056] With this configuration, the differential pair (11, 12) consisting of the transistors 11 and 12 passes a current pair corresponding to the difference between the reference voltage VIk, which is the voltage of the node nd1, and the voltage of the node nd2 to the nodes nd11 and nd12.

[0057] The amplifier stage 10 receives the power supply voltages VDD and VSS to operate, and outputs a current corresponding to the difference between the currents flowing through the nodes nd11 and nd12 to the output node nd0 so that the voltage of the output node nd0 coincides with the reference voltage VIk. At this time, the output node nd0 is connected to the tap Tk of the resistor string LD2, and the voltage of the output node nd0 is applied to the tap Tk of the resistor string LD2 as the gamma voltage VGk.

[0058] One end of the source and drain of the transistor 16 is connected to the output node nd0, and the other end of the source and drain is connected to a node nd2. The transistor 16 receives at its gate a low-amplitude control signal SCk supplied from the control signal output circuit A2_k_1, and is turned off when the low-amplitude control signal SCk has a high voltage corresponding to logic level 1. On the other hand, when the low-amplitude control signal SCk has a low voltage corresponding to logic level 0, the transistor 16 is turned on and supplies the voltage of the output node nd0 to the gate of the transistor 12 via the node nd2.

[0059] One end of the source and drain of the transistor 17 is connected to the gate of the transistor 11 via the node nd1, and the other end of the source and drain is connected to a node nd5. The transistor 17 also receives at its gate a switch signal XS2 supplied from the control circuit CNT, and is turned off when the switch signal XS2 has a high voltage corresponding to a logic level 1. On the other hand, when the switch signal XS2 has a low voltage corresponding to a logic level 0, the transistor 17 is turned on and connects the node nd1 to the node nd5.

[0060] One end of the source and drain of the transistor 18 is connected to the output node nd0, and the other end of the source and drain is connected to a node nd5. The transistor 18 also receives at its gate a switch signal S2 supplied from the control circuit CNT, and is turned off when the switch signal S2 has a high voltage corresponding to a logic level 1. On the other hand, when the switch signal S2 has a low voltage corresponding to a logic level 0, the transistor 18 is turned on, and connects the output node nd0 to the node nd5.

[0061] The capacitor Ca has one end connected to the node nd2 and the other end connected to a node nd5.

[0062] The differential pair (11, 12) and the amplifier stage 10 described above constitute an operational amplifier that is the core of the gamma buffer GBk, and the capacitor Ca and the transistors 16 to 18, each serving as a switch element, form an offset cancellation circuit that removes the offset of the operational amplifier.

[0063] The control signal output circuit A2_k_1 includes P-channel transistors 21 and 22.

[0064] The transistor 21 receives the gamma voltage VG(k+1) output by the gamma buffer GB(k+1) to the tap T(k+1) of the resistor string LD2 at one end of its source and drain, and receives the switch signal S1 supplied from the control circuit CNT at its gate. However, the transistor 21 of the gamma buffer GB(m-1) receives the power supply voltage VSS at one end of its source and drain.

[0065] The transistor 22 receives the gamma voltage VG(k-1) output by the gamma buffer GB(k-1) to the tap T(k-1) of the resistor string LD2 at one end of its source and drain, and receives the switch signal XS1 supplied from the control circuit CNT at its gate. However, the transistor 22 of the gamma buffer GB0 receives the power supply voltage VDD at one end of its source and drain.

[0066] Furthermore, the other ends of the sources and drains of the transistors 21 and 22 are commonly connected to the gate of the transistor 16 .

[0067] The gamma voltages VG(k-1), VGk, and VG(k+1) and the power supply voltages VDD and VSS have the following magnitude relationships.

[0068] VDD>VG(k-1)>VGk>VG(k+1)>VSS Also, the voltage difference between the gamma voltage VGk and the gamma voltage VG(k+1) is higher than the threshold voltage of the transistor 16 .

[0069] Here, the transistor 21 is turned off when the switch signal S1 received at its gate has a power supply voltage VDD corresponding to logic level 1. On the other hand, when the switch signal S1 has a power supply voltage VSS corresponding to logic level 0, the transistor 21 is turned on and supplies a signal having the gamma voltage VG(k+1) as the low-amplitude control signal SCk to the gate of the transistor 16. As a result, the transistor 16 is controlled to be turned on.

[0070] On the other hand, when the switch signal XS1 received at its gate has the power supply voltage VDD corresponding to logic level 1, the transistor 22 is turned off. On the other hand, when the switch signal XS1 has the power supply voltage VSS corresponding to logic level 0, the transistor 22 is turned on and supplies a signal having the gamma voltage VG(k-1) as the low-amplitude control signal SCk to the gate of the transistor 16. As a result, the transistor 16 is controlled to be turned off.

[0071] The operation of the k-th (k is an integer from 1 to m-2) gamma buffer GBk shown in FIG. 5 is selected from among the gamma buffers GB0 to GB(m-1) and will be described below.

[0072] First, the control circuit CNT generates switch signals S1, XS1, S2, and XS2 that control the operation of the offset cancellation circuits (16 to 18, Ca) in accordance with the vertical synchronization signal (Vsyn) included in the video data signal DVS, and supplies them to the gamma buffer GBk.

[0073] FIG. 6 is a time chart showing the waveforms of the switch signals S1, XS1, S2, and XS2 and the low-amplitude control signal SCk in FIG. 5, and the transition of the state of the transistor 16. In FIG.

[0074] During the vertical blanking period of each frame (from time t0 to time t1), the switch signals S1 and XS2 transition from, for example, logic level 1 (VDD) that indicates an OFF state to logic level 0 (VSS) that indicates an ON state at time ts, and maintain that state until time th within the vertical blanking period (step 1).Then, the switch signals S1 and XS2 transition to logic level 1 (VDD) that indicates an OFF state at time th, and maintain that state until time ts within the next vertical blanking period (step 2).

[0075] On the other hand, the switch signals S2 and XS1 transition from, for example, logic level 0 (VSS) that prompts an ON state to logic level 1 (VDD) that prompts an OFF state at time ts during the vertical blanking period of each frame period, and maintain that state until time th within the vertical blanking period (step 1).Then, the switch signals S2 and XS1 transition to logic level 0 (VSS) that prompts an ON state at time th, and maintain that state until time ts within the next vertical blanking period (step 2).

[0076] In this way, each of the switch signals S1, XS1, S2, and XS2 is a binary signal with a relatively large amplitude whose signal level changes between the power supply voltage VDD and the power supply voltage VSS. 6, the switch signals XS1 and S2 are nearly synchronized signals, but strictly speaking, it is preferable to control them so that at time th, the change in the low-amplitude control signal SCk that changes the transistor 16 to the off state occurs before or simultaneously with the change in the switch signal S2 that changes the transistor 18 to the on state. In other words, since it is the switch signal XS1 that changes the low-amplitude control signal SCk at time th, the timing of the change in the switch signal S1X near time th is set to be slightly before the timing of the change in the switch signal S2.

[0077] Next, the offset cancel operation performed in each of the gamma buffers GB1 to GBm in response to the switch signals S1 (XS2) and S2 (XS1) will be described. [1st step] FIG. 7A is a schematic circuit diagram in which the on / off states of the transistors 16 to 18, 21, and 22 of the gamma buffer GBk in the first step shown in FIG. 6 and the current paths are indicated by thick solid lines.

[0078] As shown in FIG. 7A, in the first step, transistors 17 and 21 are turned on, and transistors 18 and 22 are turned off.

[0079] When the transistor 21 is turned on, a low-amplitude control signal SCk having the gamma voltage VG(k+1) is supplied to the gate of the transistor 16. At this time, the gamma voltage VG(k+1) is lower than the gamma voltage Vk and the voltage difference therebetween is higher than the threshold voltage of the transistor 16, so the transistor 16 is turned on.

[0080] Therefore, when transistor 16 is turned on, the voltage of output node nd0 is applied as a feedback voltage to one end of capacitor Ca as well as to the gate of transistor 12 via transistor 16, as shown by the thick solid line in Fig. 7A. Furthermore, in the first step, when transistor 17 is turned on and transistor 18 is turned off as described above, the gates of transistors 11 and 12 of the differential pair are connected to each other via capacitor Ca, as shown by the thick solid line in Fig. 7A.

[0081] In this case, if the offset voltage of the offset cancellation amplifier A1_k_1 occurs in the voltage of the output node nd0, the voltage on the node nd2 becomes a voltage (VIk+Voff) obtained by adding an offset voltage Voff, which is the amount of offset, to the reference voltage VIk that should originally be the voltage of the output node nd0. As a result, a voltage (VIk+Voff) is applied to one end of the capacitor Ca, and the reference voltage VIk is applied to the other end, and the offset voltage Voff is accumulated in the capacitor Ca.

[0082] That is, in the first step, the offset voltage occurring in the voltage of the output node nd0 is detected. [Second process] FIG. 7B is a schematic circuit diagram in which the on / off states of the transistors 16 to 18, 21 and 22 of the gamma buffer GBk and the current paths are indicated by thick solid lines during the second step shown in FIG. 6, that is, during normal operation.

[0083] As shown in FIG. 7B, in the second step, transistors 18 and 22 are turned on, and transistor 17 is turned off.

[0084] When the transistor 22 is turned on, a low-amplitude control signal SCk having the gamma voltage VG(k-1) is supplied to the gate of the transistor 16. At this time, since the gamma voltage VG(k-1) is higher than the gamma voltage Vk, the transistor 16 is turned off.

[0085] Therefore, with transistor 18 turned on and transistors 16 and 17 turned off, as shown by the thick solid line in Figure 7B, reference voltage VIk is applied to the gate of transistor 11 of the differential pair, and the voltage of output node nd0 is supplied to the gate of transistor 12 via transistor 18 and capacitor Ca.

[0086] As a result, the offset voltage Voff occurring in the voltage of the output node nd0 is cancelled out by the offset voltage Voff held in the capacitor Ca.

[0087] Therefore, the gamma buffer GBk can output a highly accurate voltage from which the offset (Voff) has been removed, that is, a gamma voltage VGk having a voltage value equal to the voltage value of the input reference voltage VIk.

[0088] Furthermore, in the gamma buffer GBk, the control signal output circuit A2_k_1 controls, from on to off, the transistor 16 that holds the voltage accumulated in the first step at node nd2, which is the transistor that has the greatest effect on the offset voltage among the transistors involved in the offset cancellation operation, using a low-amplitude control signal SCk.

[0089] That is, when the control signal output circuit A2_k_1 turns on the transistor 16 using the switch signals S1 and XS1, it supplies a low-amplitude control signal SCk having the gamma voltage VG(k+1) to the gate of the transistor 16 via the transistor 21. On the other hand, when the transistor 16 is turned off, the control signal output circuit A2_k_1 supplies a low-amplitude control signal SCk having the gamma voltage VG(k-1) to the gate of the transistor 16 via the transistor 22.

[0090] Therefore, the transistor 16 is controlled to be on and off by a low-amplitude control signal SCk consisting of gamma voltages VG(k+1) and VG(k-1), which has a smaller amplitude than the high-amplitude control signal consisting of the power supply voltages VDD and VSS.

[0091] As a result, when transitioning from the first step to the second step shown in Figure 6, the feedthrough caused by the parasitic capacitance of the transistor 16 is reduced compared to when the transistor 16 is transitioned from an on to an off state using a control signal of high amplitude (VDD to VSS), making it possible to output a highly accurate gamma voltage VGk.

[0092] Here, feedthrough refers to fluctuations in the charge in the parasitic capacitance of the transistor 16 due to capacitive coupling between the gate and drain (source) of the transistor 16, causing fluctuations in the voltage stored at the node nd2. In particular, if the amplitude of the control signal supplied to the gate of the transistor 16 is large, fluctuations in the charge in the parasitic capacitance described above also become large when the level of the control signal transitions, causing a problem in that an offset voltage is generated in the voltage held at the node nd2.

[0093] Therefore, in the gamma buffer GBk, the control signal output circuit A2_k_1 generates a binary signal representing the gamma voltages VG(k+1) and VG(k-1), whose voltage difference is lower than the power supply voltage VDD, as a binary signal (logical levels 0, 1) as a low-amplitude control signal SCk for controlling the transistor 16.

[0094] This suppresses the amount of charge fluctuation at the node nd2 due to capacitive coupling in the transistor 16, making it possible to output a highly accurate gamma voltage VGk in which the offset voltage associated with the amount of charge fluctuation is suppressed.

[0095] Therefore, the gamma buffer GBk shown in FIG. 5 can generate gamma voltages that conform to desired gamma characteristics with high precision without increasing the size of each of the transistors that make up the gamma buffer GBk.

[0096] Therefore, the grayscale voltage generating circuit 122 can generate grayscale voltages VR0 to VR(n-1) as a plurality of level voltages in accordance with the desired gamma characteristics while minimizing the circuit area.

[0097] In the above embodiment, the low-amplitude control signal SCk is generated using the gamma voltages VG(k+1) and VG(k-1). However, the low-amplitude control signal SCk may be generated using the gamma voltage VG output by the gamma buffer GBk itself and the gamma voltage VG(k+1).

[0098] FIG. 5 is a circuit diagram showing an example of the internal configuration of the k-th (k is an integer from 1 to m-2) gamma buffer GBk selected from among the gamma buffers GB0 to GB(m-1) in FIG. 4A.

[0099] Fig. 8 is a circuit diagram showing the configuration of a gamma buffer GBk_1 as a first modified example of the gamma buffer GBk that has been made in consideration of the above points. Note that the gamma buffer GBk_1 in Fig. 8 is also any gamma buffer on the high-voltage side among the gamma buffers GB0 to GB(m-1) in Fig. 4B.

[0100] In the configuration shown in FIG. 8, a control signal output circuit A2_k_2 is used instead of the control signal output circuit A2_k_1 shown in FIG. 5, and the other configurations are the same as those shown in FIG.

[0101] Therefore, the configuration of the control signal output circuit A2_k_2 and the effects of employing the control signal output circuit A2_k_2 will be described below.

[0102] The control signal output circuit A2_k_2 has transistors 21 and 22, similar to the control signal output circuit A2_k_1.

[0103] However, in the control signal output circuit A2_k_2, one end of the source and drain of the transistor 22 is connected to the tap Tk of the resistor string LD2. That is, the gamma voltage VGk output by the gamma buffer GBk_1 itself, rather than the gamma voltage VG(k-1), is applied to the drain of the transistor 22.

[0104] Therefore, with this configuration, when the control signal output circuit A2_k_2 turns on the transistor 16 using the switch signals S1 and XS1, it supplies a low-amplitude control signal SCk having the gamma voltage VG(k+1) to the gate of the transistor 16 via the transistor 21, just like the control signal output circuit A2_k_1.

[0105] On the other hand, when the transistor 16 is turned off, the control signal output circuit A2_k_2 supplies a low-amplitude control signal SCk having the gamma voltage VGk to the gate of the transistor 16 via the transistor 22.

[0106] As a result, the transistor 16 is controlled to be on and off by a low-amplitude control signal SCk having an even smaller amplitude than when the control signal output circuit A2_k_1 shown in FIG. 5 is employed, thereby making it possible to further reduce feedthrough.

[0107] Therefore, the configuration of the gamma buffer GBk_1 shown in FIG. 8 makes it possible to output the gamma voltage VGk with high accuracy.

[0108] FIG. 9 is a circuit diagram showing the configuration of a gamma buffer GBk_2 as a second modification of the gamma buffer GBk. As explained above, there is a problem in that the parasitic capacitance coupling between the gate and drain (source) of the transistor constituting the switch element causes an offset voltage to be generated in the voltage held at node nd2. In addition to this capacitive coupling, there is also a problem in that when the transistor constituting the switch element changes from the on state to the off state, the charge in the channel moves to the drain or source side as the channel disappears, increasing the offset voltage. FIG. 9 shows an example of the configuration of a gamma buffer that not only addresses the above-mentioned capacitive coupling but also improves the problem associated with the movement of charge in the channel, enabling even more accurate voltage output.

[0109] In the configuration shown in FIG. 9, an offset cancellation amplifier A1_k_2 is used instead of the offset cancellation amplifier A1_k_1 described above, and a control signal output circuit A2_k_3 is used instead of the control signal output circuit A2_k_1 described above.

[0110] In this case, the offset cancellation amplifier A1_k_2 has the same configuration as that shown in FIG. 5, except that a switch circuit 20 is used instead of the transistor 16 shown in FIG.

[0111] Therefore, the configurations of the switch circuit 20 and the control signal output circuit A2_k_3, and the effects resulting from the adoption of these switch circuit 20 and control signal output circuit A2_k_3 will be described below.

[0112] The switch circuit 20 includes P-channel transistors 16a, 16b, and 16c.

[0113] The transistor 16a has one end of its source and drain connected to the output node nd0, and the other end of its source and drain connected via a node nd2 to the gate of the transistor 12. The transistor 16a also receives at its gate the low-amplitude control signal SCk supplied from the control signal output circuit A2_k_3.

[0114] The transistor 16b has one of its source and drain connected to the output node nd0, and the other of its source and drain connected to one end of the capacitor Ca via a node nd2a. The transistor 16b also receives the low-amplitude control signal SCk at its gate.

[0115] The transistor 16c has one end of its source and drain connected to the node nd2, and the other end of its source and drain connected to one end of the capacitor Ca via the node nd2a. The transistor 16c also receives at its gate the inverted low-amplitude control signal XSCk supplied from the control signal output circuit A2_k_3.

[0116] The control signal output circuit A2_k_3 includes P-channel transistors 23 and 24 in addition to the transistors 21 and 22 included in the control signal output circuit A2_k_1.

[0117] The transistor 23 receives, at one end of its source and drain, the gamma voltage VG(k+1) output by the gamma buffer GB(k+1) to the tap T(k+1) of the resistor string LD2. The transistor 23 also has its drain connected to the drain of the transistor 24, and receives, at its gate, the switch signal XS1 supplied from the control circuit CNT.

[0118] The transistor 24 receives at one end of its source and drain the gamma voltage VG(k-1) output by the gamma buffer GB(k-1) to the tap T(k-1) of the resistor string LD2, and receives at its gate the switch signal S1 supplied from the control circuit CNT. Furthermore, the other ends of the sources and drains of the transistors 23 and 24 are commonly connected to the gate of the transistor 16c.

[0119] That is, in the control signal output circuit A2_k_3, the transistors 23 and 24 invert the logic level of the low-amplitude control signal SCk generated by the transistors 21 and 22 to generate an inverted low-amplitude control signal XSCk.

[0120] That is, when the transistors 21 and 22 of the control signal output circuit A2_k_3 receive the switch signal S1 of logic level 1 and the switch signal XS1 of logic level 0, they supply the low-amplitude control signal SCk having the gamma voltage VG(k-1) to the gates of the transistors 16a and 16b, respectively. As a result, the transistors 16a and 16b are controlled to be in the off state. On the other hand, when the transistors 21 and 22 receive the switch signal S1 of logic level 0 and the switch signal XS1 of logic level 1, they supply the low-amplitude control signal SCk having the gamma voltage VG(k+1) to the gates of the transistors 16a and 16b, respectively. As a result, the transistors 16a and 16b are controlled to be in the on state.

[0121] Furthermore, when the transistors 23 and 24 of the control signal output circuit A2_k_3 receive the switch signal S1 of logic level 1 and the switch signal XS1 of logic level 0, they supply a signal having the gamma voltage VG(k+1) as the inverted low-amplitude control signal XSCk to the gate of the transistor 16c. As a result, the transistor 16c is controlled to be in the on state. On the other hand, when the transistors 23 and 24 receive the switch signal S1 of logic level 0 and the switch signal XS1 of logic level 1, they supply the inverted low-amplitude control signal XSCk having the gamma voltage VG(k-1) to the gate of the transistor 16c. As a result, the transistor 16c is controlled to be in the off state.

[0122] That is, when the transistors 16a and 16b are turned on by the low-amplitude control signal SCk and the inverted low-amplitude control signal XSCk, the transistor 16c is turned off, whereas when the transistors 16a and 16b are turned off, the transistor 16c is turned on. Note that, although the gate of the transistor 12 is connected to the node nd2 and one end of the capacitor Ca is connected to the node nd2a in Fig. 9, the gate of the transistor 12 and one end of the capacitor Ca may be commonly connected to either the node nd2 or nd2a.

[0123] Next, the operation of the switch circuit 20 (16a to 16c) shown in FIG. 9 will be described with reference to FIGS. 10A and 10B. FIGS. 10A and 10B are cross-sectional views that schematically illustrate the cross-sectional structure of each of the transistors 16a to 16c and their connection to one another. FIG. 10A illustrates the state of each transistor in the first step shown in FIG. 6, and FIG. 10B illustrates the state of each transistor during the transition from the first step to the second step. The source and drain of each of the transistors 16a to 16c of the switch circuit 20 may be interchanged depending on the magnitude of their respective potentials. However, for the sake of convenience, the terminals of the transistors 16a and 16b connected to the output node nd0 will be referred to as the source, the terminals of the transistors 16a and 16b connected to the terminal of the transistor 16b will be referred to as the drain, and the two terminals of the transistor 16c connected to the transistors 16a and 16b will be referred to as the source and drain, respectively.

[0124] [1st step] 10A, in the first step, transistor 16a receives a low-amplitude control signal SCk of logic level 0 at its gate Ga, turning it on and forming a channel CH between its source region Sa and drain region Da. Furthermore, transistor 16b also receives a low-amplitude control signal SCk of logic level 0 at its gate Gb, turning it on and forming a channel CH between its source region Sb and drain region Db. In the first step, transistor 16c receives an inverted low-amplitude control signal XSCk of logic level 1 at its gate Gc, turning it off. Therefore, no channel is formed between the source region Sc and drain region Dc of transistor 16c.

[0125] According to this first step, the transistor 16a supplies the voltage of the output node nd0 to the gate of the transistor 12 via the node nd2, and the transistor 16b supplies the voltage of the output node nd0 to one end of the capacitor Ca via the node nd2a. At this time, in the first step, the reference voltage VIk is applied to the other end of the capacitor Ca via the transistor 17, so that the offset voltage occurring at the output node nd0 is held in the capacitor Ca, similar to the configuration shown in FIG.

[0126] [Second process] 10B, when the first step is shifted to the second step, the low-amplitude control signal SCk supplied to the gate Ga of the transistor 16a and the gate Gb of the transistor 16b transitions from a voltage [VG(k+1)] corresponding to logic level 0 to a voltage [VG(k-1)] corresponding to logic level 1. As a result, both the transistors 16a and 16b transition from an on state to an off state. Furthermore, the inverted low-amplitude control signal XSCk supplied to the gate Gc of the transistor 16c transitions from a voltage [VG(k-1)] corresponding to logic level 1 to a voltage [VG(k+1)] corresponding to logic level 0, causing the transistor 16c to transition from an off state to an on state.

[0127] When the voltage at the gate of each of the transistors 16a to 16c transitions as described above, charges move in the direction indicated by the thick solid line in FIG. 10B via the parasitic capacitance Cpc that exists between each gate and source, and between the gate and drain.

[0128] That is, due to parasitic capacitance coupling of the transistors during switching, charges move from the drain region Da of the transistor 16a to the gate Ga. Charges also move from the drain region Db of the transistor 16b to the gate Gb. Furthermore, charges move from the gate Gc of the transistor 16c to the source region Sc and the drain region Dc.

[0129] Therefore, the voltage fluctuation at node nd2 caused by charge transfer from the drain region Da to the gate Ga of transistor 16a is offset by the voltage fluctuation at node nd2 caused by charge transfer from the gate Gc to the source region Sc of transistor 16c. Furthermore, the voltage fluctuation at node nd2a caused by charge transfer from the drain region Db to the gate Gb of transistor 16b is offset by the voltage fluctuation at node nd2a caused by charge transfer from the gate Gc to the source region Sc of transistor 16c. As a result, charge transfer due to parasitic capacitance coupling of transistors during switching has almost no effect on the charge stored in capacitor Ca, and potential fluctuation at node nd2a can be suppressed. Furthermore, the transition between the on and off states of the transistors during switching causes the creation and disappearance of channels CH, resulting in charge migration. In Figures 10A and 10B, the charges accumulated in the channels CH of transistors 16a and 16b in the on state in the first step disperse and migrate to the drain and source regions of each transistor when they are switched off in the second step and the channels CH disappear. Approximately half of the charges in the channel CH of transistor 16a migrate toward the drain region Da, as shown by the bold solid line in Figure 10B, and then migrate into the channel CH of transistor 16c, which is in the on state in the second step. Similarly, approximately half of the charges in the channel CH of transistor 16b migrate toward the drain region Db, as shown by the bold solid line in Figure 10B, and then migrate into the channel CH of transistor 16c, which is in the on state in the second step.

[0130] That is, about half of the charge in the channel CH of the transistor 16a in the first step moves directly to the channel CH of the transistor 16c in the second step via the node nd2, and about half of the charge in the channel CH of the transistor 16b in the first step also moves directly to the channel CH of the transistor 16c in the second step via the node nd2a. Therefore, the charge movement in the channel CH of the transistor during switching has almost no effect on the charge stored in the capacitor Ca, and fluctuations in the potential of the node nd2a can be suppressed.

[0131] As a result, during the transition from the first step to the second step, the voltage fluctuations of the voltage at one end of the capacitor Ca (the voltage at the node nd2a) and the voltage at the node nd2 caused by the switching operation of each of the transistors 16a to 16c included in the offset cancellation circuit can be suppressed, and the state after the end of the first step can be maintained. Therefore, it is possible to perform high-precision offset cancellation without increasing the capacitance of the capacitor Ca.

[0132] 5, the on / off control of the transistor 16 by the low-amplitude control signal SCk having a small amplitude can suppress the voltage fluctuation (increase in offset voltage) caused by capacitive coupling at the node nd22 during the transition from the first step to the second step. However, when the transistor 16 transitions from the on state to the off state, the channel of the transistor 16 disappears, and approximately half of the charge in the channel moves to the node nd2 side, and this is added to the charge stored in the capacitor Ca, causing a voltage fluctuation (increase in offset voltage).

[0133] Therefore, by employing the control signal output circuit A2_k_3 and switch circuit 20 as shown in Fig. 9, the two problems of voltage fluctuation due to capacitive coupling and voltage fluctuation due to charge transfer within the channel CH can be resolved. Furthermore, by employing the configuration shown in Fig. 9, it is possible to achieve a highly accurate offset cancellation operation with reduced offset voltage even if the capacitance of the capacitor Ca is small. Of course, by employing the control signal output circuit A2_k_3 and switch circuit 20 for the gamma buffer GBk_1 of Fig. 8, the same effect as that of Fig. 9 can be achieved.

[0134] FIG. 11 is a circuit diagram showing the configuration of a gamma buffer GBk_3 as a third modified example of the gamma buffer GBk shown in FIG.

[0135] The gamma buffer GBk_3 shown in Fig. 11 is obtained by making the conductivity types of the transistor group (11, 12, 16 to 18) constituting the gamma buffer GBk shown in Fig. 5 opposite to each other. Furthermore, in the configuration shown in Fig. 11, an amplifier stage 30 is used instead of the amplifier stage 10 shown in Fig. 5, and a capacitor Cf is used instead of the capacitor Ca, and the respective connection forms are the same as those shown in Fig. 5.

[0136] That is, in the configuration shown in FIG. 11, a control signal output circuit A2_k_4 is used in place of the control signal output circuit A2_k_1 shown in FIG. 5, and an offset cancellation amplifier A1_k_3 is used in place of the offset cancellation amplifier A1_k_1.

[0137] In this case, in the offset cancellation amplifier A1_k_3, the N-channel transistors 11 and 12 constituting the differential pair shown in FIG.

[0138] A differential pair consisting of transistors 31 and 32 sends a current pair corresponding to the difference between a reference voltage VIk, which is the voltage of node nd1, and the voltage of node nd2 to nodes nd31 and nd32. The amplifier stage 30 operates by receiving power supply voltages VDD and VSS, and outputs a current corresponding to the difference between the currents flowing through nodes nd31 and nd32 to output node nd0 so that the voltage of output node nd0 matches reference voltage VIk.

[0139] The configuration shown in FIG. 11 is suitable as a gamma buffer that outputs a low-voltage gamma voltage VGk, which has a voltage value closer to the power supply voltage VSS than to the power supply voltage VDD, among the gamma buffers GB0 to GB(m-1).

[0140] The gamma buffer GBk shown in FIG. 5 is equipped with an offset cancellation circuit made up of the transistors 16 to 18 and the capacitor Ca, but the offset cancellation circuit is not limited to a configuration made up of the transistors 16 to 18 and the capacitor Ca.

[0141] FIG. 12 is a circuit diagram showing the configuration of a gamma buffer GBk_4 as a fourth modification of the gamma buffer GBk shown in FIG. 5, which has been made in consideration of the above points.

[0142] In the configuration shown in FIG. 12, an offset cancellation amplifier A1_k_4 is used instead of the offset cancellation amplifier A1_k_1 shown in FIG. 5, and the control signal output circuit A2_k_1 is the same as that shown in FIG.

[0143] The offset cancellation amplifier A1_k_4 employs P-channel transistors 45-48, capacitors Cb and Cd, a current source Id2, and N-channel transistors 45 and 46 forming a differential pair, instead of the transistors 16-18 and capacitor Ca shown in FIG. 5 as an offset cancellation circuit. The differential pair (11, 12), current source Id, and amplifier stage 10 as an operational amplifier are the same as those shown in FIG. 5.

[0144] The source of the transistor 13 is connected to the current source Id2, and the drain of the transistor 13 is connected to a node nd11. The gate of the transistor 13 is connected to one end of the capacitor Cb via a node nd3. The power supply voltage VSS is applied to the other end of the capacitor Cb.

[0145] The source of the transistor 14 is connected to the current source Id2, and the drain of the transistor 14 is connected to the node nd12. The gate of the transistor 14 is connected to one end of the capacitor Cd via the node nd4. The power supply voltage VSS is applied to the other end of the capacitor Cd. The transistors 13 and 14 operate as a differential pair for offset cancellation.

[0146] The transistor 45 receives the low-amplitude control signal SCk at its gate, and is turned off when the low-amplitude control signal SCk represents, for example, a logic level 1, and is turned on when the low-amplitude control signal SCk represents a logic level 0. When the transistor 45 is turned on, it connects the node nd1 and the node nd3.

[0147] The transistor 46 receives the low-amplitude control signal SCk at its gate, and is turned off when the low-amplitude control signal SCk represents, for example, a logic level 1, and is turned on when the low-amplitude control signal SCk represents a logic level 0. When the transistor 46 is turned on, it connects the node nd4 and the output node nd0.

[0148] The transistor 47 receives the switch signal XS2 at its gate and is in an off state while the switch signal XS2 is at, for example, logic level 1, and is in an on state while the switch signal XS2 is at logic level 0. When in an on state, the transistor 47 connects the node nd1 and the node nd2.

[0149] The transistor 48 receives the switch signal S2 and is in an off state while the switch signal S2 is, for example, at logic level 1, and is in an on state while the switch signal S2 is at logic level 0. When in an on state, the transistor 48 connects the output node nd0 and the node nd2.

[0150] Next, the offset canceling operation by the offset canceling circuit (45 to 48, Cb and Cd, Id2, 45 and 46) shown in FIG. 12 will be described in the order of the first and second steps shown in FIG.

[0151] [1st step] FIG. 13A is a schematic circuit diagram in which the current path in the first step of the gamma buffer shown in FIG. 12 is indicated by a thick solid line.

[0152] As shown in FIG. 13A, in the first step, the transistor 47 is turned on in response to the switch signal XS2, thereby connecting the gates of the differential pair of transistors 11 and 12 to each other, as indicated by the thick solid line.

[0153] In the first step, the transistor 21 is turned on in response to the switch signal S1, and a low-amplitude control signal SCk having a gamma voltage VG(k+1) corresponding to logic level 0 is supplied to the gates of the transistors 45 and 46, as indicated by the thick solid lines. This turns the transistor 45 on, and as indicated by the thick solid lines, the reference voltage VIk is applied to the gate of the transistor 13 and one end of the capacitor Cb via the transistor 45 and the node nd3, and the capacitor Cb is charged by the reference voltage VIk.

[0154] As a result, the voltage Va at one end of the capacitor Cb is Va=VIk This voltage Va is stored in the capacitor Cb.

[0155] Furthermore, the transistor 46 is turned on in response to the low-amplitude control signal SCk having the gamma voltage VG(k+1), and the voltage of the output node nd0 is applied to the gate of the transistor 14 and one end of the capacitor Cd via the transistor 46 and the node nd4, as shown by the thick solid line. At this time, the voltage of the output node nd0 is essentially equal to the reference voltage VIk, but if an offset voltage occurs at the output node nd0, a voltage in which the offset voltage Voff is superimposed on VIk will appear at the output node nd0.

[0156] As a result, the voltage Vb at one end of the capacitor Cd is Vb=VIk+Voff and the voltage Vb is stored in the capacitor Cd.

[0157] [Second process] FIG. 13B is a schematic circuit diagram in which the current paths in the second step of the gamma buffer shown in FIG. 12 are indicated by thick solid lines.

[0158] 13B, in the second step, the transistor 47 is turned off in response to the switch signal XS2, and the transistor 48 is turned on in response to the switch signal S2. As a result, as shown by the thick solid line, the voltage of the output node nd0 is supplied to the gate of the transistor 12 of the differential pair via the transistor 48 and the node nd2.

[0159] In the second step, the transistor 22 is turned on in response to the switch signal XS1, and a low-amplitude control signal SCk having a gamma voltage VG(k-1) corresponding to logic level 1 is supplied to the gates of the transistors 45 and 46, as indicated by the thick solid lines. This turns the transistors 45 and 46 off, and the voltages stored in the capacitors Cb and Cd are maintained.

[0160] Therefore, the gate of transistor 13 is supplied with the voltage Va (=VIk) held in capacitor Cb, and the gate of transistor 14 is supplied with the voltage Vb (=VIk+Voff) held in capacitor Cd.

[0161] As a result, the differential pair (13, 14) continues from the first step to pass a current pair corresponding to the difference between the voltage Va (=VIk) and the voltage Vb (=VIk+Voff), that is, the offset voltage Voff, to the nodes nd11 and nd12.

[0162] At this time, the differential pair (11, 12) passes a current pair corresponding to the difference between the input reference voltage VIk and the voltage of the output node nd0 through the nodes nd11 and nd12, and a current pair corresponding to the offset described above is superimposed on this current pair. Since the current pair output from the differential pair (13, 14) to the nodes nd11 and nd12 is the same as in the first step, the current pair output from the differential pair (11, 12) to the nodes nd11 and nd12 also acts to be the same as in the first step. Therefore, due to the amplification action of the amplifier stage 10, a high-precision gamma voltage VGk having a voltage value equal to the reference voltage VIk and with the offset removed is generated at the output node nd0.

[0163] 12, the on / off control of the transistors 45 and 46 for offset cancellation control is performed by the low-amplitude control signal SCk. Therefore, even when the offset cancellation circuit (45 to 48, Cb and Cd, Id2, 45 and 46) as shown in Fig. 12 is employed, the on / off control of the transistors 45 and 46 by the low-amplitude control signal SCk with a small amplitude can suppress voltage fluctuations caused by capacitive coupling occurring at the nodes nd3 and nd4 during the transition from the first process to the second process, and a highly accurate gamma voltage VGk with reduced offset voltage can be generated. [Example]

[0164] FIG. 14 is a block diagram showing the internal configuration of a grayscale voltage generating circuit 122_1 as a second embodiment of the grayscale voltage generating circuit 122. As shown in FIG.

[0165] In addition, the grayscale voltage generation circuit 122_1 shown in Figure 14 is identical in configuration to that shown in Figure 3, except that a gamma buffer unit GAG_1 is used instead of the gamma buffer unit GAG shown in Figure 3, and a control circuit CNT_1 is used instead of the control circuit CNT.

[0166] Similar to the control circuit CNT, the control circuit CNT_1 supplies a gamma characteristics designation signal de that designates gamma characteristics to the gamma selector GSL, and generates switch signals S1, XS1, S2, and XS2 having waveforms shown in FIG.

[0167] Furthermore, the control circuit CNT_1 generates switch signals S1q, XS1q, S2q, and XS2q that execute the first step at a timing different from that of the first step executed in response to the switch signals S1, XS1, S2, and XS2 within the vertical blanking period (V-BLANK) of each frame.

[0168] Then, the control circuit CNT_1 supplies the switch signals S1q, XS1q, S2q, and XS2q to the gamma buffer unit GAG_1, along with the switch signals S1, XS1, S2, and XS2.

[0169] FIG. 15 is a time chart showing waveforms of the switch signals S1, XS1, S2, and XS2, and the switch signals S1q, XS1q, S2q, and XS2q, generated by the control circuit CNT_1 for each frame period.

[0170] 15, during the vertical blanking period of each frame (from time t0 to time t1), the switch signals S1 and XS2 transition from logic level 1 (VDD), which prompts an OFF state, to logic level 0 (VSS), which prompts an ON state, at time ts1, and maintain that state until time th1 within the vertical blanking period (first step A).Then, the switch signals S1 and XS2 transition to logic level 1 (VDD), which prompts an OFF state, at time th1, and maintain that state until time ts1 within the next vertical blanking period (second step A).

[0171] At time ts1 within the vertical blanking period of each frame, the switch signals S2 and XS1 transition from, for example, logic level 0 (VSS) which prompts an ON state to logic level 1 (VDD) which prompts an OFF state, and maintain that state until time th1 within the vertical blanking period (first step A).Then, at time th1, the switch signals S2 and XS1 transition to logic level 0 (VSS) which prompts an ON state, and maintain that state until time ts1 within the next vertical blanking period (second step A).

[0172] At time ts2 after time th1 during the vertical blanking period, switch signals S1q and XS2q transition from logic level 1 (VDD) that prompts an OFF state to logic level 0 (VSS) that prompts an ON state, and maintain that state until time th2 within the vertical blanking period (first step B).Then, switch signals S1q and XS2q transition to logic level 1 (VDD) that prompts an OFF state at this time th2, and maintain that state until time ts2 within the next vertical blanking period (second step B).

[0173] At time ts2 within the vertical blanking period of each frame, the switch signals S2q and XS1q transition from, for example, logic level 0 (VSS) that prompts an ON state to logic level 1 (VDD) that prompts an OFF state, and maintain that state until time th2 within the vertical blanking period (first step B).Then, at time th2, the switch signals S2q and XS1q transition to logic level 0 (VSS) that prompts an ON state, and maintain that state until time ts2 within the next vertical blanking period (second step B).

[0174] FIG. 16 is a block diagram showing the internal configuration of the gamma buffer unit GAG_1.

[0175] Note that the gamma buffers GB0 to GB(m-1) shown in Figure 16, like the gamma buffer unit GAG shown in Figure 4, each have the internal configuration shown in Figure 5, Figure 9, Figure 11 or Figure 12, and adjacent ones are connected in the same manner as Figure 4.

[0176] However, in the gamma buffer unit GAG_1, among the gamma buffers GB0 to GB(m-1), the even-numbered gamma buffers GB0, GB2, GB4, ..., GB(m-1) each receive switch signals S1, XS1, S2, and XS2. Furthermore, the odd-numbered gamma buffers GB1, GB3, GB5, ..., GB(m-2) each receive switch signals S1q, XS1q, S2q, and XS2q. That is, each of the odd-numbered gamma buffers GB1, GB3, GB5, ..., GB(m-2) receives S1q as switch signal S1, XS1q as switch signal XS1, S2q as switch signal S2, and XS2q as switch signal XS2.

[0177] In this way, in the grayscale voltage generating circuit 122_1, the execution timing of the offset cancel operation in the first step is shifted between the even-numbered gamma buffer group and the odd-numbered gamma buffer group.

[0178] For example, when odd-numbered gamma buffer GB1 outputs gamma voltage VG1 without offset voltage through the offset cancellation operation of the first process, a low-amplitude control signal generated from gamma voltages VG0 and VG2 is used. At this time, even-numbered gamma buffers GB0 and GB2 that output gamma voltages VG0 and VG2 are in a stable state in the second process, so the offset cancellation operation of gamma buffer GB1 is performed using a stable low-amplitude control signal. Similarly, when even-numbered gamma buffers output gamma voltages without offset voltage through the offset cancellation operation of the first process, a low-amplitude control signal generated from the gamma voltage output from odd-numbered gamma buffers that are in a stable state in the second process is used. As described above, the offset voltage generated by the coupling of the parasitic capacitance of the transistor constituting the switch element depends on the amount of change (voltage difference) in the voltage applied to the gate when the transistor transitions between on and off, so a stable low-amplitude control signal is desirable. If temporary noise occurs in the gamma voltage that generates the low-amplitude control signal, and the amplitude of the low-amplitude control signal in the first step temporarily increases, the offset voltage may increase depending on the timing.

[0179] Therefore, by shifting the execution timing of the offset cancel operation in the first step between the even-numbered gamma buffer group and the odd-numbered gamma buffer group, as in the grayscale voltage generation circuit 122_1, it is possible to use stable low-amplitude control signals for each, thereby enabling the output of gamma voltages with higher accuracy.

[0180] In the grayscale voltage generation circuit 122 or 122_1 as a level voltage generation circuit, the reference voltages VI0 to VI(m-1) are generated by a reference voltage generation unit consisting of amplifiers GA0 and GA1, a resistor string LD1, and a gamma selector GSL, but the configuration is not limited to this. In other words, the reference voltage generation unit may be any circuit that generates a plurality of reference voltages in accordance with the desired gamma characteristics.

[0181] In the above embodiment, all of the gamma buffers GB0 to GB(m-1) are configured with offset cancellation amplifiers, but it is sufficient if at least one of them is equipped with an offset cancellation amplifier.

[0182] Furthermore, in the above-described embodiments, the offset cancellation circuit shown in FIG. 5, FIG. 8, FIG. 9, FIG. 11 or FIG. 12 is shown, but the offset cancellation circuit may have a configuration other than that shown in FIG. 5, FIG. 8, FIG. 9, FIG. 11 or FIG. 12.

[0183] In short, the level generating circuit (grayscale voltage generating circuit) according to the present invention may be one that includes the following resistor string, reference voltage generating section, and first to mth gamma buffers.

[0184] That is, the resistor string (LD2) includes a plurality of resistors connected in series to each other via a plurality of taps, and outputs level voltages [VR0 to VR(n-1)] having different voltage levels from each of the taps.

[0185] The reference voltage generating units (GA0, GA1, LD1, GSL) generate m reference voltages [VI0 to VI(m-1)] that conform to desired gamma characteristics.

[0186] The first to mth gamma buffers [GB0 to GB(m-1)] each receive m reference voltages individually and operate by being supplied with two power supply voltages (VDD and VSS), thereby amplifying the m reference voltages individually to generate m voltages as m gamma voltages [VG0 to VG(m-1)] and output them to m taps out of the multiple taps.

[0187] At least one gamma buffer (VBk) among the first to m-th gamma buffers includes the following offset cancellation amplifier and control signal output circuit. That is, the offset cancellation amplifier (e.g., A1_k_1) includes an offset cancellation circuit (e.g., 16 to 18 and Ca) that removes the offset voltage occurring in the gamma voltage (VGk) output by itself in accordance with a binary control signal (SCk, XSCk). The control signal output circuit (e.g., A2_k_1) receives the m gamma voltages output by the first to m-th gamma buffers including itself and two voltages [e.g., VG(k-1) and VG(k+1)] selected from two power supply voltages (VDD and VSS) whose voltage difference is lower than the difference between the two power supply voltages, generates a control signal representing these two voltages as a binary value, and outputs it to the offset cancellation circuit. [Explanation of symbols]

[0188] 10 Amplification stage 11, 12, 16-18, 21, 22 Transistors 103 Data Driver 122 Gradation voltage generation circuit A1_k_1 Offset cancellation amplifier A2_k_1 control signal output circuit CNT control circuit GAG Gamma Buffer GB0~GB(m-1) Gamma buffer LD1, LD2 resistor string

Claims

1. a resistor string including a plurality of resistors connected in series to each other via a plurality of taps, and outputting a plurality of level voltages having different voltage levels from each of the taps; a reference voltage generating unit that generates m (m is an integer of 2 or more) reference voltages each having a different voltage value according to a desired gamma characteristic; first to m-th gamma buffers that individually receive the m reference voltages, operate by receiving two power supply voltages, and amplify the m reference voltages to generate m voltages as m gamma voltages, and output the m voltages to m taps among the plurality of taps; At least one gamma buffer among the first to m-th gamma buffers an offset cancellation amplifier including an offset cancellation circuit that removes an offset voltage generated in the gamma voltage output by the offset cancellation amplifier in response to a binary control signal; a control signal output circuit that receives the m gamma voltages output by the first to m-th gamma buffers including itself and two voltages selected from the two power supply voltages, the voltage difference between which is lower than the difference between the two power supply voltages, generates the control signal in which the two voltages are binary-valued, and outputs the control signal to the offset cancellation circuit.

2. 2. The level voltage generating circuit according to claim 1, wherein one of the two voltages is the gamma voltage output from the one gamma buffer.

3. 2. The level voltage generating circuit according to claim 1, wherein the two voltages are two gamma voltages output from two gamma buffers excluding the first gamma buffer among the first to mth gamma buffers.

4. the offset cancellation circuit includes a first capacitive element; The offset cancellation amplifier a first step of storing the offset voltage or the gamma voltage generating the offset voltage in the first capacitance element based on the control signal; a second step of holding the voltage stored in the first capacitance element and removing the offset voltage from the gamma voltage output by the first gamma buffer, and supplying the resulting gamma voltage to the tap of the resistor string; The control signal output circuit includes:

2. The level voltage generating circuit according to claim 1, wherein the first step generates the control signal having one of the two voltages, and the second step generates the control signal having the other of the two voltages.

5. The offset cancellation amplifier an output node that outputs the gamma voltage; a first differential pair including a first input terminal for receiving the reference voltage and a second input terminal for receiving the voltage of the output node, the first differential pair outputting a pair of currents corresponding to a difference between the reference voltage and the voltage of the output node; an amplifier stage that outputs a current corresponding to a difference between the pair of currents to the output node; the offset cancellation circuit includes a first switch element that is on / off controlled in response to the control signal and that connects one end of the first capacitance element and the second input end of the first differential pair to the output node when in an on state; In the first step, the control signal output circuit supplies the first switch element with the control signal that turns the first switch element on, while the first input terminal of the first differential pair and the other terminal of the first capacitive element are connected, thereby causing the offset voltage to be accumulated in the first capacitive element; 5. The level voltage generating circuit according to claim 4, wherein in the second step, in a state in which the output node and the other end of the first capacitance element are connected, the control signal output circuit supplies the control signal that turns the first switch element to an off state to the first switch element, thereby retaining the offset voltage accumulated in the first capacitance element, and as a result, removing the offset voltage from the voltage of the output node.

6. 6. The level voltage generating circuit according to claim 5, wherein the offset cancellation amplifier sequentially executes the first step and the second step while supplying the voltage of the output node as the gamma voltage to the tap of the resistor string.

7. The offset cancellation circuit a second switch element that connects the first input terminal of the first differential pair and the other terminal of the first capacitive element when in an on state; a third switch element that connects the other end of the first capacitance element and the output node when in an on state; 6. The level voltage generating circuit according to claim 5, wherein the first differential pair is composed of a pair of transistors of a first conductivity type, and each of the first switch element to the third switch element is composed of a transistor of a second conductivity type.

8. The offset cancellation amplifier an output node that outputs the gamma voltage; a first differential pair including a first input terminal for receiving the reference voltage and a second input terminal for receiving the voltage of the output node, the first differential pair outputting a pair of currents corresponding to a difference between the reference voltage and the voltage of the output node; an amplifier stage that outputs a current corresponding to a difference between the pair of currents to the output node; the control signal output circuit generates an inverted control signal by inverting the level of the control signal; The offset cancellation circuit a first switch element that is on / off controlled in response to the control signal and that connects the output node to the second input end of the first differential pair when in an on state; a second switch element that is on / off controlled in response to the control signal and that connects the output node to one end of the first capacitance element when in an on state; a third switch element that is on / off controlled in response to the inverted control signal and that connects one end of the first capacitance element to the second input end of the first differential pair when in an on state; In the first step, in a state in which the first input terminal of the first differential pair and the other terminal of the first capacitance element are connected, the control signal output circuit supplies the control signal that turns the first and second switch elements on to the first and second switch elements, and supplies the inverted control signal that turns the third switch element off to the third switch element, thereby storing the offset voltage in the first capacitance element; 5. The level voltage generation circuit according to claim 4, wherein in the second step, with the output node and the other end of the first capacitance element connected, the control signal output circuit supplies the control signal that turns the first and second switch elements to an off state to the first and second switch elements and supplies the inverted control signal that turns the third switch element to an on state to the third switch element, thereby retaining the offset voltage accumulated in the first capacitance element and, as a result, removing the offset voltage from the voltage of the output node.

9. The offset cancellation amplifier an output node that outputs the gamma voltage; a first differential pair including a first input terminal receiving a voltage of the output node and a second input terminal receiving the reference voltage, and causing a pair of currents corresponding to a difference between the voltage of the output node and the reference voltage to flow through a pair of nodes; an amplifier stage that outputs a current corresponding to a difference between currents flowing through the pair of nodes to the output node, The offset cancellation circuit a switch circuit that selects and supplies one of the reference voltage and the voltage of the output node to the first input terminal of the first differential pair; a second capacitive element in addition to the first capacitive element; a second differential pair having a first input terminal connected to one end of the first capacitance element and a second input terminal connected to one end of the second capacitance element, and causing a pair of currents corresponding to a difference between a voltage at the one end of the first capacitance element and a voltage at the one end of the second capacitance element to flow through the pair of nodes; a first switch element that is on / off controlled in response to the control signal and that applies the voltage of the output node to the one end of the first capacitance element when in an on state; a second switch element that is on / off controlled in response to the control signal and that applies the reference voltage to the one end of the second capacitance element when in an on state; In the first step, the switch circuit is controlled so that the reference voltage is supplied to the first input terminal of the first differential pair, and the first switch element and the second switch element are turned on based on the control signal, thereby storing the voltage of the output node where the offset voltage is generated in the first capacitance element and storing the reference voltage in the second capacitance element; 5. The level voltage generation circuit according to claim 4, wherein in the second step, the switch circuit is controlled so that the voltage of the output node is supplied to the first input terminal of the first differential pair, and the first switch element and the second switch element are turned off based on the control signal, so that the voltages stored in the first and second capacitive elements in the first step are held as the voltage of the first input terminal and the voltage of the second input terminal of the second differential pair, respectively, and as a result, the offset voltage is removed from the voltage of the output node.

10. 10. The level voltage generating circuit according to claim 9, wherein the offset cancellation amplifier sequentially executes the first step and the second step while supplying the voltage of the output node as the gamma voltage to the tap of the resistor string.

11. A display driver including the level voltage generating circuit according to claim 4 as a grayscale voltage generating circuit, The display driver is characterized in that the first step is performed within a vertical blanking period of a frame period of a video signal.

12. The display driver according to claim 11, characterized in that the first to mth gamma buffers are divided into at least two gamma buffer groups, and the first step is performed at different timings for each of the gamma buffer groups during the vertical blanking period.

13. 13. The display driver according to claim 12, wherein the first to m-th gamma buffers are divided into two groups: a group of odd-numbered gamma buffers and a group of even-numbered gamma buffers.

14. a display panel including a plurality of data lines on which a plurality of display cells are arranged; a display driver that includes the level voltage generation circuit according to claim 1 as a gradation voltage generation circuit, that sets the plurality of level voltages output from the level voltage generation circuit as a plurality of gradation voltages, that selects, for each pixel based on a video signal, a gradation voltage corresponding to a luminance level indicated by the pixel from among the plurality of gradation voltages, and that outputs a drive signal having the selected gradation voltage to the data line.

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