Laminated ceramic electronic component and method of manufacturing the same

Abstract

To provide a laminated ceramic electronic component which has high reliability and the capacity of which is easily secured, and a method of manufacturing the same.SOLUTION: A laminated ceramic electronic component comprises: a protective part including an end surface facing a first direction, a plurality of peripheral surfaces connected to the end surface and extending in the first direction, and a ridgeline part having a concave part extending along the first direction and connecting the plurality of peripheral surfaces; a ceramic body having a functional part disposed inside the protective part; and an external electrode. The functional part includes a plurality of internal electrode layers laminated in a second direction orthogonal to the first direction. The protection part includes a cover part laminated in the second direction with respect to the functional part, and a side margin part covering the functional part from a third direction orthogonal to the first direction and the second direction. The ridgeline part includes a first ridgeline part provided on a cover part side and a second ridgeline part provided on a side margin part side with a concave part therebetween. In a cross section including the second direction and the third direction, a curvature radius R1 of the first ridgeline part is larger than a curvature radius R2 of the second ridgeline part.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic electronic component and a method for manufacturing the same. [Background technology]

[0002] In recent years, with the miniaturization and high performance of electronic devices, there has been an increasing demand for smaller, larger-capacity multilayer ceramic electronic components such as multilayer ceramic capacitors. To meet this demand, a method has been proposed in which margins that protect the periphery of internal electrode layers are formed later in order to make the margins as thin as possible (see, for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-89755 [Patent Document 2] Patent Publication No. 2021-44533 Summary of the Invention [Problem to be solved by the invention]

[0004] Generally, a multilayer ceramic electronic component comprises a capacitance-forming portion formed by stacking multiple internal electrode layers with dielectric layers sandwiched between them, and an element body (chip) in which a protective portion is formed around the capacitance-forming portion. The protective portion can be formed by the methods disclosed in Patent Documents 1 and 2. If the ridge portion of the element body, i.e., the portion where the main surface and side surface are connected, is formed in a curved shape with an appropriate radius of curvature, it becomes easier to avoid damage such as chipping at the ridge portion of the element body.

[0005] Conventionally, barrel polishing has been used to form curved shapes at the ridges of element bodies. In barrel polishing, element bodies cut into individual pieces are placed in a container along with a liquid containing an abrasive and an adsorbent, and the container is then set in a centrifuge and rotated. In other words, the centrifuge is operated to collide the element bodies with each other and form the ridges. However, as element bodies become smaller, the impact force (energy) when they collide with each other becomes smaller, making it difficult to form them into the desired shape.

[0006] Furthermore, it is known that as the radius of curvature of the ridgeline portion increases, the protective portion at the ridgeline portion becomes thinner, shortening the distance between the surface of the element body and the capacitance-forming portion, thereby reducing the reliability of the multilayer ceramic electronic component. For this reason, in the past, the protective portion was made thicker at the expense of the area of ​​the internal electrode layers, providing a margin for ensuring the desired radius of curvature. However, as multilayer ceramic electronic components become increasingly miniaturized, attempting to ensure the thickness of the protective portion increases the proportion of the area of ​​the internal electrode layers sacrificed relative to the overall dimensions, which tends to reduce capacitance. In other words, as multilayer ceramic electronic components become increasingly miniaturized, it is becoming increasingly difficult to achieve both capacitance and reliability.

[0007] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a highly reliable multilayer ceramic electronic component that is easy to ensure capacitance even in a multilayer ceramic electronic component that has become increasingly miniaturized, and a method for manufacturing the same. [Means for solving the problem]

[0008] In order to achieve the above object, a multilayer ceramic electronic component includes a pair of end faces each facing a first direction, a pair of main faces connected to the end faces and each facing a second direction orthogonal to the first direction, and a pair of side faces connected to the end faces and each facing a third direction orthogonal to the first and second directions, the multilayer ceramic electronic component including a protective portion including ridge portions connecting adjacent main faces and side faces and corner portions connecting adjacent end faces and the main faces or adjacent end faces and side faces, and a capacitance-forming portion disposed inside the protective portion; and a capacitance-forming portion provided on one of the end faces and connecting the pair of main faces. a first external electrode provided on the other end face, extending to the pair of main surfaces and the pair of side surfaces, and connected to a first internal electrode layer included in the capacitance forming portion; and a second external electrode provided on the other end face, extending to the pair of main surfaces and the pair of side surfaces, and connected to a second internal electrode layer included in the capacitance forming portion, wherein a radius of curvature R1 of the ridge portion in a cross section including the second direction and the third direction is larger than a radius of curvature R2 of the corner portion in a cross section including the first direction and the second direction and a radius of curvature R3 of the corner portion in a cross section including the first direction and the third direction.

[0009] In the multilayer ceramic electronic component having the above-described configuration, the protective portion may have an uneven portion formed along the first direction in the portion where the main surface is formed or the portion where the side surface is formed.

[0010] Furthermore, in the multilayer ceramic electronic component having the above configuration, when the non-uniform portion is provided on the side surface, the non-uniform portion may be arranged in an area within 40% on each side of the center of the side surface in the second direction.

[0011] Furthermore, in the multilayer ceramic electronic component having the above configuration, when the non-uniform portion is provided on the main surface, the non-uniform portion may be arranged in an area within 40% on each side of the center of the main surface in the third direction.

[0012] In the monolithic ceramic electronic component having the above-described configuration, the radius of curvature R1 of the ridge line portion may be 10 μm or more and 20 μm or less.

[0013] In addition, the multilayer ceramic electronic component having the above configuration may have a dimension of 0.6 mm or less along the first direction.

[0014] Furthermore, in the multilayer ceramic electronic component having the above configuration, the dimension of the multilayer ceramic electronic component in the second direction can be smaller than the dimension of the multilayer ceramic electronic component in the first direction and the dimension of the multilayer ceramic electronic component in the third direction.

[0015] In the multilayer ceramic electronic component having the above configuration, the dimension of the multilayer ceramic electronic component in the second direction may be 110 μm or less.

[0016] Furthermore, in the multilayer ceramic electronic component having the above-described configuration, the non-uniform portion may be an undulating portion in which the thickness of the protective portion is non-uniform when it appears in a cross section of the element body that includes the second direction and the third direction.

[0017] In the monolithic ceramic electronic component having the above configuration, the undulating portions may be recesses, and the ratio of the depth of the recesses to the thickness of the protective portion may be 10% or more and 30% or less.

[0018] Furthermore, in the multilayer ceramic electronic component having the above configuration, the undulating portion may be a stepped portion, and the ratio of the height of the stepped portion to the thickness of the protective portion may be 10% or more and 30% or less.

[0019] Further, in order to achieve the above object, a method for manufacturing a multilayer ceramic electronic component includes a step of forming a laminated chip bar in which a first internal electrode formation layer in which a plurality of first unsintered internal electrode layers are formed at intervals along a first direction and a second internal electrode formation layer in which a plurality of second unsintered internal electrode layers are formed at intervals along the first direction, the second internal electrode formation layers being each provided offset in the first direction with respect to the first unsintered internal electrode layers, with an unsintered dielectric layer sandwiched therebetween; and a step of forming a laminated chip bar in which a dimension in a short side direction of the laminated chip bar in a second direction perpendicular to the first direction and a dimension in a third direction perpendicular to the first direction and the second direction of the laminated chip bar are The method can include the steps of: preparing two ceramic sheets corresponding to the total dimensions in the first direction; a clamping step of placing the two ceramic sheets on a pair of surfaces of the laminated chip bar facing the second direction or a pair of surfaces of the laminated chip bar facing the third direction and sandwiching the laminated chip bar between the two ceramic sheets; a pressing step of pressing the two ceramic sheets against the outer peripheral surfaces of the laminated chip bar and crimping them together; and a cutting step of cutting the laminated chip bar to which the ceramic sheets have been crimped at a predetermined position along the first direction.

[0020] In the method for manufacturing a multilayer ceramic electronic component having the above configuration, the pressure-bonding step may be a hydrostatic pressing step.

[0021] Furthermore, in the method for manufacturing a multilayer ceramic electronic component having the above-described configuration, the two ceramic sheets sandwiching the multilayer chip bar may each have a longitudinal dimension corresponding to the dimension of the multilayer chip bar in the first direction.

[0022] In order to achieve the above object, another method for manufacturing a multilayer ceramic electronic component can include the steps of: forming a laminated chip bar in which a first internal electrode forming layer in which a plurality of first unsintered internal electrode layers are formed at intervals along a first direction, and a second internal electrode forming layer in which a plurality of second unsintered internal electrode layers are formed at intervals along the first direction, each of which is offset in the first direction relative to the first unsintered internal electrode layer, with an unsintered dielectric layer sandwiched therebetween; a winding step in which a ceramic sheet is wrapped around an outer peripheral surface formed along the longitudinal direction of the laminated chip bar; a pressing step in which the ceramic sheet is pressed against the outer peripheral surface of the laminated chip bar and compressed; and a cutting step in which the laminated chip bar to which the ceramic sheet is compressed is cut at a predetermined position along the first direction.

[0023] In the method for manufacturing a multilayer ceramic electronic component having the above configuration, the pressure-bonding step may be a hydrostatic pressing step.

[0024] Furthermore, the method for manufacturing a multilayer ceramic electronic component having the above configuration can be embodied in such a manner that it further includes a step of cutting off an excess portion of the single ceramic sheet wrapped around the entire outer periphery of the multilayer chip bar.

[0025] In the method for manufacturing a multilayer ceramic electronic component having the above configuration, the single ceramic sheet wrapped around the outer peripheral surface of the laminated chip bar can have a dimension that corresponds to twice the total dimension of the dimension of the laminated chip bar in a second direction perpendicular to the first direction and the dimension of the laminated chip bar in a third direction perpendicular to the first and second directions. [Effects of the Invention]

[0026] According to the present invention, it is possible to provide a highly reliable multilayer ceramic electronic component and a method for manufacturing the same, which makes it easy to ensure capacitance even in a multilayer ceramic electronic component that has become increasingly miniaturized. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 1 is a perspective view of the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 2] Fig. 2(A) is a cross-sectional view taken along line AA' of the multilayer ceramic capacitor shown in Fig. 1. Fig. 2(B) is a cross-sectional view taken along line BB' of the multilayer ceramic capacitor shown in Fig. 1. Fig. 2(C) is a cross-sectional view taken along a line corresponding to line AA' of the multilayer ceramic capacitor of the comparative example. [Figure 3] Fig. 3(A) is a cross-sectional view taken along line CC' of the multilayer ceramic capacitor shown in Fig. 1. Fig. 3(B) is an end view of a ceramic body included in the multilayer ceramic capacitor shown in Fig. 1, viewed from the X direction. [Figure 4] Fig. 4(A) is a cross-sectional view showing an embodiment of a multilayer ceramic capacitor in which recesses are formed in different positions, and Fig. 4(B) is a cross-sectional view showing an embodiment of a multilayer ceramic capacitor in which recesses are formed in side margin portions. [Figure 5] FIG. 5 is a cross-sectional view illustrating an area where undulating portions (recesses) are provided. [Figure 6] Fig. 6(A) is an explanatory diagram showing the measurement position of the radius of curvature R1, Fig. 6(B) is an explanatory diagram showing the measurement position of the radius of curvature of the ridge line portion of the multilayer ceramic capacitor of the first embodiment, and Fig. 6(C) is a diagram explaining another method of measuring the radius of curvature of the ridge line portion. [Figure 7] FIG. 7 is a flowchart showing an example of a method for manufacturing the multilayer ceramic capacitor according to the first embodiment. [Figure 8] FIG. 8 is a perspective view showing a part of the manufacturing process of the laminated chip bar. [Figure 9] FIG. 9 is an explanatory view showing an enlarged portion of the laminated chip bar in the manufacturing process. [Figure 10] Fig. 10(A) is a diagram showing the laminated chip bar as viewed from the X direction, and Fig. 10(B) is a diagram showing the laminated chip bar sandwiched between two ceramic sheets as viewed from the X direction. [Figure 11]Fig. 11(A) is a perspective view of a laminated chip bar sandwiched between ceramic sheets, and Fig. 11(B) is a perspective view of an envelope in which the laminated chip bar is wrapped between two ceramic sheets. [Figure 12] Fig. 12(A) is an explanatory diagram schematically showing the state of a ceramic body when the radius of curvature R1 is smaller than the appropriate range, Fig. 12(B) is an explanatory diagram schematically showing the state of a ceramic body when the radius of curvature R1 is within the appropriate range, and Fig. 12(C) is an explanatory diagram schematically showing the state of a ceramic body when the radius of curvature R1 is larger than the appropriate range. [Figure 13] FIG. 13 is a cross-sectional view of a modified multilayer ceramic capacitor. [Figure 14] FIG. 14 is a perspective view of the multilayer ceramic capacitor in accordance with the second embodiment. [Figure 15] Fig. 15(A) is a cross-sectional view of a multilayer ceramic capacitor in which an uneven portion is formed in a cover portion, Fig. 15(B) is a cross-sectional view of a multilayer ceramic capacitor in which an uneven portion is formed in a side margin portion, and Fig. 15(C) is a cross-sectional view of a multilayer ceramic capacitor in which an uneven portion is formed near the boundary between the cover portion and the side margin portion. [Figure 16] FIG. 16 is a cross-sectional view illustrating a region where an uneven portion is provided. [Figure 17] FIG. 17 is an explanatory diagram of the winding process in which a ceramic sheet is wound around the outer periphery of a laminated chip bar. [Figure 18] Fig. 18(A-1) is a diagram showing a part of the process for manufacturing the multilayer ceramic capacitor of the third embodiment. Fig. 18(A-2) is a diagram showing the multilayer ceramic capacitor of the third embodiment as viewed from the X direction. Fig. 18(B-1) is a diagram showing a part of the process for manufacturing the multilayer ceramic capacitor of a modified example of the third embodiment. Fig. 18(B-2) is a diagram showing the multilayer ceramic capacitor of the modified example of the third embodiment as viewed from the X direction. DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The drawings show X-axis, Y-axis, and Z-axis, which are mutually orthogonal as appropriate. The X-axis, Y-axis, and Z-axis are common to all the drawings. The X-axis direction corresponds to the first direction, the Y-axis direction corresponds to the third direction, and the Z-axis direction corresponds to the second direction.

[0029] First Embodiment [Overall Configuration of Multilayer Ceramic Capacitor 10] 1 to 3(B) are diagrams showing a multilayer ceramic capacitor 10 according to a first embodiment of the present invention. FIG. 1 is a perspective view of the multilayer ceramic capacitor 10 according to the first embodiment. FIG. 2(A) is a cross-sectional view of the multilayer ceramic capacitor 10 taken along line AA'. FIG. 2(B) is a cross-sectional view of the multilayer ceramic capacitor 10 taken along line BB'. FIG. 2(C) is a cross-sectional view of a comparative multilayer ceramic capacitor 80 taken along a line corresponding to line AA'. FIG. 3(A) is a cross-sectional view of the multilayer ceramic capacitor 10 taken along line CC'. FIG. 3(B) is an end view of a ceramic body 11 included in the multilayer ceramic capacitor 10, viewed from the X direction.

[0030] The multilayer ceramic capacitor 10 includes a ceramic body 11, which is an element body made of ceramic, and a first external electrode 14a and a second external electrode 14b. The two external electrodes 14a and 14b are formed on the surfaces of the ceramic body 11.

[0031] The ceramic body 11 has a capacitance-forming portion 16 and a protective portion 17. The protective portion 17 forms the peripheral portion of the ceramic body 11 and has a pair of end faces 11a facing the X-axis direction, a pair of side faces 11b facing the Y-axis direction, and a pair of main faces 11c facing the Z-axis direction. The pair of end faces 11a are connected to the pair of side faces 11b and the pair of main faces 11c, respectively.

[0032] Protective portion 17 has ridge portions 21 that connect adjacent side surfaces 11b and main surfaces 11c. There are four locations where side surfaces 11b and main surfaces 11c are adjacent to each other. Therefore, ridge portions 21 are formed in four locations.

[0033] The protective portion 17 has corners 22 that connect the adjacent end face 11a and main surface 11c. The protective portion 17 also has corners 22 that connect the adjacent end face 11a and side face 11b. Therefore, the protective portion 17 has four corners 22 per end face 11a, for a total of eight corners 22. The corners 22 are sometimes referred to as edge portions.

[0034] In each drawing, the end surface 11a, the side surface 11b, and the main surface 11c are configured as, for example, substantially flat surfaces, but may also be rounded.

[0035] In detail, the protective portion 17 has a cover portion 18 located outside the capacitance forming portion 16 in the Z-axis direction, a side margin portion 19 located outside the capacitance forming portion 16 in the Y-axis direction, and an end margin portion 20 located outside the capacitance forming portion 16 in the X-axis direction.

[0036] The capacitance forming portion 16 is disposed inside the protective portion 17, and constitutes a functional portion in this embodiment. The capacitance forming portion 16 is formed by laminating a plurality of first internal electrode layers 12 and a plurality of second internal electrode layers 13 in the Z-axis direction with ceramic layers 15 (see FIG. 2(A)) interposed therebetween. The first internal electrode layers 12 and the second internal electrode layers 13 are both sheet-shaped extending along the XY plane, and are arranged alternately along the Z-axis direction.

[0037] The internal electrode layers 12 and 13 are each formed of a good electrical conductor and function as internal electrode layers of the multilayer ceramic capacitor 10. Examples of good electrical conductors that form the internal electrode layers 12 and 13 include metals and alloys containing, as a main component, nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), and gold (Au).

[0038] 2(A), the first internal electrode layer 12 is extended to, for example, one end face 11a of the ceramic body 11 and connected to one external electrode 14a. The second internal electrode layer 13 is extended to the other end face 11a and connected to the other external electrode 14b.

[0039] The ceramic layers 15 are made of dielectric ceramics. In the multilayer ceramic capacitor 10, a dielectric ceramic with a high dielectric constant is used to increase the capacitance of each ceramic layer 15 between the internal electrode layers 12 and 13. Examples of dielectric ceramics with a high dielectric constant include perovskite-structured materials containing barium (Ba) and titanium (Ti), such as barium titanate (BaTiO).

[0040] In addition to barium titanate-based materials, the dielectric ceramics may also be strontium titanate (SrTiO3)-based, calcium titanate (CaTiO3)-based, magnesium titanate (MgTiO3)-based, calcium zirconate (CaZrO3)-based, calcium titanate zirconate (Ca(Zr,Ti)O3)-based, barium zirconate (BaZrO3)-based, titanium oxide (TiO2)-based, etc.

[0041] The protective portion 17 is also made of a dielectric ceramic. The material for the protective portion 17 may be any insulating ceramic, but using a material with the same composition as the ceramic layer 15 improves manufacturing efficiency and suppresses internal stress in the ceramic body 11.

[0042] Each of the external electrodes 14a, 14b has an undercoat film (not shown) formed to cover the end face 11a, and a plating film (not shown) formed on the undercoat film. The undercoat film is formed, for example, by baking a conductive paste or by sputtering. The plating film is formed by electrolytic plating. Each of the films of the external electrodes 14a, 14b is formed of a metal or alloy containing, for example, nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), or the like as a main component.

[0043] [Detailed structure of multilayer ceramic capacitor 10] Next, the detailed configuration of the multilayer ceramic capacitor 10 will be described.

[0044] (recess) 1, 3(A), and 3(B), the multilayer ceramic capacitor 10 includes a recess 23 extending along the X direction in the cover portion 18. The recess 23 corresponds to an undulating portion as an uneven portion. The recess 23 may be discontinuous as long as it exists along the X direction. The recess 23 is formed by the protective portion 17, in this case, the cover portion 18, having an uneven thickness. From the viewpoint of ensuring the reliability of the multilayer ceramic capacitor 10, the depth d

[23] of the recess 23 is preferably 10% to 30% of the thickness t

[18] of the cover portion 18, where t

[18] is the thickness of the cover portion 18. The thickness t

[18] may be the dimension of the thickest portion of the cover portion 18. Alternatively, the thickness t

[18] may be the average value of the thicknesses of several points on the cover portion 18.

[0045] The recesses 23 are formed as traces of the manufacturing method of the multilayer ceramic capacitor 10, which will be described in detail later. The formation of the recesses 23 increases the circumferential length of the ceramic body 11, thereby increasing the contact area with the external electrodes 14a, 14b. Furthermore, the plating film for the external electrodes 14a, 14b, for example, Ni paste, wets into the recesses 23, thereby improving the adhesion of the external electrodes 14a, 14b to the ceramic body 11. This improves the overall strength of the multilayer ceramic capacitor 10, including, for example, improved resistance to bending. Furthermore, the complex cross-sectional shape of the ceramic body 11 is believed to improve the strength of the ceramic body 11 itself. This improved strength of the multilayer ceramic capacitor 10 is believed to suppress the occurrence of cracks in the multilayer ceramic capacitor 10.

[0046] Fig. 4(A) shows a modified multilayer ceramic capacitor 10'. The position of the recess 23 in the multilayer ceramic capacitor 10' is different from the position of the recess 23 shown in Fig. 3(A). As such, the recess 23 may be formed in various positions.

[0047] FIG. 4(B) shows a multilayer ceramic capacitor 10'' of yet another modified example. In the multilayer ceramic capacitor 10 shown in FIG. 3(A) and the multilayer ceramic capacitor 10' shown in FIG. 4(A), the recesses 23 are formed in the cover portion 18. In contrast, in the multilayer ceramic capacitor 10'' shown in FIG. 4(B), the recesses 23 are formed in the side margin portion 19. In this way, the recesses 23 may be formed in the cover portion 18, i.e., the main surface 11c, or the side margin portion 19, i.e., the side surface 11b.

[0048] Here, preferred positions for forming recesses 23 as undulating portions will be described with reference to Fig. 5. First, a case where recesses 23 are provided in cover portion 18 (main surface 11c) will be described. When recesses 23 are provided in cover portion 18, it is desirable that recesses 23 be disposed in an area within 40% on each side of center Cm of cover portion 18 in the Y direction.

[0049] Next, a case where the recess 23 as the undulating portion is provided in the side margin portion 19 (side surface 11b) will be described. When the recess 23 is provided in the side margin portion 19, it is desirable that the recess 23 be located in an area within 40% on each side of the center Cs of the side margin portion 19 in the Z direction.

[0050] This makes it easier to ensure a desired radius of curvature R1 at the ridge line portion 21, which will be described below.

[0051] (Ring curvature radius R1) Next, the radius of curvature R1 of the ridge line portion 21 will be described. Referring to FIGS. 3A and 3B, the radius of curvature R1 of the ridge line portion 21 formed on the ceramic body 11 of the multilayer ceramic capacitor 10 is set to R1. The radius of curvature R1 is preferably 10 μm or more and 20 μm or less. The multilayer ceramic capacitor 10 may be a so-called 0603 size or smaller. That is, the length dimension L

[10] along the X direction may be 0.6 mm or less, and the width dimension W

[10] along the Y direction may be 0.3 mm or less. To ensure the capacitance of the capacitance forming portion 16, the radius of curvature R1 of the ridge line portion 21 is preferably within an appropriate range. Setting the radius of curvature R1 to 10 μm or more and 20 μm or less ensures the capacitance of the capacitance forming portion 16.

[0052] The radius of curvature R1 of the ridge portion 21 can be set appropriately within a range of 10 μm or more and 20 μm or less. Here, the measurement position and method of the radius of curvature R1 will be described with reference to FIGS. 6A and 6B. Referring to FIG. 6A, the length of one external electrode 14a in the direction along the X-axis is set to L[14a]. In this embodiment, the measurement position of the radius of curvature R1 is set to a position L[14a] / 2 from the end face of the external electrode 14a. Therefore, first, the multilayer ceramic capacitor 10 is polished from the end face of the external electrode 14a to a position L[14a] / 2 to expose the cross section. Then, the exposed cross section is photographed using an optical microscope.

[0053] Then, for the ridgeline portion 21 that appears in the photograph, the radius of curvature R1 can be measured using a virtual circle Vc, as shown, for example, in FIG. 6(B) (first method). First, three points, a first point P1, a second point P2, and a third point P3, are set on the contour of the ridgeline portion 21 that appears in the photograph. The first point P1 is set as follows: A virtual line L1 extending in the Y-axis direction along the main surface 11c is set. The first point P1 is set at a position where this virtual line L1 moves away from the ridgeline portion 21. The second point P2 is set at the end of the ridgeline portion 21 opposite to the first point P1. The third point P3 is set at the vertex of the first ridgeline portion 24a. The vertex of the ridgeline portion 21 (third point P3) is identified as follows: A virtual line L2 that passes through the second point P2 and extends in the Z-direction is set. The virtual lines L1 and L2 are perpendicular to each other. A virtual line L3 is set that passes through the intersection of virtual lines L1 and L2 and has an angle of θ = 45° from virtual line L1. The intersection of virtual line L3 and the outline of ridge line portion 21 is identified as the vertex of ridge line portion 21, and a third point P3 is set at this point.

[0054] Then, a virtual circle Vc is set so that the degree of coincidence between the first point P1 to the third point P3 is equal to or greater than a predetermined value, and the radius of the virtual circle Vc is set as the radius of curvature R1.

[0055] The radius of curvature R1 can also be measured by other methods. For example, as shown in Fig. 6(C), imaginary circles Vc of various radii Rn are superimposed on the contour of the ridgeline portion 21. Then, when the degree of coincidence between the contour of the ridgeline portion 21 and the imaginary circle Vc is equal to or greater than a predetermined value, the radius of the imaginary circle Vc may be determined to be the radius of curvature R1 (second method).

[0056] Note that the measurement positions are just an example, and other positions along the X-axis direction may be used as measurement positions, or multiple positions may be used as measurement positions. When measurements are taken at multiple positions, the average value may be used.

[0057] 2(A), the ceramic body 11 has a corner 22 that appears in a cross section including the X direction and the Z direction. The corner 22 shown in FIG. 2(A) has a radius of curvature R2. The radius of curvature R2 can be measured in the cross section shown in FIG. 2(A) in a manner similar to that used to measure the radius of curvature R1 described above.

[0058] 2(B), the ceramic body 11 has a corner 22 that appears in a cross section including the X and Y directions. The corner 22 shown in FIG. 2(A) has a radius of curvature R3. The radius of curvature R3 can be measured in the cross section shown in FIG. 2(B) in a manner similar to that used to measure the radius of curvature R1 described above.

[0059] In this embodiment, the radius of curvature R1 is larger than the radii of curvature R2 and R3. Such a radius of curvature R1 is achieved while maintaining the distance between the surface of the ceramic body 11 and the capacitance generating portion 16, i.e., the thickness of the protective portion 17 (particularly the cover portion 18 and the side margin portion 19), thin. As a result, the capacitance of the capacitance generating portion 16 is ensured. [Method of manufacturing the multilayer ceramic capacitor 10] FIG. 7 is a flowchart showing a method for manufacturing a multilayer ceramic capacitor 10. FIG. 8 is a perspective view showing part of the manufacturing process for a laminated chip bar. FIG. 9 is an explanatory view showing an enlarged portion of a laminated chip bar. FIG. 10(A) is a view showing the laminated chip bar as viewed from the X direction. FIG. 10(B) is a view showing the laminated chip bar sandwiched between two ceramic sheets as viewed from the X direction. FIG. 11(A) is a perspective view of the laminated chip bar sandwiched between ceramic sheets. FIG. 11(B) is a perspective view of an envelope in which the laminated chip bar is wrapped between two ceramic sheets. The method for manufacturing a multilayer ceramic capacitor 10 will be described below with reference to FIG. 7 and, where appropriate, FIGS. 8 to 11.

[0060] (Step S01: Fabrication of laminated chip bar Cbar) In step S01, ceramic sheets 101 and 102 for forming capacitance forming portions 16 are laminated and cut to produce an unfired laminated chip bar Cbar. As shown in Figures 9 and 11(A), the laminated chip bar Cber is a laminate in which laminated chips are lined up in the X direction, and is a laminate before being cut to a desired length.

[0061] 8 are formed as unfired dielectric green sheets containing a ceramic material made of dielectric ceramic, an organic binder, and other additives. An unfired first internal electrode layer 112 corresponding to the first internal electrode layer 12 is formed on the ceramic sheet 101. An unfired second internal electrode layer 113 corresponding to the second internal electrode layer 13 is formed on the ceramic sheet 102.

[0062] Each of the internal electrode layers 112 and 113 has a plurality of strip-shaped electrode patterns that cross a cutting line Lx parallel to the X-axis direction and extend along a cutting line Ly parallel to the Y-axis direction. These internal electrode layers 112 and 113 are formed by applying a conductive paste to the ceramic sheets 101 and 102 by a printing method or the like.

[0063] 8, the ceramic sheets 101 and 102 are alternately stacked in the Z-axis direction. The stack of the ceramic sheets 101 and 102 corresponds to the capacitance forming portion 16 and the end margin portion 20. The number of stacked ceramic sheets 101 and 102 can be adjusted as appropriate.

[0064] Next, the laminate of the ceramic sheets 101 and 102 is pressed together in the Z-axis direction and cut along the cutting lines Lx (i.e., cutting along the cutting lines Ly is not performed here), thereby producing the laminated chip bar Cbar.

[0065] The laminated chip bar Cbar has an unsintered capacitance forming portion 116 on which unsintered internal electrode layers 112, 113 are formed, and an unsintered end margin portion 120. In the laminated chip bar Cbar, ends of the unsintered internal electrode layers 112, 113 are exposed from a side surface Cb, which is a cut surface corresponding to the cutting line Lx.

[0066] (Step S02: Prepare ceramic sheet 117S) In step S02, two ceramic sheets 117S are prepared to abut against the side surfaces Cb of the laminated chip bar Cbar and sandwich the laminated chip bar bar. The ceramic sheets 117S are formed as unsintered dielectric green sheets, similar to the ceramic sheets 101 and 102. Here, the dimensions of the ceramic sheets 117S will be described with reference to FIGS. 10(A) to 11(A). First, the dimensions of the laminated chip bar Cbar will be described. With reference to FIG. 10(A), the Y-direction dimension of the laminated chip bar Cbar, i.e., its width dimension, is W[CBar], and its Z-direction dimension, i.e., its height dimension, is H[Cbar]. With reference to FIG. 10(B), the width dimension of the ceramic sheet 117S is W[117S]. Here, the width dimension W[117S] can be calculated as the width dimension W[CBar] + the height dimension H[Cbar]. As a result, the ceramic sheet 117S abutting against the side surface Cb of the laminated chip bar Cbar can extend to the main surface Cc of the laminated chip bar Cbar. Here, the width dimension W[Cbar] is assumed to be approximately 0.2 mm or more and 0.3 mm or less, and the height dimension H[Cbar] is assumed to be approximately 0.1 mm or more and 0.25 mm or less. In other words, the width dimension W[117S] can be approximately 0.3 mm or more and 0.55 mm or less. The thickness dimension T[117S] of the ceramic sheet 117S can be, for example, 20 μm or more and 30 μm or less. The lower limit of the thickness dimension T[117S], 20 μm, is set to a thickness that ensures the reliability of the cover portion 18 and the side margin portion 19. As will be described later, the ceramic sheet 117S is arranged around the laminated chip bar Cbar so as to wrap around the laminated chip bar Cbar. At this time, the ceramic sheet 117S passes through the corner where the side surface Cb and the main surface Cc of the laminated chip bar Cbar are connected. Therefore, it is expected that the ceramic sheet 117S will shrink partially during the manufacturing process, and as a result, there will be some areas that become slightly thinner. The lower limit of the thickness dimension T[117S] is set to a thickness that will ensure the reliability of the cover portion 18 and the side margin portion 19 even after such a process.On the other hand, the upper limit of the thickness dimension T[117S], 30 μm, is set as a thickness that ensures the area of ​​the internal electrode layers 12, 13 and the desired capacitance of the capacitance forming portion 16. If the thickness of the cover portion 18 and the side margin portion 19 increases, the capacitance of the capacitance forming portion 16 decreases accordingly, so the upper limit of the thickness dimension T[117S] is set so as to ensure the desired capacitance.

[0067] Referring to FIG. 11(A), the length L[Cbar] of the laminated chip bar Cbar along the X direction and the length L[117S] of the ceramic sheet 117S along the X direction are set to the same value.

[0068] (Step S03: Clamping) In step S03, ceramic sheets 117S are placed on the side surfaces Cb of the laminated chip bar Cbar, and the laminated chip bar Cbar is sandwiched between the two ceramic sheets 117S. After sandwiching the laminated chip bar Cbar between the two ceramic sheets 117S, the ends of the ceramic sheets 117S are pressed together as shown by arrow 1a. This results in an envelope 121 in which the laminated chip bar Cbar is wrapped in the ceramic sheets 117S. Alternatively, the ceramic sheets 117S may be placed on the main surfaces Cc, and the laminated chip bar Cbar may be sandwiched between the ceramic sheets 117S.

[0069] (Step S04: Crimping) In step S04, pressure is applied uniformly to the periphery to perform compression bonding. For example, compression bonding is performed using an isostatic press. As a result, the ceramic sheet 117S adheres tightly to the laminated chip bar Cbar in the envelope 121. In such a laminated chip bar Cbar, a ridge portion 21 with a radius of curvature R1 is formed. Here, in this embodiment, the thickness dimension T[117S] of the ceramic sheet 117S is set to, for example, 20 μm or more and 30 μm or less, and the ceramic sheet 117S wraps around from the side surface Cb of the laminated chip bar Cbar to the main surface Cc, so that the radius of curvature R1 falls within the range of 10 μm or more and 20 μm or less.

[0070] (Step S05: Cut) In step S05, the envelope 121 in which the ceramic sheet 117S is in close contact with the laminated chip bar Cbar is cut along the cutting lines Ly (see FIG. 9), thereby obtaining unfired laminated chips.

[0071] (Step S06: Forming external electrodes) In step S06, the external electrodes 14a, 14b are formed. Specifically, first, an unsintered electrode material is applied to the end face 11a, and then the unsintered electrode material is also applied to the side face 11b, the main face 11c, and part of the ridge line portion 21 that are connected to the end face 11a. The application method is, for example, a dipping method. In the dipping method, the end face 11a side of the ceramic body 11 is immersed in a dipping bath containing an electrode material such as a conductive paste.

[0072] The method for forming the undercoat film is not limited to the dipping method, but may be, for example, a printing method, a sputtering method, or a combination of these. In other words, various conventionally known methods may be employed.

[0073] The green electrode material is then baked, for example, in a reducing atmosphere or a low oxygen partial pressure atmosphere.

[0074] Then, a plating film is formed, thereby forming the external electrodes 14a and 14b.

[0075] (Step S07: Firing) In step S07, the ceramic body on which the external electrodes 14a, 14b have been formed in step S06 is fired to produce the ceramic body 11. The firing temperature in step S07 can be determined based on the sintering temperature of the ceramic body 111. Furthermore, firing can be performed, for example, in a reducing atmosphere or a low-oxygen partial pressure atmosphere.

[0076] In this manner, the multilayer ceramic capacitor 10 is manufactured. In this embodiment, the cover portion 18 and the side margin portion 19 are continuously formed by the two ceramic sheets 117S sandwiching the multilayer chip bar Cbar. Accordingly, the ceramic sheets 117S are curved to form ridge portions 21. As a result, the ceramic body 11 has ridge portions 21 with a radius of curvature R1. In other words, in this embodiment, the ridge portions 21 with a radius of curvature R1 can be formed without barrel polishing.

[0077] In this embodiment, barrel polishing is not performed. Therefore, the corners 22 are in a state where the laminated chip bars Cbar are cut. As a result, the curvature radii R2 and R3 of the corners 22 are smaller than the curvature radius R1.

[0078] In the manufacturing method of this embodiment, the edges of the ceramic sheets 117S are butted together to wrap the laminated chip bar Cbar. Therefore, in order for the protective portion 17 to properly cover the capacitance forming portion 16, the radius of curvature R1 needs to be within an appropriate range.

[0079] The ceramic body 11′ shown in FIG. 13(A) has a radius of curvature R1<10 μm. If the radius of curvature R1 is small, the ends of the ceramic sheets 117S cannot be joined properly, resulting in an improper formation of the cover portion. If the ceramic sheets 117S are too thin or the pressure-bonding force is too strong, the configuration shown in FIG. 13(A) is likely to occur. Furthermore, the ceramic body 11″ shown in FIG. 13(C) has a radius of curvature R1>20 μm. If the radius of curvature R1 is large, the ceramic sheets 117S cannot adhere to the capacitance forming portion 16 and may peel off. If the pressure-bonding force of the ceramic sheets 117S is too weak, the configuration shown in FIG. 13(C) is likely to occur. In contrast, for example, if the radius of curvature R1 is 15 μm, as shown in FIG. 13(B), the ends of the ceramic sheets 117S can be joined properly.

[0080] (Variation) Here, a description will be given of a multilayer ceramic capacitor 30 of a modified example, focusing on the differences from the multilayer ceramic capacitor 10 of the first embodiment, with reference to Fig. 14. The uneven portions in the multilayer ceramic capacitor 10 are formed as recesses 23. In contrast, the multilayer ceramic capacitor 30 has stepped portions 24 instead of the recesses 23. Other than this, the configuration is generally the same between the two, and therefore the common components are denoted by the same reference numerals in the drawings, and detailed description thereof will be omitted.

[0081] In the multilayer ceramic capacitor 30 shown in FIG. 14, the step portion 24 is formed in the cover portion 18, but it may also be formed in the side margin portion 19.

[0082] The ratio of the height h

[24] of the step portion 24 in the multilayer ceramic capacitor 30 to the thickness t

[18] of the cover portion 18 can be set to 10% or more and 30% or less, thereby enabling the multilayer ceramic capacitor 30 to be stably mounted on the substrate.

[0083] Here, the thickness t

[18] of the cover portion 18 is the thickness of the higher side of the step portion 24. The height h

[24] of the step portion 24 is the difference between the thickness of the higher side and the thickness of the lower side of the step portion 24. The thickness of the higher side of the step portion 24 can be the dimension of the thickest part of the cover portion 18. Furthermore, the thickness of the higher side of the step portion 24 may be the average value of the thicknesses of several points on the higher side of the step portion 24. The thickness of the lower side of the step portion 24 can be the dimension of the thinnest part of the cover portion 18. Furthermore, the thickness of the lower side of the step portion 24 may be the average value of the thicknesses of several points on the lower side of the step portion 24. When the step portion 24 is formed in the side margin portion 19, the height h

[24] of the step portion 24 can be set in a similar manner.

[0084] The multilayer ceramic capacitor 30 has four ridge lines 21, similar to the multilayer ceramic capacitor 10. The radii of curvature R1 of the ridge lines 21 may be different values. It is assumed that the radii of curvature R1 of the ridge lines 21 continuing to the lower side of the step portion 24 is smaller than the radii of curvature R1 of the ridge lines 21 continuing to the higher side of the step portion 24. However, it is sufficient that the radii of curvature R1 of all the ridge lines 21 are set to be 10 μm or more and 20 μm or less.

[0085] In the multilayer ceramic capacitor 30, the formation of the step portion 24 increases the circumferential length of the ceramic body 11, and the contact area with the external electrodes 14a, 14b. As a result, the overall strength of the multilayer ceramic capacitor 30 is improved, and for example, the resistance to bending is also improved. Furthermore, it is believed that the strength of the ceramic body 11 itself is improved by making the cross-sectional shape of the ceramic body 11 more complex. It is believed that the improvement in the strength of the multilayer ceramic capacitor 10 in this way will suppress the occurrence of cracks in the multilayer ceramic capacitor 30.

[0086] The multilayer ceramic capacitor 30 can be fabricated in the same manner as the multilayer ceramic capacitor 10. In the multilayer ceramic capacitor 30, recesses 23 or steps 24 are formed due to discrepancies in the timing, speed, or magnitude of the force with which two ceramic sheets 117S (see FIGS. 11(A), 11(B), etc.) approach each other when their ends are butted together, or due to slight discrepancies in the dimensions of the two ceramic sheets 117S. In either case, the strength of the multilayer ceramic capacitor 10 (30) can be improved. Note that while the preferred positions for forming the recesses 23 have been described with reference to FIG. 5, it is preferable that the steps 24 be formed in similar positions.

[0087] Second Embodiment [Configuration of multilayer ceramic capacitor 40] Next, a multilayer ceramic capacitor 40 according to a second embodiment will be described with reference to Fig. 15 to Fig. 17. The multilayer ceramic capacitor 40 includes a ceramic body 41 instead of the ceramic body 11 included in the multilayer ceramic capacitor 10 according to the first embodiment. The ceramic body 41 has recesses 54 (see Fig. 15(A) and Fig. 15(B)) or step portions 53 (see Fig. 15(C)) formed as non-uniform portions instead of the recesses 23 of the first embodiment.

[0088] In other respects, the configuration of the multilayer ceramic capacitor 40 is generally the same as that of the multilayer ceramic capacitor 10. For example, the radius of curvature of the ridge line portion 51 is R1, which is larger than the radii of curvature R2 and R3 of the corner portions 22. For this reason, the common components are denoted by the same reference numerals in the drawings, and detailed description thereof will be omitted.

[0089] While recesses 23 are formed in two places, step portion 53 or recess 54 is formed in only one place around the entire periphery of ceramic body 41. This is due to the manufacturing method of multilayer ceramic capacitor 40, which will be described later.

[0090] Here, the location of the uneven portion will be described with reference to FIGS. 15(A) to 16. The ceramic body 41 includes a protective portion 47. The protective portion 47 includes a cover portion 48 and a side margin portion 49. FIG. 15(A) shows an example in which a step portion 53 is formed in one of the pair of cover portions 48 on which the main surface 41c is formed. FIG. 15(B) shows an example in which the step portion 53 is formed in one of the pair of side margin portions 49 on which the side surface 41b is formed. FIG. 15(C) shows an example in which a recess 54 is formed in one of the pair of cover portions 48. The step portion 53 shown in FIGS. 15(A) and 15(B) may be a recess 54, and the recess 54 shown in FIG. 15(C) may be a step portion 53. The positions of the step portion 53 and the recess 54 in each drawing are merely examples. That is, in the second embodiment, one step portion 53 or recess 54 is provided around the entire periphery of the ceramic body 41.

[0091] However, in order to set the radius of curvature R1 within an appropriate range, it is desirable that the step portion 53 and the recessed portion 54 be provided within a predetermined range.

[0092] Here, a preferred position where the uneven portion is formed will be described with reference to Fig. 16. As described above, this embodiment includes the step portion 53 or the recess 54, but the following description will be given as an example where the step portion 53 is provided. First, a case where the step portion 53 is provided on the cover portion 48 (main surface 41c) will be described. When the step portion 53 is provided on the cover portion 48, it is desirable that the step portion 53 be disposed in an area within 40% on each side of the center Cm of the cover portion 48 in the Y direction.

[0093] Next, a case where the step portion 53 is provided on the side margin portion 49 (side surface 41b) will be described. When the step portion 53 is provided on the side margin portion 49, it is desirable that the step portion 53 be disposed in an area within 40% on each side of the center Cs of the side margin portion 49 in the Z direction.

[0094] This makes it easier to ensure a desired radius of curvature R1 at the ridge line portion 51, which will be described below.

[0095] [Method of manufacturing the multilayer ceramic capacitor 40] Next, a method for manufacturing the multilayer ceramic capacitor 40 will be described with reference to Fig. 17. The method for manufacturing the multilayer ceramic capacitor 40 is generally the same as the method for manufacturing the multilayer ceramic capacitor 10 of the first embodiment, the flowchart of which is shown in Fig. 7. However, the method for manufacturing the multilayer ceramic capacitor 40 differs from the method for manufacturing the multilayer ceramic capacitor 40 in steps S02 and S03 in the flowchart of Fig. 7. This point will be mainly described below.

[0096] In step S02, one ceramic sheet 117S' is prepared instead of the two ceramic sheets 117S. The ceramic sheet 117S' is wrapped around the outer periphery of the laminated chip bar Cbar. Referring to FIG. 18, the ceramic sheet 117S' has dimensions L[117S'] x W[117S'] x T[117S']. The dimension L[117S'] is the dimension along the X direction of the laminated ceramic capacitor 40 when it is finally formed into the laminated ceramic capacitor 40. The dimension W[117S'] is the dimension along the circumferential direction of the four outer peripheries formed along the X direction of the laminated chip bar Cbar. Therefore, the dimension W[117S'] is set to twice the total dimension of the height dimension H[Cbar] and width dimension W[Cbar] of the laminated chip bar Cbar. Here, the width dimension W[Cbar] is expected to be approximately 0.2 mm or more and 0.3 mm or less, and the height dimension H[Cbar] is expected to be approximately 0.1 mm or more and 0.25 mm or less. That is, the dimension W[117S'] can be approximately 0.6 mm or more and 1.1 mm or less. The thickness dimension T[117S'] of the ceramic sheet 117S' can be, for example, 20 μm or more and 30 μm or less, similar to the thickness dimension T[117S] of the ceramic sheet 117S. The upper and lower limits of the thickness dimension T[117S'] of the ceramic sheet 117S' are set from the same perspective as the setting of the thickness dimension T[117S] in the first embodiment, and therefore detailed description thereof will be omitted here. The process of preparing the laminated chip bar Cbar is the same as in the manufacturing method of the first embodiment.

[0097] In step S03, instead of the sandwiching step using two ceramic sheets 117S in the first embodiment, a winding step using one ceramic sheet 117' is performed. In the winding step, as shown in Fig. 17, the laminated chip bar Cbar is mounted on the ceramic sheet 117', and the laminated chip bar Cbar is rolled to wrap the ceramic sheet 117' around the entire circumference of the laminated chip bar Cbar.

[0098] Although the dimension W[117S'] corresponds to one laminated chip bar Cbar, the ceramic sheet 117S' may have a dimension that can accommodate multiple laminated chip bars Cbar. In this case, a process of wrapping the ceramic sheet 117S' around the four sides of one laminated chip bar CBar and then cutting off the excess portions may be included. In other words, the process of wrapping the ceramic sheet 117S' and the process of cutting off the excess portions can be performed alternately. Even in this case, a ceramic sheet 117S' with dimension W[117S'] is used for one laminated chip bar Cbar.

[0099] The wrapping body (not shown) obtained by wrapping the ceramic sheet 117' around the laminated chip bar Cbar is then pressure-bonded to the laminated chip bar Cbar and the ceramic sheet 117'. As a result, the wrapping body (not shown) is obtained in which the step portion 53 and the recessed portion 54 are formed.

[0100] Thereafter, the multilayer ceramic capacitor 40 is obtained through steps S04 to S07.

[0101] Third Embodiment Next, a multilayer ceramic capacitor 70 according to a third embodiment will be described with reference to Fig. 18(A-1) and Fig. 18(A-2). Fig. 18(A-1) is a diagram showing a part of the process for manufacturing the multilayer ceramic capacitor 70 according to the third embodiment. Fig. 18(A-2) is a diagram showing the multilayer ceramic capacitor 70 according to the third embodiment as viewed from the X direction.

[0102] 18(A-1), the multilayer ceramic capacitor 70 is fabricated by wrapping the multilayer chip bar Cbar' between two ceramic sheets 217 and compressing them together. That is, the multilayer ceramic capacitor 70 can be fabricated in the same manner as in the first embodiment.

[0103] For this reason, the multilayer ceramic capacitor 70 has recesses 73. The multilayer ceramic capacitor 70 also has ridges 71. The ridges 71 have a radius of curvature R1. Note that reference numeral 74 in FIG. 18(A-1) denotes external electrodes.

[0104] The height dimension h

[70] of the multilayer ceramic capacitor 70 is smaller than the width dimension w

[70] . The height dimension h

[70] is also smaller than the length dimension (not shown). In other words, the multilayer ceramic capacitor 70 is a so-called low-profile multilayer ceramic capacitor. The height dimension h

[70] can be 110 μm or less.

[0105] Even such a low-profile multilayer ceramic capacitor 70 can be provided with ridge lines 71 having a radius of curvature R1 by fabricating it by sandwiching the multilayer chip bar Cbar' between ceramic sheets 217 and pressure-bonding them.

[0106] (Variation) Next, a multilayer ceramic capacitor 70' according to a modified example of the third embodiment will be described with reference to Fig. 18(B-1) and Fig. 18(B-2). Fig. 18(B-1) is a diagram showing a part of the process for fabricating the multilayer ceramic capacitor 70' according to the modified example of the third embodiment. Fig. 18(B-2) is a diagram showing the multilayer ceramic capacitor 70' according to the modified example of the third embodiment as viewed from the X direction.

[0107] In the manufacturing method of the multilayer ceramic capacitor 70' of the modified example, the direction in which the multilayer chip bar Cbar' is sandwiched between the ceramic sheets 217 differs from that of the third embodiment. As a result, the position of the recess 73 differs from that of the multilayer ceramic capacitor 70 of the third embodiment. This multilayer ceramic capacitor 70' can also have a ridge portion 71 with a curvature radius R1 similar to that of the first embodiment. [Example]

[0108] Next, examples will be described. First, examples 1-1 to 1-4 and comparative examples 1-1 to 1-5 shown in Table 1 will be described. Examples 1-1 to 1-4 correspond to the multilayer ceramic capacitor 10 of the first embodiment. Comparative examples 1-1 to 1-5 have an external shape corresponding to the multilayer ceramic capacitor 10, but the range of recess depth (%) described below differs from that of examples 1-1 to 1-4. Examples 1-1 to 1-4 and comparative examples 1-1 to 1-5 were evaluated for the presence or absence of cracks during mounting and reliability, and a comprehensive evaluation was performed accordingly. Samples for evaluation were obtained from the same lot. Therefore, the evaluation was performed for the production lot.

[0109] The evaluation of crack occurrence was carried out for each example and comparative example, with the number of evaluation objects extracted from the target lot set at N = 100. Products with a crack occurrence rate of less than 10% were evaluated as acceptable (◯), and products with a crack occurrence rate of 10% or more were evaluated as defective (×).

[0110] The reliability evaluation was performed with N=100 for each example and comparative example. The reliability evaluation was performed based on the results of a moisture resistance test. Products with abnormal appearance or decreased capacity were deemed defective. Products with a defect rate of 0% or more but less than 5% were deemed acceptable (◯), and products with a defect rate of 5% or more were deemed defective (△ or ×). In Table 1, a defect rate of 5% or more but less than 10% is indicated by △, and a defect rate of 10% or more is indicated by ×. In the moisture resistance test, samples according to the examples and comparative examples were kept at a temperature of 85°C, a humidity of 85%, and a rated voltage of 4 V was applied for 60 hours.

[0111] The ridge curvature radius in Table 1 is the curvature radius R1 of the multilayer ceramic capacitor 10 of the first embodiment. The recess depth (%) is the ratio of the depth d

[23] to the thickness t

[18] , that is, 100×d

[23] / t

[18] . The edge curvature radius is the average value of the curvature radius R2 and the curvature radius R3 of the multilayer ceramic capacitor 10. The thickness t

[18] , recess depth d

[23] , and curvature radii R1, R2, and R3 for each lot are average values ​​for N=20, where N=20 is the number of evaluation targets extracted from the target lot of finished products.

[0112] [Table 1]

[0113] comparison In Example 1-1, the ridge curvature radius was 15 μm, the recess depth was 0%, and the edge curvature radius was 15 μm. In Comparative Example 1-1, the evaluation of the presence or absence of cracks was ×, the reliability evaluation was ◯, and the overall evaluation was △.

[0114] The curvature radius of the ridgeline of Comparative Example 1-2 was 15 μm, the recess depth was 50%, and the curvature radius of the edge was 1 μm. The evaluation of the presence or absence of cracks in Comparative Example 1-2 was ◯, the reliability evaluation was ×, and the overall evaluation was ×.

[0115] The curvature radius of the ridgeline of Comparative Example 1-3 was 5 μm, the depth of the recess was 80%, and the curvature radius of the edge was 2 μm. The evaluation of the presence or absence of cracks of Comparative Example 1-3 was ◯, the reliability evaluation was ×, and the overall evaluation was ×.

[0116] The curvature radius of the ridgeline of Comparative Example 1-4 was 20 μm, the recess depth was 40%, and the curvature radius of the edge was 2 μm. The evaluation of the presence or absence of cracks in Comparative Example 1-4 was ◯, the reliability evaluation was △, and the overall evaluation was △.

[0117] The curvature radius of the ridgeline of Comparative Example 1-5 was 15 μm, the recess depth was 40%, and the curvature radius of the edge was 3 μm. The evaluation of the presence or absence of cracks in Comparative Example 1-5 was ◯, the reliability evaluation was △, and the overall evaluation was △.

[0118] In Example 1-1, the radius of curvature of the ridgeline was 15 μm, the depth of the recess was 30%, and the radius of curvature of the edge was 1 μm. In Example 1-1, the evaluation of the presence or absence of cracks was ◯, the reliability was ◯, and the overall evaluation was ◯.

[0119] In Example 1-2, the radius of curvature of the ridgeline was 10 μm, the depth of the recess was 20%, and the radius of curvature of the edge was 3 μm. In Example 1-2, the evaluation of the presence or absence of cracks was rated as ◯, the reliability was rated as ◯, and the overall evaluation was rated as ◯.

[0120] In Example 1-3, the radius of curvature of the ridgeline was 5 μm, the depth of the recess was 30%, and the radius of curvature of the edge was 1 μm. In Example 1-3, the evaluation of the presence or absence of cracks was rated as ◯, the reliability was rated as ◯, and the overall evaluation was rated as ◯.

[0121] In Example 1-4, the radius of curvature of the ridge line was 20 μm, the depth of the recess was 10%, and the radius of curvature of the edge was 3 μm. In Example 1-4, the evaluation of the presence or absence of cracks was rated as ◯, the reliability was rated as ◯, and the overall evaluation was rated as ◯.

[0122] Thus, it was confirmed that the Example was less susceptible to cracking during mounting compared to the Comparative Example, and had higher reliability.

[0123] Next, Examples 2-1 to 2-4 and Comparative Examples 2-1 to 2-5 shown in Table 2 will be described. Examples 2-1 to 2-4 correspond to the multilayer ceramic capacitor 30 of the second embodiment. Comparative Examples 2-1 to 2-5 have an external shape corresponding to the multilayer ceramic capacitor 30, but the range of the step height (%) described below differs from Examples 2-1 to 2-4. Examples 2-1 to 2-4 and Comparative Examples 2-1 to 2-5 were evaluated for the presence or absence of cracks during mounting and for mountability, and a comprehensive evaluation was performed based on these. Samples for evaluation were obtained from the same lot. Therefore, the evaluation was performed for the manufacturing lot.

[0124] The evaluation of crack occurrence was carried out for each example and comparative example, with the number of evaluation objects extracted from the target lot set at N = 100. Products with a crack occurrence rate of less than 10% were evaluated as acceptable (◯), and products with a crack occurrence rate of 10% or more were evaluated as defective (×).

[0125] Mountability was evaluated by evaluating the step height (%), since it is believed that a higher step height will make the multilayer ceramic capacitor mounted on the substrate more likely to tilt. For each example and comparative example, the number of evaluation targets extracted from the target lot was N=20. Mountability was evaluated as passing (◯) when the step height (%) was 0% or more but less than 30%, and failing (△ or ×) when the step height was 30% or more. In Table 2, a step height of 30% or more but less than 50% is indicated by △, and a step height of 50% or more is indicated by ×.

[0126] The ridge curvature radius in Table 2 is the curvature radius R1 of the multilayer ceramic capacitor 30 of the first embodiment. The step height (%) is the ratio of the height h

[24] to the thickness t

[18] , that is, 100 × h

[24] / t

[18] . The edge curvature radius is the average value of the curvature radius R2 and the curvature radius R3 of the multilayer ceramic capacitor 10. For each lot, the thickness t

[18] , step height h

[24] , and curvature radii R1, R2, and R3 are the average values ​​for N=20, where N=20 is the number of evaluation targets extracted from the target lot.

[0127] [Table 2]

[0128] The curvature radius of the ridgeline of Comparative Example 2-1 was 15 μm, the height of the step was 0%, and the curvature radius of the edge was 15 μm. The evaluation of the presence or absence of cracks of Comparative Example 1-1 was ×, the reliability was ◯, and the overall evaluation was △.

[0129] The curvature radius of the ridgeline of Comparative Example 2-2 was 15 μm, the height of the step was 60%, and the curvature radius of the edge was 1 μm. The evaluation of the presence or absence of cracks of Comparative Example 2-2 was ◯, the reliability evaluation was ×, and the overall evaluation was ×.

[0130] The curvature radius of the ridgeline of Comparative Example 2-3 was 20 μm, the height of the step was 100%, and the curvature radius of the edge was 3 μm. The evaluation of the presence or absence of cracks of Comparative Example 2-3 was ◯, the reliability evaluation was ×, and the overall evaluation was ×.

[0131] The curvature radius of the ridgeline of Comparative Example 2-4 was 5 μm, the height of the step was 50%, and the curvature radius of the edge was 3 μm. The evaluation of the presence or absence of cracks in Comparative Example 2-4 was ◯, the reliability was △, and the overall evaluation was △.

[0132] The curvature radius of the ridgeline of Comparative Example 2-5 was 10 μm, the height of the step was 40%, and the curvature radius of the edge was 2 μm. The evaluation of the presence or absence of cracks in Comparative Example 2-5 was ◯, the reliability evaluation was △, and the overall evaluation was △.

[0133] In Example 2-1, the radius of curvature of the ridgeline was 15 μm, the height of the step was 20%, and the radius of curvature of the edge was 1 μm. In Example 2-1, the evaluation of the presence or absence of cracks was rated as ◯, the reliability was rated as ◯, and the overall evaluation was rated as ◯.

[0134] In Example 2-2, the radius of curvature of the ridgeline was 20 μm, the height of the step was 30%, and the radius of curvature of the edge was 2 μm. In Example 2-2, the evaluation of the presence or absence of cracks was rated as ◯, the reliability evaluation was rated as ◯, and the overall evaluation was rated as ◯.

[0135] In Example 2-3, the ridge curvature radius was 5 μm, the step height was 10%, and the edge curvature radius was 1 μm. In Example 2-3, the evaluation of the presence or absence of cracks was rated as ◯, the reliability evaluation was rated as ◯, and the overall evaluation was rated as ◯.

[0136] In Example 2-4, the ridge curvature radius was 10 μm, the step height was 20%, and the edge curvature radius was 1 μm. In Example 2-4, the evaluation of the presence or absence of cracks was rated as ◯, the reliability evaluation was rated as ◯, and the overall evaluation was rated as ◯.

[0137] Thus, it was confirmed that the Examples were less susceptible to cracking during mounting compared to the Comparative Examples, and had high mountability.

[0138] In the above embodiment, the multilayer ceramic capacitor 10 has been described as an example of a multilayer ceramic electronic component, but the present invention is applicable to all multilayer ceramic electronic components in which ceramic layers and internal electrode layers are stacked. Examples of such multilayer ceramic electronic components include chip varistors, chip thermistors, and multilayer inductors. [Explanation of symbols]

[0139] 10, 30, 40... Multilayer ceramic capacitors 11, 41...Ceramic body 12...First internal electrode layer 13...Second internal electrode layer 14a...First external electrode 14b…Second external electrode 21, 51 Ridge 22 Corner 23, 54 recess 24, 53 Step section

Claims

1. an element body having a pair of end faces each facing a first direction, a pair of main faces connected to the end faces and each facing a second direction orthogonal to the first direction, and a pair of side faces connected to the end faces and each facing a third direction orthogonal to the first and second directions, the protective portion including ridge portions connecting the main faces and the side faces adjacent to each other and corner portions connecting the adjacent end faces and the main faces or the adjacent end faces and the side faces, and a capacitance forming portion disposed inside the protective portion; a first external electrode provided on one of the end surfaces, extending to the pair of main surfaces and the pair of side surfaces, and connected to a first internal electrode layer included in the capacitance forming portion; a second external electrode provided on the other end surface, extending to the pair of principal surfaces and the pair of side surfaces, and connected to a second internal electrode layer included in the capacitance forming portion; A multilayer ceramic electronic component comprising: a radius of curvature R1 of the ridge portion in a cross section including the second direction and the third direction is larger than a radius of curvature R2 of the corner portion in a cross section including the first direction and the second direction and a radius of curvature R3 of the corner portion in a cross section including the first direction and the third direction; Multilayer ceramic electronic components.

2. 2. The multilayer ceramic electronic component according to claim 1, the protective portion includes an uneven portion formed along the first direction in a portion where the main surface is formed or a portion where the side surface is formed, Multilayer ceramic electronic components.

3. 3. The multilayer ceramic electronic component according to claim 2, When the uneven portion is provided on the side surface, the non-uniform portion is disposed in an area within 40% on each side of the center of the side surface in the second direction, Multilayer ceramic electronic components.

4. 3. The multilayer ceramic electronic component according to claim 2, When the non-uniform portion is provided on the main surface, the non-uniform portion is disposed in an area within 40% of each of both sides of a center portion of the main surface in the third direction, Multilayer ceramic electronic components.

5. 2. The multilayer ceramic electronic component according to claim 1, The radius of curvature R1 of the ridge line portion is 10 μm or more and 20 μm or less. Multilayer ceramic electronic components.

6. 6. The multilayer ceramic electronic component according to claim 5, The dimension of the multilayer ceramic electronic component along the first direction is 0.6 mm or less. Multilayer ceramic electronic components.

7. 6. The multilayer ceramic electronic component according to claim 5, the dimension of the multilayer ceramic electronic component in the second direction is smaller than the dimension of the multilayer ceramic electronic component in the first direction and the dimension of the multilayer ceramic electronic component in the third direction; Multilayer ceramic electronic components.

8. 8. The multilayer ceramic electronic component according to claim 7, The dimension of the multilayer ceramic electronic component in the second direction is 110 μm or less. Multilayer ceramic electronic components.

9. 3. The multilayer ceramic electronic component according to claim 2, the non-uniform portion is an undulating portion in which the thickness of the protective portion is non-uniform when it appears in a cross section of the element body including the second direction and the third direction. Multilayer ceramic electronic components.

10. 10. The multilayer ceramic electronic component according to claim 9, The undulating portion is a recess, and the ratio of the depth of the recess to the thickness of the protective portion is 10% or more and 30% or less. Multilayer ceramic electronic components.

11. 10. The multilayer ceramic electronic component according to claim 9, The undulating portion is a stepped portion, and the ratio of the height of the stepped portion to the thickness of the protective portion is 10% or more and 30% or less. Multilayer ceramic electronic components.

12. a step of forming a laminated chip bar in which a first internal electrode forming layer in which a plurality of first unsintered internal electrode layers are formed at intervals along a first direction, and a second internal electrode forming layer in which a plurality of second unsintered internal electrode layers are formed at intervals along the first direction, each of which is provided so as to be shifted in the first direction with respect to the first unsintered internal electrode layer, are provided with an unsintered dielectric layer sandwiched therebetween; preparing two ceramic sheets whose short-side dimensions correspond to the sum of the dimensions of the laminated chip bar in a second direction perpendicular to the first direction and the dimensions of the laminated chip bar in a third direction perpendicular to the first and second directions; a sandwiching step of placing the two ceramic sheets on a pair of surfaces of the laminated chip bar facing the second direction or a pair of surfaces of the laminated chip bar facing the third direction, and sandwiching the laminated chip bar between the two ceramic sheets; a pressure-bonding step of pressing the two ceramic sheets against the outer peripheral surface of the laminated chip bar; a cutting step of cutting the laminated chip bar to which the ceramic sheet is pressure-bonded at a predetermined position along the first direction; Including, Manufacturing method for multilayer ceramic electronic components.

13. 13. A method for manufacturing a multilayer ceramic electronic component according to claim 12, comprising: The pressing step is an isostatic pressing step. Manufacturing method for multilayer ceramic electronic components.

14. 13. A method for manufacturing a multilayer ceramic electronic component according to claim 12, comprising: the two ceramic sheets sandwiching the laminated chip bar each have a longitudinal dimension corresponding to the dimension of the laminated chip bar in the first direction; Manufacturing method for multilayer ceramic electronic components.

15. a step of forming a laminated chip bar in which a first internal electrode forming layer in which a plurality of first unsintered internal electrode layers are formed at intervals along a first direction, and a second internal electrode forming layer in which a plurality of second unsintered internal electrode layers are formed at intervals along the first direction, each of which is provided so as to be shifted in the first direction with respect to the first unsintered internal electrode layer, are provided with an unsintered dielectric layer sandwiched therebetween; a winding step of winding a ceramic sheet around an outer peripheral surface formed along the longitudinal direction of the laminated chip bar; a pressure-bonding step of pressing the single ceramic sheet against an outer peripheral surface of the laminated chip bar; a cutting step of cutting the laminated chip bar to which the ceramic sheet is pressure-bonded at a predetermined position along the first direction; Including, Manufacturing method for multilayer ceramic electronic components.

16. 16. A method for manufacturing a multilayer ceramic electronic component according to claim 15, The pressing step is an isostatic pressing step. Manufacturing method for multilayer ceramic electronic components.

17. 16. A method for manufacturing a multilayer ceramic electronic component according to claim 15, The method further includes a step of cutting off an excess portion of the single ceramic sheet wrapped around the entire outer periphery of the laminated chip bar. Manufacturing method for multilayer ceramic electronic components.

18. 16. A method for manufacturing a multilayer ceramic electronic component according to claim 15, The single ceramic sheet wrapped around the outer peripheral surface of the laminated chip bar has a dimension corresponding to twice the total dimension of the dimension of the laminated chip bar in a second direction perpendicular to the first direction and the dimension of the laminated chip bar in a third direction perpendicular to the first direction and the second direction. Manufacturing method for multilayer ceramic electronic components.

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