Inverter device

Abstract

To reduce common-mode noise and suppress the possibility of malfunction and circuit failure.SOLUTION: An inverter device includes N high-side switches, N high-side drivers, N high-side insulated transmission circuits, and a high-side DC / DC converter. For the N high-side switches, when a high-side switch with the smallest absolute value of a potential difference between a low-potential side terminal during conduction and a low-potential side terminal during non-conduction is designated as a first switch, and when the switches are sequentially numbered so that a high-side switch with the largest absolute value of the potential difference is the Nth switch, the first through N high-side insulated transmission circuits each include at least n segmented insulated transmission circuits connected in series. A reference potential side terminal among two output terminals of the segmented insulated transmission circuits from the nth onward is connected to a point having the same potential as the low-potential side terminal of the nth high-side switch when non-conductive.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to an inverter device. [Background technology]

[0002] For example, high-voltage pulses with an amplitude of several kV to several tens of kV may be applied to a plasma device or the like (see Patent Document 1). Such inverter devices that generate high-voltage pulses use high-voltage MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) or high-voltage IGBTs (Insulated-Gate Bipolar Transistors) as switches.

[0003] An inverter device that generates such high-voltage pulses includes an isolated transmission circuit that transmits signals by insulating the wiring between the switch and a control circuit that controls the switch. For example, an inverter device that generates high-voltage pulses includes an isolated transmission circuit that transmits signals by electrically insulating the wiring on the input side (primary side) from the wiring on the output side (secondary side) using a transformer. Also, for example, an inverter device that generates high-voltage pulses may include a transmission circuit that uses optical fiber to achieve isolation by converting an electrical signal into light using a light-emitting element and then converting the light into an electronic signal using a light-receiving element. Furthermore, an inverter device that generates high-voltage pulses includes an isolated DC / DC converter as a power conversion circuit that supplies power to the drive circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2023-95483 [Patent Document 2] Japanese Patent Publication No. 2020-114142 [Non-patent literature]

[0005] [Non-Patent Document 1] Katsuya Jingu, Keiji Wada, "Voltage Balance Control in Series-Connected SiC-MOSFETs Using Gate Signal Delay", November 1, 2018, IEEJ Transactions on Industrial Applications, Vol. 138 (2018) No. 11, pp. 864-870 Summary of the Invention [Problem to be solved by the invention]

[0006] When an inverter device generates high-voltage pulses and switches at high speed, common-mode noise, which is a large voltage change over time (dV / dt), occurs between the input and output of an isolated circuit. When large common-mode noise occurs, isolated transmission circuits and isolated DC / DC converters may malfunction or fail due to current changes caused by the voltage change over time. For example, the resistance of transmission circuits using optical fiber or transformers to such current changes is specified as common-mode transient immunity or common-mode immunity (CMTI). When an isolated transmission circuit is realized using general semiconductors, it has a resistance of several tens of kV / μs to several hundreds of kV / μs. Furthermore, the resistance of isolated DC / DC converters to such current changes is specified as common-mode current resistance.

[0007] Inverter devices that generate high-voltage pulses must use expensive circuits or slow down the switching speed of their switches if they use isolated transmission circuits within the specified ranges of common-mode transient immunity and common-mode immunity. Similarly, inverter devices that generate high-voltage pulses must use expensive circuits or slow down the switching speed of their switches if they use isolated DC / DC converters within the specified ranges of common-mode current immunity. However, using expensive circuits increases the cost of inverter devices that generate high-voltage pulses, and slowing down the switching speed increases switch loss.

[0008] As a countermeasure, an inverter device that generates high-voltage pulses can reduce the burden of common-mode noise on each circuit by connecting multiple isolated transmission circuits in series or connecting multiple isolated DC / DC converters in series (for example, Patent Document 2 and Non-Patent Document 1). However, because each circuit has variations in parasitic capacitance between the input and output, a larger voltage is applied between the input and output of a circuit with a smaller capacitance than between the input and output of a circuit with a larger capacitance. Therefore, it is preferable to reduce the burden of common-mode noise on each circuit in an inverter device that generates high-voltage pulses, even if multiple isolated transmission circuits or multiple DC / DC converters are connected in series.

[0009] The present invention has been made in view of the above, and provides an inverter device that can reduce the common-mode noise applied to each of N high-side isolated transmission circuits and suppress the possibility of malfunction and circuit failure. [Means for solving the problem]

[0010] In order to solve the above-mentioned problems and achieve the object, an inverter device according to the present invention includes N high-side switches (N is an integer of 2 or more) connected in series between a first input terminal to which a first voltage is applied and a pulse voltage output terminal, N high-side drivers provided in a one-to-one correspondence with the N high-side switches, each receiving a high-side control signal and switching a corresponding one of the N high-side switches between conductive and non-conductive in accordance with the high-side control signal, N high-side isolated transmission circuits provided in a one-to-one correspondence with the N high-side drivers, each receiving a signal output from a control circuit and providing the high-side control signal, isolated from the control circuit, to a corresponding one of the N high-side drivers, and a high-side DC / DC converter for supplying a drive voltage to each of the N high-side drivers, When the high-side switches are numbered in order such that the high-side switch with the smallest absolute value of the potential difference between the potential of its terminal at its low potential side when non-conducting is designated as the first, and the high-side switch with the largest absolute value of said potential difference is designated as the Nth, the reference potential side terminal of one of the two output terminals of an nth high-side isolated transmission circuit (n is an integer between 1 and N) among the first to Nth high-side isolated transmission circuits is connected to a point at the same potential as the low-potential side terminal of the nth high-side switch when non-conducting or to a point at a potential with a predetermined potential difference from the low-potential side terminal, and the first to Nth high-side isolated transmission circuits each include at least n divided isolated transmission circuits connected in series, and the reference potential side terminal of one of the two output terminals of the nth or later divided isolated transmission circuits counting from the control circuit side is connected to a point at the same potential as the low-potential side terminal of the nth high-side switch when non-conducting or to a point at a potential with a predetermined potential difference from the low-potential side terminal. [Effects of the Invention]

[0011] According to the present invention, it is possible to reduce the common mode noise applied to each of the N high-side isolated transmission circuits, thereby suppressing the possibility of malfunction and circuit failure. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram showing a transmitting device and an inverter device according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing the configuration of the inverter device according to the first embodiment. [Figure 3] FIG. 3 is a diagram showing the configuration of the high-side drive circuit according to the first embodiment, together with N high-side switches. [Figure 4] FIG. 4 is a diagram showing a modified example of the configuration of the high-side driver circuit according to the first embodiment. [Figure 5] FIG. 5 is a diagram showing the configuration of the low-side drive circuit according to the first embodiment, together with M low-side switches. [Figure 6] FIG. 6 is a diagram showing the configuration of the nth high-side driver and the nth high-side potential difference circuit. [Figure 7] FIG. 7 is a diagram showing the configuration of an inverter device according to the second embodiment. [Figure 8] FIG. 8 is a diagram showing the configuration of a high-side drive circuit according to the second embodiment, together with N high-side switches. [Figure 9] FIG. 9 is a diagram showing the configuration of a low-side drive circuit according to the second embodiment, together with M low-side switches. DETAILED DESCRIPTION OF THE INVENTION

[0013] (First embodiment) FIG. 1 is a diagram showing a transmitter device 10 and an inverter device 20 according to the first embodiment.

[0014] The transmitting device 10 transmits a control signal to the inverter device 20. For example, the transmitting device 10 may transmit an optical signal as the control signal to the inverter device 20. Alternatively, the transmitting device 10 may transmit an electrical signal as the control signal to the inverter device 20.

[0015] The inverter device 20 receives a control signal from the transmitter device 10 and performs switching in response to the received control signal. The inverter device 20 includes a first input terminal 22, a second input terminal 24, a reference voltage input terminal 26, a drive voltage input terminal 28, a signal input terminal 32, and a pulse voltage output terminal 34. The first input terminal 22, the second input terminal 24, the reference voltage input terminal 26, the drive voltage input terminal 28, the signal input terminal 32, and the pulse voltage output terminal 34 may be electrodes or metal pads, or may be part of electrical wiring.

[0016] A first voltage is applied to the first input terminal 22. A second voltage lower than the first voltage is applied to the second input terminal 24. In this embodiment, the second voltage is a negative voltage. In this embodiment, the first voltage is 0 V, which is the ground potential of the power line system on the output side. In this embodiment, the second voltage is −3 kV, which is the ground potential of the power line system on the output side. Note that as long as the second voltage is lower than the first voltage, the first voltage and the second voltage are not limited to these voltage values ​​and may be other voltage values. For example, the first voltage may be 0 V, which is the ground potential, and the second voltage may be −10 kV, or the first voltage may be 15 kV, and the second voltage may be 0 V, which is the ground potential. Furthermore, each of the first voltage and the second voltage may be a voltage that changes over time. For example, each of the first voltage and the second voltage may be a pulse voltage, a sinusoidal voltage, or the like.

[0017] A reference voltage of 0 V, which is the reference voltage of the input-side power line system, is applied to the reference voltage input terminal 26. A power supply voltage is applied to the drive voltage input terminal 28. In this embodiment, +24 V of the input-side power line system is applied to the drive voltage input terminal 28 as the power supply voltage. The power supply voltage is not limited to +24 V, and may be any other DC voltage.

[0018] The signal input terminal 32 receives the control signal output from the transmitter 10 .

[0019] The pulse voltage output terminal 34 outputs either the first voltage (0 V) applied to the first input terminal 22 or the second voltage (−3 kV) applied to the second input terminal 24. Note that the pulse voltage output terminal 34 may be in a high impedance state without outputting either the first voltage (0 V) or the second voltage (−3 kV).

[0020] In response to a control signal supplied to the signal input terminal 32, the inverter device 20 switches between outputting a first voltage (0 V) to be applied to the first input terminal 22 and outputting a second voltage (−3 kV) to be applied to the second input terminal 24 from the pulse voltage output terminal 34. The internal circuit of the inverter device 20 is driven based on the power supplied from the drive voltage input terminal 28.

[0021] FIG. 2 is a diagram showing the configuration of the inverter device 20 according to the first embodiment.

[0022] The inverter device 20 includes N high-side switches 42 (42-1 to 42N) (N is an integer of 2 or more), M low-side switches 44 (44-1 to 44-M) (M is an integer of 2 or more), a high-side drive circuit 46, a low-side drive circuit 48, and a control circuit 50.

[0023] The N high-side switches 42 are connected in series between the first input terminal 22 and the pulsed voltage output terminal 34. Each of the N high-side switches 42 can be switched between conductive and non-conductive states. When all of the N high-side switches 42 are switched to conductive states, they can establish conduction between the first input terminal 22 and the pulsed voltage output terminal 34. When at least one of the N high-side switches 42 is switched to non-conductive states, they can establish non-conduction between the first input terminal 22 and the pulsed voltage output terminal 34.

[0024] The M low-side switches 44 are connected in series between the second input terminal 24 and the pulsed voltage output terminal 34. Each of the M low-side switches 44 can be switched to a conductive or non-conductive state. When all of the M low-side switches 44 are switched to a conductive state, they can establish conduction between the second input terminal 24 and the pulsed voltage output terminal 34. When at least one of the M low-side switches 44 is switched to a non-conductive state, they can establish non-conduction between the second input terminal 24 and the pulsed voltage output terminal 34.

[0025] The control circuit 50 receives a control signal transmitted from the transmitting device 10 via the signal input terminal 32. The control circuit 50 generates a first control signal and a second control signal in response to the control signal received via the signal input terminal 32. The first control signal and the second control signal are signals whose logic is inverted from each other. When the first control signal is high logic (for example, a 5V voltage signal), the second control signal is low logic (for example, a 0V voltage signal). When the first control signal is low logic, the second control signal is high logic.

[0026] The high-side drive circuit 46 receives a first control signal from the control circuit 50, and synchronously switches the N high-side switches 42 between conductive and non-conductive states in response to a change in the logic of the first control signal. The high-side drive circuit 46 operates using the power supply voltage (+24 V) as its power source.

[0027] The low-side drive circuit 48 receives a second control signal from the control circuit 50, and synchronously switches the M low-side switches 44 between conductive and non-conductive states in accordance with changes in the logic of the second control signal. The low-side drive circuit 48 operates using the power supply voltage (+24 V) as its power source.

[0028] For example, the high-side drive circuit 46 makes the N high-side switches 42 conductive when the first control signal is high logic, and makes the N high-side switches 42 non-conductive when the first control signal is low logic. For example, the low-side drive circuit 48 makes the M low-side switches 44 conductive when the second control signal is high logic, and makes the M low-side switches 44 non-conductive when the second control signal is low logic. As a result, when the N high-side switches 42 are conductive, the control circuit 50 can make the M low-side switches 44 non-conductive. Furthermore, when the N high-side switches 42 are non-conductive, the control circuit 50 can make the M low-side switches 44 conductive. Therefore, the N high-side switches 42 and the M low-side switches 44 are switched between conductive and non-conductive in a complementary manner. This allows the inverter device 20 to switch between outputting the first voltage (0 V) or the second voltage (−3 kV) from the pulse voltage output terminal 34 in accordance with the control signal applied to the signal input terminal 32.

[0029] Each of the N high-side switches 42 is an N-channel MOSFET. Fig. 2 shows a configuration example where N = 3. The N high-side switches 42 are connected such that their drains and sources are arranged in series. For each of the N high-side switches 42, the drain is arranged on the side of the first input terminal 22 and the source is arranged on the side of the pulse voltage output terminal 34. Furthermore, a voltage is applied between the gate and source of each of the N high-side switches 42 from a high-side drive circuit 46. For each of the N high-side switches 42, the drain-source is switched between conductive (ON) or non-conductive (OFF) depending on the voltage applied between the gate and source.

[0030] A higher voltage is applied to the first input terminal 22 than to the second input terminal 24. Each of the N high-side switches 42 includes a body diode. The anode of the body diode is connected to the source, and the cathode is connected to the drain. Therefore, in each of the N high-side switches 42, the drain serves as a high-potential terminal when the switch is not conducting, and the source serves as a low-potential terminal when the switch is not conducting.

[0031] When conductive, the potential of the low potential side terminal (source) of each of the N high-side switches 42 becomes the first voltage (0 V) applied to the first input terminal 22.

[0032] When the N high-side switches 42 are non-conductive, the potential of the pulse voltage output terminal 34 is the second voltage (-3 V) applied to the second input terminal 24. Therefore, when the N high-side switches 42 are non-conductive, the potential of the low-potential side terminal (source) is a value obtained by multiplying the potential difference (3 kV) between the potential (0 V) of the first input terminal 22 and the potential (-3 kV) of the second input terminal 24 by the first voltage division ratio, and adding this divided voltage to the potential (-3 kV) of the pulse voltage output terminal 34. The first voltage division ratio is a value obtained by dividing N by the number of body diodes from the pulse voltage output terminal 34 to the low-potential side terminal (source).

[0033] Here, the N high-side switches 42 are numbered in ascending order of potential difference, with the high-side switch 42 having the smallest absolute value of the potential difference between the potential of the low-potential side terminal when conductive and the potential of the low-potential side terminal when non-conductive being designated as the first high-side switch 42, and the high-side switch 42 having the largest absolute value of the potential difference being designated as the Nth high-side switch 42. In this case, the n-th high-side switch 42 (n is an integer greater than or equal to 1 and less than or equal to N) having the smallest absolute value of the potential difference among the first to Nth high-side switches 42 is designated as the n-th high-side switch 42-n.

[0034] 2, the high-side switch 42 arranged closest to the first input terminal 22 has a low-potential side terminal (source) with a potential of 0V when conductive (ON) and a low-potential side terminal (source) with a potential of −1 kV when non-conductive (OFF), resulting in a potential difference of 1 kV. The high-side switch 42 arranged second from the first input terminal 22 has a low-potential side terminal (source) with a potential of 0V when conductive (ON) and a low-potential side terminal (source) with a potential of −2 kV when non-conductive (OFF), resulting in a potential difference of 2 kV. The high-side switch 42 arranged closest to the pulse voltage output terminal 34 has a low-potential side terminal (source) with a potential of 0V when conductive (ON) and a low-potential side terminal with a potential of −3 kV when non-conductive (OFF), resulting in a potential difference of 3 kV. 2, the high-side switch 42 arranged closest to the first input terminal 22 is the first high-side switch 42-1. The high-side switch 42 arranged second from the first input terminal 22 is the second high-side switch 42-2. The high-side switch 42 arranged closest to the pulse voltage output terminal 34 is the third high-side switch 42-3.

[0035] Each of the M low-side switches 44 is an N-channel MOSFET. FIG. 2 shows a configuration example where M=3. The M low-side switches 44 are connected such that their drains and sources are arranged in series. The drain of each of the M low-side switches 44 is arranged on the pulse voltage output terminal 34 side, and the source is arranged on the second input terminal 24 side. A voltage is applied between the gate and source of each of the M low-side switches 44 from a low-side drive circuit 48. The drain-source of each of the M low-side switches 44 is switched between conductive (ON) and non-conductive (OFF) depending on the voltage applied between the gate and source.

[0036] A higher voltage is applied to the first input terminal 22 than to the second input terminal 24. Each of the M low-side switches 44 includes a body diode. The anode of the body diode is connected to the source, and the cathode is connected to the drain. Therefore, in each of the M low-side switches 44, the drain serves as a high-potential terminal when non-conductive, and the source serves as a low-potential terminal when non-conductive.

[0037] When conductive, the potential of the low potential side terminal (source) of each of the M low-side switches 44 becomes the second voltage (−3 kV) applied to the second input terminal 24.

[0038] When the M low-side switches 44 are non-conductive, the potential of the pulse voltage output terminal 34 becomes the first voltage (0 V) applied to the first input terminal 22. Therefore, when the M low-side switches 44 are non-conductive, the potential of the low-potential side terminal (source) becomes a value obtained by adding the divided voltage obtained by multiplying the potential difference between the potential (0 V) of the first input terminal 22 and the potential (-3 kV) of the second input terminal 24 by the second voltage division ratio to the potential (-3 kV) of the second input terminal 24. The second voltage division ratio is a value obtained by dividing M by the number of body diodes from the second input terminal 24 to the low-potential side terminal (source).

[0039] Here, the M low-side switches 44 are numbered in ascending order of potential difference, with the low-side switch 44 having the smallest absolute value of the potential difference between the potential of the low-potential side terminal when conductive and the potential of the low-potential side terminal when non-conductive being designated as the first low-side switch 44, and the low-side switch 44 having the largest absolute value of the potential difference being designated as the Mth low-side switch 44. In this case, the mth low-side switch 44 (m is an integer greater than or equal to 1 and less than or equal to M) having the smallest absolute value of the potential difference among the first to Mth low-side switches 44 is designated as the mth low-side switch 44-m.

[0040] 2, the low-side switch 44 arranged closest to the second input terminal 24 has a low-potential side terminal (source) with a potential of −3 kV when not conducting (OFF) and a low-potential side terminal (source) with a potential of −3 kV when conducting (ON), resulting in a potential difference of 0 V. The low-side switch 44 arranged second from the second input terminal 24 has a low-potential side terminal (source) with a potential of −2 kV when not conducting (OFF) and a low-potential side terminal (source) with a potential of −3 kV when conducting (ON), resulting in a potential difference of −1 kV. The low-side switch 44 arranged closest to the pulse voltage output terminal 34 has a low-potential side terminal with a potential of −1 kV when not conducting (OFF) and a low-potential side terminal (source) with a potential of −3 kV when conducting (ON), resulting in a potential difference of −2 kV. 2, the low-side switch 44 arranged closest to the second input terminal 24 is the first low-side switch 44-1. The low-side switch 44 arranged second from the second input terminal 24 is the second low-side switch 44-2. The low-side switch 44 arranged closest to the pulse voltage output terminal 34 is the third low-side switch 44-3.

[0041] FIG. 3 is a diagram showing the configuration of a high-side drive circuit 46 according to the first embodiment, together with N high-side switches 42 (42-1 to 42-N).

[0042] The high-side drive circuit 46 has N high-side potential difference circuits 52 (52-1 to 52-N) and N high-side reference potential lines 54 (54-1 to 54-N).

[0043] The N high-side potential difference circuits 52 are provided in a one-to-one correspondence with the N high-side switches 42. For example, the n-th high-side potential difference circuit 52-n of the first to N-th high-side potential difference circuits 52 corresponds to the n-th high-side switch 42-n of the N high-side switches 42.

[0044] Each of the N high-side potential difference circuits 52 generates a potential with a predetermined potential difference from the potential of the low-potential side terminal (source) of the corresponding high-side switch 42 of the N high-side switches 42 when the switch is not conducting. For example, the n-th high-side potential difference circuit 52-n generates a potential with a predetermined potential difference from the potential of the source of the n-th high-side switch 42-n.

[0045] In this embodiment, the n-th high-side potential difference circuit 52-n generates a potential that is lower than the source of the n-th high-side switch 42-n by about 6 V. The predetermined potential difference may be 0 V.

[0046] The N high-side reference potential lines 54 are provided in a one-to-one correspondence with the N high-side switches 42. For example, the n-th high-side reference potential line 54-n of the first to N-th high-side reference potential lines 54 corresponds to the n-th high-side switch 42-n.

[0047] Each of the N high-side reference potential lines 54 is connected to a location at the same potential as the low-potential side terminal (source) of the corresponding high-side switch 42 when it is not conducting, or to a location at a predetermined potential difference with respect to the low-potential side terminal (source) of the corresponding high-side switch 42 when it is not conducting. For example, the n-th high-side reference potential line 54-n is directly connected to the source of the n-th high-side switch 42-n. Alternatively, the n-th high-side reference potential line 54-n is connected to a terminal of the n-th high-side potential difference circuit 52-n that generates a potential with a predetermined potential difference with respect to the source of the n-th high-side switch 42-n.

[0048] Furthermore, the high-side drive circuit 46 has N high-side drivers 56 (56-1 to 56-N), N high-side isolated transmission circuits 58 (58-1 to 58-N), and a high-side DC / DC converter 60.

[0049] The N high-side drivers 56 are provided in a one-to-one correspondence with the N high-side switches 42. For example, an n-th high-side driver 56-n of the first to N-th high-side drivers 56 corresponds to the n-th high-side switch 42-n.

[0050] Each of the N high-side drivers 56 includes a negative drive potential terminal 62 and a positive drive potential terminal 64 .

[0051] The negative drive potential terminal 62 of each of the N high-side drivers 56 is connected to the high-side reference potential line 54 corresponding to the corresponding high-side switch 42. For example, the negative drive potential terminal 62 of the n-th high-side driver 56-n is connected to the n-th high-side reference potential line 54-n.

[0052] Each of the N high-side drivers 56 receives a drive voltage, referenced to the potential of the corresponding high-side reference potential line 54, from the high-side DC / DC converter 60 at its positive-side drive potential terminal 64. For example, the n-th high-side driver 56-n receives a drive voltage that is +24 V relative to the potential of the n-th high-side reference potential line 54-n at its positive-side drive potential terminal 64. In this embodiment, each of the N high-side drivers 56 receives a drive voltage generated by mutually isolated circuits included in the high-side DC / DC converter 60. Each of the N high-side drivers 56 operates using the supplied drive voltage as a power source.

[0053] Each of the N high-side drivers 56 receives a high-side control signal from a corresponding one of the N high-side isolated transmission circuits 58 via a control signal input terminal. The control voltage output terminal of each of the N high-side drivers 56 is connected to the gate of the corresponding high-side switch 42. Each of the N high-side drivers 56 switches the control voltage output terminal to the potential of the negative-side drive potential terminal 62 or the potential of the positive-side drive potential terminal 64 according to the logic of the high-side control signal received from the control signal input terminal. The potential of the negative-side drive potential terminal 62 of each of the N high-side drivers 56 is the same as the potential of the source of the corresponding high-side switch 42 or has a predetermined potential difference with respect to the source of the corresponding high-side switch 42. Therefore, each of the N high-side drivers 56 can switch the corresponding high-side switch 42 between conductive and non-conductive states according to the logic of the high-side control signal. For example, the nth high-side driver 56-n can switch the drain-source of the nth high-side switch 42-n between conductive and non-conductive states by changing the gate-source voltage of the nth high-side switch 42-n in accordance with the logic of the received high-side control signal.

[0054] The N high-side isolated transmission circuits 58 are provided in a one-to-one correspondence with the N high-side switches 42. For example, the n-th high-side isolated transmission circuit 58-n of the first to N-th high-side isolated transmission circuits 58 corresponds to the n-th high-side switch 42-n.

[0055] Each of the N high-side isolated transmission circuits 58 includes two input terminals (a reference potential side input terminal 581 and a signal input terminal 582). The reference potential side input terminal 581, which is one of the two input terminals in each of the N high-side isolated transmission circuits 58, is connected to 0 V, which is the ground potential of the input-side power line system, and the other of the two input terminals, the signal input terminal 582, receives a first control signal from the control circuit 50.

[0056] Each of the N high-side isolated transmission circuits 58 includes two output terminals (a reference potential output terminal 583 and a signal output terminal 584). The reference potential output terminal 583, which is one of the two output terminals in each of the N high-side isolated transmission circuits 58, is connected to the high-side reference potential line 54 corresponding to the corresponding high-side switch 42. For example, the reference potential output terminal 583, one of the two output terminals in the n-th high-side isolated transmission circuit 58-n, is connected to the n-th high-side reference potential line 54-n. That is, the reference potential output terminal 583, one of the two output terminals in the n-th high-side isolated transmission circuit 58-n, is connected to a location at the same potential as the low-potential terminal (source) of the n-th high-side switch 42-n when the n-th high-side switch 42-n is not conducting, or to a location at a potential that is a predetermined potential difference from the low-potential terminal (source).

[0057] The signal output terminal 584, which is the other of the two output terminals in each of the N high-side isolated transmission circuits 58, supplies a high-side control signal to a corresponding high-side driver 56 among the N high-side drivers 56. For example, the signal output terminal 584, which is one of the two output terminals in the n-th high-side isolated transmission circuit 58-n, supplies a high-side control signal to the n-th high-side driver 56-n.

[0058] In this embodiment, each of the N high-side isolated transmission circuits 58 includes N divided isolated transmission circuits 66 (66-1 to 66-N) connected in series.

[0059] Each of the N divided insulated transmission circuits 66 is a signal transmission means having an insulating function, and outputs an input signal while isolating it. For example, each of the N divided insulated transmission circuits 66 is a transmission circuit using an optical fiber or a transformer.

[0060] Each of the N divided insulated transmission circuits 66 includes two input terminals and two output terminals. In each of the N divided insulated transmission circuits 66, the two input terminals and the two output terminals are insulated from each other.

[0061] Each of the N divided isolated transmission circuits 66 has two input terminals, one of which is connected to a reference potential on the input side, and an input signal is applied to the other of the two input terminals. Each of the N divided isolated transmission circuits 66 has two output terminals, one of which is connected to a reference potential on the output side, and the other of the two output terminals outputs an output signal.

[0062] The first divided isolated transmission circuit 66 of the N divided isolated transmission circuits 66 connected in series has one of its two input terminals connected to 0 V, which is the ground potential of the input-side power line system, as the input-side reference potential. The other of the two input terminals of the first divided isolated transmission circuit 66 receives a first control signal from the control circuit 50 as an input signal.

[0063] Of the N split isolated transmission circuits 66, one of the two input terminals of each split isolated transmission circuit 66 other than the first is connected as the input side reference potential to a reference potential side terminal that is one of the two output terminals of the split isolated transmission circuit 66 connected in the previous stage. The other of the two input terminals of each split isolated transmission circuit 66 other than the first receives, as an input signal, an output signal output from the other of the two output terminals of the split isolated transmission circuit 66 connected in the previous stage.

[0064] The final divided isolated transmission circuit 66 among the N divided isolated transmission circuits 66 has two output terminals, one of which outputs an output signal, that supplies a high-side control signal to the corresponding high-side driver 56 .

[0065] Here, the reference potential side terminal of one of the two output terminals in each of the nth and subsequent divided isolated transmission circuits 66-n to 66-N, counting from the control circuit 50 side, of the first to Nth divided isolated transmission circuits 66 included in the nth high side isolated transmission circuit 58-n, is connected to the nth high side reference potential line 54-n. That is, the reference potential side terminal of one of the two output terminals in the nth and subsequent divided isolated transmission circuits 66 included in the nth high side isolated transmission circuit 58-n is connected to a location at the same potential as the low potential side terminal of the nth high side switch 42-n when the nth high side switch 42-n is not conducting, or to a location at a potential with a predetermined potential difference from the low potential side terminal.

[0066] For example, the reference potential side terminal of the two output terminals of each of the first and subsequent divided isolated transmission circuits 66-1 to 66-N included in the first high side isolated transmission circuit 58-1 is connected to the first high side reference potential line 54-1. Also, for example, the reference potential side terminal of the two output terminals of each of the second and subsequent divided isolated transmission circuits 66-2 to 66-N included in the second high side isolated transmission circuit 58-2 is connected to the second high side reference potential line 54-2. Also, for example, the reference potential side terminal of the two output terminals of each of the third and subsequent divided isolated transmission circuits 66-3 to 66-N included in the third high side isolated transmission circuit 58-3 is connected to the third high side reference potential line 54-3.

[0067] Furthermore, of the N divided isolated transmission circuits 66 included in the nth high-side isolated transmission circuit 58-n, the reference potential side terminal of the two output terminals of the pth divided isolated transmission circuit 66-p (p is an integer greater than or equal to 1 and less than n) that is in the stage before the nth one as counted from the control circuit 50 side is connected to the pth high-side reference potential line 54-p. That is, the reference potential side terminal of the two output terminals of the pth divided isolated transmission circuit 66-p that is in the stage before the nth one that is included in the nth high-side isolated transmission circuit 58-n is connected to a location at the same potential as the low-potential side terminal of the pth high-side switch 42-p when it is not conducting, or to a location at a potential that has a predetermined potential difference from the low-potential side terminal.

[0068] For example, the reference potential side terminal of the two output terminals of the first divided isolated transmission circuit 66-1 included in the second high-side isolated transmission circuit 58-2 is connected to the first high-side reference potential line 54-1. For example, the reference potential side terminal of the two output terminals of the first divided isolated transmission circuit 66-1 included in the third high-side isolated transmission circuit 58-3 is connected to the first high-side reference potential line 54-1. For example, the reference potential side terminal of the two output terminals of the second divided isolated transmission circuit 66-2 included in the third high-side isolated transmission circuit 58-3 is connected to the second high-side reference potential line 54-2.

[0069] The nth high-side isolated transmission circuit 58-n may include at least n divided isolated transmission circuits 66 connected in series. For example, the first high-side isolated transmission circuit 58-1 of the N high-side isolated transmission circuits 58 may include at least one divided isolated transmission circuit 66. The second high-side isolated transmission circuit 58-2 of the N high-side isolated transmission circuits 58 may include at least two divided isolated transmission circuits 66 connected in series. The third high-side isolated transmission circuit 58-3 of the N high-side isolated transmission circuits 58 may include at least three divided isolated transmission circuits 66 connected in series.

[0070] The high-side DC / DC converter 60 receives a power supply voltage output from an external circuit and generates a drive voltage by performing isolated DC-DC power conversion on the power supply voltage. The high-side DC / DC converter 60 supplies the drive voltage to each of the N high-side drivers 56. In this embodiment, the high-side DC / DC converter 60 receives a power supply voltage of +24 V and supplies the drive voltage of +24 V to each of the N high-side drivers 56.

[0071] The high-side DC / DC converter 60 includes N split DC / DC converters 68 (68-1 to 68-N) connected in series. Each of the N split DC / DC converters 68 includes a transformer and performs isolated DC-DC power conversion.

[0072] The first divided DC / DC converter 68 of the N divided DC / DC converters 68 receives a +24V power supply voltage output from an external circuit and generates a +24V drive voltage that is insulated from the external circuit. Each of the divided DC / DC converters 68 other than the first of the N divided DC / DC converters 68 performs isolated DC-DC power conversion on the +24V drive voltage output from the divided DC / DC converter 68 in the previous stage, and generates a +24V drive voltage that is insulated from the divided DC / DC converter 68 in the previous stage.

[0073] Furthermore, the N split DC / DC converters 68 are provided in a one-to-one correspondence with the N high-side drivers 56 .

[0074] The N divided DC / DC converters 68 are numbered in order, with the divided DC / DC converter 68 that receives the voltage output from the external circuit being the first divided DC / DC converter 68-1 and the last divided DC / DC converter 68 being the Nth divided DC / DC converter 68-N.

[0075] In this case, the first to Nth N divided DC / DC converters 68 supply drive voltages to their corresponding high-side drivers 56 in order from the high-side driver 56 corresponding to the high-side switch 42 having the smallest absolute value of the potential at its low-potential side terminal when non-conducting among the N high-side switches 42 to the high-side driver 56 corresponding to the high-side switch 42 having the largest absolute value of the potential at its low-potential side terminal when non-conducting. More specifically, the nth divided DC / DC converter 68-n of the first to Nth N divided DC / DC converters 68 supplies drive voltage to the nth high-side driver 56-n.

[0076] Furthermore, the reference potential side terminal of the two output terminals of the nth divided DC / DC converter 68-n is connected to the nth high-side reference potential line 54-n. That is, the reference potential side terminal of the two output terminals of the nth divided DC / DC converter 68-n is connected to a location at the same potential as the low-potential side terminal of the nth high-side switch 42-n when it is not conducting, or to a location at a potential that is a predetermined potential difference from the low-potential side terminal.

[0077] For example, the reference potential side terminal of one of the two output terminals of the first divided DC / DC converter 68-1 is connected to a location at the same potential as the low potential side terminal of the first high-side switch 42-1 when it is not conducting, or to a location at a potential with a predetermined potential difference from the low potential side terminal. The reference potential side terminal of one of the two output terminals of the second divided DC / DC converter 68-2 is connected to a location at the same potential as the low potential side terminal of the second high-side switch 42-2 when it is not conducting, or to a location at a potential with a predetermined potential difference from the low potential side terminal. The reference potential side terminal of one of the two output terminals of the third divided DC / DC converter 68-3 is connected to a location at the same potential as the low potential side terminal of the third high-side switch 42-3 when it is not conducting, or to a location at a potential with a predetermined potential difference from the low potential side terminal.

[0078] 4 is a diagram showing a modified configuration of the high-side drive circuit 46 according to the first embodiment. As shown in FIG. 4, the high-side drive circuit 46 may be configured not to include N high-side potential difference circuits 52 (52-1 to 52-N). In this case, the n-th high-side reference potential line 54-n is directly connected to the source of the n-th high-side switch 42-n.

[0079] FIG. 5 is a diagram showing the configuration of a low-side drive circuit 48 according to the first embodiment, together with M low-side switches 44 (44-1 to 44-M).

[0080] The low-side drive circuit 48 has M low-side potential difference circuits 72 (72-1 to 72-M) and M low-side reference potential lines 74 (74-1 to 74-M).

[0081] The M low-side potential difference circuits 72 are provided in a one-to-one correspondence with the M low-side switches 44. For example, the m-th low-side potential difference circuit 72-m of the first to M low-side potential difference circuits 72 corresponds to the m-th low-side switch 44-m of the M low-side switches 44.

[0082] Each of the M low-side potential difference circuits 72 generates a potential with a predetermined potential difference from the potential of the low-potential side terminal (source) of the corresponding low-side switch 44 when it is not conducting among the M low-side switches 44. For example, the m-th low-side potential difference circuit 72-m generates a potential with a predetermined potential difference from the potential of the source of the m-th low-side switch 44-m.

[0083] In this embodiment, the m-th low-side potential difference circuit 72-m generates a potential that is lower than the source of the m-th low-side switch 44-m by about 6 V. The predetermined potential difference may be 0 V.

[0084] The M low-side reference potential lines 74 are provided in a one-to-one correspondence with the M low-side switches 44. For example, the m-th low-side reference potential line 74-m of the first to M-th low-side reference potential lines 74 corresponds to the m-th low-side switch 44-m.

[0085] Each of the M low-side reference potential lines 74 is connected to a location at the same potential as the low-potential side terminal (source) of the corresponding low-side switch 44 when it is not conducting, or to a location at a predetermined potential difference with respect to the low-potential side terminal (source) of the corresponding low-side switch 44 when it is not conducting. For example, the m-th low-side reference potential line 74-m is directly connected to the source of the m-th low-side switch 44-m. Alternatively, the m-th low-side reference potential line 74-m is connected to a terminal of the m-th low-side potential difference circuit 72-m that generates a potential with a predetermined potential difference with respect to the source of the m-th low-side switch 44-m.

[0086] Furthermore, the low-side drive circuit 48 has M low-side drivers 76 (76-1 to 76-M), M low-side isolated transmission circuits 78 (78-1 to 78-M), and a low-side DC / DC converter 80.

[0087] The M low-side drivers 76 are provided in a one-to-one correspondence with the M low-side switches 44. For example, an m-th low-side driver 76-m of the first to M-th low-side drivers 76 corresponds to the m-th low-side switch 44-m.

[0088] Each of the M low-side drivers 76 includes a negative drive potential terminal 82 and a positive drive potential terminal 84 .

[0089] In each of the M low-side drivers 76, the negative drive potential terminal 82 is connected to the low-side reference potential line 74 corresponding to the corresponding low-side switch 44. For example, in the m-th low-side driver 76-m, the negative drive potential terminal 82 is connected to the m-th low-side reference potential line 74-m.

[0090] Each of the M low-side drivers 76 receives a drive voltage, referenced to the potential of the corresponding low-side reference potential line 74, from the low-side DC / DC converter 80 at its positive-side drive potential terminal 84. For example, the m-th low-side driver 76-m receives a drive voltage that is +24 V relative to the potential of the m-th low-side reference potential line 74-m at its positive-side drive potential terminal 84. In this embodiment, each of the M low-side drivers 76 receives a drive voltage generated by mutually isolated circuits included in the low-side DC / DC converter 80. Each of the M low-side drivers 76 operates using the supplied drive voltage as a power source.

[0091] Each of the M low-side drivers 76 receives a low-side control signal from a corresponding low-side isolated transmission circuit 78 among the M low-side isolated transmission circuits 78 via a control signal input terminal. The control voltage output terminal of each of the M low-side drivers 76 is connected to the gate of the corresponding low-side switch 44. Each of the M low-side drivers 76 switches the control voltage output terminal to the potential of the negative-side drive potential terminal 82 or the potential of the positive-side drive potential terminal 84 according to the logic of the low-side control signal received from the control signal input terminal. The potential of the negative-side drive potential terminal 82 of each of the M low-side drivers 76 is the same potential as the source of the corresponding low-side switch 44 or has a predetermined potential difference with respect to the source of the corresponding low-side switch 44. Therefore, each of the M low-side drivers 76 can switch the corresponding low-side switch 44 between conductive and non-conductive states according to the logic of the low-side control signal. For example, the mth low-side driver 76-m can switch the drain-source of the mth low-side switch 44-m between conductive and non-conductive states by changing the gate-source voltage of the mth low-side switch 44-m depending on the logic of the received low-side control signal.

[0092] The M low-side isolated transmission circuits 78 are provided in a one-to-one correspondence with the M low-side switches 44. For example, the m-th low-side isolated transmission circuit 78-m of the first to M-th low-side isolated transmission circuits 78 corresponds to the m-th low-side switch 44-m.

[0093] Each of the M low-side isolated transmission circuits 78 includes two input terminals (a reference potential side input terminal 781 and a signal input terminal 782). The reference potential side input terminal 781, which is one of the two input terminals in each of the M low-side isolated transmission circuits 78, is connected to 0 V, which is the ground potential of the input-side power line system, and the other of the two input terminals, the signal input terminal 782, receives a second control signal from the control circuit 50.

[0094] Each of the M low-side isolated transmission circuits 78 includes two output terminals (a reference potential output terminal 783 and a signal output terminal 784). The reference potential output terminal 783, which is one of the two output terminals in each of the M low-side isolated transmission circuits 78, is connected to the low-side reference potential line 74 corresponding to the corresponding low-side switch 44. For example, the reference potential output terminal 783, one of the two output terminals in the m-th low-side isolated transmission circuit 78-m, is connected to the m-th low-side reference potential line 74-m. That is, the reference potential output terminal 783, one of the two output terminals in the m-th low-side isolated transmission circuit 78-m, is connected to a location at the same potential as the low-potential side terminal (source) of the m-th low-side switch 44-m when the m-th low-side switch 44-m is not conducting, or to a location at a potential that is a predetermined potential difference from the low-potential side terminal (source).

[0095] The signal output terminal 784, which is the other of the two output terminals in each of the M low-side isolated transmission circuits 78, supplies a low-side control signal to a corresponding low-side driver 76 out of the M low-side drivers 76. For example, the signal output terminal 784, which is one of the two output terminals in the m-th low-side isolated transmission circuit 78-m, supplies a low-side control signal to the m-th low-side driver 76-m.

[0096] In this embodiment, each of the M low-side isolated transmission circuits 78 includes M divided isolated transmission circuits 86 (86-1 to 86-M) connected in series.

[0097] Each of the M divided insulated transmission circuits 86 is a signal transmission means having an insulating function, and outputs an input signal while isolating it. For example, each of the N divided insulated transmission circuits 66 is a transmission circuit using an optical fiber or a transformer.

[0098] Each of the M divided isolated transmission circuits 86 includes two input terminals and two output terminals. Each of the M divided isolated transmission circuits 86 has two input terminals and two output terminals that are internally insulated from each other.

[0099] Each of the M divided isolated transmission circuits 86 has two input terminals, one of which is connected to a reference potential on the input side, and an input signal is supplied to the other of the two input terminals. Each of the M divided isolated transmission circuits 86 has two output terminals, one of which is a reference potential terminal, connected to a reference potential on the output side, and the other of the two output terminals outputs an output signal.

[0100] The first divided isolated transmission circuit 86 of the M divided isolated transmission circuits 86 connected in series has one of its two input terminals connected to 0 V, which is the ground potential of the input-side power line system, as the input-side reference potential. The other of the two input terminals of the first divided isolated transmission circuit 86 receives a second control signal from the control circuit 50 as an input signal.

[0101] Of the M split isolated transmission circuits 86, one of the two input terminals of each split isolated transmission circuit 86 other than the first is connected, as the input side reference potential, to a reference potential side terminal that is one of two output terminals of the split isolated transmission circuit 86 connected in the preceding stage. The other of the two input terminals of each split isolated transmission circuit 86 other than the first receives, as an input signal, an output signal that is output from the other of the two output terminals of the split isolated transmission circuit 86 connected in the preceding stage.

[0102] The final divided isolated transmission circuit 86 among the M divided isolated transmission circuits 86 has two output terminals, one of which outputs an output signal, that supplies a low-side control signal to the corresponding low-side driver 76 .

[0103] Here, the reference potential side terminal of one of the two output terminals in each of the mth and subsequent divided isolated transmission circuits 86-m to 66-M, counting from the control circuit 50 side, of the first to Mth divided isolated transmission circuits 86 included in the mth low-side isolated transmission circuit 78-m is connected to the mth low-side reference potential line 74-m. That is, the reference potential side terminal of one of the two output terminals in the mth and subsequent divided isolated transmission circuits 86 included in the mth low-side isolated transmission circuit 78-m is connected to a location at the same potential as the low potential side terminal of the mth low-side switch 44-m when it is not conducting, or to a location at a potential with a predetermined potential difference from the low potential side terminal.

[0104] For example, the reference potential side terminal of the two output terminals of each of the first and subsequent divided isolated transmission circuits 86-1 to 66-M included in the first low-side isolated transmission circuit 78-1 is connected to the first low-side reference potential line 74-1. Also, for example, the reference potential side terminal of the two output terminals of each of the second and subsequent divided isolated transmission circuits 86-2 to 66-M included in the second low-side isolated transmission circuit 78-2 is connected to the second low-side reference potential line 74-2. Also, for example, the reference potential side terminal of the two output terminals of each of the third and subsequent divided isolated transmission circuits 86-3 to 66-M included in the third low-side isolated transmission circuit 78-3 is connected to the third low-side reference potential line 74-3.

[0105] Furthermore, of the M divided isolated transmission circuits 86 included in the mth low-side isolated transmission circuit 78-m, the reference potential side terminal of the two output terminals of the qth divided isolated transmission circuit 86-q (q is an integer greater than or equal to 1 and less than m) that is in the stage before the mth one when counting from the control circuit 50 side is connected to the qth low-side reference potential line 74-q. That is, the reference potential side terminal of the two output terminals of the qth divided isolated transmission circuit 86-q that is in the stage before the mth one included in the mth low-side isolated transmission circuit 78-m is connected to a location at the same potential as the low potential side terminal of the qth low-side switch 44-q when it is not conducting, or to a location at a potential with a predetermined potential difference from the low potential side terminal.

[0106] For example, the reference potential side terminal of the two output terminals of the first divided isolated transmission circuit 86-1 included in the second low-side isolated transmission circuit 78-2 is connected to the first low-side reference potential line 74-1. For example, the reference potential side terminal of the two output terminals of the first divided isolated transmission circuit 86-1 included in the third low-side isolated transmission circuit 78-3 is connected to the first low-side reference potential line 74-1. For example, the reference potential side terminal of the two output terminals of the second divided isolated transmission circuit 86-2 included in the third low-side isolated transmission circuit 78-3 is connected to the second low-side reference potential line 74-2.

[0107] The m-th low-side isolated transmission circuit 78-m may include at least m divided isolated transmission circuits 86 connected in series. For example, the first low-side isolated transmission circuit 78-1 of the M low-side isolated transmission circuits 78 may include at least one divided isolated transmission circuit 86. The second low-side isolated transmission circuit 78-2 of the M low-side isolated transmission circuits 78 may include at least two divided isolated transmission circuits 86 connected in series. The third low-side isolated transmission circuit 78-3 of the M low-side isolated transmission circuits 78 may include at least three divided isolated transmission circuits 86 connected in series.

[0108] The low-side DC / DC converter 80 receives a power supply voltage output from an external circuit and generates a drive voltage by performing isolated DC-DC power conversion on the power supply voltage. The low-side DC / DC converter 80 supplies the drive voltage to each of the M low-side drivers 76. In this embodiment, the low-side DC / DC converter 80 receives a power supply voltage of +24 V and supplies the drive voltage of +24 V to each of the M low-side drivers 76.

[0109] The low-side DC / DC converter 80 includes M split DC / DC converters 88 (88-1 to 88-M) connected in series. Each of the M split DC / DC converters 88 includes a transformer and performs isolated DC-DC power conversion.

[0110] The first divided DC / DC converter 88 of the M divided DC / DC converters 88 receives a +24V power supply voltage output from an external circuit, and generates a +24V drive voltage that is insulated from the external circuit. Each of the divided DC / DC converters 88 other than the first of the M divided DC / DC converters 88 performs isolated DC-DC power conversion on the +24V drive voltage output from the divided DC / DC converter 88 in the previous stage, and generates a +24V drive voltage that is insulated from the divided DC / DC converter 88 in the previous stage.

[0111] Furthermore, the M split DC / DC converters 88 are provided in a one-to-one correspondence with the M low-side drivers 76 .

[0112] The M divided DC / DC converters 88 are numbered in order, with the divided DC / DC converter 88 that receives a voltage output from an external circuit being the first divided DC / DC converter 88-1 and the last divided DC / DC converter 88 being the Mth divided DC / DC converter 88-M.

[0113] In this case, the first to Mth M divided DC / DC converters 88 supply drive voltages to the corresponding low-side drivers 76 in order from the low-side driver 76 corresponding to the low-side switch 44 having the smallest absolute value of the potential at its low-potential side terminal when non-conducting among the M low-side switches 44 to the low-side driver 76 corresponding to the low-side switch 44 having the largest absolute value of the potential at its low-potential side terminal when non-conducting. More specifically, the mth divided DC / DC converter 88-m of the first to Mth M divided DC / DC converters 88 supplies drive voltage to the mth low-side driver 76-m.

[0114] Furthermore, the reference potential side terminal of the two output terminals of the mth divided DC / DC converter 88-m is connected to the mth low-side reference potential line 74-m. That is, the reference potential side terminal of the two output terminals of the mth divided DC / DC converter 88-m is connected to a location at the same potential as the low potential side terminal of the mth low-side switch 44-m when it is not conducting, or to a location at a potential that is a predetermined potential difference from the low potential side terminal.

[0115] For example, the reference potential side terminal of the two output terminals of the first divided DC / DC converter 88-1 is connected to a location at the same potential as the low potential side terminal of the first low-side switch 44-1 when it is not conducting, or to a location at a potential with a predetermined potential difference from the low potential side terminal. Furthermore, the reference potential side terminal of the two output terminals of the second divided DC / DC converter 88-2 is connected to a location at the same potential as the low potential side terminal of the second low-side switch 44-2 when it is not conducting, or to a location at a potential with a predetermined potential difference from the low potential side terminal. Furthermore, the reference potential side terminal of the two output terminals of the third divided DC / DC converter 88-3 is connected to a location at the same potential as the low potential side terminal of the third low-side switch 44-3 when it is not conducting, or to a location at a potential with a predetermined potential difference from the low potential side terminal.

[0116] The low-side drive circuit 48 according to the first embodiment may be configured not to include M low-side potential difference circuits 72 (72-1 to 72-M). In this case, the m-th low-side reference potential line 74-m is directly connected to the source of the m-th low-side switch 44-m.

[0117] FIG. 6 is a diagram showing the configuration of the nth high-side driver 56-n and the nth high-side potential difference circuit 52-n.

[0118] The n-th high-side driver 56-n includes a positive-side switch 102, a negative-side switch 104, a buffer circuit 106, and an inverter circuit 108.

[0119] The positive-side switch 102 establishes conduction or non-conduction between the positive-side drive potential terminal 64 and the gate of the n-th high-side switch 42-n in response to the logic signal output from the buffer circuit 106. The negative-side switch 104 establishes conduction or non-conduction between the negative-side drive potential terminal 62 and the gate of the n-th high-side switch 42-n in response to the logic signal output from the inverter circuit 108.

[0120] The buffer circuit 106 and the inverter circuit 108 receive a high-side control signal from the n-th high-side isolated transmission circuit 58-n. The buffer circuit 106 switches the positive-side switch 102 between conductive and non-conductive states according to the logic of the high-side control signal. The inverter circuit 108 switches the negative-side switch 104 between conductive and non-conductive states according to the high-side control signal and its inverted logic.

[0121] The nth high-side driver 56-n configured in this manner can switch the drain-source of the nth high-side switch 42-n between conductive and non-conductive states by changing the gate-source voltage of the nth high-side switch 42-n in accordance with the logic of the high-side control signal.

[0122] The mth low-side driver 76-m has the same configuration as the nth high-side driver 56-n. However, the positive-side switch 102 establishes conduction or non-conduction between the positive-side drive potential terminal 84 and the gate of the mth low-side switch 44-m. The negative-side switch 104 establishes conduction or non-conduction between the negative-side drive potential terminal 82 and the gate of the mth low-side switch 44-m. The mth low-side driver 76-m receives a low-side control signal instead of a high-side control signal from the mth low-side isolated transmission circuit 78-m. The mth low-side driver 76-m configured as described above can switch the drain-source of the mth low-side switch 44-m between conduction and non-conduction by changing the gate-source voltage of the mth low-side switch 44-m in accordance with the logic of the low-side control signal.

[0123] The n-th high-side potential difference circuit 52 - n includes a resistor 112 , a Zener diode 114 , a first capacitor 116 , and a second capacitor 118 .

[0124] A resistor 112 is provided between the positive drive potential terminal 64 of the n-th high-side driver 56-n and the source of the n-th high-side switch 42-n. An anode of a Zener diode 114 is connected to the negative drive potential terminal 62 of the n-th high-side driver 56-n and a cathode of the Zener diode 114 is connected to the source of the n-th high-side switch 42-n. A first capacitor 116 is provided in parallel with the resistor 112. A second capacitor 118 is provided in parallel with the Zener diode 114.

[0125] The nth high-side potential difference circuit 52-n configured in this manner can set the nth high-side reference potential line 54-n to a potential that is a predetermined potential difference from the potential of the low-potential side terminal (source) when the nth high-side switch 42-n is not conducting.

[0126] The mth low-side potential difference circuit 72-m has the same configuration as the nth high-side potential difference circuit 52-n. However, a resistor 112 is provided between the positive drive potential terminal 84 of the mth low-side driver 76-m and the source of the mth low-side switch 44-m. The anode of the Zener diode 114 is connected to the negative drive potential terminal 82 of the mth low-side driver 76-m, and the cathode is connected to the source of the mth low-side switch 44-m. The mth low-side potential difference circuit 72-m configured in this manner can set the mth low-side reference potential line 74-m to a potential that is a predetermined potential difference from the potential of the low-potential terminal (source) of the mth low-side switch 44-m when the mth low-side switch 44-m is not conductive.

[0127] The inverter device 20 according to the first embodiment as described above has the following advantages.

[0128] In the inverter device 20, when the N high-side switches 42 transition from a non-conducting state to a conducting state, i.e., when they are turned on, the potential of the low-potential side terminal (in this embodiment, the source) of each of the N high-side switches 42 when it is non-conducting changes suddenly.

[0129] If the rate of change of this potential is high, it may cause malfunction of the high-side isolated transmission circuits 58 corresponding to each of the N high-side switches 42, or may result in component damage. This is because, when the rate of change of this potential is high, the time rate of change of the potential of the reference potential side output terminal 583, one of the two output terminals in the corresponding high-side isolated transmission circuit 58, also increases, resulting in increased common-mode noise. Note that the common-mode noise increases in proportion to the absolute value of the difference between the rate of change of the potential of the reference potential side input terminal 581, one of the two input terminals in the high-side isolated transmission circuit 58, and the rate of change of the potential of the reference potential side output terminal 583, one of the two output terminals in the high-side isolated transmission circuit 58.

[0130] To prevent malfunctions and component damage caused by such common-mode noise, specifications limit the rate of potential change in the high-side isolated transmission circuit 58. Therefore, the circuit must be designed so that the rate of potential change falls within the range specified for the high-side isolated transmission circuit 58.

[0131] Here, at the low-potential terminal (the source in this embodiment) of the high-side switch 42 when it is not conducting, the potential difference between the potential when the high-side switch 42 is conducting and the potential when it is not conducting differs for each individual high-side switch 42, and is greater for the high-side switch 42 closer to the pulsed voltage output terminal 34 than for the high-side switch 42 closer to the first input terminal 22. For this reason, malfunctions, component damage, and the like are likely to occur in the high-side isolated transmission circuit 58 corresponding to the high-side switch 42 closer to the pulsed voltage output terminal 34, where the absolute value of the potential difference is large.

[0132] However, each of the first to Nth high-side isolated transmission circuits 58 according to this embodiment includes at least n divided isolated transmission circuits 66 connected in series. Furthermore, of the at least n divided isolated transmission circuits 66 included in the nth high-side isolated transmission circuit 58-n, the nth and subsequent divided isolated transmission circuits 66 counting from the control circuit 50 side have the reference potential side terminal of the two output terminals connected to a location at the same potential as the low-potential side terminal of the nth high-side switch 42-n when the nth high-side switch 42-n is not conductive, or to a location at a potential with a predetermined potential difference from the low-potential side terminal. Of the at least n divided isolated transmission circuits 66 included in the nth high-side isolated transmission circuit 58-n, the pth divided isolated transmission circuit 66-p (p is an integer greater than or equal to 1 and less than n) that is in the stage before the nth divided isolated transmission circuit 66 counting from the control circuit 50 has a reference potential side terminal of one of its two output terminals that is connected to a location at the same potential as the low potential side terminal of the pth high-side switch 42-p when it is non-conductive, or to a location at a potential that is a predetermined potential difference from the low potential side terminal. Therefore, the potential of the reference potential side terminal of one of its two output terminals in the first to nth divided isolated transmission circuits 66 when the first to Nth high-side switches 42 are non-conductive changes in stages.

[0133] Furthermore, of the at least n divided isolated transmission circuits 66 included in the nth high-side isolated transmission circuit 58-n, the divided isolated transmission circuit 66-1 that is closest to the control circuit 50 has its reference potential side terminal of the two input terminals connected to the reference potential, and therefore the rate of change of the potential on the input terminal side is zero.

[0134] Therefore, the absolute value of the difference between the rate of change of the potential of the reference potential side terminal of one of the two input terminals in each divided isolated transmission circuit 66 and the rate of change of the potential of the reference potential side terminal of one of the two output terminals is smaller than that in the case of a non-divided high-side isolated transmission circuit 58 (provided that n is 2 or more).As a result, each of the N high-side isolated transmission circuits 58 according to this embodiment reduces common-mode noise in at least the n divided isolated transmission circuits 66 included therein, making it possible to suppress malfunctions, component damage, and the like.

[0135] Furthermore, in this embodiment, each of the N high-side isolated transmission circuits 58 includes N divided isolated transmission circuits 66. In this case, the transmission delay time of each of the N high-side isolated transmission circuits 58 is the same. Therefore, in this case, the inverter device 20 can make the delay time from when it receives a control signal until the high-side control signal is supplied to the N high-side drivers 56 the same, and can switch the N high-side switches 42 in precise synchronization. Note that each of the N high-side isolated transmission circuits 58 may be configured to include N or more divided isolated transmission circuits 66.

[0136] Furthermore, in the inverter device 20, when the M low-side switches 44 transition from a non-conducting state to a conducting state, i.e., when they are turned on, the potential of the low-potential side terminal (in this embodiment, the source) of each of the M low-side switches 44 when it is non-conducting changes rapidly. Therefore, if the rate of change of this potential is high, the low-side isolated transmission circuits 78 corresponding to the M low-side switches 44 may malfunction or may cause component damage, just as on the high-side side.

[0137] However, each of the first to mth low-side isolated transmission circuits 78 according to this embodiment includes at least m series-connected divided isolated transmission circuits 86. Furthermore, of the at least m divided isolated transmission circuits 86 included in the mth low-side isolated transmission circuit 78-m, the reference potential side terminal of each of the mth and subsequent divided isolated transmission circuits 86 counting from the control circuit 50 side has a reference potential side terminal of two output terminals connected to a location at the same potential as the low potential side terminal of the mth low-side switch 44-m when it is not conducting, or to a location at a potential with a predetermined potential difference from the low potential side terminal. Of the at least m divided isolated transmission circuits 86 included in the mth low-side isolated transmission circuit 78-m, the qth divided isolated transmission circuit 86-q (q is an integer greater than or equal to 1 and less than m) that is in the stage before the mth divided isolated transmission circuit 86 counting from the control circuit 50 has a reference potential side terminal of one of its two output terminals that is connected to a location at the same potential as the low potential side terminal of the qth low-side switch 44-q when it is non-conductive, or to a location at a potential that is a predetermined potential difference from the low potential side terminal. Therefore, the potential of the reference potential side terminal of one of its two output terminals in the first to mth divided isolated transmission circuits 86 when the first to Mth low-side switches 44 are non-conductive changes in stages.

[0138] Furthermore, of the at least m divided isolated transmission circuits 86 included in the m-th low-side isolated transmission circuit 78-m, the divided isolated transmission circuit 86-1 that is closest to the control circuit 50 has one of its two input terminals on the reference potential side that is connected to the reference potential, and therefore the rate of change of the potential on the input terminal side is zero.

[0139] Therefore, the absolute value of the difference between the rate of change of the potential of the reference potential side terminal of the two input terminals in each divided isolated transmission circuit 86 and the rate of change of the potential of the reference potential side terminal of the two output terminals is smaller than that in the case of a non-divided low-side isolated transmission circuit 78 (provided that m is 2 or more).As a result, each of the M low-side isolated transmission circuits 78 according to this embodiment reduces common-mode noise in at least the m divided isolated transmission circuits 86 included therein, making it possible to suppress malfunctions, component damage, and the like.

[0140] Furthermore, in this embodiment, each of the M low-side isolated transmission circuits 78 includes M divided isolated transmission circuits 86. The transmission delay time of each of the M low-side isolated transmission circuits 78 is the same. Therefore, in this case, the inverter device 20 can make the delay time from when it receives a control signal until the low-side control signal is supplied to the M low-side drivers 76 the same, and can switch the M low-side switches 44 in precise synchronization. Note that each of the M low-side isolated transmission circuits 78 may be configured to include M or more divided isolated transmission circuits 86.

[0141] Furthermore, in the inverter device 20, the high-side DC / DC converter 60 may also malfunction or break down components due to the influence of common mode noise, similar to the high-side isolated transmission circuit 58.

[0142] However, the high-side DC / DC converter 60 according to this embodiment is configured by series-connecting N divided DC / DC converters 68, each of which performs isolated DC-DC power conversion and is provided in a one-to-one correspondence with N high-side drivers 56. Furthermore, the reference potential side terminal of the two output terminals of the nth divided DC / DC converter 68-n is connected to a location at the same potential as the low potential side terminal of the nth high-side switch 42-n when it is not conducting, or to a location at a potential with a predetermined potential difference from the low potential side terminal. Therefore, the potential of the reference potential side terminal of the two output terminals of the first to Nth divided DC / DC converters 68 changes in stages.

[0143] Furthermore, because the reference potential side terminal of the input terminals of the first divided DC / DC converter 68-1 is connected to the reference potential, the rate of change of potential on the input terminal side is 0. Therefore, the absolute value of the difference between the rate of change of potential of the reference potential side terminal of the two input terminals in each divided DC / DC converter 68 and the rate of change of potential of the reference potential side terminal of the two output terminals is smaller than in the case of a non-divided high-side DC / DC converter 60 (provided that n is 2 or greater). As a result, common-mode noise in each divided DC / DC converter 68 is reduced, making it possible to suppress malfunctions, component damage, and the like.

[0144] Furthermore, in the inverter device 20, the low-side DC / DC converter 80 may also malfunction or break down components due to the influence of common mode noise, similar to the low-side isolated transmission circuit 78.

[0145] However, the low-side DC / DC converter 80 according to this embodiment is configured by series-connecting M divided DC / DC converters 88, each performing isolated DC-DC power conversion, and provided one-to-one with the M low-side switches 44. Furthermore, the reference potential side terminal of the two output terminals of the mth divided DC / DC converter 88-m is connected to a location at the same potential as the low potential side terminal of the mth low-side switch 44-m when it is not conducting, or to a location at a potential with a predetermined potential difference from the low potential side terminal. Therefore, the potential of the reference potential side terminal of the two output terminals of the first to Mth divided DC / DC converters 88 changes in stages.

[0146] Furthermore, because the reference potential side terminal of the input terminals of the first divided DC / DC converter 88-1 is connected to the reference potential, the rate of change of potential on the input terminal side is 0. Therefore, the absolute value of the difference between the rate of change of potential of the reference potential side terminal of the two input terminals in each divided DC / DC converter 88 and the rate of change of potential of the reference potential side terminal of the two output terminals is smaller than in the case of a non-divided low-side DC / DC converter 80 (provided that m is 2 or greater). As a result, common mode noise in each divided DC / DC converter 88 is reduced, making it possible to suppress malfunctions, component damage, and the like.

[0147] (Second embodiment) Next, an inverter device 20 according to a second embodiment will be described. The inverter device 20 according to the second embodiment has substantially the same configuration as that of the first embodiment, and therefore circuits having substantially the same functions and configurations are assigned the same reference numerals, and detailed descriptions thereof will be omitted except for differences.

[0148] FIG. 7 is a diagram showing the configuration of an inverter device 20 according to the second embodiment.

[0149] In this embodiment, the first voltage is a positive voltage, for example, 3 kV, and the second voltage is 0 V, which is the ground potential of the power line system on the output side.

[0150] The pulse voltage output terminal 34 outputs either the first voltage (3 kV) applied to the first input terminal 22 or the second voltage (0 V) applied to the second input terminal 24. In response to a control signal supplied to the signal input terminal 32, the inverter device 20 switches between outputting the first voltage (3 kV) applied to the first input terminal 22 or outputting the second voltage (0 V) applied to the second input terminal 24 from the pulse voltage output terminal 34.

[0151] 7, the high-side switch 42 arranged closest to the first input terminal 22 has a low-potential side terminal (source) with a potential of 3 kV when conductive (ON) and a low-potential side terminal (source) with a potential of 2 kV when non-conductive (OFF), resulting in a potential difference of 1 kV. The high-side switch 42 arranged second from the first input terminal 22 has a low-potential side terminal (source) with a potential of 3 kV when conductive (ON) and a low-potential side terminal (source) with a potential of 1 kV when non-conductive (OFF), resulting in a potential difference of 2 kV. The high-side switch 42 arranged closest to the pulse voltage output terminal 34 has a low-potential side terminal (source) with a potential of 3 kV when conductive (ON) and a low-potential side terminal with a potential of 0 V when non-conductive (OFF), resulting in a potential difference of 3 kV. 7, the high-side switch 42 arranged closest to the first input terminal 22 is the first high-side switch 42-1. The high-side switch 42 arranged second from the first input terminal 22 is the second high-side switch 42-2. The high-side switch 42 arranged closest to the pulse voltage output terminal 34 is the third high-side switch 42-3.

[0152] 7, the low-side switch 44 arranged closest to the second input terminal 24 has a low-potential side terminal (source) with a potential of 0V when not conducting (OFF), and a low-potential side terminal (source) with a potential of 0V when conducting (ON), resulting in a potential difference of 0V. The low-side switch 44 arranged second from the second input terminal 24 has a low-potential side terminal (source) with a potential of 1 kV when not conducting (OFF), and a low-potential side terminal (source) with a potential of 0V when conducting (ON), resulting in a potential difference of -1 kV. The low-side switch 44 arranged closest to the pulse voltage output terminal 34 has a low-potential side terminal with a potential of 2 kV when not conducting (OFF), and a low-potential side terminal (source) with a potential of 0V when conducting (ON), resulting in a potential difference of -2 kV. 7, the low-side switch 44 arranged closest to the second input terminal 24 is the first low-side switch 44-1. The low-side switch 44 arranged second from the second input terminal 24 is the second low-side switch 44-2. The low-side switch 44 arranged closest to the pulse voltage output terminal 34 is the third low-side switch 44-3.

[0153] 8 is a diagram showing the configuration of a high-side drive circuit 46 according to the second embodiment, together with N high-side switches 42. In the second embodiment, the N divided DC / DC converters 68 are numbered in order, with the divided DC / DC converter 68 that receives a voltage output from an external circuit being the Nth divided DC / DC converter 68-N, and the last divided DC / DC converter 68 being the first divided DC / DC converter 68-1.

[0154] In the second embodiment, the first to Nth N divided DC / DC converters 68 supply drive voltages to the corresponding high-side drivers 56 in the order from the high-side driver 56 corresponding to the high-side switch 42 having the smallest absolute value of the potential at the low-potential side terminal when non-conducting among the N high-side switches 42 to the high-side driver 56 corresponding to the high-side switch 42 having the largest absolute value of the potential at the low-potential side terminal when non-conducting.

[0155] Furthermore, in the second embodiment, the reference potential side terminal of the two output terminals of the n-th divided DC / DC converter 68-n is connected to the n-th high-side reference potential line 54-n. That is, the reference potential side terminal of the two output terminals of the n-th divided DC / DC converter 68-n is connected to a location at the same potential as the low-potential side terminal of the n-th high-side switch 42-n when it is not conducting, or to a location at a potential that is a predetermined potential difference from the low-potential side terminal.

[0156] FIG. 9 is a diagram showing the configuration of a low-side drive circuit 48 according to the second embodiment, together with M low-side switches 44.

[0157] In the second embodiment, the M divided DC / DC converters 88 are numbered in order such that the divided DC / DC converter 88 that receives a voltage output from an external circuit is designated as the Mth divided DC / DC converter 88-M, and the last divided DC / DC converter 88 is designated as the first divided DC / DC converter 88-1.

[0158] In the second embodiment, the first to Mth M divided DC / DC converters 88 supply drive voltages to the corresponding low-side drivers 76 in the order from the low-side driver 76 corresponding to the low-side switch 44 having the smallest absolute value of the potential at the low-potential side terminal when non-conducting among the M low-side switches 44 to the low-side driver 76 corresponding to the low-side switch 44 having the largest absolute value of the potential at the low-potential side terminal when non-conducting.

[0159] Furthermore, in the second embodiment, the reference potential side terminal of the two output terminals of the mth divided DC / DC converter 88-m is connected to the mth low-side reference potential line 74-m. That is, the reference potential side terminal of the two output terminals of the mth divided DC / DC converter 88-m is connected to a location at the same potential as the low potential side terminal of the mth low-side switch 44-m when it is not conducting, or to a location at a potential that is a predetermined potential difference from the low potential side terminal.

[0160] The inverter device 20 according to the second embodiment having such a configuration can achieve the same effects as the first embodiment.

[0161] Although the embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. Various modifications can be made to the embodiments. [Explanation of symbols]

[0162] 10 transmitter, 20 inverter device, 22 first input terminal, 24 second input terminal, 26 reference voltage input terminal, 28 drive voltage input terminal, 32 signal input terminal, 34 pulse voltage output terminal, 42 high-side switch, 44 low-side switch, 46 high-side drive circuit, 48 low-side drive circuit, 50 control circuit, 52 high-side potential difference circuit, 54 high-side reference potential line, 56 high-side driver, 58 high-side isolated transmission circuit, 60 high-side DC / DC converter, 62 negative-side drive potential terminal, 64 positive-side drive potential terminal, 66 split isolated transmission circuit, 68 split DC / DC converter, 72 low-side potential difference circuit, 74 low-side reference potential line, 76 low-side driver, 78 low-side isolated transmission circuit, 80 low-side DC / DC converter, 82 negative-side drive potential terminal, 84 positive-side drive potential terminal, 86 split isolated transmission circuit, 88 split DC / DC converter, 581 Reference potential side input terminal, 582 signal input terminal, 583 reference potential side output terminal, 584 signal output terminal

Claims

1. N high-side switches (N is an integer equal to or greater than 2) connected in series between a first input terminal to which a first voltage is applied and a pulse voltage output terminal; N high-side drivers are provided in a one-to-one correspondence with the N high-side switches, receive high-side control signals, and switch corresponding high-side switches among the N high-side switches between conductive and non-conductive states in response to the high-side control signals; N high-side isolated transmission circuits are provided in a one-to-one correspondence with the N high-side drivers, each of which receives a signal output from a control circuit and supplies the high-side control signal isolated from the control circuit to a corresponding one of the N high-side drivers; a high-side DC / DC converter that supplies a drive voltage to each of the N high-side drivers; Equipped with When the N high-side switches are numbered in order such that the high-side switch having the smallest absolute value of the potential difference between the potential of the low-potential side terminal when conductive and the potential of the low-potential side terminal when non-conductive is designated as the first high-side switch, and the high-side switch having the largest absolute value of the potential difference is designated as the Nth high-side switch, a reference potential side terminal of one of two output terminals of an n-th high-side isolated transmission circuit (n is an integer of 1 or more and N or less) among the first to N-th high-side isolated transmission circuits is connected to a location at the same potential as a low-potential side terminal when the n-th high-side switch is non-conducting, or to a location at a potential that is a predetermined potential difference from the low-potential side terminal; The first to Nth high-side isolated transmission circuits each include at least n divided isolated transmission circuits connected in series, and the reference potential side terminal of each of the two output terminals of the nth and subsequent divided isolated transmission circuits counting from the control circuit side is connected to a location at the same potential as the low potential side terminal when the nth high-side switch is non-conducting, or to a location at a potential with a predetermined potential difference from the low potential side terminal. Inverter device.

2. M low-side switches (M is an integer equal to or greater than 2) connected in series between the pulse voltage output terminal and a second input terminal to which a second voltage lower than the first voltage is applied; M low-side drivers are provided in a one-to-one correspondence with the M low-side switches, receive low-side control signals, and switch corresponding low-side switches among the M low-side switches between conductive and non-conductive states in response to the low-side control signals; M low-side isolated transmission circuits are provided in a one-to-one correspondence with the M low-side drivers, each of which receives a signal output from the control circuit and provides the low-side control signal isolated from the control circuit to a corresponding one of the M low-side drivers; a low-side DC / DC converter that supplies a drive voltage to each of the M low-side drivers; Equipped with When the M low-side switches are numbered in order such that the low-side switch having the smallest absolute value of the potential difference between the potential of the low-potential side terminal when conductive and the potential of the low-potential side terminal when non-conductive is designated as the first low-side switch, and the low-side switch having the largest absolute value of the potential difference is designated as the M low-side switch, a reference potential side terminal of one of two output terminals of an m-th low-side isolated transmission circuit (m is an integer of 1 or more and M or less) among the first to M-th low-side isolated transmission circuits is connected to a point at the same potential as the low-potential side terminal of the m-th low-side switch when it is non-conducting, or to a point at a potential that is a predetermined potential difference from the low-potential side terminal; The first to M-th low-side isolated transmission circuits each include at least m divided isolated transmission circuits connected in series, and the reference potential side terminal of each of the two output terminals of the m-th and subsequent divided isolated transmission circuits counting from the control circuit side is connected to a location at the same potential as the low potential side terminal when the m-th low-side switch is not conducting or to a location at a potential with a predetermined potential difference from the low potential side terminal. The inverter device according to claim 1 .

3. the N high-side switches are synchronously switched to conductive or non-conductive states; the M low-side switches are synchronously switched to conductive or non-conductive states; The N high-side switches and the M low-side switches are switched between conductive and non-conductive states in a complementary manner. The inverter device according to claim 2 .

4. Each of the N high-side isolated transmission circuits N split isolated transmission circuits connected in series; Each of the N divided isolated transmission circuits receives a signal from a preceding circuit connected in series, and outputs a signal corresponding to the received signal, the signal being isolated from the preceding circuit; The first divided isolated transmission circuit of the N divided isolated transmission circuits receives the signal output from the control circuit, and the last divided isolated transmission circuit of the N divided isolated transmission circuits provides the high-side control signal to the corresponding high-side driver. The inverter device according to claim 1 .

5. Each of the M low-side isolated transmission circuits M serially connected split isolated transmission circuits; Each of the M divided isolated transmission circuits receives a signal from a preceding circuit connected in series, and outputs a signal corresponding to the received signal, the signal being isolated from the preceding circuit; The first divided isolated transmission circuit among the M divided isolated transmission circuits receives the signal output from the control circuit, and the last divided isolated transmission circuit among the M divided isolated transmission circuits provides the low-side control signal to the corresponding low-side driver. The inverter device according to claim 2 .

6. the high-side DC / DC converter is provided in a one-to-one correspondence with the N high-side drivers, and is configured by N series-connected split DC / DC converters, each of which performs isolated DC-DC power conversion; When the N divided DC / DC converters are numbered in order such that the divided DC / DC converter that receives a voltage output from an external circuit is the first divided DC / DC converter and the last divided DC / DC converter is the Nth divided DC / DC converter, the first to Nth divided DC / DC converters supply drive voltages to the corresponding high-side drivers in the order from the high-side driver corresponding to the high-side switch having the smallest absolute value of potential at its low-potential side terminal when non-conducting among the N high-side switches to the high-side driver corresponding to the high-side switch having the largest absolute value of potential at its low-potential side terminal when non-conducting, The reference potential side terminal of the two output terminals of the nth divided DC / DC converter is connected to a location at the same potential as the low potential side terminal when the nth high-side switch is not conducting or to a location at a potential with a predetermined potential difference from the low potential side terminal. The inverter device according to claim 1 .

7. the low-side DC / DC converters are provided in a one-to-one correspondence with the M low-side drivers, and are configured by M series-connected split DC / DC converters, each of which performs isolated DC-DC power conversion; When the M divided DC / DC converters are numbered in order such that the divided DC / DC converter that receives a voltage output from an external circuit is the first divided DC / DC converter and the last divided DC / DC converter is the Mth divided DC / DC converter, the first to Mth divided DC / DC converters supply drive voltages to the low-side drivers corresponding thereto in the order from the low-side driver corresponding to the low-side switch having the smallest absolute value of potential at its low-potential side terminal when non-conducting among the M low-side switches to the low-side driver corresponding to the low-side switch having the largest absolute value of potential at its low-potential side terminal when non-conducting, The reference potential side terminal of the two output terminals of the mth divided DC / DC converter is connected to a location at the same potential as the low potential side terminal when the mth low-side switch is not conducting or to a location at a potential with a predetermined potential difference from the low potential side terminal. The inverter device according to claim 2 .

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