Metal laminate and method for producing multilayer circuit board

Abstract

To provide a metal laminate having suppressed warpage.SOLUTION: A metal laminate including a first metal layer 10, a second metal layer 20, and an etching barrier layer 30 provided between the first metal layer 10 and the second metal layer 20, the kurtosis (Sku) of the surface (second surface 24) of the second metal layer 20 being from 8.0 to 30.0.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a metal laminate and a method for manufacturing a multilayer circuit board, and more particularly to a metal laminate for forming an electronic circuit and a method for manufacturing a multilayer circuit board using the same. [Background technology]

[0002] Conventionally, circuit boards such as printed wiring boards have been widely used as electronic components for various electronic devices. In recent years, with the progress of miniaturization and high performance of electronic devices, multi-layer circuit boards have been studied. For example, Patent Document 1 describes a method for manufacturing a multi-layer circuit board. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-156565 Summary of the Invention [Problem to be solved by the invention]

[0004] In the manufacture of multilayer circuit boards, a circuit pattern is formed on a laminate consisting of an insulating substrate and a metal layer, and then the laminate is pressed together with other laminates. This process is prone to dimensional errors, resulting in low yields. Therefore, the present inventors have studied methods for manufacturing multilayer circuit boards and found that multilayer circuit boards can be efficiently manufactured by using a metal laminate including a first metal layer, a second metal layer, and an etching barrier layer disposed between the first metal layer and the second metal layer. However, the metal laminate used in this manufacturing method may warp, and excessive warping of the metal laminate may cause problems such as it falling off a conveyor or coming into contact with various sensors during transport in the manufacturing process of a multilayer circuit board.

[0005] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a metal laminate in which warpage is suppressed. Another object of the present disclosure is to provide an efficient method for manufacturing a multilayer circuit board. [Means for solving the problem]

[0006] As a result of extensive research into a metal laminate including a first metal layer, a second metal layer, and an etching barrier layer disposed between the first metal layer and the second metal layer, the inventors discovered that the above-mentioned problems can be solved by controlling the kurtosis Sku of the surface of the second metal layer within a predetermined range, and thus completed an embodiment of the present invention.

[0007] That is, in one aspect, an embodiment of the present invention includes a first metal layer, a second metal layer, and an etching barrier layer disposed between the first metal layer and the second metal layer; The metal laminate has a surface kurtosis Sku of the second metal layer of 8.0 to 30.0.

[0008] In another aspect, an embodiment of the present invention relates to a method for manufacturing a multilayer circuit board, including the steps of: preparing the metal laminate; etching the second metal layer of the metal laminate to form a circuit; embedding the circuit with an insulating resin; removing the first metal layer and the etching barrier layer of the metal laminate to form a circuit board; and stacking a plurality of the circuit boards. [Effects of the Invention]

[0009] According to one aspect of the present invention, a metal laminate in which warpage is suppressed can be provided. According to another aspect of the present invention, an embodiment of the present invention can provide an efficient method for manufacturing a multilayer circuit board. [Brief explanation of the drawings]

[0010] [Figure 1]1 is a schematic cross-sectional view of a metal laminate according to an embodiment of the present invention. [Figure 2] 2A to 2C are schematic cross-sectional views illustrating steps of a method for manufacturing a multilayer circuit board according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Preferred embodiments of the present invention will be described in detail below, but the present invention should not be construed as being limited thereto, and various modifications and improvements can be made based on the knowledge of those skilled in the art without departing from the gist of the present invention. The multiple components disclosed in the following embodiments can be appropriately combined to form various inventions. For example, some components may be deleted from all the components shown in the following embodiments, or components from different embodiments may be appropriately combined.

[0012] (1. Metal laminate) A metal laminate according to an embodiment of the present invention includes a first metal layer, a second metal layer, and an etching barrier layer disposed between the first and second metal layers, and the surface of the second metal layer has a kurtosis Sku of 8.0 to 30.0. This configuration can suppress warping of the metal laminate.

[0013] FIG. 1 is a schematic cross-sectional view of a metal laminate according to an embodiment of the present invention. As shown in FIG. 1, the metal stack includes a first metal layer 10, a second metal layer 20, and an etching barrier layer 30 disposed between the first metal layer 10 and the second metal layer 20.

[0014] <First metal layer 10> The first metal layer 10 is a metal layer that supports the second metal layer 20 and the etching barrier layer 30 . The first metal layer 10 has a first surface 12 and a second surface 14. The first surface 12 is the surface that becomes the surface of the metal laminate, and the second surface 14 is the inner surface side of the metal laminate, i.e., the surface on the etching barrier layer 30 side.

[0015] The surface (first side 12) of the first metal layer 10 preferably has a kurtosis Sku (hereinafter sometimes abbreviated as "Sku") of 8.0 to 30.0, more preferably 8.0 to 20.0, even more preferably 10.0 to 20.0, and even more preferably 13.0 to 18.0. By controlling Sku within such a range, warpage of the metal laminate can be easily suppressed. Here, Sku is a parameter related to the distribution in the height direction, as defined in ISO 25178-2:2012. Specifically, Sku represents the degree of peaking (kurtosis) of a height histogram created based on the average height. For example, an Sku of 3.0 indicates that the height distribution is normal. When Sku is greater than 3.0, the greater the value, the more concentrated the height distribution. Conversely, when Sku is less than 3.0, the smaller the value, the more dispersed the height distribution. Therefore, a surface with an Sku of 8.0 to 30.0 indicates a surface in which heights are distributed in a concentrated manner within a certain range, i.e., a surface with a highly uniform height distribution. Here, Sku in this specification can be measured in accordance with ISO 25178-2:2012 by the method described below.

[0016] The surface (first surface 12) of the first metal layer 10 preferably has a maximum peak height Sp (hereinafter sometimes abbreviated as "Sp") of 0.01 to 1.50 μm, more preferably 0.10 to 1.40 μm, and even more preferably 0.20 to 1.30 μm. By controlling Sp within this range, warping of the metal laminate can be easily suppressed. Here, Sp is a parameter for peak height defined in ISO 25178-2: 2012. Specifically, Sp indicates the maximum value of the average height from the standard surface, and represents the unevenness of the surface. In addition, Sp in this specification can be measured in accordance with ISO 25178-2:2012 by the method described below.

[0017] The surface (first surface 12) of the first metal layer 10 preferably has a root mean square height Sq (hereinafter sometimes abbreviated as "Sq") of 0.01 to 0.80 μm, more preferably 0.03 to 0.70 μm, and even more preferably 0.05 to 0.60 μm. By controlling Sq within this range, warping of the metal laminate can be easily suppressed. Here, Sq is a parameter equivalent to the standard deviation of the distance from the mean surface as defined in ISO 25178-2: 2012. Specifically, Sq represents the variation in surface height. Furthermore, Sq in this specification can be measured in accordance with ISO 25178-2:2012 by the method described below.

[0018] The surface (first surface 12) of the first metal layer 10 preferably has a skewness Ssk (hereinafter sometimes abbreviated as "Ssk") of -5.00 to -0.10, more preferably -4.00 to -1.00, and even more preferably -3.50 to -2.00. Controlling Ssk within this range makes it easier to suppress warpage of the metal laminate. Here, Ssk is a parameter related to the height distribution defined in ISO 25178-2:2012. That is, Ssk, like Sku, is an index for evaluating the height distribution of surface irregularities. Specifically, Ssk represents the degree of bias (skewness) of a height histogram created based on the average height. When Ssk is 0, it means that the height distribution is symmetrical with respect to the average line. Furthermore, when Ssk is a positive value, the larger the absolute value of the numerical value, the more the height distribution is biased upward with respect to the average line, i.e., the more convex portions there are. Conversely, when Ssk is a negative value, the larger the absolute value of the numerical value, the more the height distribution is biased downward with respect to the average line, i.e., the more concave portions there are. Therefore, a surface with an Ssk of -5.00 to -0.10 means that the surface has many concave portions. Furthermore, Ssk in this specification can be measured in accordance with ISO 25178-2:2012 by the method described below.

[0019] The surface (first surface 12) of the first metal layer 10 preferably has a maximum valley depth Sv (hereinafter sometimes abbreviated as "Sv") of 0.50 to 5.00, more preferably 0.60 to 4.80. By controlling Sv within this range, warping of the metal laminate can be easily suppressed. In addition, Sv in this specification can be measured in accordance with ISO 25178-2:2012 by the method described below.

[0020] The surface (first surface 12) of the first metal layer 10 preferably has a Vickers hardness Hv of 50 to 200, more preferably 60 to 180, and even more preferably 80 to 130. By controlling the Vickers hardness of the surface of the first metal layer 10 within such a range, warping of the metal laminate can be easily suppressed. The Vickers hardness in this specification can be measured by the method described below.

[0021] The average crystal grain size of the metal constituting first metal layer 10 is preferably 0.30 to 1.00 μm, and more preferably 0.40 to 0.70 μm. By controlling the average crystal grain size of the metal within this range, warping of the metal laminate can be easily suppressed. Here, the average crystal grain size of the metal can be determined by measuring it using EBSD (Electron Backscatter Diffraction). EBSD can analyze the average crystal grain size by utilizing reflected electron Kikuchi diffraction (Kikuchi pattern) that occurs when a sample is irradiated with an electron beam inside a SEM (Scanning Electron Microscope). The average crystal grain size can be measured by observing it from the first surface 12 side, as described below.

[0022] The first metal layer 10 is not particularly limited and may be made of, for example, copper or a copper alloy. A first metal layer 10 made of copper or a copper alloy is preferred because it can be removed using a general etching solution used in circuit formation. When the first metal layer 10 is made of copper or a copper alloy, for example, a copper foil can be used. In this specification, the term "copper foil" includes copper alloy foils that contain copper as the main component and also contain components other than copper.

[0023] The copper foil is not particularly limited, and electrolytic copper foil or rolled copper foil can be used. As the material for the rolled copper foil, high-purity copper such as tough pitch copper (JIS H3100 alloy number C1100) or oxygen-free copper (JIS H3100 alloy number C1020 or JIS H3510 alloy number C1011), which are commonly used for circuit boards, can be used. Copper alloys such as Sn-containing copper, Ag-containing copper, copper alloys containing Cr, Zr, or Mg, and Corson copper alloys containing Ni and Si can also be used. When the copper foil is an electrolytic copper foil, it can be produced by a general electrolytic process.

[0024] The thickness of the first metal layer 10 is not particularly limited, but if the thicknesses of the second metal layer 20 and the etching barrier layer 30 are small, it may be difficult to handle the metal laminate during circuit formation. In this case, the handleability of the metal laminate can be improved by increasing the thickness of the first metal layer 10 (for example, controlling it to about 10 to 150 μm). Therefore, the first metal layer 10 can act as a carrier that improves the handleability of the metal laminate.

[0025] The first metal layer 10 can be produced by a known method, for example, by a casting and rolling method or an electrolytic plating method.

[0026] <Second metal layer 20> The second metal layer 20 is a metal layer that will become a circuit by etching. The second metal layer 20 has a first surface 22 and a second surface 24. The first surface 22 is the inner surface side of the metal laminate, i.e., the surface on the etching barrier layer 30 side, and the second surface 24 is the surface that becomes the surface of the metal laminate.

[0027] The second metal layer 20 is a metal layer that plays a role in the circuitry of the multilayer circuit board. Both surfaces (first surface 22 and second surface 24) of the second metal layer 20 are preferably relatively smooth. After a circuit is formed on the second metal layer 20 by etching, the second metal layer 20 is embedded in insulating resin to form a circuit board, and the circuit board is then multilayered to produce a multilayer circuit board. Interlayer connections in this multilayer circuit board are made by forming interlayer connection wiring by filling with conductive paste or conductive metal plating. To improve adhesion between the interlayer connection wiring and the circuit formed by etching, it is preferable that at least the second surface 24 of the second metal layer 20 is smooth. In particular, smoothing at least the second surface 24 of the second metal layer 20 makes it less likely that gaps will form between the interlayer connection wiring and the circuit formed by etching. On the other hand, the first surface 22 of the second metal layer is preferably smooth in order to reduce pinholes in the etching barrier layer 30 described below.

[0028] The surface (second surface 24) of the second metal layer 20 has a kurtosis Sku of 8.0 to 30.0. A surface with an Sku of 8.0 to 30.0 means that the surface has a uniform height distribution. By controlling the Sku within this range, warpage of the metal laminate can be suppressed. From the viewpoint of stably ensuring this effect, the Sku of the surface of the second metal layer 20 is preferably 8.0 to 20.0, more preferably 10.0 to 20.0, and even more preferably 14.0 to 18.0.

[0029] The surface (second surface 24) of the second metal layer 20 preferably has a maximum peak height Sp of 0.01 to 2.00 μm, more preferably 0.01 to 1.50 μm, even more preferably 0.10 to 1.20 μm, and particularly preferably 0.20 to 1.00 μm. By controlling Sp within this range, warping of the metal laminate can be easily suppressed.

[0030] The ratio of Sp on the surface of the first metal layer 10 to Sp on the surface of the second metal layer 20 is preferably 0.3 to 3.0, and more preferably 0.5 to 2.0. By controlling the Sp ratio within this range, warping of the metal laminate can be easily suppressed.

[0031] The surface (second surface 24) of the second metal layer 20 preferably has a root mean square height Sq of 0.01 to 0.80 μm, more preferably 0.05 to 0.70 μm, and even more preferably 0.10 to 0.50 μm. By controlling Sq within this range, warping of the metal laminate can be easily suppressed.

[0032] The surface (second surface 24) of the second metal layer 20 preferably has a skewness Ssk of -5.00 to -0.10, more preferably -4.00 to -1.00, and even more preferably -3.50 to -2.00. By controlling Sq within such a range, warpage of the metal laminate can be easily suppressed.

[0033] The surface (second surface 24) of the second metal layer 20 preferably has a maximum valley depth Sv of 1.00 to 5.00, more preferably 1.50 to 4.00, and even more preferably 2.00 to 3.50. By controlling Sv within such a range, warping of the metal laminate can be easily suppressed.

[0034] The surface of the second metal layer 20 has a Vickers hardness Hv of preferably 50 to 200, more preferably 60 to 180, and even more preferably 80 to 130. By controlling the Vickers hardness Hv of the surface of the second metal layer 20 within such a range, warping of the metal laminate can be easily suppressed.

[0035] The second metal layer 20 preferably has an average crystal grain size of 0.30 to 1.00 μm, and more preferably 0.40 to 0.70 μm. By controlling the average crystal grain size of the metal within this range, warping of the metal laminate can be easily suppressed. The average crystal grain size is observed from the second surface 24 side.

[0036] The thickness of second metal layer 20 is not particularly limited, but is preferably 2 to 100 μm, more preferably 2 to 80 μm, even more preferably 3 to 50 μm, particularly preferably 10 to 40 μm, and even more preferably 15 to 25 μm. By controlling second metal layer 20 to such a thickness, when a circuit is formed by etching, the circuit board can be made small and thin.

[0037] The second metal layer 20 is not particularly limited and can be made of copper or a copper alloy. A second metal layer 20 made of copper or a copper alloy is preferred because a circuit can be easily formed using an etching solution. When the second metal layer 20 is made of copper or a copper alloy, for example, copper foil can be used. As with the first metal layer, electrolytic copper foil or rolled copper foil can be used as the copper foil. Details of the copper foil material are the same as those described above and will not be described here.

[0038] The second metal layer 20 can be produced by a known method. For example, the second metal layer 20 can be produced by rolling or electrolytic plating. From the viewpoint of suppressing warping of the metal laminate, it is preferable to produce the second metal layer 20 by the same method as the first metal layer 10 described above. In other words, when the first metal layer 10 is produced by electrolytic plating, it is preferable to also produce the second metal layer 20 by electrolytic plating.

[0039] <Vickers Hardness Ratio Between First Metal Layer 10 and Second Metal Layer 20> The ratio of the Vickers hardness Hv of the surface of the first metal layer 10 to the Vickers hardness Hv of the surface (second surface 24) of the second metal layer 20 is preferably 0.70 to 1.40, and more preferably 0.80 to 1.20. By controlling the Vickers hardness ratio within this range, warping of the metal laminate can be easily suppressed.

[0040] <Average Crystal Grain Size Ratio of First Metal Layer 10 to Second Metal Layer 20> The average crystal grain size of the first metal layer 10 and the average crystal grain size of the second metal layer 20 are thought to be related to the internal stress of each metal layer. Therefore, it is thought that a smaller ratio of the average crystal grain size of the first metal layer 10 to the average crystal grain size of the second metal layer 20 reduces the difference in internal stress between the first metal layer and the second metal layer, and as a result, warping of the metal laminate is suppressed. Therefore, the ratio of the average crystal grain size of the first metal layer 10 to the average crystal grain size of the second metal layer 20 is preferably 0.70 to 1.60, and more preferably 0.80 to 1.30.

[0041] <Etching barrier layer 30> The etching barrier layer 30 is a layer that is difficult to remove by the etching solution used in forming the circuit. Therefore, it is preferable that the etching barrier layer 30 can be selectively removed separately from the first metal layer 10 and / or the second metal layer 20. The etching barrier layer 30 is not particularly limited, but can be made of a metal or alloy with an etching rate different from that of copper or a copper alloy. Specific examples of the etching barrier layer 30 include zinc, cobalt, nickel, tin, indium, and alloys thereof. The above metals and alloys are easily removed selectively from copper by etching. In particular, the etching barrier layer 30 is preferably made of nickel or a nickel alloy. An etching barrier layer 30 made of nickel or a nickel alloy is difficult to remove with an etching solution commonly used in circuit formation. Furthermore, etching solutions capable of selectively removing nickel or nickel alloys are common and inexpensive.

[0042] The thickness of the etching barrier layer 30 is not particularly limited. Generally, the thicker the etching barrier layer 30, the less likely pinholes are to occur in the etching barrier layer 30 during manufacturing. The reason why pinholes in the etching barrier layer 30 should be avoided will be described later. On the other hand, the thinner the etching barrier layer 30, the easier it is to remove it by etching during circuit board fabrication. From the above viewpoint, the thickness of the etching barrier layer 30 is preferably 0.1 to 5.0 μm, more preferably 0.3 to 2.0 μm. By controlling the etching barrier layer 30 to such a thickness, it is possible to easily remove the etching barrier layer 30 during circuit board fabrication while ensuring the function of the etching barrier layer 30.

[0043] The method for producing the etching barrier layer 30 is not particularly limited, but for example, the etching barrier layer 30 can be formed by applying electroless plating and / or electrolytic plating to the surface (second surface 14) of the first metal layer 10 or the surface (first surface 22) of the second metal layer 20.

[0044] The metal laminate may have an anti-corrosion layer such as a chromate treatment layer provided on the surface thereof, if necessary.

[0045] A metal laminate including the first metal layer 10, the second metal layer 20, and the etching barrier layer 30 as described above can be used to form electronic circuits. In particular, this metal laminate is suitable for use in a method for manufacturing a multilayer circuit board because warping is suppressed.

[0046] (2. Method for manufacturing metal laminate) The method for producing the metal laminate according to the embodiment of the present invention is not particularly limited as long as it has the above-mentioned characteristics, and can be carried out in accordance with a known method. An example of a typical method for manufacturing a metal laminate according to an embodiment of the present invention will be described below. The metal laminate according to the embodiment of the present invention can be produced by a method including the following steps (a) to (c). (a) Step of preparing a first metal layer 10 (b) providing a second metal layer 20 and forming an etching barrier layer 30 on the first surface 22; (c) A step of bonding the first metal layer 10 to the second metal layer 20 on which the etching barrier layer 30 has been formed.

[0047] The first metal layer 10, the second metal layer 20 and the etching barrier layer 30 can be fabricated according to the methods described above. The joining method is not particularly limited, but a so-called cladding method in which joining is performed using a rolling roll or the like can be used.

[0048] (3. Manufacturing method of multilayer circuit board) The method for manufacturing a multilayer circuit board according to an embodiment of the present invention is carried out using the above-described metal laminate. 2A to 2C are schematic cross-sectional views illustrating each step of the method for manufacturing a multilayer circuit board according to an embodiment of the present invention.

[0049] In this manufacturing method, first, a step of preparing the metal laminate is carried out (S1). The metal laminate may be produced by the method described above.

[0050] Next, a step of etching the second metal layer 20 of the metal laminate to form the circuit 50 is performed (S2). The method for forming the circuit 50 by etching is not particularly limited and can be performed according to known methods. For example, the circuit can be formed as follows. First, a photosensitive resist layer is formed on the second surface 24 of the second metal layer 20, and then predetermined positions are exposed and developed to form a predetermined resist pattern layer. Next, the second metal layer 20 with the predetermined resist pattern layer formed thereon is etched. Finally, the resist pattern layer is removed, thereby forming the circuit 50. In the method for forming this circuit 50, as described above, the occurrence of pinholes in the etching barrier layer 30 should be avoided. If pinholes exist in the etching barrier layer 30, the etching liquid will reach the first metal layer 10 through the pinholes when etching the second metal layer 20. If the etching liquid is also capable of etching the first metal layer 10, a problem will occur in which part of the first metal layer 10 will be lost. This is the reason why the occurrence of pinholes in the etching barrier layer 30 should be avoided.

[0051] Next, a step of embedding the circuit 50 in insulating resin 60 is carried out (S3). The insulating resin is not particularly limited, and known insulating resins can be used. Examples of insulating resins that can be used include thermosetting resins such as epoxy resin, phenol resin, and polyimide resin, and thermoplastic resins such as polyethersulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenyl ether (PPE), polyetherimide (PI), and fluororesin.

[0052] Next, a step of removing the first metal layer 10 and the etching barrier layer 30 of the metal laminate to form the circuit board 70 is performed (S4). The method for removing the first metal layer 10 and the etching barrier layer 30 is not particularly limited and may be a chemical removal method or a physical removal method. In a preferred embodiment, the first metal layer 10 and the etching barrier layer 30 are each removed using an etching solution capable of etching each layer.

[0053] Next, a step of stacking a plurality of circuit boards 70 is performed (not shown). The lamination method is not particularly limited, but may be performed using a known method such as a thermoforming press.

[0054] The method for manufacturing a multilayer circuit board according to an embodiment of the present invention can efficiently manufacture a multilayer circuit board by carrying out the above steps. In particular, this manufacturing method is less likely to cause dimensional errors and can improve the yield of multilayer circuit boards compared to conventional manufacturing methods in which a circuit pattern is formed on a laminate plate in which a metal layer is laminated on an insulating base material, and then the laminate plate is pressed together with other laminate plates. [Example]

[0055] Hereinafter, the embodiments of the present invention will be described in more detail with reference to examples, but the present invention is not limited to these examples in any way. Example 1 An electrolytic drum and electrodes were placed around the electrolytic drum at predetermined intervals in an electrolytic cell. Next, electrolysis was carried out in this electrolytic cell under the following conditions, and copper was deposited on the surface of the electrolytic drum while the drum was rotating. Next, the copper deposited on the surface of the rotating drum was peeled off to produce an electrolytic copper foil with a thickness of 70 μm, which was used as the first metal layer. <Electrolysis conditions> Electrolyte composition: 100g / L Cu, 100g / L H2SO4, 0.1ppm glue Current density: 80A / dm 2 Electrolyte temperature: 60℃ Electrolysis time: 220 seconds

[0056] Using the same equipment and electrolysis conditions as above, only the electrolysis time was changed to 70 seconds to prepare an electrolytic copper foil having a thickness of 20 μm, which was used as the second metal layer.

[0057] Next, an etching barrier layer (nickel layer) with a thickness of 0.5 μm was formed on the S surface (drum surface side) of the second metal layer (electrolytic copper foil) by electroplating under the following conditions. Plating solution composition: 250g / L nickel sulfate hexahydrate, 7g / L trisodium citrate dihydrate pH: 4.0 Plating solution temperature: 50℃ Electroplating conditions: current density 5A / dm 2 , time 40 seconds

[0058] Next, the second metal layer (electrolytic copper foil) on which the etching barrier layer (nickel layer) was formed and the first metal layer (electrolytic copper foil) were joined by cladding with a rolling roll so that the etching barrier layer was positioned between the first metal layer and the second metal layer, thereby obtaining a metal laminate.

[0059] Example 2 A 70 μm thick HA-V2 foil (rolled copper foil) manufactured by JX Nippon Mining & Metals Corporation was prepared and subjected to a degreasing treatment. As the second metal layer, the same second metal layer (electrolytic copper foil) as in Example 1 was prepared. Next, electroplating was performed on the S surface (drum surface side) of the second metal layer (electrolytic copper foil) under the following conditions to form an etching barrier layer (nickel layer) with a thickness of 1 μm. Plating solution composition: 250g / L nickel sulfate hexahydrate, 7g / L trisodium citrate dihydrate pH: 4.0 Plating solution temperature: 50℃ Electroplating conditions: current density 10A / dm 2 , time 40 seconds Next, the second metal layer (electrolytic copper foil) on which the etching barrier layer (nickel layer) was formed and the first metal layer (electrolytic copper foil) were joined by cladding with a rolling roll so that the etching barrier layer was positioned between the first metal layer and the second metal layer, thereby obtaining a metal laminate.

[0060] Example 3 A metal laminate was obtained under the same conditions as in Example 1, except that the electrolysis time for the second metal layer in Example 1 was changed to 110 seconds, an electrolytic copper foil having a thickness of 35 μm was produced, and this electrolytic copper foil was used as the second metal layer.

[0061] The metal laminate obtained above was evaluated as follows. <Sku, Sp, Sq, and Ssk of the surfaces of the metal laminate (first surface of the first metal layer and second surface of the second metal layer)> Images were taken using a laser microscope (LEXT OLS4000) manufactured by Olympus Corporation. The captured images were analyzed using analysis software for a laser microscope (LEXT OLS4100) manufactured by Olympus Corporation. Measurements of Sku, Sp, Sq, and Ssk were performed in accordance with ISO 25178-2:2012. The measurement results were calculated by averaging values ​​measured at three arbitrary locations. The temperature during measurement was 23 to 25°C. The main settings for the laser microscope and analysis software were as follows:

[0062] Objective lens: MPLAPON50XLEXT (Magnification: 50x, Numerical Aperture: 0.95, Immersion Type: Air, Mechanical Tube Length: ∞, Cover Glass Thickness: 0, Field Number: FN18) Optical zoom magnification: 1x Scanning mode: XYZ high speed (height resolution: 60 nm, number of pixels of captured data: 1024 x 1024) Captured image size [pixels]: 257 μm wide x 258 μm high [1024 x 1024] (As the measurement is made in the horizontal direction, the evaluation length is equivalent to 257 μm) DIC: Off Multilayer: Off Laser Intensity: 100 Offset: 0 Confocal level: 0 Beam diameter aperture: Off Image average: 1 time Noise reduction: On Brightness correction: On Optical noise filter: On Cutoff: λc=200μm, λs=2μm, no λf Filter: Gaussian filter Noise reduction: Measurement preprocessing Surface (tilt) correction: Implemented Brightness: Adjusted to a range of 30-50 Brightness should be set as appropriate according to the color tone of the measurement target. The above settings are appropriate values when measuring the surface of a surface-treated copper foil with L* ranging from -69 to -10, a* ranging from 2 to 32, and b* of 221.

[0063] <Vickers hardness> The Vickers hardness of the first surface of the first metal layer and the second surface of the second metal layer was measured under the following conditions. The Vickers hardness was measured using a Vickers hardness tester MVK-E manufactured by Akashi Seisakusho Co., Ltd. After placing the sample on the stainless steel plate equipped in the apparatus, the diagonal length of the depression of the trace where the indenter was removed was measured. The vicinity of the center of the test piece for measurement was used as the measurement location, and it was measured 3 times to obtain the average value. The main setting conditions are as follows. Test load: 25 gf Load holding time: 15 seconds Microscope magnification: 400 times (objective lens 40 times, eyepiece lens 10 times)

[0064] <Average crystal grain size> The average crystal grain size of the first surface of the first metal layer and the second surface of the second metal layer was measured under the following conditions. <Measurement conditions of EBSD, etc.> Electropolishing of the copper foil was performed under the following electrolytic solution and test conditions, and about 1 μm of thickness was removed from the sample surface. The sample was placed so that one side of the observation field was parallel to the width direction of the copper foil, and EBSD patterns (Kikuchi patterns) were measured at a step size of 0.15 μm for an arbitrarily set observation range of 50 μm × 50 μm to obtain data for analysis. This measurement was performed at room temperature. Note that there may be parts with local unevenness, abnormal parts such as adhesion of foreign substances or scratches on a part of the sample surface used for EBSD measurement. When performing EBSD measurement, the measurement location should be set avoiding the abnormal parts. <Composition of electrolytic solution (example)> · Distilled water 250 ml · Phosphoric acid 125 ml · Urea 2.5 g · Ethanol grade 1 125 ml · 1-Propanol 25 ml <Electropolishing conditions> Applied voltage: 10V Electrolysis time: 10 seconds

[0065] <SEM conditions> Equipment: Scanning electron microscope (Quanta FEG650) manufactured by FEI Company, Japan Type of electron gun: Field emission electron gun (Schottky type) Emitter of electron gun: ZrO tungsten cathode Type of objective lens: Out-lens type Presence or absence of focus correction: Yes (Dynamic focus: 50) Beam conditions Accelerating voltage: 20 kV Working distance: 25 mm Irradiation current: 15 nA SEM probe diameter: 0.5 - 2 nm Observation magnification: 3000 times

[0066] <EBSD equipment conditions> Detector: Slow-scan CCD camera manufactured by TSL Solutions Co., Ltd. ·Data processing conditions Data collection software: OIM Data Collection manufactured by TSL Solutions Co., Ltd. Phase: Copper Number of pixels of CCD camera: 1394 × 1040 pixels Binning: 8 × 8 Exposure time: 4 - 5 milliseconds Gain: 300 - 600 Presence or absence of background processing: Yes Scanning method of measurement points: Hexagonal lattice ·Hough transform (1) Hough Type: Classic (2) Hough Resolution: Low (3) Classic Hough ·Convolution Mask: 9 × 9 Min Peak Magnitude: 11 Min Peak Distance: 23 Peak Symmetry: 0.8 Vertical Bias: 25% (4) General Parameters Binned Pattern Size: 120 Theta Step Size (Angle Step Size): 1° Rho Fraction: 89% Max Peak Count: 8 Min Peak Count: 3 The above measurement data was collected using OIM Data Collection manufactured by TSL Solutions Co., Ltd., and the data was analyzed using OIM Analysis V8 manufactured by TSL Solutions Co., Ltd. to output the grain size (diameter). <Warping> One metal laminate cut into a 52 cm square was placed on a flat, horizontal reference plate and evaluated for the presence or absence of warping. If the metal laminate warped toward the first metal layer, the first metal layer was placed facing upward, and if the metal laminate warped toward the second metal layer, the second metal layer was placed facing upward. The amount of warping was measured by measuring the minimum vertical distance between the four vertices of the metal laminate and the reference plate using a metal ruler. In this evaluation, if the amount of warping was less than 10 mm, it was designated A, if it was 10 mm or more but less than 20 mm, it was designated B, and if it was 20 mm or more, it was designated C.

[0067] The results of the above evaluations are shown in Table 1.

[0068] [Table 1]

[0069] As shown in Table 1, the metal laminates of Examples 1 to 3, in which the kurtosis Sku of the surface of the second metal layer was 8.0 to 30.0, had little warpage. As can be seen from the above results, according to the embodiment of the present invention, <1> ~ <8> This makes it possible to provide a metal laminate with reduced warpage and an efficient method for manufacturing a multilayer circuit board.

[0070] <1> a first metal layer, a second metal layer, and an etch barrier layer disposed between the first metal layer and the second metal layer; A metal laminate in which the kurtosis Sku of the surface of the second metal layer is 8.0 to 30.0. <2> The kurtosis Sku of the surface of the second metal layer is 10.0 to 20.0. <1> The metal laminate according to claim 1. <3> The kurtosis Sku of the surface of the second metal layer is 14.0 to 18.0. <2> The metal laminate according to claim 1. <4> a ratio of a maximum peak height Sp of the surface of the first metal layer to a maximum peak height Sp of the surface of the second metal layer is 0.3 to 3.0; <1> ~ <3> 10. The metal laminate according to claim 9, wherein <5> The ratio of the maximum peak height Sp is 0.5 to 2.0. <4> The metal laminate according to claim 1. <6> The Vickers hardness of the surface of the first metal layer is 50 to 200. <1> ~ <5> 10. The metal laminate according to claim 9, wherein <7> The Vickers hardness of the surface of the first metal layer is 80 to 130. <6> The metal laminate according to claim 1. <8> a ratio of the Vickers hardness of the surface of the first metal layer to the Vickers hardness of the surface of the second metal layer is 0.70 to 1.40; <1> ~ <7> 10. The metal laminate according to claim 9, wherein <9> a ratio of the Vickers hardness of the surface of the first metal layer to the Vickers hardness of the surface of the second metal layer is 0.80 to 1.20; <8> The metal laminate according to claim 1. <10> The etching barrier layer is made of nickel or a nickel alloy. <1> ~ <9> 10. The metal laminate according to claim 9, wherein <11> For forming electronic circuits, <1> ~ <10> 10. The metal laminate according to claim 9, wherein <12> <1> ~ <11> preparing a metal laminate according to any one of the above; etching the second metal layer of the metal stack to form a circuit; embedding the circuit in insulating resin; removing the first metal layer and the etching barrier layer of the metal laminate to form a circuit board; stacking a plurality of the circuit boards; A method for manufacturing a multilayer circuit board, comprising:

[0071] (Potential contribution to SDGs) According to an embodiment of the present invention, it is possible to provide a metal laminate for forming electronic circuits with reduced warpage. Use of a metal laminate according to an embodiment of the present invention may improve product yield in the manufacture of electronic devices and the like. Improving product yield leads to a stable supply of products and reduced loss of metal raw materials, which are limited resources. Therefore, the above-mentioned embodiment may contribute to the achievement of Goal 9 "Build resilient infrastructure, promote inclusive and sustainable industrialization and foster innovation" and Goal 12 "Ensure sustainable consumption and production patterns" of the United Nations-led Sustainable Development Goals (SDGs). [Explanation of symbols]

[0072] 10 First metal layer 12 Front page 14 Side 2 20 Second metal layer 22 Page 1 24 Side 2 30 Etching barrier layer 50 circuits 60 Insulating resin 70 Circuit Board

Claims

1. a first metal layer, a second metal layer, and an etch barrier layer disposed between the first metal layer and the second metal layer; A metal laminate in which the kurtosis (Sku) of the surface of the second metal layer is 8.0 to 30.

0.

2. 2. The metal laminate according to claim 1, wherein the surface kurtosis Sku of the second metal layer is 10.0 to 20.

0.

3. The metal laminate according to claim 2, wherein the surface kurtosis Sku of the second metal layer is 14.0 to 18.

0.

4. 2. The metal laminate according to claim 1, wherein a ratio of a maximum peak height Sp of the surface of said first metal layer to a maximum peak height Sp of the surface of said second metal layer is 0.3 to 3.

0.

5. 5. The metal laminate according to claim 4, wherein the ratio of the maximum peak heights Sp is 0.5 to 2.

0.

6. 4. The metal laminate according to claim 3, wherein the Vickers hardness of the surface of the first metal layer is 50 to 200.

7. 6. The metal laminate according to claim 5, wherein the Vickers hardness of the surface of the first metal layer is 80 to 130.

8. 7. The metal laminate according to claim 6, wherein the ratio of the Vickers hardness of the surface of said first metal layer to the Vickers hardness of the surface of said second metal layer is 0.70 to 1.

40.

9. 9. The metal laminate according to claim 8, wherein the ratio of the Vickers hardness of the surface of said first metal layer to the Vickers hardness of the surface of said second metal layer is 0.80 to 1.

20.

10. The metal laminate according to any one of claims 1 to 9, wherein the etching barrier layer is made of nickel or a nickel alloy.

11. The metal laminate according to any one of claims 1 to 9, which is used for forming an electronic circuit.

12. A step of preparing the metal laminate according to any one of claims 1 to 9; etching the second metal layer of the metal stack to form a circuit; embedding the circuit in insulating resin; removing the first metal layer and the etching barrier layer of the metal laminate to form a circuit board; stacking a plurality of the circuit boards; A method for manufacturing a multilayer circuit board, comprising:

Images