Multilayer circuit board, manufacturing method thereof, and electronic device including multilayer circuit board

Abstract

A multilayer circuit board, a manufacturing method thereof, and an electronic device including the multilayer circuit board are provided, wherein the multilayer circuit board can reduce the number of processes and manufacturing costs by using a single-sided FCCL and RCC. The multilayer circuit board comprises: a core layer; a second circuit layer formed on a first surface of the core layer; a first interlayer insulating layer covering the second circuit layer; a first circuit layer formed on the first interlayer insulating layer; a second interlayer insulating layer formed on a second surface of the core layer; and a third circuit layer formed on the second interlayer insulating layer.

Description

A multilayer circuit board, a method for manufacturing the same, and an electronic device including the multilayer circuit board

[0001] The present invention relates to a manufacturing method for efficiently producing a multilayer circuit board, a multilayer circuit board produced according to the manufacturing method, and an electronic device including the multilayer circuit board.

[0002] In the case of manufacturing a three-layer circuit board, conventionally, a second circuit layer and a third circuit layer are formed on both sides of a base film, respectively, and then a first circuit layer is formed on the second circuit layer. However, according to this method, a through hole for electrically connecting the second circuit layer and the third circuit layer is formed first, and then a via hole for electrically connecting the first circuit layer and the second circuit layer is formed. Additionally, a protective film is attached to the third circuit layer before forming the first circuit layer, and the protective film is removed from the third circuit layer after forming the first circuit layer. As such, according to the conventional method, multiple processes must be performed to manufacture a three-layer circuit board, and the associated costs may increase.

[0003] The technical problem to be solved by the present invention is to provide a method for manufacturing a multilayer circuit board capable of reducing the number of process steps and manufacturing costs, a multilayer circuit board produced according to the manufacturing method, and an electronic device including the multilayer circuit board.

[0004] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below.

[0005] An aspect of a multilayer circuit board according to the present invention for achieving the above technical problem comprises: a core layer; a second circuit layer formed on a first surface of the core layer; a first interlayer insulating layer covering the second circuit layer; a first circuit layer formed on the first interlayer insulating layer; a second interlayer insulating layer formed on a second surface of the core layer; and a third circuit layer formed on the second interlayer insulating layer.

[0006] One aspect of the electronic device of the present invention for achieving the above technical problem includes a multilayer circuit board formed with a structure as described above.

[0007] One aspect of a method for manufacturing a multilayer circuit board according to the present invention for achieving the above technical problem comprises: a step of forming a second circuit layer on a first surface of a core layer; a step of forming a first interlayer insulating layer and a first metal layer on the second circuit layer; a step of forming a first via hole that penetrates the first interlayer insulating layer and the first metal layer and exposes at least a portion of the second circuit layer; a step of forming a first partial metal layer within the first via hole; a step of forming a second partial metal layer within the first via hole; and a step of forming a first circuit layer based on the first metal layer.

[0008] The method for manufacturing the multilayer circuit board further comprises the steps of: forming a second interlayer insulating layer and a second metal layer on a second surface of the core layer; forming a second via hole that penetrates the core layer, the second interlayer insulating layer, and the second metal layer, while exposing at least a portion of the second circuit layer; forming a first partial metal layer within the second via hole; forming a second partial metal layer within the second via hole; and forming a third circuit layer based on the second metal layer.

[0009] Alternatively, the method for manufacturing the multilayer circuit board further comprises the steps of: forming a fourth circuit layer on a second surface of the core layer; forming a second interlayer insulating layer and a second metal layer on the fourth circuit layer; forming a third via hole that penetrates the second interlayer insulating layer and the second metal layer while exposing at least a portion of the fourth circuit layer; forming a first partial metal layer within the third via hole; forming a second partial metal layer within the third via hole; and forming a third circuit layer based on the second metal layer.

[0010] Another aspect of the multilayer circuit board of the present invention for achieving the above technical problem is manufactured according to the above manufacturing method.

[0011] Another aspect of the electronic device of the present invention for achieving the above technical problem includes a multilayer circuit board manufactured according to the above manufacturing method.

[0012] Specific details of other embodiments are included in the detailed description and drawings.

[0013] According to the present invention, the following effects can be obtained.

[0014] First, via holes electrically connecting the first circuit layer and the second circuit layer, and via holes electrically connecting the second circuit layer and the third circuit layer can be formed simultaneously. This can reduce the number of processes in manufacturing a multilayer circuit board.

[0015] Second, the process of attaching a protective film on the third circuit layer and the process of removing the protective film from the third circuit layer can be omitted. The number of processes can be reduced in manufacturing a multilayer circuit board.

[0016] Third, manufacturing costs can be reduced by decreasing the number of process steps in manufacturing multilayer circuit boards.

[0017] The effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below.

[0018] FIG. 1 is a first flowchart for explaining, step by step, a method for manufacturing a multilayer circuit board according to some embodiments of the present invention.

[0019] FIG. 2 is a first example diagram for explaining the product structure at step S110 of the manufacturing method of a multilayer circuit board.

[0020] Figure 3 is a second example diagram for explaining the product structure at step S110 of the manufacturing method of a multilayer circuit board.

[0021] FIG. 4 is a first example diagram for explaining the product structure at step S120 of the manufacturing method of a multilayer circuit board.

[0022] FIG. 5 is a second example diagram for explaining the product structure at step S120 of the manufacturing method of a multilayer circuit board.

[0023] FIG. 6 is a first example diagram for explaining the product production method in step S120 of the manufacturing method of a multilayer circuit board.

[0024] FIG. 7 is a second example diagram illustrating a product production method in step S120 of a method for manufacturing a multilayer circuit board.

[0025] FIG. 8 is a third example diagram illustrating a product production method in step S120 of a method for manufacturing a multilayer circuit board.

[0026] FIG. 9 is a third example diagram illustrating the product structure at step S120 of the manufacturing method of a multilayer circuit board.

[0027] FIG. 10 is a fourth example diagram illustrating the product structure at step S120 of the manufacturing method of a multilayer circuit board.

[0028] Figure 11 is an example diagram illustrating the product structure at step S130 of the manufacturing method of a multilayer circuit board.

[0029] FIG. 12 is a first example diagram for explaining the product structure at step S140 of the manufacturing method of a multilayer circuit board.

[0030] FIG. 13 is a second example diagram for explaining the product structure at step S140 of the manufacturing method of a multilayer circuit board.

[0031] FIG. 14 is a third example diagram illustrating the product structure at step S140 of the manufacturing method of a multilayer circuit board.

[0032] FIG. 15 is a fourth example diagram illustrating the product structure at step S140 of the manufacturing method of a multilayer circuit board.

[0033] FIG. 16 is a first example diagram for explaining the product structure at step S150 of the manufacturing method of a multilayer circuit board.

[0034] FIG. 17 is a second example diagram for explaining the product structure at step S150 of the manufacturing method of a multilayer circuit board.

[0035] FIG. 18 is an example diagram illustrating the product structure at step S160 of the manufacturing method of a multilayer circuit board.

[0036] FIG. 19 is a second flowchart for explaining, step by step, a method for manufacturing a multilayer circuit board according to some embodiments of the present invention.

[0037] FIG. 20 is an example diagram illustrating a product production method in step S125 of a method for manufacturing a multilayer circuit board.

[0038] FIG. 21 is a third flowchart for explaining, step by step, a method for manufacturing a multilayer circuit board according to some embodiments of the present invention.

[0039] FIG. 22 is an example diagram illustrating the product structure at step S155 of the manufacturing method of a multilayer circuit board.

[0040] Embodiments of the present invention will be described in detail below with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0041] The first direction (D1) and the second direction (D2) can form a two-dimensional plane. The first direction (D1) may be the X-axis direction and the second direction (D2) may be the Y-axis direction. The first direction (D1) may be the left-right direction and the second direction (D2) may be the front-back direction. Alternatively, the first direction (D1) may be the front-back direction and the second direction (D2) may be the left-right direction. The third direction (D3) can form a three-dimensional solid with the first direction (D1) and the second direction (D2). The third direction (D3) is a direction perpendicular to the plane formed by the first direction (D1) and the second direction (D2). The third direction (D3) may be the Z-axis direction. The third direction (D3) may be the up-down direction.

[0042] Multilayer circuit boards can be produced more efficiently than in conventional cases by reducing the number of process steps and manufacturing costs. Multilayer circuit boards can be provided as flexible circuit boards. For example, multilayer circuit boards can be provided as Flexible PCBs (FPCBs). Additionally, multilayer circuit boards can be provided as substrates for mounting electronic components for display driving. For example, multilayer circuit boards can be provided as Chip On Films (COFs). Meanwhile, it is also possible for multilayer circuit boards to be provided as coil substrates.

[0043] A method for manufacturing a multilayer circuit board is described below. The following description will use a method for manufacturing a three-layer circuit board as an example, but the present invention is not limited thereto. It goes without saying that the present invention can be equally applied to manufacturing a multilayer circuit board of four layers or more. FIG. 1 is a first flowchart for explaining, step-by-step, a method for manufacturing a multilayer circuit board according to some embodiments of the present invention.

[0044] When the core layer is prepared, a second circuit layer is formed on one side of the core layer (S110). The core layer may be provided as a product in which a metal layer is laminated on one or both sides of an insulating film. For example, the core layer may be provided as an FCCL (Flexible Copper Clad Laminate) in which a metal layer is formed on one or both sides of an insulating film. Referring to FIG. 2, the core layer (210) may be provided including a base film (310) and a second metal layer (320). FIG. 2 is a first example diagram for explaining the product structure at step S110 of the method for manufacturing a multilayer circuit board.

[0045] The base film (310) may be provided with a constant thickness. The base film (310) may be made of an insulating resin. For example, the base film (310) may be made of at least one polymer material such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), epoxy, and glass fiber. However, the polymer material constituting the base film (310) is not limited to these, and any flexible material having insulating properties can be used as the constituent material of the base film (310).

[0046] Additionally, the base film (310) may have a thickness of 10 µm to 100 µm. For example, the base film (310) may have a thickness of 10 µm to 40 µm. If the thickness of the base film (310) exceeds 100 µm, it may be difficult to implement miniaturization of the electronic device equipped with the multilayer circuit board as the thickness of the multilayer circuit board increases. If the thickness of the base film (310) is less than 10 µm, problems such as crumpling, tearing, or shrinkage of the base film (310) may occur due to external stress, such as heat or pressure, during a number of process flows including the circuit layer formation process or lamination process described later.

[0047] The second metal layer (320) may be made of an electrically conductive material. For example, the second metal layer (320) may be formed from any one metal selected from conductive metals such as nickel (Ni), chromium (Cr), copper (Cu), gold (Au), silver (Ag), platinum (Pt), aluminum (Al), palladium (Pd), titanium (Ti), and tin (Sn). Alternatively, the second metal layer (320) may be formed by alloying or laminating a plurality of metals selected from the conductive metals.

[0048] Meanwhile, the core layer (210) may also be provided as a product in which a metal layer is not laminated on at least one side of the base film (310). In this case, a metal layer may be formed on the core layer (210) before forming the circuit layer. Physical or chemical methods such as deposition, adhesion, or plating may be applied to the method of forming the metal layer.

[0049] Referring to FIG. 3, the second circuit layer (220) can be formed by processing the second metal layer (320). The second circuit layer (220) can be formed on the first surface (210a) of the core layer (210). The circuit layer may not be formed on the second surface (210b) of the core layer (210). FIG. 3 is a second example diagram for explaining the product structure at step S110 of the method for manufacturing a multilayer circuit board.

[0050] The second circuit layer (220) can be formed using an etching method. For example, the second circuit layer (220) can be formed on the core layer (210) through photo etching. Alternatively, the second circuit layer (220) can be formed on the core layer (210) using a plating method. For example, the second circuit layer (220) can be formed on the core layer (210) through an Additive Process (AP), a Semi-Additive Process (SAP), printing, coating, etc. When using a plating method, the second circuit layer (220) can be formed on the core layer (210) through a method selected from electrolytic plating and electroless plating.

[0051] Additionally, the second circuit layer (220) can be formed in various shapes, such as a line shape or a spiral shape, and can be formed with a thickness of 3 μm to 200 μm. The thickness of the second circuit layer (220) can be selectively applied depending on the application of the electronic device to which the flexible circuit board according to the present invention is applied. For example, if the electronic device is for screen display purposes such as a display, the second circuit layer (220) can be formed with a thickness of 3 μm to 20 μm. By being formed within the above thickness range, it is effective for signal transmission for miniaturization, thinning, and high-resolution output of the electronic device. As another example, if the electronic device is for electromagnetic force generation purposes such as a camera module or an inductor, the second circuit layer (220) can be formed with a thickness of 30 μm to 200 μm (more preferably 30 μm to 150 μm). Through this, electromagnetic force effective for correcting lens shake or inducing voltage changes can be generated.

[0052] Meanwhile, the second circuit layer (220) may be formed with a width of 0.01 to 1 aspect ratio relative to its thickness, and if it is formed with a width exceeding the aspect ratio, it is impossible to implement the desirable effects even if the thickness range of the second circuit layer (220) described above is satisfied.

[0053] Additionally, the circuit layer formed on the multilayer circuit board according to the present invention, including the first circuit layer and the third circuit layer described below, may be formed within the range of the thickness and / or width of the second circuit layer (220).

[0054] Although not illustrated in FIGS. 2 and 3, a seed layer may be provided between the core layer (210) and the second circuit layer (220). The seed layer may be formed on the base film (310) before the second metal layer (320). The seed layer may be provided as a conductive layer in the form of a thin film. For example, the seed layer may be formed from any one metal selected from conductive metals such as nickel (Ni), chromium (Cr), copper (Cu), gold (Au), aluminum (Al), and palladium (Pd). Alternatively, the seed layer may be formed from an alloy comprising a plurality of metals selected from the conductive metals. The seed layer may be formed by physical or chemical methods such as deposition, adhesion, or plating. The seed layer can improve the bonding between the core layer (210) and the second circuit layer (220).

[0055] Referring again to Fig. 1, the explanation will be provided.

[0056] When a second circuit layer (220) is formed on the first surface (210a) of the core layer (210), an interlayer insulating layer and a metal layer are formed on both sides (210a, 210b) of the core layer (210), respectively (S120). Referring to FIG. 4, a first interlayer insulating layer (230) and a first metal layer (330) may be formed on the first surface (210a) of the core layer (210). The first interlayer insulating layer (230) may be formed on the second circuit layer (220), and the first metal layer (330) may be formed on the first interlayer insulating layer (230). Additionally, a second interlayer insulating layer (240) and a third metal layer (340) may be formed on the second surface (210b) of the core layer (210). The second interlayer insulating layer (240) is formed on the core layer (210), and the third metal layer (340) can be formed on the second interlayer insulating layer (240). FIG. 4 is a first example diagram for explaining the product structure at step S120 of the method for manufacturing a multilayer circuit board.

[0057] The first interlayer insulating layer (230) may cover the second circuit layer (220) on the first surface (210a) of the core layer (210). The first interlayer insulating layer (230) may cover the entire second circuit layer (220), but is not limited thereto, and it is also possible to not cover a part of the second circuit layer (220). A part of the second circuit layer (220) not covered by the first interlayer insulating layer (230) may be provided as a connection lead and may be electrically connected to an electronic component or an external electronic device.

[0058] The first interlayer insulation layer (230) and the second interlayer insulation layer (240) may be made of an insulating material. The first interlayer insulation layer (230) and the second interlayer insulation layer (240) may be made of an insulating material of a different type from the base film (310). For example, the base film (310) may be made of polyimide (PI). On the other hand, the first interlayer insulation layer (230) and the second interlayer insulation layer (240) may be made of resin. However, they are not limited thereto, and it is also possible for the first interlayer insulation layer (230) and the second interlayer insulation layer (240) to be made of an insulating material equivalent to the base film (310). The first interlayer insulation layer (230) and the second interlayer insulation layer (240) may be made of one or more resins among synthetic resins such as polyimide-based, acrylic-based, epoxy-based, urethane-based, and phenol-based resins. The first interlayer insulation layer (230) and the second interlayer insulation layer (240) may be formed simultaneously. However, this is not limited thereto, and it is also possible for either the first interlayer insulation layer (230) or the second interlayer insulation layer (240) to be formed before the other insulation layer.

[0059] As will be described later, the first circuit layer can be formed on the second circuit layer (220). The first interlayer insulating layer (230) can cover the second circuit layer (220) and separate the first circuit layer and the second circuit layer (220). Referring to FIG. 5, the first interlayer insulating layer (230) and the second interlayer insulating layer (240) can be formed on each side of the core layer (210). The second interlayer insulating layer (240) can be formed with a first thickness (T1). The first circuit layer can be separated from the second circuit layer (220) by a second thickness (T2). The first thickness (T1) may be equal to the second thickness (T2). The first thickness (T1) may be different from the second thickness (T2). The first thickness (T1) may be greater than the second thickness (T2). Preferably, the first thickness (T1) can be formed at a level of 100% to 150% of the second thickness (T2). When the first thickness (T1) is formed at such a level compared to the second thickness (T2), the thermal properties can be balanced, and the effect of suppressing substrate bowing can be obtained when manufacturing a multilayer circuit board. FIG. 5 is a second example diagram for explaining the product structure at step S120 of the method for manufacturing a multilayer circuit board. In FIG. 5, the first interlayer insulating layer (230) on one side of the base film (210) on which the second circuit layer (220) is formed is shown to be formed with a thinner thickness (T2) than the second interlayer insulating layer (240) on the other side of the base film (210). However, depending on the bending direction or thermal characteristic balance of the multilayer circuit board according to the present invention, the thickness of the first interlayer insulating layer (230) may be formed to a first thickness (T1), and the thickness of the second interlayer insulating layer (240) may be formed to a second thickness (T2).

[0060] The first metal layer (330) and the third metal layer (340) may be made of an electrically conductive material. The first metal layer (330) and the third metal layer (340) may be made of a conductive metal equivalent to the second metal layer (320), but the present embodiment is not necessarily limited thereto. The first metal layer (330) and the third metal layer (340) may be formed simultaneously, but are not limited thereto, and it is also possible for one of the first metal layer (330) and the third metal layer (340) to be formed before the other metal layer.

[0061] The first metal layer (330) and the third metal layer (340) may each be formed with a predetermined thickness. The first metal layer (330) and the third metal layer (340) may be formed with equal thickness. The first metal layer (330) and the third metal layer (340) may be formed with different thicknesses. The first metal layer (330) and the third metal layer (340) may be formed with a thickness of 1 μm to 35 μm. Preferably, the first metal layer (330) and the third metal layer (340) may be formed with a thickness of 1 μm to 12 μm. More preferably, the first metal layer (330) and the third metal layer (340) may be formed with a thickness of 1 μm to 3 μm.

[0062] Referring to FIG. 6, the first interlayer insulating layer (230) and the first metal layer (330) can be formed simultaneously. FIG. 6 is a first example diagram for explaining a product production method in step S120 of a method for manufacturing a multilayer circuit board.

[0063] The first interlayer insulating layer (230) and the first metal layer (330) may be provided as a product in the form of a film. For example, the first interlayer insulating layer (230) and the first metal layer (330) may be provided as resin-coated copper (RCC). However, not limited thereto, the first interlayer insulating layer (230) and the first metal layer (330) may also be provided as a product in the form of a paste. Alternatively, the first interlayer insulating layer (230) and the first metal layer (330) may also be provided as a product in the form of a laminate.

[0064] The first interlayer insulating layer (230) and the first metal layer (330) may be formed using a method selected according to the form of the product. For example, if provided as a film-type product, the first interlayer insulating layer (230) and the first metal layer (330) may be formed using a lamination method. If provided as a paste-type product, the first interlayer insulating layer (230) and the first metal layer (330) may be formed using a coating method. If provided as a laminated-type product, the first interlayer insulating layer (230) and the first metal layer (330) may be formed by laminating the laminated product.

[0065] It is also possible for the first interlayer insulating layer (230) and the first metal layer (330) not to be formed simultaneously. Referring to FIG. 7, the first interlayer insulating layer (230) may first be formed on the first surface (210a) of the core layer (210) to cover the second circuit layer (220), and then the first metal layer (330) may be formed on the first interlayer insulating layer (230). FIG. 7 is a second example diagram for explaining the product production method in step S120 of the method for manufacturing a multilayer circuit board.

[0066] The second interlayer insulating layer (240) and the third metal layer (340) may be formed simultaneously, but are not limited thereto and may also be formed sequentially. When the second interlayer insulating layer (240) and the third metal layer (340) are formed simultaneously, any one of the following may be utilized: a film-type product, a paste-type product, or a laminate-type product. The second interlayer insulating layer (240) and the third metal layer (340) may be formed in a manner equivalent to the first interlayer insulating layer (230) and the first metal layer (330), but the present embodiment is not necessarily limited thereto.

[0067] Referring to FIG. 8, the first interlayer insulating layer (230) and the first metal layer (330) can be formed simultaneously with the second interlayer insulating layer (240) and the third metal layer (340). In this case, the first interlayer insulating layer (230) and the first metal layer (330) may utilize any one of a product selected from a film-type product, a paste-type product, and a laminate-type product. Similarly, the second interlayer insulating layer (240) and the third metal layer (340) may also utilize any one of a product selected from a film-type product, a paste-type product, and a laminate-type product. FIG. 8 is a third example diagram for explaining the product production method in step S120 of the manufacturing method of a multilayer circuit board.

[0068] It is also possible for the first interlayer insulating layer (230) and the first metal layer (330) not to be formed simultaneously with the second interlayer insulating layer (240) and the third metal layer (340). In this case, the first interlayer insulating layer (230) and the first metal layer (330) may be formed before the second interlayer insulating layer (240) and the third metal layer (340). Alternatively, the second interlayer insulating layer (240) and the third metal layer (340) may be formed before the first interlayer insulating layer (230) and the first metal layer (330). The first interlayer insulating layer (230) and the first metal layer (330) may be formed simultaneously, but they may also be formed sequentially. Likewise, the second interlayer insulating layer (240) and the third metal layer (340) may be formed simultaneously, but they may also be formed sequentially.

[0069] Meanwhile, it is also possible for the first interlayer insulating layer (230) and the second interlayer insulating layer (240) to be formed first, followed by the first metal layer (330) and the third metal layer (340). The first interlayer insulating layer (230) and the second interlayer insulating layer (240) may be formed simultaneously, but they may also be formed sequentially. Likewise, the first metal layer (330) and the third metal layer (340) may be formed simultaneously, but they may also be formed sequentially.

[0070] As previously explained, a first interlayer insulating layer (230) and a first metal layer (330) may be formed on the second circuit layer (220). The first interlayer insulating layer (230) and the first metal layer (330) are examples of cases where a two-layer RCC (Resin Coated Copper) is provided on the second circuit layer (220). Here, the number of layers of the RCC means that they are distinguished according to the composition or characteristics such as hardness, meltability, and viscosity constituting each layer, and the number of layers of the three-layer RCC described later has the same meaning. The two-layer RCC may be formed by a laminating method. Alternatively, the two-layer RCC may be formed by a casting method.

[0071] It is also possible to provide a 3-layer RCC on the second circuit layer (220). FIG. 9 is a third example diagram for explaining the product structure at step S120 of the method for manufacturing a multilayer circuit board. Referring to FIG. 9, the 3-layer RCC may include a first interlayer insulating layer (230), a first metal layer (330), and a seed layer (610). The seed layer (610) may be provided between the first interlayer insulating layer (230) and the first metal layer (330).

[0072] The seed layer (610) may be provided as a conductive layer in the form of a thin film. The seed layer (610) may be formed from any one metal selected from conductive metals such as nickel (Ni), chromium (Cr), copper (Cu), gold (Au), aluminum (Al), and palladium (Pd). Alternatively, the seed layer (610) may be formed from an alloy comprising a plurality of metals selected from the conductive metals. The seed layer (610) may be formed by physical or chemical methods such as deposition, adhesion, or plating. The seed layer (610) may be provided integrally with the first interlayer insulating layer (230) and the first metal layer (330). The three-layer RCC may be provided as a single-sided FCCL (Flexible Copper Clad Laminate) including the seed layer (610).

[0073] It is also possible to provide a 4-layer RCC on the second circuit layer (220). FIG. 10 is a fourth example diagram for explaining the product structure at step S120 of the method for manufacturing a multilayer circuit board. Referring to FIG. 10, the 4-layer RCC may include a first interlayer insulating layer (230), a first metal layer (330), a seed layer (610), and an insulating portion (620). The insulating portion (620) may be provided between the first interlayer insulating layer (230) and the seed layer (610).

[0074] The insulating part (620) may be made of an insulating material. For example, the insulating part (620) may be made of a polyimide (PI) film. The insulating part (620) may be made of an insulating material of the same type as the core layer (210). The insulating part (620) may be made of an insulating material of a different type from the first interlayer insulating layer (230). For example, the first interlayer insulating layer (230) may be made of a resin containing epoxy, and the insulating part (620) may be made of polyimide (PI). However, it is not limited thereto, and it is also possible for the insulating part (620) to be made of an insulating material of the same type as the first interlayer insulating layer (230). For example, the first interlayer insulation layer (230) and the insulation portion (620) may be formed by including polyimide (PI), and may be polyimide (PI) of equivalent physical properties or state. Alternatively, the polyimide (PI) included in the first interlayer insulation layer (320) may have higher meltability or lower curing degree compared to the polyimide (PI) included in the insulation portion (620), thereby increasing the filling capacity of the space between adjacent second circuit layers (220) while ensuring rigidity against stress provided in the first circuit layer (270) formation process described later.

[0075] The insulating portion (620) may be provided integrally with the seed layer (610) and the first metal layer (330). The insulating portion (620), the seed layer (610), and the first metal layer (330) may be provided as single-sided FCCL. The four-layer RCC may be provided by forming an adhesive layer on the single-sided FCCL. The first interlayer insulating layer (230) may be provided as an adhesive layer. The four-layer RCC may be provided as FRCC (Flexible Resin Coated Copper). The four-layer RCC including a polyimide (PI) film can enhance heat resistance and rigidity when the RCC is laminated on a core substrate.

[0076] Meanwhile, although not shown in the drawing, it is also possible that a seed layer (610) is not provided between the insulating part (620) and the first metal layer (330). In this case, a three-layer RCC including the first interlayer insulating layer (230), the first metal layer (330), and the insulating part (620) may be provided on the second circuit layer (220).

[0077] A 3-layer RCC or a 4-layer RCC may also be provided on the second surface (210b) of the core layer (210) where the second circuit layer (220) is not formed. When a 3-layer RCC is provided on the second circuit layer (220), a 3-layer RCC may be provided on the second surface (210b) of the core layer (210). When a 3-layer RCC is provided on the second surface (210b) of the core layer (210), a seed layer (610) may be provided between the second interlayer insulating layer (240) and the third metal layer (340). When a 4-layer RCC is provided on the second circuit layer (220), a 4-layer RCC may be provided on the second surface (210b) of the core layer (210). When a 4-layer RCC is provided on the second surface (210b) of the core layer (210), an insulating portion (620) may be provided between the second interlayer insulating layer (240) and the seed layer (610). It is also possible for an insulating portion (620) to be provided between the second interlayer insulating layer (240) and the third metal layer (340) and for the seed layer (610) not to be provided.

[0078] Referring again to Fig. 1, the explanation will be provided.

[0079] When a first interlayer insulating layer (230), a first metal layer (330), a second interlayer insulating layer (240), and a third metal layer (340) are formed on both sides (210a, 210b) of the core layer (210), via holes are formed on each side (210a, 210b) of the core layer (210) (S130). Referring to FIG. 11, the first via hole (350) may be formed on the first side (210a) of the core layer (210). The second via hole (360) may be formed on the second side (210b) of the core layer (210). FIG. 11 is an example diagram for explaining the product structure at step S130 of the method for manufacturing a multilayer circuit board.

[0080] The first via hole (350) can penetrate the first metal layer (330) and the first interlayer insulating layer (230) in sequence. The first via hole (350) can be formed using a laser method. Alternatively, the first via hole (350) can be formed using an etching method. The first via hole (350) can come into contact with the second circuit layer (220). The first via hole (350) can expose the second circuit layer (220). A portion of the second circuit layer (220) may be exposed to the outside.

[0081] The second via hole (360) can penetrate the third metal layer (340), the second interlayer insulating layer (240), and the core layer (210) in sequence. The second via hole (360) can be formed using a laser method. Alternatively, the second via hole (360) can be formed using an etching method. The second via hole (360) can come into contact with the second circuit layer (220). The second via hole (360) can expose the second circuit layer (220). The portion exposed by the first via hole (350) may be part of one side of the second circuit layer (220), and the portion exposed by the second via hole (360) may be part of the other side of the second circuit layer (220). The portion exposed to the outside may be the upper surface of the second circuit layer (220). Alternatively, the parts exposed to the outside may be the upper and side surfaces of the second circuit layer (220).

[0082] The first via hole (350) and the second via hole (360) may be formed simultaneously. However, this is not limited thereto, and it is also possible for one of the first via hole (350) and the second via hole (360) to be formed before the other via hole. The first via hole (350) and the second via hole (360) may be formed using equivalent methods, but this embodiment is not necessarily limited thereto.

[0083] Although not shown in the drawing, an insulating layer may be added between the first interlayer insulating layer (230) and the first metal layer (330). Likewise, an insulating layer may be added between the second interlayer insulating layer (240) and the third metal layer (340). The first via hole (350) and the second via hole (360) may also penetrate the insulating layer. A fourth circuit layer may be further included on the second surface (210b) of the core layer, in which case the second via hole (360) may be formed so as to expose the fourth circuit layer.

[0084] Referring again to Fig. 1, the explanation will be provided.

[0085] When via holes (350, 360) are formed on each side (210a, 210b) of the core layer (210), each via hole (350, 360) is filled with a conductive material (S140). Referring to FIG. 12, the first circuit connection layer (250) can be created by filling the first via hole (350) with a conductive material. The second circuit connection layer (260) can be created by filling the second via hole (360) with a conductive material. FIG. 12 is a first example diagram for explaining the product structure at step S140 of the method for manufacturing a multilayer circuit board.

[0086] The first circuit connection layer (250) can be electrically connected to the second circuit layer (220). The first circuit connection layer (250) can be electrically connected to the first metal layer (330). The first circuit connection layer (250) can electrically connect the second circuit layer (220) and the first metal layer (330). The first circuit connection layer (250) can be made of an electrically conductive material. For example, the first circuit connection layer (250) can be formed from any one metal selected from conductive metals such as copper (Cu), gold (Au), silver (Ag), aluminum (Al), tin (Sn), and palladium (Pd), or can be formed by alloying or laminating a plurality of metals selected from the conductive metals.

[0087] The second circuit connection layer (260) may be electrically connected to the second circuit layer (220). The second circuit connection layer (260) may be electrically connected to the third metal layer (340). The second circuit connection layer (260) may electrically connect the second circuit layer (220) and the third metal layer (340). The first circuit connection layer (250) and the second circuit connection layer (260) may electrically connect the second circuit layer (220), the first metal layer (330), and the third metal layer (340). The second circuit connection layer (260) may be made of an electrically conductive material. The second circuit connection layer (260) may be formed by including a conductive metal equivalent to that of the first circuit connection layer (250), but the present embodiment is not necessarily limited thereto.

[0088] Additionally, in FIG. 12, the thickness of the first circuit connection layer (250) is shown as being thinner than the thickness of the second circuit connection layer (260), but the present invention is not limited thereto. The thickness of the first circuit connection layer (250) and the thickness of the second circuit connection layer (260) may be formed at an equal level or differently. This can be selectively applied depending on the direction in which the second circuit layer (220) is formed, the amount of current flowing through the base film (210), etc.

[0089] Meanwhile, a circuit layer may be further included on the second surface (210b) of the core layer (210), and the second circuit connection layer (260) may electrically connect the circuit layer and the third metal layer (340).

[0090] The first circuit connection layer (250) may be provided after the first metal layer (330) is formed. However, it is not limited thereto, and the first circuit connection layer (250) may also be provided before the first metal layer (330) is formed. As will be described later, the method of forming the partial metal layer within the first circuit connection layer (250) may vary depending on the timing of the provision of the first circuit connection layer (250). Likewise, the second circuit connection layer (260) may also be provided after the third metal layer (340) is formed, and it may also be provided before the third metal layer (340) is formed.

[0091] The first circuit connection layer (250) and the second circuit connection layer (260) may be formed as a single layered structure, but it is also possible to form them as multiple layered structures. Below, the case in which the first circuit connection layer (250) is formed as multiple layered structures will be described. FIG. 13 is a second example diagram for explaining the product structure at step S140 of the method for manufacturing a multilayer circuit board.

[0092] Referring to FIG. 13, the first circuit connection layer (250) may include a first partial metal layer (251) and a second partial metal layer (252). The first partial metal layer (251) may contact the inner wall of the first via hole (350). The first partial metal layer (251) may surround the second partial metal layer (252). The first partial metal layer (251) may be electrically connected to the second partial metal layer (252). The second partial metal layer (252) may not contact the inner wall of the first via hole (350) by the first partial metal layer (251). The first partial metal layer (251) and the second partial metal layer (252) may be formed sequentially. The first partial metal layer (251) may be provided as a seed layer for forming the second partial metal layer (252). That is, a first partial metal layer (251) is formed in the internal space of the first via hole (350), and then a second partial metal layer (252) can be formed in the internal space of the first partial metal layer (251).

[0093] A first partial metal layer (251) may be formed within the first via hole (350), and then a second partial metal layer (252) may be formed. A first circuit connection layer (250) comprising the first partial metal layer (251) and the second partial metal layer (252) may be formed within the first via hole (350). A cleaning process may be performed after forming the first partial metal layer (251) and before forming the second partial metal layer (252).

[0094] The first partial metal layer (251) can be formed using a hole conductivity method. The conductive layer can be formed to cover the upper surface of the first metal layer (330), the inner wall of the first via hole (350), and the second circuit layer (220) exposed to the outside by the first via hole (350). The conductive layer can be formed with a predetermined thickness. The conductive layer can be formed with a thickness of 10 nm to 200 nm. Preferably, the conductive layer can be formed with a thickness of 30 nm to 80 nm. The conductive layer formed on the upper surface of the first metal layer (330) can be removed before forming the second partial metal layer (252). The conductive layer formed on the second circuit layer (220) can also be removed before forming the second partial metal layer (252). The conductive layer formed on the inner wall of the first via hole (350) may remain. A conductive layer formed on the inner wall of the first via hole (350) may be provided as a first partial metal layer (251). The first partial metal layer (251) may be made of metal. The first partial metal layer (251) may be made of any one metal or a plurality of metals selected from conductive metals including nickel (Ni), chromium (Cr), copper (Cu), gold (Au), aluminum (Al) and palladium (Pd).

[0095] A conductive layer may be formed on the surface of the second circuit layer (220) through hole conductivity to form the first partial metal layer (251). The conductive layer formed on the surface of the second circuit layer (220) may weaken the bonding strength between the second partial metal layer (252) and the second circuit layer (220). It is necessary to remove the conductive layer formed on the surface of the second circuit layer (220) through a cleaning process.

[0096] However, the cleaning process cannot completely remove the conductive layer remaining on the surface of the second circuit layer (220) or the first metal layer (330), and as a result, the surface of the second circuit layer (220) or the first metal layer (330) may be contaminated or deteriorated. The conductive layer remaining on the surface of the second circuit layer (220) may also cause voids within the circuit board.

[0097] In the present invention, a cleaning process may be performed after forming the first partial metal layer (251), but it is also possible to perform the micro-etching process described later. Referring to FIG. 14, the micro-etching process may partially or entirely etch the second circuit layer (220) exposed to the outside through the first via hole (350). The micro-etching process may partially or entirely etch the second circuit layer (220) to a predetermined thickness (T3). For example, the micro-etching process may etch the upper surface of the second circuit layer (220) to a thickness of 0.5 μm to 3 μm. The micro-etching process may remove the conductive layer formed on the surface of the second circuit layer (220). The micro-etching process may also remove the second circuit layer (220) on which the conductive layer is formed. The micro-etching process can prevent voids from forming within the circuit board and can also prevent the bonding strength between the second partial metal layer (252) and the second circuit layer (220) from weakening. FIG. 14 is a third example diagram illustrating the product structure at step S140 of the method for manufacturing a multilayer circuit board.

[0098] Although not illustrated in FIG. 14, the micro-etching process can also remove the conductive layer formed on the upper surface of the first metal layer (330). The thickness of the first metal layer (330) may be thinner than before. The thickness of the first metal layer (330), which was formed with a thickness of 1 μm to 35 μm, may be reduced to 0.1 μm to 2 μm. Alternatively, the etching thickness may be further increased so that the thickness of the first metal layer (330) becomes 0.1 μm to 1.5 μm. Alternatively, if the thickness of the first metal layer (330) is 1 μm to 5 μm, it may be formed to 0.1 μm to 1 μm after micro-etching, and if the thickness of the first metal layer (330) is 7 μm to 12 μm, it may be formed to 1 μm to 5 μm after micro-etching. Alternatively, the thickness of the first metal layer (330) etched by micro-etching may be 0.1 μm or more and 3.0 μm or less. Preferably, the thickness of the first metal layer (330) etched by micro-etching may be 0.5 μm to 2 μm.

[0099] The second partial metal layer (252) can fill the etched portion (630) of the second circuit layer (220). The etched portion (630) of the second circuit layer (220) can be provided as a groove. Referring to FIGS. 14 and 15, the second partial metal layer (252) can simultaneously fill the first via hole (350) and the etched portion (630) of the second circuit layer (220). The bonding strength of the second partial metal layer (252) with the second circuit layer (220) can be strengthened. FIG. 15 is a fourth example diagram for explaining the product structure at step S140 of the method for manufacturing a multilayer circuit board.

[0100] The first partial metal layer (251) can be formed using sputtering. The first partial metal layer (251) can be formed by a physical dry method. The first partial metal layer (251) can be formed by a physical dry method using sputtering when the first metal layer (330) is not formed on the first interlayer insulating layer (230). Alternatively, the first partial metal layer (251) can be formed using the Crimson Process. The first partial metal layer (251) can be formed by a chemical wet method. When the first metal layer (330) is formed on the first interlayer insulating layer (230), the first partial metal layer (251) can be formed by a chemical wet method using the Crimson Process. The Crimson Process refers to a method of direct plating of a metal (e.g., copper).

[0101] Here, an insulating layer may be included between the first interlayer insulating layer (230) and the first metal layer (330), and the first partial metal layer (251) may be formed to include a portion that becomes the inner wall of the first via hole (350) in the first insulating layer.

[0102] The second partial metal layer (252) can be formed using a different method than the first partial metal layer (251). The second partial metal layer (252) can be formed using a plating method. The second partial metal layer (252) can be formed using electrolytic plating or electroless plating.

[0103] When the second circuit connection layer (260) is formed with a plurality of layered structures, it may be formed to include a first partial metal layer (251) and a second partial metal layer (252). When the second circuit connection layer (260) is formed to include the first partial metal layer (251) and the second partial metal layer (252), the method described with reference to FIGS. 14 and FIGS. 15 may also be applied to the second circuit connection layer (260). Both the first circuit connection layer (250) and the second circuit connection layer (260) may be formed with a plurality of layered structures, but it is also possible for only one of the circuit connection layers, either the first circuit connection layer (250) or the second circuit connection layer (260), to be formed with a plurality of layered structures. The first partial metal layer (251) and the second partial metal layer (252) may be made of an electrically conductive material. The first partial metal layer (251) and the second partial metal layer (252) may be formed by including equivalent conductive metals, but the present embodiment is not necessarily limited thereto. The second partial metal layer (252) may be made of any one or more metals selected from conductive metals including copper (Cu), gold (Au), and aluminum (Al). Alternatively, the second partial metal layer (252) may have at least one metal component equivalent to the second circuit layer (220).

[0104] Meanwhile, the first circuit connection layer (250) and the second circuit connection layer (260) may be formed simultaneously, but it is also possible for one circuit connection layer selected from the first circuit connection layer (250) and the second circuit connection layer (260) to be formed before the other circuit connection layer.

[0105] Referring again to Fig. 1, the explanation will be provided.

[0106] After forming circuit connection layers (250, 260) on each side (210a, 210b) of the core layer (210), a first circuit layer and a third circuit layer are formed on the first metal layer (330) and the third metal layer (340), respectively (S150). The first metal layer (330) may be provided as a base for forming the first circuit layer. The third metal layer (340) may be provided as a base for forming the third circuit layer.

[0107] Referring to FIG. 16, a first circuit layer (270) may be formed on a first metal layer (330). The first circuit layer (270) may be electrically connected to a first circuit connection layer (250) through the first metal layer (330). The first circuit layer (270) may be electrically connected to a second circuit layer (220) through the first circuit connection layer (250). The first circuit layer (270) may be formed after the first circuit connection layer (250) is formed. However, it is not limited thereto, and it is also possible for the first circuit layer (270) to be formed simultaneously with the first circuit connection layer (250). Specifically, the first circuit layer (270) may be formed simultaneously with the second partial metal layer (252). The first circuit layer (270) may be formed integrally with the second partial metal layer (252). The first circuit layer (270) can be formed using a material of the same type as the second partial metal layer (252).

[0108] Likewise, the third circuit layer (280) may be formed on the third metal layer (340). The third circuit layer (280) may be electrically connected to the second circuit connection layer (260) through the third metal layer (340). The third circuit layer (280) may be electrically connected to the second circuit layer (220) through the second circuit connection layer (260). The third circuit layer (280) may be electrically connected to the first circuit layer (270) through the first circuit connection layer (250) and the second circuit connection layer (260). The third circuit layer (280) may be formed after the second circuit connection layer (260) is formed. However, it is not limited thereto, and it is also possible for the third circuit layer (280) to be formed simultaneously with the second circuit connection layer (260). Specifically, the third circuit layer (280) can be formed simultaneously with the second partial metal layer (252) within the second circuit connection layer (260).

[0109] Meanwhile, a fourth circuit layer may be included on the second surface (210b) of the core layer (210), and the third circuit layer (280) may be electrically connected to the fourth circuit layer through the second circuit connection layer (260). FIG. 16 is a first example diagram for explaining the product structure at step S150 of the method for manufacturing a multilayer circuit board.

[0110] The first circuit layer (270) and the third circuit layer (280) can be formed using equivalent methods. The first circuit layer (270) and the third circuit layer (280) can be formed using an etching method. For example, the first circuit layer (270) and the third circuit layer (280) can be formed using photo etching. The first circuit layer (270) and the third circuit layer (280) may also be formed using plating methods such as additive, semi-additive, or printing. However, they are not limited thereto, and the first circuit layer (270) and the third circuit layer (280) may also be formed using different methods. The first circuit layer (270) and the third circuit layer (280) may be formed using any one of these methods. Alternatively, the first circuit layer (270) and the third circuit layer (280) may be formed by mixing multiple methods.

[0111] The first circuit layer (270) and the third circuit layer (280) may be formed simultaneously. However, this is not limited thereto, and it is also possible for any one circuit layer selected from the first circuit layer (270) and the third circuit layer (280) to be formed before the other circuit layer. The first circuit layer (270) and the third circuit layer (280) may be formed by including a conductive metal equivalent to that of the second circuit layer (220), but the present embodiment is not necessarily limited thereto.

[0112] Referring to FIG. 17, the first circuit layer (270) and the third circuit layer (280) may be formed by processing the first metal layer (330) and the third metal layer (340). The first metal layer (330) may be formed relatively thicker than when provided as a seed layer. Likewise, the second metal layer (340) may also be formed relatively thicker than when provided as a seed layer. FIG. 17 is a second example diagram for explaining the product structure at step S150 of the method for manufacturing a multilayer circuit board.

[0113] Referring again to Fig. 1, the explanation will be provided.

[0114] When two circuit layers (270, 280) are formed on each side (210a, 210b) of the core layer (210), a protective layer can be formed thereon (S160). Referring to FIG. 18, a first protective layer (410) can be formed on the first circuit layer (270). Additionally, a second protective layer (420) can be formed on the third circuit layer (280). FIG. 18 is an example diagram for explaining the product structure at step S160 of the manufacturing method of a multilayer circuit board (500).

[0115] The first protective layer (410) can cover the first circuit layer (270). The first protective layer (410) can protect the first circuit layer (270). The first protective layer (410) can cover a portion of the first circuit layer (270), but is not limited thereto and can also cover the entire first circuit layer (270). The portion of the first circuit layer (270) that is not covered by the first protective layer (410) may be provided as at least one lead among an inner lead and an outer lead. If the first circuit layer (270) is provided as an inner lead, the multilayer circuit board (500) can be electrically connected to a semiconductor chip. If the first circuit layer (270) is provided as an outer lead, the multilayer circuit board (500) can be electrically connected to an external electronic device. The multilayer circuit board (500) may not include at least one of the first protective layer (410) and the second protective layer (420).

[0116] The first protective layer (410) may cover the first circuit layer (270) entirely. For example, the first protective layer (410) may cover both the top surface and the side surface of the first circuit layer (270). However, it is not limited thereto, and the first protective layer (410) may also partially cover the first circuit layer (270). For example, the first protective layer (410) may cover only the top surface of the first circuit layer (270).

[0117] The second protective layer (420) may cover the third circuit layer (280) to protect the third circuit layer (280). The second protective layer (420) may cover a portion of the third circuit layer (280) so that it can be provided as an inner lead and / or an outer lead, but the present embodiment is not limited thereto. Additionally, the second protective layer (420) may cover the third circuit layer (280) entirely, but it is also possible to cover the third circuit layer (280) partially.

[0118] The first protective layer (410) and the second protective layer (420) may be made of an insulating material. The first protective layer (410) and the second protective layer (420) may be formed using various methods such as printing, bonding, coating, and photolithography. When the first protective layer (410) and the second protective layer (420) are formed using printing, coating, etc., they may be formed by printing or coating a liquid solder resist. When the first protective layer (410) and the second protective layer (420) are formed using bonding, etc., they may be formed by bonding a coverlay film in a lamination manner. The first protective layer (410) and the second protective layer (420) may be formed using equivalent methods, but the present embodiment is not necessarily limited thereto.

[0119] The first metal layer (330) and the third metal layer (340) may be provided as seed layers for forming the first circuit layer (270) and the third circuit layer (280) thereon. Alternatively, the first metal layer (330) and the third metal layer (340) may be processed to form the first circuit layer (270) and the third circuit layer (280). In manufacturing a multilayer circuit board, it is desirable to increase the bonding properties of the first metal layer (330) and the third metal layer (340).

[0120] To increase the bonding between the two metal layers (330, 340), a heat treatment process may be added. Referring to FIG. 19, the heat treatment process (S125) may be performed after forming the first interlayer insulating layer (230), the first metal layer (330), the second interlayer insulating layer (240), and the third metal layer (340). The heat treatment process (S125) may be performed before forming the first via hole (350) and the second via hole (360). The heat treatment process (S125) may be performed between step S120 and step S130. FIG. 19 is a second flowchart for explaining step-by-step a method for manufacturing a multilayer circuit board according to some embodiment of the present invention.

[0121] Referring to FIG. 20, the heat treatment process (S125) may be provided on the first surface (210a) of the core layer (210). Additionally, the heat treatment process (S125) may be provided on the second surface (210b) of the core layer (210). The heat treatment process (S125) can improve both the bonding properties of the first metal layer (330) and the bonding properties of the third metal layer (340). However, it is not limited thereto, and the heat treatment process (S125) may also be provided on only one of the two surfaces (210a, 210b) of the core layer (210). FIG. 20 is an illustrative diagram for explaining a product production method at step S125 of a method for manufacturing a multilayer circuit board.

[0122] Although not illustrated in the drawings, a heat treatment process may also be provided after forming the first circuit layer (270). If the first partial metal layer (251) is formed using sputtering, a heat treatment process may be added after forming the first circuit layer (270). The heat treatment process may be performed between steps S150 and S160. The heat treatment process may improve the interfacial bonding between the first partial metal layer (251) and the second partial metal layer (252).

[0123] Likewise, if the second circuit connection layer (260) includes a first partial metal layer (251) and a second partial metal layer (252), and the first partial metal layer (251) is formed using sputtering, a heat treatment process may be provided after forming the third circuit layer (280).

[0124] If the first circuit layer (270) and the third circuit layer (280) do not have sufficient thickness when formed according to an etching or plating method, they may not function properly as circuits. Additionally, the thickness of the first circuit layer (270) and the third circuit layer (280) may not be uniform depending on the method. A process for forming a plating layer may be added.

[0125] Referring to FIG. 21, the plating layer formation process (S155) may be performed after forming the first circuit layer (270) and the third circuit layer (280). The plating layer formation process (S155) may be performed before forming the first protective layer (410) and the second protective layer (420). The plating layer formation process (S155) may be performed between step S150 and step S160. FIG. 21 is a third flowchart for explaining step-by-step a method for manufacturing a multilayer circuit board according to some embodiment of the present invention.

[0126] Referring to FIG. 22, the first plating layer (430) can cover the first circuit layer (270). The first plating layer (430) can cover the first circuit layer (270) entirely, but is not limited thereto, and it is also possible to cover the first circuit layer (270) partially. For example, in the former case, the first plating layer (430) can cover the upper surface and side surface of the first circuit layer (270), and in the latter case, the first plating layer (430) can cover only the upper surface of the first circuit layer (270). Likewise, the second plating layer (440) can cover the third circuit layer (280). The second plating layer (440) can cover the third circuit layer (280) entirely, but is not limited thereto, and it is also possible to cover the third circuit layer (280) partially. FIG. 22 is an example diagram illustrating the product structure at step S155 of the manufacturing method of a multilayer circuit board.

[0127] The first plating layer (430) and the second plating layer (440) may be made of an electrically conductive material. For example, the first plating layer (430) and the second plating layer (440) may be formed from any one metal selected from conductive metals such as tin (Sn), gold (Au), chromium (Cr), nickel (Ni), and silver (Ag), or may be formed by alloying multiple metals selected from said conductive metals. The first plating layer (430) and the second plating layer (440) may be formed by including a conductive metal equivalent to that of the first circuit layer (270) and the third circuit layer (280), but the present embodiment is not necessarily limited thereto. The first plating layer (430) and the second plating layer (440) may be formed simultaneously, but it is acceptable for any one of the first plating layer (430) and the second plating layer (440) to be formed before the other plating layer.

[0128] Next, a method for manufacturing a circuit board with four or more layers will be described. Below, the explanation of parts that overlap with the method for manufacturing a three-layer circuit board will be omitted, and only the parts that differ will be explained.

[0129] When manufacturing a 3-layer circuit board, a second circuit layer (220) may be formed on a first surface (210a) of a core layer (210), a first circuit layer (270) may be formed on the second circuit layer (220), and a third circuit layer (280) may be formed on a second surface (210b) of the core layer (210). When manufacturing a 4-layer circuit board, a fourth circuit layer may be added below the third circuit layer (280). That is, a fourth circuit layer may be formed on the other surface (210b) of the core layer (210), and a third circuit layer (280) may be formed on the fourth circuit layer. The fourth circuit layer may be electrically connected to the first circuit layer (270) and / or the second circuit layer (220) through a through hole penetrating the core layer (210).

[0130] The fourth circuit layer can be formed in the same manner as the second circuit layer (220). The fourth circuit layer can be formed simultaneously with the second circuit layer (220). Alternatively, the fourth circuit layer can be formed sequentially with the second circuit layer (220). The third circuit layer (280) and the fourth circuit layer can be formed symmetrically with respect to the first circuit layer (270) and the second circuit layer (220) with respect to the core layer (210). The fourth circuit layer is formed on the core layer (210), and the second interlayer insulation layer (240) can be formed to cover the fourth circuit layer.

[0131] A through hole can be formed by penetrating the core layer (210). A conductive electrode can be formed within the through hole. The conductive electrode can be formed from any one metal selected from conductive metals such as nickel (Ni), chromium (Cr), copper (Cu), gold (Au), aluminum (Al), and palladium (Pd). The conductive electrode can be formed from an alloy comprising a plurality of metals selected from the conductive metals. The conductive electrode can be formed by physical methods such as deposition, adhesion, or plating, or by chemical methods. The fourth circuit layer can be electrically connected to at least one of the first circuit layer (270) and the second circuit layer (220) through the conductive electrode formed within the through hole.

[0132] Although not provided in the drawings, if the second interlayer insulating layer (240) covers the fourth circuit layer, the third via hole is formed by penetrating the second interlayer insulating layer (240), and the third circuit connection layer can be filled within the third via hole using a conductive metal. The third circuit connection layer may be made of a material equivalent to the first circuit connection layer (250) and / or the second circuit connection layer (260). The third circuit connection layer may be formed in a manner equivalent to the first circuit connection layer (250) and / or the second circuit connection layer (260).

[0133] When manufacturing a circuit board with five or more layers, a method for manufacturing a three-layer circuit board or a method for manufacturing a four-layer circuit board may be utilized. When manufacturing a circuit board having an odd number of circuit layers, a method for manufacturing a three-layer circuit board may be utilized. For example, when manufacturing a five-layer circuit board, a fourth circuit layer may be formed on the first circuit layer (270), and a fifth circuit layer may be formed on the third circuit layer (280). The fourth circuit layer and the fifth circuit layer may be formed in a manner equivalent to that of the first circuit layer (270) and the third circuit layer (280).

[0134] When manufacturing a circuit board including an even number of circuit layers, a method for manufacturing a 4-layer circuit board may be utilized. For example, when manufacturing a 6-layer circuit board, a 5th circuit layer may be formed on the 1st circuit layer (270), and a 6th circuit layer may be formed on the 3rd circuit layer (280). The 5th circuit layer and the 6th circuit layer may be formed in a manner equivalent to that of the 1st circuit layer (270) and the 3rd circuit layer (280).

[0135] The above describes a method for manufacturing a multilayer circuit board and the structure of the multilayer circuit board formed step by step. A multilayer circuit board can be formed by first forming a second circuit layer (220) on a single-sided FCCL using an etching method, then stacking RCC on the surface and back surface respectively, and subsequently forming a blind via hole (BVH) to simultaneously connect the first circuit layer (270), the second circuit layer (220), and the third circuit layer (280), and then forming the first circuit layer (270) and the third circuit layer (280) using a plating method (e.g., a semi-additive method). The multilayer circuit board can be manufactured using a hybrid method that combines the etching method and the plating method. The multilayer circuit board can achieve a reduction in manufacturing processes and manufacturing costs.

[0136] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

[0137] The present invention may be applied to circuit boards and devices including the same. For example, the present invention may be applied to multilayer circuit boards or coil boards. For example, the present invention may be applied to chip-on-film installed in a display device.

Claims

1. Core layer; A second circuit layer formed on the first surface of the core layer; A first interlayer insulating layer covering the second circuit layer; A first circuit layer formed on the first interlayer insulating layer; A second interlayer insulating layer formed on the second surface of the core layer; and A multilayer circuit board comprising a third circuit layer formed on the second interlayer insulating layer.

2. In Paragraph 1, A multilayer circuit board further comprising an insulating portion provided between the first interlayer insulating layer and the first circuit layer, or between the second interlayer insulating layer and the third circuit layer.

3. In Paragraph 1, A multilayer circuit board further comprising a fourth circuit layer formed on the second surface of the core layer.

4. In Paragraph 1, A multilayer circuit board further comprising a seed layer provided between the first interlayer insulating layer and the first circuit layer, or between the second interlayer insulating layer and the third circuit layer.

5. In Paragraph 1, A multilayer circuit board in which at least one of the first interlayer insulating layer and the second interlayer insulating layer is made of a material of a different type from the core layer.

6. In Paragraph 1, A multilayer circuit board in which the thickness of the second interlayer insulating layer is equal to or thicker than the spacing distance between the first circuit layer and the second circuit layer.

7. In Paragraph 1, A first via hole connecting the first circuit layer and the second circuit layer; and A multilayer circuit board further comprising a first circuit connection layer formed within the first via hole.

8. In Paragraph 1, A second via hole connecting the second circuit layer and the third circuit layer; and A multilayer circuit board further comprising a second circuit connection layer formed within the second via hole.

9. In Paragraph 7, The above first circuit connection layer is, First partial metal layer; and It includes a second partial metal layer surrounding the first partial metal layer, and The second partial metal layer is formed to fill the space surrounded by the first partial metal layer, or The above second partial metal layer is a multilayer circuit board formed integrally with the above first circuit layer.

10. In Paragraph 7, The second circuit layer above includes a groove, and The first circuit connection layer is extended to fill the groove, and The above groove is a multilayer circuit board formed when removing a conductive layer formed on the surface of the second circuit layer.

11. In Paragraph 2, A multilayer circuit board in which the insulating portion and the first metal layer serving as a base for forming the first circuit layer are integrally provided.

12. A step of forming a second circuit layer on the first surface of the core layer; A step of forming a first interlayer insulating layer and a first metal layer on the second circuit layer; A step of forming a first via hole that penetrates the first interlayer insulating layer and the first metal layer, while exposing at least a portion of the second circuit layer; A step of forming a first partial metal layer within the first via hole; A step of forming a second partial metal layer within the first via hole; and A method for manufacturing a multilayer circuit board comprising the step of forming a first circuit layer based on the first metal layer.

13. In Paragraph 12, A step of forming a second interlayer insulating layer and a second metal layer on the second surface of the core layer; A step of forming a second via hole that penetrates the core layer, the second interlayer insulating layer, and the second metal layer, while exposing at least a portion of the second circuit layer; A step of forming the first partial metal layer within the second via hole; A step of forming the second partial metal layer within the second via hole; and A method for manufacturing a multilayer circuit board, further comprising the step of forming a third circuit layer based on the second metal layer.

14. In Paragraph 12, A step of forming a fourth circuit layer on the second surface of the core layer; A step of forming a second interlayer insulating layer and a second metal layer on the fourth circuit layer; A step of forming a third via hole that penetrates the second interlayer insulating layer and the second metal layer, while exposing at least a portion of the fourth circuit layer; A step of forming the first partial metal layer within the third via hole; A step of forming the second partial metal layer within the third via hole; and A method for manufacturing a multilayer circuit board, further comprising the step of forming a third circuit layer based on the second metal layer.

15. In Paragraph 12, An insulating portion is further included between the first interlayer insulating layer and the first metal layer, or A method for manufacturing a multilayer circuit board comprising a seed layer further comprising the first interlayer insulating layer and the first circuit layer.

16. In Paragraph 13, The first circuit layer and the third circuit layer are formed simultaneously, or A method for manufacturing a multilayer circuit board in which the first circuit layer or the third circuit layer is simultaneously formed integrally with the second partial metal layer.

17. In Paragraph 12, The step of forming the first partial metal layer is, A hole conduction step of forming a first partial metal layer on the surface of the first metal layer, the first via hole, and the second circuit layer; and A method for manufacturing a multilayer circuit board comprising a micro-etching step of etching a portion of the first metal layer and the second circuit layer to remove a first partial metal layer formed on the surface of the first metal layer and the second circuit layer.

18. In Paragraph 17, The thickness of the first metal layer etched by the above micro-etching is 0.5㎛ or more and 3.0㎛ or less, and A method for manufacturing a multilayer circuit board in which the thickness of the first metal layer after the etching step is 0.1 μm or more and 2.0 μm or less.

19. A multilayer circuit board manufactured by the manufacturing method according to claim 12.

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