Electronic semiconductor component, and method for manufacturing pre-processed composite substrate for electronic semiconductor component

Abstract

To provide high-performance, high-quality electronic semiconductor components.SOLUTION: An electronic semiconductor component (50) includes a crystal (53) made of single-crystal SiC, the orientation of at least some subareas of a first surface (58) of a SiC crystal (52) extends substantially perpendicular to the c-direction (c) of the crystal structure of the crystal (53). The manufacturing process is also disclosed.SELECTED DRAWING: Figure 19

Description

[Technical Field]

[0001] The present invention relates to electronic semiconductor components and methods for making pre-processed composite substrates for electronic semiconductor components.

[0002] Discrete high-blocking power semiconductor components with nominal blocking voltages above 600V are typically constructed vertically in both silicon and SiC. What this means for diodes, i.e., MPS (merged pin Schottky) diodes, Schottky diodes, or pn diodes, is that the cathode is located on the front side of the substrate and the anode on the back side of the substrate. A similar configuration can be applied for vertical power MOS (metal-oxide semiconductor) components. The gate and source electrodes are on the front side of the substrate, and the drain electrode is on the back side of the substrate. The actual transistor element or channel region of a conventional power MOSFET can be located parallel to the surface (D-MOS) or perpendicular to the surface (trench MOS). SiC MOSFETs, e.g., trench transistors, have established specific structures.

[0003] The width of the drift zone (= active zone, voltage absorption layer) is adjusted depending on the required reverse blocking voltage. For example, the width of the drift zone of a 600V MOSFET component in silicon is about 50µm.

[0004] In the case of so-called superjunction components, the width of the voltage absorption layer may be slightly narrower compared to "simple" vertical MOSFETs. A special feature of this type of vertical component is that the drift zone is characterized by an alternating arrangement of vertical p-doped and n-doped columns. The additional p-doping introduced in the blocking case compensates for the elevated charge of the n-doped region, which determines the resistance between the source and drain electrodes in the on-state. Thus, for the same blocking capability, the on-resistance can be reduced by approximately up to a factor of 10 compared to conventional vertical MOS transistors. The actual transistor element, i.e. the channel region of a superjunction MOSFET architecture, can be arranged parallel to the surface (D-MOS) or perpendicular to the surface (trench MOS).

[0005] The specific material properties of SiC for vertical power semiconductor components require the provision of specific manufacturing methods and the use of specific architectures for the channel and transistor regions.

[0006] Typically, the active zone of all vertical power diodes or all power transistors (MOSFETs and J-FETs) is formed in a single-crystalline epitaxial layer. These epitaxial layers are formed or deposited on a crystalline carrier wafer. This means that the doping and vertical extent (thickness) of the active epitaxial zone can be adapted to the respective blocking voltage, and the highly doped carrier wafer can be optimized with respect to doping to minimize its contribution to the on-resistance.

[0007] Fabricating the aforementioned layer structure is complex and expensive, especially for SiC substrates, due to the enormous costs involved in depositing the epitaxial layers and preparing the monocrystalline carrier wafer. Furthermore, in this fabrication method, the wafer surface is oriented at a 4° angle relative to the perpendicular c-direction of the crystal structure. This, firstly, increases complexity and, secondly, degrades the performance of many structural elements of semiconductor components incorporated into the wafer, particularly the channel region, Schottky junction, or switching pn junction. For example, a 4° tilt reduces charge carrier mobility. In the case of trench MOSFETs, this necessitates the implementation of non-perpendicular trenches (4° deviation) to compensate for or optimize the reduced charge carrier mobility of the MOS channel. For planar MOS transistors, where the channel region extends parallel to the wafer surface, a 4° deviation from the optimal (0001) plane of the channel region, including the associated charge carrier mobility degradation, is generally accepted because no feasible technical remedy is available.

[0008] DE 10 2019 112 985 A1 proposes as an alternative to producing semiconductor components without epitaxial deposition by cleaving the substrate from a SiC wafer and subsequently ion implanting it into the drift zone using an energy filter.

[0009] The present invention aims to provide high performance, high quality electronic semiconductor components that can be manufactured industrially with reduced complexity and cost. A corresponding method for manufacturing a pre-processed composite substrate for electronic semiconductor components is also provided.

[0010] This object is achieved by the features of the independent claims 1 and 30. Advantageous configurations are the subject matter of the dependent claims.

[0011] The electronic semiconductor component of the present invention is preferably a vertical semiconductor component, more preferably a high-blocking vertical semiconductor component, and has a crystal made of single-crystal SiC, wherein the orientation of at least a subsection of a first surface of the crystal made of SiC deviates from a direction perpendicular to the c-direction of the crystal structure of the crystal by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably no deviation.

[0012] In this way, the performance of the semiconductor component is optimized.

[0013] In general, the following nomenclature applies: The C-face (carbon termination) of the crystal structure and the Si-face (silicon termination) of the crystal structure are aligned perpendicular to the c-direction of the crystal structure. ·The (0001) plane of the crystal structure TIFF2025156404000002.tif8162 planes are aligned perpendicular to the c direction of the crystal structure.

[0014] Each surface or plane defined herein as extending in a direction perpendicular to the c-direction extends either within the C-face (carbon terminated) of the crystal structure or within the Si-face (silicon terminated) of the crystal structure. Each surface or plane defined herein as extending in a direction perpendicular to the c-direction extends either within the (0001) plane of the crystal structure or within the Si-face (silicon terminated) of the crystal structure. TIFF2025156404000003.tif8162 extends within the plane.

[0015] Correspondingly, each surface or plane defined herein as extending in a direction parallel to the c-direction extends perpendicular to the C-face (carbon termination) of the crystal structure and perpendicular to the Si-face (silicon termination) of the crystal structure. Similarly, each surface or plane defined herein as extending in a direction parallel to the c-direction extends perpendicular to the (0001) and (0002) faces of the crystal structure. TIFF2025156404000004.tif9162 Extends perpendicular to the surface.

[0016] In particular, in the case of the first surface of a crystal, at least a subsection thereof is formed by the crystal structure It is placed either on the C-face (carbon-terminated) of TIFF2025156404000005.tif8162 or on the Si-face (silicon-terminated) of the (0001) crystal structure.

[0017] A second surface of the generally continuous crystal opposite the first surface of the SiC crystal is similarly deviated from perpendicular to the c-direction of the crystal structure of the crystal by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably not at all.

[0018] In a particularly preferred configuration, the electronic semiconductor component comprises: a first zone having a near-surface shield structure or a JFET structure in a region including at least a subsection of a first surface of the crystal; a second zone adjacent to the first zone and located on a side of the first zone remote from the first surface of the crystal, the second zone having a voltage absorption layer; a field-free contact zone or field-stop zone arranged on a side of the voltage absorption layer remote from the first zone; The active component region includes:

[0019] Preferably, at least subregions of the second zone, and preferably the entire second zone, are doped. These subregions or the entire second zone are doped with a dopant concentration of 1E15 cm -3 From 5E17cm -3 It is preferably p-doped or n-doped with a dopant concentration of 0.1 to 0.5.

[0020] Preferably, the second zone is doped with one of the elements nitrogen, phosphorus, boron, or aluminum.

[0021] At least a sub-region of the first zone is preferably doped.

[0022] Preferably, at least these sub-regions of the first zone are doped with one of the elements nitrogen (N), phosphorus (P), boron (B) or aluminum (Al). Preferably, the first and second zones are doped with the same type of ions.

[0023] The first and second zones are preferably formed based on crystals consisting essentially of SiC.

[0024] The thickness of the first zone is preferably between 0.5 μm and 3.0 μm.

[0025] The thickness of the second zone is preferably between 2 μm and 50 μm, more preferably between 3 μm and 25 μm, particularly preferably between 3 μm and 15 μm.

[0026] The dopant concentration of the n-doped region of the first zone is preferably higher than the dopant concentration of the n-doped region of the second zone facing the first zone, preferably 1.5 to 100 times higher, more preferably 2 to 10 times higher.

[0027] The dopant concentration of the p-doped region of the first zone is preferably higher than the dopant concentration of the n-doped region of the second zone facing the first zone, preferably 2 to 1000 times higher, more preferably 50 to 1000 times higher.

[0028] In one configuration, the second zone, beginning from the first zone, has a substantially constant dopant depth profile in a direction toward the field-free contact zone or field-stop zone.

[0029] Alternatively, the second zone proceeding in a direction from the first zone towards the field-free contact zone or field-stop zone can have a step-like rising dopant depth profile, wherein the step is formed in the region of the second zone facing the field-free contact zone or field-stop zone up to 40%, preferably up to 30%, of the total depth of the second zone.

[0030] In this case, the difference in concentration between the highest and lowest step is preferably at least 10-fold, preferably at least 100-fold, more preferably at least 500-fold, particularly preferably at least 1000-fold.

[0031] In a step-like doping profile, the depth extent of the side regions of the steps preferably dominates over the depth extent of the step plateau.

[0032] In a further preferred alternative, the second zone, starting from the first zone, has a dopant depth profile that rises continuously in a direction towards the field-free contact zone or field-stop zone.

[0033] The continuously increasing dopant depth profile of the second zone is preferably a profile according to the following formula: TIFF2025156404000006.tif23162 where, D max is the maximum dopant concentration, α is a value between 10 and 10,000, z is the distance from the first zone; b is the thickness of the second zone; f is the tolerance factor between 0.95 and 1.05, D0 is the background doping. where: TIFF2025156404000007.tif13162 where, E max is the maximum field, ε r is the relative permittivity of the semiconductor, ε0 is the dielectric constant in a vacuum, e0 is the elementary charge of an electron, V br is the breakthrough voltage. And here, TIFF2025156404000008.tif13162

[0034] The aforementioned step-like or continuously rising dopant profile takes two aspects into account: first, it provides an optimal compromise between on-resistance and a given voltage stability; second, the dopant profile has a very high concentration towards the field-free contact or field-stop zone, so field punch-through is virtually eliminated.

[0035] In one embodiment, there is an overlap region of the dopant depth profiles at the junction between the first and second zones. The two dopant depth profiles preferably have overlapping, sloping downward flanks. The combination of the two dopant depth profiles in the first and second zones may be a constant profile, a profile that rises stepwise toward the field-free contact zone or field-stop zone, or a profile that rises continuously toward the field-free contact zone or field-stop zone.

[0036] Particularly preferred are profiles in which the dopant profile steps down from the first zone to the second zone, followed within the second zone by a constant profile, a stepwise rising profile towards the field-free contact zone or field-stop zone, or a profile that continuously rises towards the field-free contact zone or field-stop zone.

[0037] Preferably, the electronic semiconductor component has a (field-free) carrier substrate on the side of the field-free contact zone or field-stop zone remote from the first zone, and the crystal made of SiC is bonded to the carrier substrate by means of a permanent adhesive bond or bonded connection in the region of the field-free contact zone or field-stop zone.

[0038] The carrier substrate is preferably thermally stable up to at least 1500° C. and has a linear expansion coefficient that deviates from that of SiC by no more than 20%, preferably no more than 10%.

[0039] In a particularly preferred configuration, the carrier substrate is formed from polycrystalline SiC or graphite.

[0040] Alternatively, the electronic semiconductor component may be a free-standing thin layer based on a crystal of SiC without a carrier substrate.

[0041] In a preferred arrangement, the electronic semiconductor component is provided with an inactive edge region that substantially completely surrounds the first and second zones in all lateral directions.

[0042] In one configuration, the edge region is substantially undoped except for the presence of edge structures that reduce the electric field near the surface.

[0043] In an alternative configuration, the edge region is substantially undoped from the first surface, except for any near-surface field-reducing edge structures present, and is provided with the same dopant concentration as the second zone or a lower dopant concentration than the second zone, from substantially the depth where the second zone begins to the depth where the field-free contact zone or field-stop zone exists, preferably at least 20% lower, more preferably at least 50% lower.

[0044] Preferably, the field-free contact zone or field-stop zone has a vertical thickness of 2 μm or less, preferably 1 μm or less.

[0045] Preferably, the single crystal SiC is of the hexagonal 4H or 6H polytype.

[0046] Preferably, the crystal is made of high-purity, high-quality semi-insulating SiC material, with HT-CVD (High Temperature Chemical Vapor Deposition) material being preferred here.

[0047] In the preferred configuration, the A-face of the crystal TIFF2025156404000009.tif8162 deviates from normal to the first surface of the crystal by less than 0.5°, more preferably less than 0.3°, even more preferably less than 0.1°, and most preferably not at all.

[0048] In a preferred arrangement, the electronic semiconductor component is a trench MOSFET, and the channel region is offset from the c-direction of the crystallographic structure of the crystal by less than 0.5°, more preferably less than 0.3°, even more preferably less than 0.1°, and most preferably not at all.

[0049] Alternatively or additionally, in the case of a configuration as a trench MOSFET, it is preferred that the channel region is arranged substantially perpendicular to the first surface of the crystal.

[0050] In the latter case, it is also preferred that the channel region be located on the A-plane of the crystal.

[0051] In an alternative preferred configuration, the electronic semiconductor component is a planar MOSFET, and the channel region is offset from perpendicular to the c-direction of the crystallographic structure of the crystal by less than 0.5°, more preferably less than 0.3°, even more preferably less than 0.1°, and most preferably not at all.

[0052] Alternatively or additionally, when configured as a planar MOSFET, the channel region preferably extends parallel to the first surface of the crystal.

[0053] In yet another preferred configuration, the electronic semiconductor component is an MPS (merged PIN Schottky) diode, and the plane parallel to the Schottky junction deviates from a direction perpendicular to the c-direction of the crystal structure of the crystal by less than 0.5°, more preferably less than 0.3°, even more preferably less than 0.1°, and most preferably not at all.

[0054] Alternatively or additionally, in the case of the configuration as an MPS diode, it is preferred that the plane of the Schottky junction is arranged parallel to the first surface of the crystal.

[0055] In yet another preferred configuration, the electronic semiconductor component is a JFET transistor (junction field effect transistor), and one or each p + The interface at the -n junction deviates from a direction parallel to the c-direction of the crystal structure of the crystal by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably not at all.

[0056] In yet another preferred configuration, the electronic semiconductor component is a JFET transistor, and one or each p + The interface at the -n junction deviates from perpendicular to the c-direction of the crystal structure of the crystal by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably not at all.

[0057] According to the present invention, a method for producing a pretreated composite substrate, which serves as a basis for further processing into an electronic semiconductor component and comprises an acceptor substrate and a first section of a donor substrate having at least one doped layer, comprises the steps of: a) providing a donor substrate comprising single crystal SiC; b) doping the first layer of the donor substrate by ion implantation using an energy filter, the energy filter being a microstructured film having a predetermined structural profile for adapting a dopant depth profile resulting from implantation into the first layer of the donor substrate, the doping creating a predetermined dopant depth profile in the first layer of the donor substrate, the first layer extending from an outer surface of the donor substrate facing the ion beam to the predetermined dopant depth and subsequently extending into the remainder of the donor substrate; c) creating an intended breakage site in the donor substrate that extends substantially parallel to an outer surface of the donor substrate; d) providing an acceptor substrate and producing a bond between the donor substrate and the acceptor substrate, wherein the first layer is disposed in the area between the acceptor substrate and the remainder of the donor substrate; e) splitting the donor substrate in the region of the intended breakage site to produce a pre-processed composite substrate, the pre-processed composite substrate comprising an acceptor substrate and a first section of the donor substrate connected thereto and having at least one doped layer, the doped layer constituting at least a part of the first layer of the donor substrate, the splitting being performed so that the first section of the donor substrate has a first surface facing away from the acceptor substrate in the region of the intended breakage site of the composite substrate, deviating from a direction perpendicular to the c-direction of the crystal structure of the first section of the donor substrate by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably not at all; It has.

[0058] The first layer is always composed of single crystal SiC. The donor substrate is preferably made entirely of single crystal SiC.

[0059] The thickness of the first layer is preferably 3 to 15 μm, as ion implantation can be carried out over a thickness of this order of magnitude.

[0060] In a preferred embodiment, the donor substrate is a crystal of high-purity, high-quality, single-crystal, semi-insulating SiC material, particularly with elemental impurities, particularly N, B, and P, with concentrations of primarily 5E15 cm -3 "Predominantly" in this context means that the criteria are applicable to substantially the entire depth profile, but deviations may exist in certain regions, e.g., at the surface. HT-CVD (High Temperature Chemical Vapor Deposition) materials are preferred here.

[0061] In a preferred embodiment, the donor substrate is composed of 4H, 6H, or 3C polytypes of SiC, which have been found to be advantageous for the fabrication of semiconductor components.

[0062] Preferably, the outer surface of the donor substrate facing the ion beam deviates from a direction perpendicular to the c-direction of the crystal structure of the donor substrate by less than 0.5°, more preferably less than 0.3°, even more preferably less than 0.1°, and most preferably not at all. A particular advantage of the substantially 0° case is that the donor substrate can be cut parallel to the outer surface, thereby obtaining many more individual wafers from one cylinder.

[0063] The donor substrate preferably has a thickness of more than 100 μm, preferably more than 200 μm, more preferably more than 300 μm, up to 15 cm, more preferably up to 10 cm.

[0064] Generally, the doping of the first layer is such that the dopant concentration or defect concentration in the first layer is 1E15 cm -3 From 5E17cm -3 It is preferable to provide a p- or n-doping of 0.01%. This dopant or defect concentration is well suited for the drift zone (active layer, power absorption layer) of many high-performance components. The doping can be constant throughout the thickness of the first layer or can exhibit a different doping profile.

[0065] The first layer is preferably doped with ions of one of the elements nitrogen, phosphorus, boron or aluminum.

[0066] The primary energy range of the ion beam for doping the first layer is preferably between 1 MeV and 50 MeV.

[0067] In a preferred embodiment, the doping of the first layer results in a constant or substantially constant dopant depth profile, which is understood to mean a profile that deviates from a perfectly flat dopant depth profile by less than 20%, preferably less than 10%. In practice, the plateau is flanked by descending flanks, i.e., the decline of the profile is not vertical or abrupt in the region of the doping depth.

[0068] In an alternative configuration, the doping of the first layer results in a dopant depth profile that descends in a step-like manner from the outer surface of the donor substrate facing the ion beam, the step being formed to face up to 40%, preferably up to 30%, of the total depth of the first layer in a region near the surface of the first layer facing the ion beam.

[0069] Here, the difference in concentration between the highest and lowest step is preferably at least 10-fold, preferably at least 100-fold, more preferably at least 500-fold, particularly preferably at least 1000-fold.

[0070] Here, the depth extent of the lateral regions of the steps dominates over the depth extent of the stepped plateau.

[0071] In an alternative configuration, the doping of the first layer results in a dopant depth profile that descends continuously from the outer surface of the donor substrate facing the ion beam.

[0072] Here, it is preferred that the continuously descending dopant depth profile is a profile according to the following formula: TIFF2025156404000010.tif22162 where, D max is the maximum dopant concentration, α is a value between 10 and 10,000, z is the distance from the outer surface, b is the thickness of the first layer, f is the tolerance factor between 0.95 and 1.05, D0 is the background doping, where: TIFF2025156404000011.tif13162 where, E max is the maximum field, ε r is the relative permittivity of the semiconductor, ε0 is the dielectric constant in a vacuum, e0 is the elementary charge of an electron, V br is the breakthrough voltage, And here, TIFF2025156404000012.tif14162

[0073] Generally, a further step of creating a contact layer on the surface region of the first layer or applying a contact layer to the outer surface of the first layer is preferred, wherein the bond between the donor substrate and the acceptor substrate is established via the contact layer, resulting in the following sequence: acceptor substrate, contact layer, remaining part of the first layer or first layer, remaining part of the donor substrate. This makes it possible to achieve a particularly good low-resistance connection between the donor substrate and the acceptor substrate.

[0074] The contact layer is preferably created by ion implantation.

[0075] The dopant concentration of the contact layer is preferably at least 100 times, preferably at least 1000 times, more preferably at least 10000 times, and even more preferably at least 100000 times higher than the average dopant concentration of the remainder of the first layer or the first layer, thereby providing a very low resistance bond and preventing field punch-through to the interface of the semiconductor component.

[0076] In a preferred configuration, the dopant concentration in the contact layer is 1E17 cm -3 Larger, preferably 1E19cm -3 Greater than.

[0077] The intended damage site is preferably within a region of the first layer, more preferably within an edge region of the first layer close to the predetermined doping depth, preferably 1 μm or less, so that a minimal amount of doped material remains on the donor substrate after splitting.

[0078] In an alternative configuration, the intended damage site is in the region of the remaining portion of the donor substrate, and further, after step e), a further step of performing ion implantation into the composite substrate is performed from the side away from the acceptor substrate. This has the advantage of forming an active zone with a greater total thickness. Since this allows for overlap between the two different implants, it is also possible to create different preferred dopant profiles or to create a preferred dopant profile in stages.

[0079] In connection with this alternative configuration, the ion implantation into the composite substrate preferably provides a dopant depth profile of the auxiliary doped layer that extends at least to the doped layer.

[0080] Ion implantation into the composite substrate can be performed such that the combined dopant depth profile of the doped and auxiliary doped layers is a constant profile, a stepwise increasing profile toward the acceptor substrate, or a continuous increasing profile toward the acceptor substrate, although other profile types are also possible.

[0081] The obliquely descending flanks in the transition region of the two dopant depth profiles of the doped layer and the auxiliary doped layer may overlap each other.

[0082] It is particularly preferred that the dopant concentration in the auxiliary doped layer is higher than in the region of the doped layer facing the auxiliary doped layer, preferably 1.5 to 100 times higher, more preferably 2 to 10 times higher. The dopant concentration in the doped layer may again have a constant profile, a profile that increases stepwise towards the acceptor substrate, or a profile that increases continuously towards the acceptor substrate.

[0083] Preferably, the intended damage site is created by ion implantation of split trigger ions.

[0084] The split trigger ions are preferably introduced across the entire width of the donor substrate to create a highly uniform split surface.

[0085] Alternatively, the split trigger ions may be introduced across only a portion of the width of the donor substrate, which reduces the complexity of the ion implantation.

[0086] It is preferred to introduce split trigger ions only into the edge region of the donor substrate.

[0087] In a preferred embodiment, the split trigger ion is selected from hydrogen (H or H2), helium (He), and boron (B).

[0088] In principle, it is advantageous if the split trigger ions are energetic ions with energies between 0.5 and 10 MeV, preferably between 0.5 and 5 MeV, more preferably between 0.5 and 2 MeV.

[0089] The particle dose of the split trigger ion is 1E15cm in each case. -2 and 5E17cm -2 This dose provides reliable fractionation.

[0090] The energy spread (ΔE / E) of the split trigger ion beam is preferably 10 -2 less than 10 -4 In this way, it is ensured that the intended damage site has a minimum thickness and that the ion energy loss peak at the intended damage site is very sharp.

[0091] Splitting of the donor substrate is preferably caused by heat treatment of the donor substrate at a temperature between 600° C. and 1300° C., preferably between 750° C. and 1200° C., more preferably between 850° C. and 1050° C. Alternatively, mechanical methods are also contemplated.

[0092] In a preferred embodiment, the bond is established by heat treating the composite substrate at a temperature between 800°C and 1600°C, preferably between 900°C and 1300°C.

[0093] This method is considered simplified in that both the establishment of the bond and the splitting of the donor substrate are achieved by thermal treatment, and both steps are performed simultaneously.

[0094] Preferably, the bonding step is preceded by a pretreatment of at least one, preferably both, of the surfaces to be bonded, in particular a wet chemical treatment, a plasma treatment or an ion beam treatment.

[0095] The acceptor substrate is preferably thermally stable up to at least 1500°C and has a linear expansion coefficient that deviates from that of SiC by 20% or less, preferably 10% or less, thereby effectively preventing bending of the composite substrate.

[0096] In a particularly preferred configuration, the acceptor substrate is formed from polycrystalline SiC or graphite.

[0097] Preferably, the dividing step is followed by post-treatment of the surface of the composite substrate in the region of the intended break side, in particular by polishing and / or removing (near-surface) defects.

[0098] In a preferred extension of this method, the implanted defects in the pretreated composite substrate are tempered at temperatures between 1500°C and 1750°C. This can be accomplished during the manufacture of the pretreated composite substrate, or only during subsequent further processing into electrical semiconductor components.

[0099] In a preferred extension of this method, the pretreated composite substrate is used to manufacture an electronic semiconductor component, preferably a vertical semiconductor component, more preferably a high-blocking vertical power semiconductor component, wherein further structural elements of the semiconductor component are introduced into or arranged on the first surface of the composite substrate from or on the first surface.

[0100] Examples of structural elements include active and passive regions of different doping (source, J-FET p-doped gate structure; MOSFET channel, shield region, pn junction, resurf edge region, source-gate contact region, J-FET channel region), insulating oxide, gate oxide, contact region (metal, silicide), Schottky contact (metal, alloy), ohmic contact, source-gate metallization or wire, passivation layer, trench for gate electrode, bonding pad, contact hole or contact trench.

[0101] In the context of this description, the first and second zones are described for the semiconductor component, and the doped layer and auxiliary doped layer are described for the preprocessed composite substrate. In the absence of an additional doped layer, the first zone may be formed together with the second zone solely from the doped layer of the composite substrate. Similarly, the first zone may be formed from the auxiliary doped layer, and the second zone may be formed from the doped layer. Finally, the doped layer and the auxiliary doped layer may be present in the composite substrate, but the boundary between the first and second zones of the semiconductor component is not at the junction between the doped layer and the auxiliary doped layer, but is within the doped layer or the auxiliary doped layer. [Brief explanation of the drawings]

[0102] FIG. 1 is a schematic cross-sectional view of a first configuration of a donor substrate that can be used in the method of the present invention.

[0103] FIG. 2 is a schematic diagram of an irradiation arrangement with an energy filter for irradiating a donor substrate.

[0104] FIG. 3 is a schematic diagram of an energy filtering mode that can be used in the method of the present invention.

[0105] FIG. 4 is a schematic illustration of the different doping profiles that can be produced by different energy filter configurations.

[0106] FIG. 5 is a schematic diagram of the doping profile of the first layer of the donor substrate and the resulting doping profile of the donor substrate.

[0107] FIG. 6 shows various options for the doping profile of the first layer of the donor substrate.

[0108] FIG. 7 shows a schematic diagram of the creation or application of a contact layer on a donor substrate.

[0109] FIG. 8 shows a schematic diagram of a first variant of creating an intended breakage site in a donor substrate.

[0110] FIG. 9 shows a schematic diagram of a second variation for creating an intended breakage site in a donor substrate.

[0111] FIG. 10 shows a schematic diagram of the formation of a bond between a donor substrate and an acceptor substrate.

[0112] FIG. 11 shows a schematic diagram of separating the remaining portion of the donor substrate from the composite substrate.

[0113] FIG. 12 shows a schematic diagram of the post-treatment of the surface of the composite substrate in the region of the split site.

[0114] FIG. 13 shows a schematic cross-sectional view of one embodiment of a pre-treated composite substrate according to the present invention.

[0115] FIG. 14 shows a cross-sectional view and corresponding dopant profile of a further embodiment of a pre-treated composite substrate according to the present invention.

[0116] FIG. 15 is a schematic diagram of the division of a wafer bar that serves as a donor substrate when used to create multiple composite substrates from the donor substrate.

[0117] FIG. 16 shows a schematic diagram of the doping profile of the first layer of the donor substrate using partial masking of the donor substrate and the resulting alternative doping profile of the donor substrate.

[0118] FIG. 17 shows a schematic cross-sectional view of an exemplary basic structure of a semiconductor component of the invention.

[0119] FIG. 18 shows a schematic cross-sectional view of another exemplary basic structure of a semiconductor component of the invention.

[0120] FIG. 19 shows a cross-sectional view of one embodiment of a semiconductor component of the invention in the form of a planar MOS transistor.

[0121] FIG. 20 shows a schematic diagram of a preferred dopant profile for a particular embodiment of the semiconductor component of the present invention.

[0122] FIG. 21 shows a schematic cross-sectional view of one embodiment of a semiconductor component of the present invention in the form of a vertical merge PIN Schottky diode.

[0123] FIG. 22 shows a schematic cross-sectional view of one embodiment of the semiconductor component of the present invention in the form of an alternative configuration of a vertical merged PIN Schottky diode.

[0124] FIG. 23 shows a schematic cross-sectional view of one embodiment of a semiconductor component of the invention in the form of a vertical trench MOSFET.

[0125] FIG. 24 shows a schematic cross-sectional view of an embodiment of a semiconductor component of the invention in the form of an alternative configuration of a vertical trench MOSFET.

[0126] FIG. 25 shows a schematic cross-sectional view of one embodiment of a semiconductor component of the invention in the form of a vertical superjunction MOSFET.

[0127] FIG. 26 shows a schematic diagram of a top view of the superjunction MOSFET of FIG.

[0128] FIG. 27 shows a schematic cross-sectional view of one embodiment of a semiconductor component of the invention in the form of a J-FET.

[0129] FIG. 28 shows a schematic cross-sectional view of an embodiment of a semiconductor component of the invention in the form of an alternative configuration of a J-FET.

[0130] The method of the present invention for producing a preprocessed composite substrate begins with providing a donor substrate 12 that includes or consists entirely of single crystal silicon carbide (SiC). See Figures 1 and 2.

[0131] The embodiment of donor substrate 12 shown in Figure 1 is a wafer composed of high-purity, high-quality semi-insulating SiC material. In particular, it has elemental impurities, e.g., N, B, P, with concentrations of 5E15 cm -3 "Predominantly" in this context means that the criteria are applicable to substantially the entire depth profile, but deviations may exist in certain regions, e.g., at the surface. HT-CVD (High Temperature Chemical Vapor Deposition) materials are particularly preferred.

[0132] The donor substrate 12 according to Figure 1 preferably has a thickness of more than 100 μm, preferably more than 200 μm, more preferably more than 300 μm, and up to 15 cm, preferably up to 10 cm. In particular, it may take the form of an undoped or weakly n-doped wafer bar, see Figure 15.

[0133] In a preferred embodiment, the donor substrate is composed of SiC of the 4H, 6H, or 3C polytype, which have been found to be advantageous for the properties of semiconductor components fabricated therewith.

[0134] In the illustrated embodiment, the outer surface of the donor substrate 12 has a deviation of 0° from normal to the c-direction. Thus, the outer surface is aligned with the (0001) plane of the crystal structure or TIFF2025156404000013.tif is on page 8162.

[0135] After the donor substrate 12 is prepared, a first layer 21 of the donor substrate is doped (see FIG. 5), which will subsequently assume or partially assume the function of at least the drift zone (also called the active zone or voltage absorption zone) in the finished component. This doping of the first layer 21 of the donor substrate 12 is carried out by ion implantation using an energy filter 20. The corresponding basic structure is shown in FIG.

[0136] 2 shows an irradiation chamber 8, which is typically in high vacuum. The irradiation chamber 8 contains a donor substrate 12 to be doped in a substrate holder 30.

[0137] An ion beam 10 is generated by a particle accelerator (not shown) and directed into irradiation chamber 8. The energy of ion beam 10 is diffused there by energy filter 20 before striking donor substrate 12 to be irradiated. Alternatively, energy filter 20 may be located within irradiation chamber 8 or in a separate, valved vacuum chamber immediately adjacent to irradiation chamber 8.

[0138] The substrate holder 30 does not need to be stationary and may optionally be equipped with a device for moving the donor substrate 12 in xy (in a plane perpendicular to the sheet surface). Another useful substrate holder 30 is a wafer wheel to which the donor substrate 12 to be implanted is fixed and which rotates during implantation. It is also possible to move the substrate holder 30 in the beam direction (z direction). Furthermore, the substrate holder 30 may be equipped with a heater or cooler, if necessary.

[0139] The basic principle of the energy filter 20 is illustrated in Figure 3. The energy of the monoenergetic ion beam 10 changes depending on the entry point as it passes through the energy filter 20, which is configured as a microstructured membrane. The resulting energy distribution of the ions of the ion beam 10 results in a modified depth profile of the implanted material within the matrix of the donor substrate 12. E1 denotes the energy of the first ion, E2 denotes the energy of the second ion, conc denotes the dopant concentration, and d denotes the depth within the donor substrate 12. The figure shows a typical Gaussian distribution, marked with reference A on the right, which would occur without the use of the energy filter 20. In contrast, reference B denotes, by way of example, a rectangular distribution that can be achieved with the use of the energy filter 20.

[0140] The layout or three-dimensional structure of energy filter 20 shown in Figure 4 illustrates basic options for creating multiple dopant depth profiles using energy filter 20. conc again denotes dopant concentration, and d again denotes depth within donor substrate 12. Filter structure profiles can, in principle, be combined with one another to obtain new filter structure profiles and thus new dopant depth profiles.

[0141] Such energy filters 20 are typically made of silicon. They have a thickness between 3 μm and 200 μm, preferably between 5 μm and 50 μm, and more preferably between 7 μm and 20 μm. They may be held in a filter frame (not shown). The filter frame may be replaceably housed in a filter holder (not shown).

[0142] For the preferred formation of an n-doped first layer 21, implantation of nitrogen or phosphorus ions is particularly suitable, while for a p-doped layer, implantation of boron or aluminum ions is particularly suitable.

[0143] In the example of the method step for doping the first layer 21 shown in FIG. 5 , ions are implanted into the donor substrate 12 from its front surface. Hereinafter, the surface of the donor substrate 12 facing the ion beam will be referred to as the outer surface 23. The short, solid black arrows indicate ions with the lowest energy passing through the energy filter 20, while the long, solid black arrows indicate ions with the highest energy passing through the energy filter 20. The resulting dopant profile in the A-A′ cross section is shown to the right of the coordinate system. Conc represents the dopant concentration. The dopant profile is based on the configuration of the donor substrate 12 according to FIG. 1 and is approximately uniform throughout the first layer 21. The first layer 21 extends from the outer surface 23 of the donor substrate 12 facing the ion beam 10 to a specific doping depth T, followed by the remaining portion 22 of the donor substrate 12, which is not affected by the ion implantation due to the energy filter.

[0144] The thickness of the first layer 21 preferably corresponds substantially to the predetermined thickness of the active layer in the subsequent semiconductor component, or substantially corresponds to the combination of the active layer and the field stop layer, or the combination of the active layer, the field stop layer and the superficial functional zone. The total thickness of the first layer 21 is therefore determined by the nature of the semiconductor component to be manufactured, in particular the voltage class. The higher the voltage class, the thicker the first layer 21. For particularly high voltage classes, see FIG. 14 and the accompanying description.

[0145] The thickness of the first layer 21 is preferably between 3 and 15 μm, which corresponds to the currently feasible doping depth T for the above-mentioned preferred ion types in SiC.

[0146] 6a to 6c show possible preferred dopant profiles in the first layer 21 of the donor substrate 12. FIG.

[0147] In principle, the doping of the first layer 21 is such that the dopant concentration (conc) or defect concentration in the first layer 21 is 1E15 cm -3 From 5E17cm -3This results in p or n doping.

[0148] FIG. 7 shows the result of an optional step of creating a contact layer 24 in the surface region of the first layer 21 or applying a contact layer 24 to the surface of the first layer 21 .

[0149] The contact layer 24 is preferably created by ion implantation into the first layer 24. The contact layer 24 has a thickness of only 10 nm to 1 μm. The implantation preferably uses P, N or Al ions (without an energy filter).

[0150] The dopant concentration in contact layer 24 is preferably at least 100 times, more preferably at least 1000 times, more preferably at least 10000 times, and even more preferably at least 100000 times higher than the average dopant concentration in the remainder of or within first layer 21.

[0151] The dopant concentration of the contact layer 24 is 1E17 cm -3 It is preferable that the thickness is more than 1E19cm. -3 It is more preferable to exceed

[0152] It is also possible to apply a thin contact layer 24, for example a few nanometers thick, to the first layer 21. This can be achieved, for example, by sputtering deposition, evaporation, or CVD deposition. The contact layer 24 does not need to be completely covering and can also consist of nanoparticles.

[0153] The application of the contact layer 24 may be accompanied by or followed by further treatment of the surface, such as physical etching.

[0154] In the next step, according to Fig. 8, an intended damage site 26 is created in the donor substrate 24. The intended damage site 26 is, in the example of Fig. 8, within the region of the first layer 21, preferably in an edge region of the first layer 21 close to the predetermined doping depth T, with the intended damage site 26 being away from the doping depth T and therefore preferably no more than 1 µm, more preferably no more than 500 nm, more preferably no more than 100 nm from the edge of the first layer 21. In particular, in the case of a rectangular profile with descending sides, the intended damage site 26 should still be within the region of the plateau.

[0155] The intended damage site 26 is preferably created by ion implantation of split trigger ions, shown schematically as black dots in FIG. 8. No energy filter is used here. According to FIG. 8, the split trigger ions are introduced across the entire width of the donor substrate 12. The split trigger ions are preferably selected from H, H, He, and B. The split trigger ions are high-energy ions having energies between 0.5 and 10 MeV, preferably between 0.5 and 5 MeV, and more preferably between 0.5 and 2 MeV. For hydrogen, an ion energy of 0.6 MeV results in the intended damage site 26 being formed to a depth of approximately 5 μm, an ion energy of 1.0 MeV results in the intended damage site 26 being formed to a depth of approximately 10 μm, and an ion energy of 1.5 MeV results in the intended damage site 26 being formed to a depth of approximately 20 μm.

[0156] The particle dose of the split trigger ion is 1E15cm in each case. -2 and 5E17cm -2 The energy spread (ΔE / E) of the ion beam of split trigger ions is preferably between 10 -2 less than 10 -4 In split-trigger ion implantation, it is advantageous to maintain the temperature within the donor substrate 12 below 300° C., preferably below 200° C. To this end, the chuck on which the donor substrate 12 rests is optionally cooled.

[0157] Using these parameters, a sharply peaked doping profile is created (see the Gaussian distribution shown in Figure 3A). In this way, the intended damage sites 26 can be reliably distributed with high doping over an extremely thin thickness. The range variation (longitudinal dispersion σ) of the ions within the donor substrate 12 is only between 100 nm and 500 nm, preferably between 200 nm and 400 nm, depending on the primary energy of the ion beam.

[0158] Alternatively, as indicated by the arrows and black horizontal bars in Figure 9, the split trigger ions can be introduced only across a portion of the width of the donor substrate 12, preferably only at one or both end regions of the donor substrate 12. In this way, the intended damage sites 26 are predefined section by section.

[0159] As an alternative to ion implantation, the intended damage site 26 can be formed by electron irradiation or laser irradiation.

[0160] The donor substrate 12 is then bonded to the acceptor substrate 28 with the first layer 21 side facing up, as shown in Figure 10. In this way, the first layer 21 is disposed in the area between the acceptor substrate 28 and the remaining portion 22 of the donor substrate 12. As shown in Figure 10 by the curved arrow that also indicates that the donor substrate 12 is flipped over, it does not matter whether the donor substrate 12 is moved towards the acceptor substrate 28 or the acceptor substrate 28 is moved towards the donor substrate 12 to establish the bond.

[0161] An intermediate result of the bonding process is shown in the bottom left of Figure 10. It is equally possible to reverse the layer order, for example if the acceptor substrate 28 is moved towards the donor substrate 12.

[0162] The acceptor substrate 28 can be any of a range of materials. The acceptor substrate 28 is preferably thermally stable up to at least 1500°C and has a linear expansion coefficient that deviates from that of SiC by no more than 20%, ideally no more than 10%. Suitable examples of materials for the acceptor substrate 28 are polycrystalline SiC or graphite.

[0163] 9 and 10 do not show the contact layer 24 in each case, but the contact layer 24 is preferably present. In that case, the bond between the donor substrate 12 and the acceptor substrate 28 is established via the contact layer 24, resulting in the following sequence: acceptor substrate 28, contact layer 24, remainder of the first layer 21 or first layer 21, remainder 22 of the donor substrate 12.

[0164] The low resistance bond is preferably established by heat treating the intermediate resulting substrate at a temperature between 800°C and 1600°C, more preferably between 900°C and 1300°C.

[0165] Prior to the step of establishing the bond, at least one, and preferably both, of the surfaces to be bonded may be pretreated, in particular by wet chemical, plasma or ion beam treatment. The treated surface may be a contact layer 24. It is also conceivable to apply a thin layer a few nanometers thick to create a subsequent low-resistance bond between the acceptor substrate 28 and the donor substrate 12. In principle, a very low-resistance contact and a high-temperature-resistant bond between the acceptor substrate 28 and the donor substrate 12 are important.

[0166] 11 shows a schematic diagram of the step of splitting donor substrate 12 in the region of intended breakage site 26 to create a preprocessed composite substrate 18 including an acceptor substrate 28 and a doped layer 32 bonded thereto, where doped layer 32 constitutes at least a portion of first layer 21 of donor substrate 12. A split portion 34 of donor substrate 12 is removed from acceptor substrate 28.

[0167] Splitting of the donor substrate 12 is preferably caused by heat treatment of the composite substrate 18 at a temperature between 600° C. and 1300° C., preferably between 750° C. and 1200° C., and more preferably between 850° C. and 1050° C. In one embodiment (see FIGS. 8 and 9), the implanted ions form bubbles that coalesce and cause the splitting.

[0168] Alternatively, an external force may be applied to the composite substrate 18 to cause the donor substrate 12 to break at the intended breakage site 26. A combination of heat treatment and external force may also be necessary or useful, especially if ions are only partially incorporated into the donor substrate 12.

[0169] If both the establishment of the bond and the splitting of the donor substrate 12 are achieved by a thermal process, the two steps can be performed simultaneously in some circumstances.

[0170] Immediately after splitting, it is preferred that the surface of the resulting donor substrate 12 be oriented exactly perpendicular to the c-direction of the crystal structure. The splitting process may result in some imprecise orientation and deviations of up to 0.5°.

[0171] Furthermore, as shown diagrammatically by the arrows in FIG. 12, after the splitting step, post-treatment of the first surface of the composite substrate 18 in the area of ​​the intended breakage site 26 may be carried out, in particular by polishing and / or removing defects.

[0172] 13 may be finally tempered in the doped layer 32 of the pre-processed composite substrate 18, preferably at a temperature between 1500° C. and 1750° C. This is preferably done during subsequent component processing in a heat treatment step to temper the low energy implants, e.g., source / drain contact implants, channel implants, p-JFET implants, etc.

[0173] It is also considered that a step of tempering the implantation defects 42 has already been performed if corresponding high temperatures were used during the division of the portion 34 of the donor substrate 12 and / or during the formation of the bond between the donor substrate 12 and the acceptor substrate 28, in which case the radiation defects could be tempered.

[0174] Contrary to what has been described so far, the step of creating a bond between the donor substrate 12 and the acceptor substrate 28 can also proceed in two stages. For example, a bonding process can be performed first at low temperature and low bond energy, followed by consolidation in a second sub-step to create a bond with high bond strength or bond energy at high temperature and low contact resistance. Consolidation can occur, for example, during or after splitting, during or after surface treatment of the composite substrate, or during or after annealing of implanted defects.

[0175] The pretreated composite substrate 18 thus produced serves as a basis for further processing into an electronic semiconductor component and is again shown in Figure 13. It comprises an acceptor substrate 28 and a doped layer 32 of single-crystal SiC bonded thereto, where the doped layer 32 preferably contains implanted defects 42 (radiation defects). A contact layer 24 may also be included between the acceptor substrate 28 and the doped layer 32.

[0176] The doped layer 32 preferably has a thickness of 3 μm to 30 μm, more preferably 3 μm to 15 μm. It is preferably composed of SiC of the 4H, 6H, or 3C polytype. The surface of the doped layer 32 preferably deviates from perpendicular to the c-direction by less than 0.5°. The doped layer 32 preferably has p- or n-doping with a dopant or defect concentration of 1E15 cm-3 to 5E17 cm-3. The doped layer 32 is preferably doped with ions of one of the elements N, P, B, or Al as the dopant.

[0177] The dopant depth profile of doped layer 32 preferably results essentially from the inverse of the dopant depth profile of first layer 21 of donor substrate 12 .

[0178] Thus, doped layer 32 may have, for example, a substantially constant dopant depth profile.

[0179] Similarly, the doped layer 32 may have a dopant depth profile that rises stepwise in a direction toward the acceptor substrate 28, where the step is formed in the region of the doped layer 32 facing the acceptor substrate 28 up to 40%, preferably up to 30%, of the total depth of the doped layer 32.

[0180] The doped layer 32 may also provide a continuously rising dopant depth profile in a direction toward the acceptor substrate 28 .

[0181] The implant defect profile substantially follows the depth profile of the implanted external atom concentration.

[0182] The acceptor substrate 28 is thermally stable up to at least 1500°C and has a linear expansion coefficient that deviates from the linear expansion coefficient of SiC by 20% or less, preferably 10% or less. More preferably, the acceptor substrate 28 is made of polycrystalline SiC or graphite.

[0183] 14 shows another configuration of pre-processed composite substrate 18 in cross section, and below that shows the dopant concentration profile along the cross section of composite substrate 18 corresponding to arrow F. This is particularly suitable for the fabrication of very high blocking components, e.g., greater than 600V.

[0184] In this case, the preprocessed composite substrate 18 includes a doped layer 32 as well as a supplemental doped layer 38 of single crystal SiC. Preferably, there is an overlap region 40 of the respective dopant depth profiles at the transition section between the doped layer 32 and the supplemental doped layer 38.

[0185] In the embodiment shown in Figure 13, the active layers (drift zone, voltage absorption layer) required in the subsequent semiconductor component are formed only by the doped layer 32 and therefore simultaneously by the first layer 21 or a (preferably large) portion of the first layer 21 in the donor substrate 12.

[0186] In contrast, the active layer in an embodiment such as that of Figure 14 is formed by the combination of the doped layer 32 and the auxiliary doped layer 38. While in Figure 14 a substantially constant cumulative dopant profile can be obtained from the superposition of the two constituent profiles, other dopant profiles can also be formed by juxtaposing and partially overlapping the dopant profiles of the doped layer 32 and the auxiliary doped layer 38. Thus, the composite overall dopant profile formed by the combination of the two dopant depth profiles of the doped layer 32 and the auxiliary doped layer 38 can also be a profile that rises stepwise toward the acceptor substrate 28 or a profile that rises continuously toward the acceptor substrate 28. Further particularly preferred dopant profiles are described in detail with reference to Figure 20.

[0187] In each of these embodiments, reference number 48 refers in each case to a first section of the donor substrate 12 that remains as part of the composite substrate 18 after separation. This first section 48 may consist of only the doped layer 32 in the absence of the auxiliary doped layer 38 (FIG. 13), or may consist of a combination of the doped layer 32 and the auxiliary doped layer 38 (FIGS. 14, 20).

[0188] Such a combined profile is obtained by creating the intended damage site 26 in the donor substrate 12 not in the first layer 21 but in the remaining portion 22 of the donor substrate 12 that is not doped by ion implantation into the donor substrate 12.

[0189] As shown in Figure 11, after splitting at the intended break site 26, the doping of the auxiliary doped layer 38 can proceed from the side farther from the acceptor substrate by further energy-filtered ion implantation. The statements made above with respect to Figures 2 to 6 regarding energy-filtered ion implantation are equally applicable to the ion implantation of the auxiliary doped layer 38. The thickness of the auxiliary doped layer 38 is typically between 3 and 15 µm. In this way, a total thickness of the implanted doped active zone of up to 30 µm can be obtained.

[0190] In principle, if the donor substrate 12 from FIG. 1 is at least twice as thick as the doped layer 32 required in the composite substrate 18, it is possible to produce more than one composite substrate 18, or even a large number of composite substrates 18, from the donor substrate 12 using the method of the present invention. This advantage is particularly significant in the case of thick wafer bars as the donor substrate 12. In this way, significant savings in production costs are possible. This is illustrated diagrammatically in FIG. 15.

[0191] As shown in FIG. 16, ion implantation into the first layer 21 of the donor substrate 12 (and / or the auxiliary doped layer 38 of the composite substrate 18) using the energy filter 20 can use a mask 46 to create one or more undoped regions 44 within the first layer 21 of the donor substrate 12 (and / or within the auxiliary doped layer 38 of the composite substrate 18).

[0192] The composite substrate 18 may become a completed semiconductor component 50 as a result of further steps, such as implanting further active areas, creating oxides, depositing gate electrodes, contacts, wires or vias, etc.

[0193] Two basic architectures of the electronic semiconductor component 50 of the present invention are shown in FIGS.

[0194] 17 includes a carrier substrate 52 that generally corresponds to the acceptor substrate 28 of the preprocessed composite substrate 18. The carrier substrate 52 is generally made of a heavily doped material and is generally field-free.

[0195] A crystal 53 of SiC is mounted on a carrier substrate 52. This crystal 53 generally corresponds to the first section 48 of the donor substrate 12 of the preprocessed composite substrate 18.

[0196] Crystal 53 has a first surface 58 facing away from carrier substrate 52. This first surface 58 is offset from a direction perpendicular to the c-direction (arrow c) of the crystal structure of crystal 53 by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably not at all.

[0197] The electronic semiconductor component 50 includes an active component region 64 having a first zone 54 within the region of a first surface 58 and a second zone 56 following the first zone 54 in depth.

[0198] The first zone 54 includes a near-surface shield structure 60 or JFET structure in a region that includes at least a subsection of the first surface 58 of the crystal 53. The shield structure or JFET structure is p + / n junctions, i.e., p + The regions are formed in multiple regions (not contiguous) and generally cannot be depleted. The region with p+ doping is designated by reference numeral 68.

[0199] The second zone 56 comprises or consists of a voltage absorption layer (also called a drift zone or active layer). The junction between the first zone 54 and the second zone 56 is identified by a dotted line. The thickness of the second zone 56 is preferably between 2 μm and 50 μm.

[0200] 19-25, semiconductor component 50 further includes a field-free contact zone or field-stop zone 62 at the junction between second zone 56 and carrier substrate 52. This field-stop zone 62 generally corresponds to contact layer 24 of preprocessed composite substrate 18. Field-free contact zone or field-stop zone 62 has a vertical thickness of 2 μm or less, preferably 1 μm or less.

[0201] The inactive edge region 66 substantially completely surrounds the first zone 54 and the second zone 56 laterally.

[0202] The second basic structure of the semiconductor component 50 of the invention shown in Figure 18 corresponds in important respects to the basic structure of Figure 17. The same reference numerals refer to the same elements. The difference is that + The difference is that the region 60 is not a buried region, but is formed continuously up to the first surface 58 .

[0203] All p-doped shield structures 60 share several common features, regardless of the specific type of semiconductor component 50. The shield structure 60 parallel to the first surface 58 is not continuous but periodically interrupted. Its distance from the first surface 58 ensures that the maximum allowable electric field strength at the first surface 58 is not exceeded in the "open" region during blocking operation. The shield structure 60 is connected to the source, gate, or anode potential either directly or via a wire (three-dimensional, not shown). The shield structure 60 is either embedded in an n-doped region in an isolated form (away from electrical connections) or formed as a doped region with a high aspect ratio extending from the first surface 58. The typical depth of the p-n junction is between 500 nm and 3.0 μm. The shield structure 60 is sufficiently heavily doped so that the region is not depleted even at the maximum blocking voltage.

[0204] The spatial boundary between the first zone 54 and the second zone 56, represented by the dashed line in Figures 17 and 18, is typically at the point where the p-doped region 68 ends depthwise into the crystal 53. A junction herein is generally defined as being parallel to the first surface 58.

[0205] It is also true throughout that the uppermost crystalline layer of the second zone 56 is oriented substantially perpendicular to the c-direction (arrow c) of the crystalline structure.

[0206] 19-26 are merely illustrative of the details of the semiconductor component 50. Each right side should be considered a cutaway side.

[0207] 19 shows a vertical power semiconductor component 50 in the form of a planar MOS transistor. The inactive edge region 66 is preferably nominally undoped, except for optional near-surface edge structures 70. Reference numeral 52 still refers to the carrier substrate, reference numeral 53 still refers to the SiC crystal, reference numeral 54 still refers to the first zone, reference numeral 56 still refers to the second zone, reference numeral 62 still refers to the field stop zone, reference numeral 52 still refers to the carrier substrate, and reference numeral 68 still refers to the p-type shielding structure. + 53. The reference numerals 72 and 75 denote a p-region (p-well), 74 an n+ region, and 75 a further p+ region. Here, the first surface 58 of the crystal 53 is flat and preferably extends over the entire width of the semiconductor component 50. The gate oxide is obviously not considered part of the first surface 58.

[0208] What is important is that first surface 58 be oriented substantially perpendicular to the c-direction (arrow c) of the crystal structure of crystal 53. Slight variations of up to 0.5° are acceptable in some circumstances. Also, channel region 76 (shown by dotted lines) extending parallel to first surface 58 of crystal 53 deviates from the direction perpendicular to the c-direction of the crystal structure of crystal 53 by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably not at all.

[0209] Similar to the illustrated planar MOSFET embodiment, where first surface 58 of crystal 53 is oriented substantially perpendicular to the c-direction (arrow c) of the crystalline structure of crystal 53, one skilled in the art will recognize many other configurations of planar MOSFETs that are also encompassed by the present invention.

[0210] The dopant profile (conc) of the semiconductor component 50 of Fig. 19, shown in Fig. 20, has a continuously rising profile in the depth direction in the region of the second zone 56, as already described for the pretreated composite substrate 18. Alternatively, the dopant profile in the region of the second zone 56 may be constant or may have a step-rising profile in the end regions of the second zone 56, as indicated by the dashed line. How such a dopant profile can be obtained has already been described above with reference to Figs. 6a to 6c.

[0211] Furthermore, in the region of the first zone 54, the dopant profile preferably has a plateau that is higher than the doping in the adjacent region of the second zone 56. Generally, the regions of the first zone 54 and the second zone 56 are each n-doped. Preferably, the dopant concentration of the n-doped region of the first zone 54 is 1.5 to 100 times, more preferably 2 to 10 times, higher than the n-doped region of the second zone 56 facing the first zone 54. The descending flanks of the doping profile are generally not perfectly vertical.

[0212] In the p+ region 68 of the first zone 54, doping deviating from the described profile is of course obtained: the dopant concentration in the p+ region 68 of the first zone 54 is preferably 2 to 1000 times, more preferably 50 to 1000 times, higher than the dopant concentration in the n-doped region of the second zone 56 facing the first zone 54.

[0213] 20, it is also possible for the doping profile of the first zone 54 and the doping profile of the second zone 56 to abut one another substantially seamlessly. This is obvious if the first zone 54 and the second zone 56 are doped by the same implantation operation (as the doped layer 32 in the donor substrate 12). However, this is also possible if the first zone 54 is doped first (e.g., as the auxiliary doped layer 38) in a subsequent implantation operation.

[0214] The doping profile of the second zone 56 of FIG. 20 is equally applicable to the second zone 56 of all other semiconductor components 50 described.

[0215] Figure 21 shows a vertical power semiconductor component 50 in the form of a vertical merged PIN Schottky diode (MPS diode), with elements that are the same as in Figure 19 being numbered the same.

[0216] Here, p+ region 68 extends the entire depth of first zone 54 from first surface 58 to the junction with second zone 56. First surface 58 is again continuous across the entire width of semiconductor component 50 and is oriented substantially perpendicular to the c-direction (arrow c) of the crystalline structure of crystal 53. Reference numeral 78 denotes the Schottky material, and reference numeral 80 denotes the metal layer (anode). Metal contact 71 functions as the cathode.

[0217] The Schottky junction 82 (shown by a dotted line) extends in a plane parallel to the first surface 58 of the crystal 53 and is therefore deviated from perpendicular to the c-direction of the crystal structure of the crystal 53 by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably not at all.

[0218] Similar to the illustrated embodiment of the MPS diode, those skilled in the art will recognize many other configurations of MPS diodes that are also encompassed by the present invention, provided that first surface 58 of crystal 53 is oriented substantially perpendicular to the c-direction of the crystal structure of crystal 53.

[0219] The MPS diode shown in Figure 22 differs from the MPS diode of Figure 21 in that edge region 66 is substantially undoped from first surface 58, except for the presence of near-surface field-reducing edge structure 70, and in that edge region 66, from substantially the depth at which second zone 56 begins to the depth at which field-free contact zone or field-stop zone 62 exists, is provided with the same dopant concentration as second zone 56 or a lower dopant concentration than second zone 56, preferably at least 20% lower, and more preferably at least 50% lower. The doped portion of edge region 66 is identified by reference numeral 84.

[0220] Such doped regions 84 may also be present in other configurations of semiconductor component 50 .

[0221] Figure 23 shows a vertical power semiconductor component 50 in the form of a vertical trench MOSFET. Like reference numerals indicate like elements to those in Figure 19. Reference numeral 86 indicates a trench at least partially lined with a gate oxide, reference numeral 88 indicates a p-doped region, reference numeral 90 indicates an n-doped region, and reference numeral 92 indicates respective channel regions (shown in dotted lines).

[0222] Channel region 92 deviates from the c-direction (arrow c) of the crystal structure of crystal 53 by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably not at all. Channel region 92 likewise deviates from the direction perpendicular to first surface 58 of crystal 53 by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably not at all. It is particularly preferred that channel region 92 be disposed on the A-plane of crystal 53.

[0223] First surface 58 in this embodiment is discontinuous, meaning that only the subsection of each surface 58 located between trenches 86 must meet the above criteria. However, it is also contemplated that each trench 86 may, at its bottom, similarly include a subsection of crystal 53 having a region perpendicular to the c-direction of the crystal structure.

[0224] The embodiment of the vertical trench MOSFET shown in FIG. 24 differs from the embodiment according to FIG. 23 substantially by the arrangement of the p+ region 68, which in this example extends along the side of the trench 86 through the first zone 54 to the first surface 58, and by the arrangement of the source electrode S.

[0225] Similar to the illustrated embodiment of the trench MOSFET, those skilled in the art will recognize many other configurations of trench MOSFETs that are also encompassed by the present invention, provided that first surface 58 of crystal 53 is oriented substantially perpendicular to the c-direction of the crystalline structure of crystal 53.

[0226] Figure 25 shows a vertical power semiconductor component 50 in the form of a superjunction trench MOSFET. Like reference numerals indicate like elements to those in Figure 23. In addition to the structural elements already defined therein, p-doped columns 94 are also formed in the second zone 56 below the p+ region 68 of the first zone 54.

[0227] The p-doped columns 94 of the second zone 2 differ from the p+ regions 68 of the first zone 54 in that they lie within a voltage absorption zone. This means that the p-doped columns 94 must be configured so that they can be fully depleted. In other words, in the case of blocking, a space charge zone extends laterally across both the p columns and the n regions 95 within the second zone 56.

[0228] The doping level and depth of the p-doped columns 94 depend on the voltage class of the component 50. The p-doped columns 94 of the second zone 56 are preferably produced by a masked, energy-filtered implant. In the case of the superjunction structure shown in FIG. 25, it is particularly advantageous for the edge regions 66 to be undoped.

[0229] This results in two preferred embodiments for the layout of the superjunction MOSFET. 1. The gate trenches 86 and the p+ regions (shield structures) 68 are implemented as long trenches. The p-doped columns 94 of the second zone 56 continue into these trenches, the section of which has the appearance shown in FIG. 2. The gate trench 86 and the p+ region (shield structure) 68 are also implemented as long trenches. In projection onto the component surface, the p-doped columns 94 in the second zone 56 are arranged perpendicular to the gate trench 86 and the p+ region 68. See the schematic top view in Figure 26.

[0230] FIG. 27 shows a vertical power semiconductor component 50 in the form of a J-FET (junction field effect transistor). Identical reference numerals indicate identical elements or regions to those in the previous figures. The p+ region 68 extends in a U-shape around a similarly U-shaped gate contact, with the associated interfaces 96 between the p+ and n regions shown in dotted lines. These interfaces 96 extend perpendicular to a subsection of the first surface 58.

[0231] Figure 28 shows another embodiment of a J-FET. Like reference numerals indicate like elements or regions as in the previous figure. Here, interface 96 extends parallel to a subsection of first surface 58.

[0232] Similar to the basic structure of semiconductor component 50 shown thus far, those skilled in the art will recognize many other configurations of semiconductor components that are also encompassed by the present invention, provided that first surface 58 of crystal 53 is oriented substantially perpendicular to the c-direction of the crystal structure of crystal 53.

[0233] Similar to the manufacturing method described above, it is also possible to not form composite substrate 18, but to temporarily stabilize crystals 53 from a thin layer of high-quality crystalline SiC material suitable for forming component 50, with their surfaces oriented substantially perpendicular to the c-direction of the crystal structure of crystals 53, and to construct them by a carrier during component manufacturing, e.g., by temporary bonding, or completely freestanding. In these cases, carrier substrate 52 of final component 50 need not be present.

[0234] In the context of the present invention, "coupled" is understood to mean directly coupled or indirectly, i.e. coupled with the intermediary of a further element. A "coupled" between two elements may be direct or indirect.

Claims

1. 1. A semiconductor component (50) comprising a crystal (53) made of single-crystal SiC, wherein the orientation of at least a subsection of a first surface (58) of the crystal (52) deviates from a direction perpendicular to the c-direction (c) of the crystal structure of the crystal (53) by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably no deviation at all.

2. a first zone (54) having a near-surface shield structure (60) or a JFET structure within a region including at least a subsection of the first surface (58) of the crystal (53); a second zone (56) disposed on a side of the first zone (54) remote from the first surface (58) of the crystal (53) and having a voltage absorbing layer adjacent to the first zone (54); a field-free contact zone or field-stop zone (64) located on a side of said second zone (56) remote from said first zone (54); 2. The electronic semiconductor component (50) of claim 1, further comprising an active component region (64) comprising:

3. 3. The electronic semiconductor component (50) of claim 2, wherein the first zone (54) and the second zone (56) are formed on the basis of the crystal (53) consisting essentially of SiC.

4. 4. The electronic semiconductor component (50) of claim 2 or 3, wherein the thickness of the first zone (54) is between 0.5 μm and 3.0 μm.

5. 5. The electronic semiconductor component (50) of any one of claims 2 to 4, wherein the thickness of the second zone (56) is between 2 μm and 50 μm.

6. 6. An electronic semiconductor component (50) according to any one of claims 2 to 5, characterized in that the dopant concentration of the n-doped region of the first zone (54) is higher than the dopant concentration of the n-doped region of the second zone (56) facing the first zone (54), preferably by a factor of 1.5 to 100, more preferably by a factor of 2 to 10.

7. 7. An electronic semiconductor component (50) according to any one of claims 2 to 6, characterized in that the dopant concentration of the p-doped region (68) of the first zone (54) is higher than the dopant concentration of the n-doped region of the region of the second zone (56) facing the first zone (54), preferably by a factor of 2 to 1000, more preferably by a factor of 50 to 1000.

8. 8. The electronic semiconductor component (50) of claim 2, wherein the second zone (56), starting from the first zone (54), has a substantially constant dopant depth profile in a direction toward the field-free contact zone or field-stop zone (66).

9. 8. The electronic semiconductor component (50) of claim 2, wherein the second zone (56) proceeding in a direction from the first zone (54) towards the field-free contact zone or field-stop zone (66) has a step-like rising dopant depth profile, the step being formed in the region of the second zone (56) facing the field-free contact zone or field-stop zone (66) over a maximum of 40%, preferably a maximum of 30%, of the total depth of the second zone (56).

10. 10. The electronic semiconductor component (50) according to claim 9, characterized in that the difference in concentration between the highest and lowest step is at least 10 times, preferably at least 100 times, more preferably at least 500 times, and particularly preferably at least 1000 times.

11. 8. The electronic semiconductor component (50) of claim 2, wherein the second zone (56), starting from the first zone (54), has a dopant depth profile that rises constantly in a direction toward the field-free contact zone or field-stop zone (66).

12. 12. The electronic semiconductor component (50) of claim 11, wherein the steadily rising dopant depth profile is a profile according to the formula:

13. 13. The electronic semiconductor component according to claim 2, further comprising a carrier substrate (52) on the side of the field-free contact zone or field stop zone (62) remote from the first zone (54), and the crystal (53) made of SiC is bonded to the carrier substrate (52) in the region of the field-free contact zone or field stop zone (66) by a permanent adhesive bond or other bonding connection.

14. 14. The electronic semiconductor component (50) of claim 2, further comprising an inactive edge region (66) that substantially completely surrounds the first zone (54) and the second zone (56) in all lateral directions.

15. 15. The electronic semiconductor component (50) of claim 14, wherein the edge region (66) is substantially undoped except for any near-surface electric field-reducing edge structures (70) present.

16. 15. The electronic semiconductor component of claim 14, wherein the edge region is substantially undoped from the first surface onward, except for any near-surface electric-field-reducing edge structures present, and has substantially the same dopant concentration as the second zone from a depth where the second zone begins to a depth where the field-free contact zone or field-stop zone is located, or has a dopant concentration lower than the second zone, preferably at least 20% lower, more preferably at least 50% lower.

17. 17. An electronic semiconductor component (50) according to any one of claims 2 to 16, characterized in that the field-free contact zone or field-stop zone (62) has a vertical thickness of 2 μm or less, preferably 1 μm or less.

18. 18. The electronic semiconductor component (50) of any one of claims 1 to 17, wherein the single crystal SiC is of the hexagonal 4H or 6H polytype.

19. 19. The electronic semiconductor component (50) according to any one of claims 1 to 18, wherein the crystal (53) is a crystal made of high-purity, high-quality semi-insulating SiC material.

20. 20. An electronic semiconductor component (50) according to any one of claims 1 to 19, characterized in that the A-plane of the crystal (53) is deviated from a direction perpendicular to the first surface (58) of the crystal (53) by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably not at all.

21. 21. The electronic semiconductor component (50) of claim 1, wherein the electronic semiconductor component (50) is a trench MOSFET, the channel region (92) being offset from the c-direction (c) of the crystal structure of the crystal (53) by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably not at all.

22. 21. The electronic semiconductor component (50) of any one of claims 1 to 20, characterized in that it is a trench MOSFET, the channel region (92) being offset from a direction normal to the first surface (58) of the crystal (53) by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably not at all.

23. 23. The electronic semiconductor component (50) of claim 22, wherein the channel region (92) is disposed in the A-plane of the crystal (53).

24. 21. The electronic semiconductor component (50) of claim 1, wherein the electronic semiconductor component (50) is a planar MOSFET, the channel region (76) being offset from a direction perpendicular to the c-direction (c) of the crystal structure of the crystal (53) by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably not at all.

25. 25. The electronic semiconductor component (50) of any one of claims 1 to 20 or claim 24, wherein the electronic semiconductor component (50) is a planar MOSFET, the channel region (76) extending parallel to the first surface (58) of the crystal (53).

26. 21. The electronic semiconductor component (50) of claim 1, wherein the electronic semiconductor component (50) is an MPS (merged-PIN Schottky) diode, and the plane of the Schottky junction (82) is deviated from a direction perpendicular to the c-direction (c) of the crystal structure of the crystal (53) by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably not at all.

27. 27. The electronic semiconductor component (50) of claim 1, wherein the electronic semiconductor component (50) is an MPS (Merge-PIN Schottky) diode, and the plane of the Schottky junction (82) extends parallel to the first surface (58) of the crystal (53).

28. JFET transistor, one or each p ＋ 21. An electronic semiconductor component (50) according to any one of claims 1 to 20, characterized in that the interface (96) at the -n junction is deviated from a direction parallel to the c-direction (c) of the crystal structure of the crystal (53) by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably not at all.

29. JFET transistor, one or each p ＋ 21. The electronic semiconductor component (50) of claim 1, wherein the interface (96) at the -n junction is offset from a direction perpendicular to the c-direction (c) of the crystal structure of the crystal (53) by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably not at all.

30. 1. A method for producing a preprocessed composite substrate (18) that serves as a basis for further processing into an electronic semiconductor component (50), the preprocessed composite substrate (18) comprising an acceptor substrate (28) and a first section (48) of a donor substrate (12) having at least one doped layer (32), the method comprising: a) providing a donor substrate (12) comprising single crystal SiC; b) doping the first layer (21) of the donor substrate (12) by ion implantation using an energy filter (20), the energy filter (20) being a microstructured film having a predetermined structural profile for adapting a dopant depth profile resulting from implantation into the first layer (21) of the donor substrate (12), the doping creating a predetermined dopant depth profile in the first layer (21) of the donor substrate (12), the first layer (21) extending from an outer surface (23) of the donor substrate (12) facing the ion beam (10) to a predetermined dopant depth (T) and subsequently extending through the remaining part (22) of the donor substrate (12); c) creating an intended breakage site (26) in the donor substrate (12) that extends substantially parallel to the outer surface (23) of the donor substrate (12); d) providing an acceptor substrate (28) and producing a bond between the donor substrate (12) and the acceptor substrate (28), wherein the first layer (21) is disposed in the area between the acceptor substrate (28) and the remaining portion (22) of the donor substrate (12); e) splitting the donor substrate (12) in the region of the intended breakage site (26) to produce the pre-processed composite substrate (18), the pre-processed composite substrate (18) including the acceptor substrate (28) and a first section (48) of the donor substrate (12) having at least one doped layer (32) connected thereto, the doped layer (32) constituting at least a portion of the first layer (21) of the donor substrate (12), and is performed such that the first section (48) of the donor substrate (12) has a first surface (58) facing away from the acceptor substrate (28) in the region of the intended breakage site (26) in the composite substrate (18), and deviates from perpendicular to the c-direction of the crystal structure of the first section (48) of the donor substrate (12) by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably no deviation at all; A method comprising:

31. 31. The method of claim 30, wherein the first layer (21) has a thickness of 3 to 15 μm.

32. 32. The method of claim 30 or 31, wherein the donor substrate (12) is a crystal of high-purity, high-quality semi-insulating SiC material.

33. 33. The method of any one of claims 30 to 32, wherein the outer surface (23) of the donor substrate (12) facing the ion beam (10) deviates from perpendicular to the c-direction (c) of the crystal structure of the donor substrate (12) by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, and most preferably not at all.

34. 34. The method according to any one of claims 30 to 33, wherein the donor substrate (12) has a thickness of more than 100 μm, preferably more than 200 μm, more preferably more than 300 μm, up to 15 cm, more preferably up to 10 cm.

35. The doping of the first layer (21) is 1E15 cm 3 in terms of dopant concentration in the first layer (21). －３ From 5E17cm －３ 35. A method according to any one of claims 30 to 34, providing a p or n doping of up to 1000 .mu.m.

36. 36. A method according to any one of claims 30 to 35, characterized in that the first layer (21) is doped with ions of one of the elements nitrogen, phosphorus, boron or aluminium.

37. 37. A method according to any one of claims 30 to 36, characterized in that the doping of the first layer (21) results in a substantially constant dopant depth profile.

38. 38. The method according to any one of claims 30 to 37, characterized in that the doping of the first layer (21) provides a dopant depth profile that descends in a step-like manner from an outer surface (23) of the donor substrate (12) facing the ion beam (10), the step being formed in a region near the surface of the first layer (21) facing the ion beam (10) by up to 40%, preferably up to 30%, of the total depth (T) of the first layer (21).

39. 39. The method of claim 38, wherein the difference in concentration between the highest and lowest step is at least 10-fold, preferably at least 100-fold, more preferably at least 500-fold, particularly preferably at least 1000-fold.

40. 37. The method of any one of claims 30 to 36, wherein the doping of the first layer (21) results in a dopant depth profile that descends continuously from the outer surface (23) of the donor substrate (12) facing the ion beam (10).

41. 41. The method of claim 40, wherein the continuously decreasing dopant depth profile is a profile according to the formula:

42. 42. The method according to claim 30, further comprising the step of creating a contact layer (24) in a surface region of the first layer (21) or applying a contact layer (24) to the surface of the first layer (21), wherein a bond between the donor substrate (12) and the acceptor substrate (28) is established via the contact layer (21), resulting in the following sequence: acceptor substrate (28), contact layer (24), the remainder of the first layer or the first layer (21), the remainder of the donor substrate (12).

43. 43. The method of claim 42, wherein the contact layer (24) is created by ion implantation.

44. 44. The method of claim 42 or 43, wherein the dopant concentration in the contact layer (24) is at least 100 times, preferably at least 1000 times, more preferably at least 10000 times, even more preferably at least 100000 times greater than the average dopant concentration in the remainder of the first layer or in the first layer (21).

45. The dopant concentration in the contact layer (24) is 1E17 cm －３ More than 1E19 cm －３ 45. The method of any one of claims 42 to 44, wherein the

46. 46. ​​The method according to any one of claims 30 to 45, characterized in that the intended damage site (26) is located in a region of the first layer (21), preferably in an edge region of the first layer (21) close to a predetermined doping height (T), the edge region being particularly preferably 1 μm or less, more preferably 100 nm or less in thickness.

47. 47. The method of claim 30, wherein the intended damage site (26) is in the region of the remaining portion (22) of the donor substrate (12), and further wherein after step e), a further step of performing ion implantation into the composite substrate (18) using an energy filter (20) is performed from the side remote from the acceptor substrate (28).

48. 48. The method of claim 47, wherein the ion implantation into the composite substrate (18) extends at least through the doped layer (32).

49. 49. The method of claim 48, wherein the ion implantation into the composite substrate (18) is carried out so that the dopant concentration in the auxiliary doped layer (38) is higher than in the region of the doped layer (32) facing the auxiliary doped layer (38), preferably by a factor of 1.5 to 100, more preferably by a factor of 2 to 10.

50. 50. The method of any one of claims 30 to 49, wherein the intended damage site (26) is created by ion implantation of split trigger ions.

51. 51. The method of claim 50, wherein the split trigger ions are introduced across the entire width of the donor substrate (12).

52. 51. The method of claim 50, wherein the split trigger ions are introduced over only a portion of the width of the donor substrate (12).

53. 53. The method of claim 52, wherein the split trigger ions are introduced only into at least one edge region of the donor substrate (12).

54. The split trigger ions are H, H ２ 54. The method of any one of claims 50 to 53, wherein the metal is selected from the group consisting of He, B.

55. 55. The method of claim 54, wherein the split trigger ions are energetic ions with energies between 0.5 and 10 MeV, preferably between 0.5 and 5 MeV, more preferably between 0.5 and 2 MeV.

56. The particle dose of the split trigger ions is in each case 1E15 cm －２ and 5E17cm －２ 56. The method of any one of claims 50 to 55, wherein:

57. The energy spread of the ion beam of the split trigger ions is 10 －２ less than 10 －４ 57. The method of any one of claims 50 to 56, wherein the

58. 58. The method according to any one of claims 30 to 57, wherein splitting of the donor substrate (12) is caused by a heat treatment of the composite substrate (18) at a temperature between 600°C and 1300°C, preferably between 750°C and 1200°C, more preferably between 850°C and 1050°C.

59. 59. A method according to any one of claims 30 to 58, characterized in that the bond is established by heat treatment of the composite substrate (18) at a temperature between 800°C and 1600°C, preferably between 900°C and 1300°C.

60. 60. The method of any one of claims 30 to 59, wherein both bonding and splitting of the donor substrate (12) are performed by thermal treatment, and both steps are performed simultaneously.

61. 61. A method according to any one of claims 30 to 60, characterized in that prior to the bonding step, a pretreatment of at least one, preferably both, of the surfaces to be bonded is carried out, in particular a wet chemical treatment, a plasma treatment or an ion beam treatment.

62. 62. The method according to any one of claims 30 to 61, characterized in that the acceptor substrate (28) is thermally stable up to at least 1500°C and has a linear expansion coefficient that deviates from that of SiC by no more than 20%, preferably no more than 10%.

63. 63. The method of claim 62, wherein the acceptor substrate (28) is formed from polycrystalline SiC or graphite.

64. 64. The method according to any one of claims 30 to 63, characterized in that after the dividing step, a post-treatment of the surface of the composite substrate (18) in the area of ​​the intended breakage site (26) is carried out, in particular by polishing and / or removal of defects.

65. 65. The method of any one of claims 30 to 64, wherein implantation defects (42) in the pretreated composite substrate (18) are tempered at a temperature between 1500°C and 1750°C.

66. 66. A method for manufacturing an electronic semiconductor component (50), comprising the steps of the method for manufacturing a pretreated composite substrate (18) according to any one of claims 30 to 65, and the further step of introducing further structural elements of a semiconductor component (50) into the composite substrate (18) from or onto the first surface (58) or arranging them on the first surface (58).

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