Semiconductor package

Abstract

To improve solder connection reliability by reducing solder stress caused by temperature change during package mounting.SOLUTION: A semiconductor package 1 includes: a semiconductor chip 20 in which an electrode 23 is formed on a first surface 21a which is a surface of a chip substrate 21 on which light is incident; a transparent substrate 10 having a wiring layer 11; a columnar electrode 40 electrically connected to an electrode 23 via the wiring layer 11; and a sealing resin layer 50 formed around the semiconductor chip 10 and on the wiring layer 11 side of the transparent substrate 10. The columnar electrode 40 is connected to the wiring layer 11 via a first conductive part 30, and the columnar electrode 40 includes a first end part 41 connected to the first conductive part 30, a second end part 42 opposed to the first end part 41, and a side surface 43 connecting the first end part 41 and the second end part 42. The sealing resin layer 50 is formed to cover the side surface 43 of the columnar electrode 40 and the side surface 31 of the first conductive part 30 so that the second end part of the columnar electrode 40 is exposed. A second conductive part 60 is formed on a second surface 21b facing the first surface 21a of the chip substrate 21 and an exposed surface 42a of the second end part 42 of the columnar electrode 40.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to semiconductor packages. [Background technology]

[0002] In recent years, in order to cope with the miniaturization and high integration of semiconductor chips, flip-chip mounting using CSP (Chip Scale Package) as a semiconductor package has been actively adopted.

[0003] CSPs have a package size similar to that of semiconductor chips, making them small and good for wafer-level process productivity, but they suffer from low solder joint reliability during package assembly.The reason for the low solder joint reliability in CSP package assembly is the large difference between the linear expansion coefficient (~3 ppm / °C) of the silicon that makes up the chip substrate of the semiconductor chip that forms the CSP's base, and the linear expansion coefficient (15-20 ppm / °C) of the mounting substrate, such as the motherboard, on which the CSP is mounted.This difference in thermal expansion causes increased stress on the solder (connection terminals) and their surroundings due to temperature changes such as temperature cycles.

[0004] Furthermore, these mounting packages have a problem in that they have few paths for dissipating heat generated by the device and have high thermal resistance, which increases the junction temperature (TJ) during device operation and causes performance degradation.

[0005] On the other hand, in conventional fan-out packages, the solder balls that form the connection terminals must be significantly larger than the device thickness, which naturally increases the pin pitch of the connection terminals and makes the package itself larger. Patent Document 1 discloses a device with a structure that solves the above problem and increases the number of terminals. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2019-40893 Summary of the Invention [Problem to be solved by the invention]

[0007] The device of Patent Document 1 uses through electrodes instead of solder balls and employs a two-layer structure of glass adhesive resin and mold resin as the sealing layer, resulting in a complex manufacturing process. Furthermore, the device of Patent Document 1 lacks sufficient measures for stress relaxation of the solder and heat dissipation of the semiconductor chip, leaving room for improvement. Furthermore, the device of Patent Document 1 is difficult to mount because the connection terminals formed on the through electrodes arranged around the semiconductor chip are positioned differently in the thickness direction from the connection terminals arranged under the semiconductor chip.

[0008] The present invention has been made in consideration of the above-mentioned circumstances, and specifically, an object of the present invention is to provide a semiconductor package that has excellent heat dissipation properties while reducing solder stress caused by temperature changes during package mounting, thereby improving solder connection reliability. [Means for solving the problem]

[0009] The above object can be achieved by any one of the following means (1) to (13).

[0010] (1) A semiconductor package comprising: a semiconductor chip having an electrode formed on a first surface, which is a surface onto which light is incident on a chip substrate; a transparent substrate having a wiring layer; a pillar-shaped electrode electrically connected to the electrode via the wiring layer; and a sealing resin layer formed around the semiconductor chip and on the wiring layer side of the transparent substrate, wherein the pillar-shaped electrode is connected to the wiring layer via a first conductive portion, and the pillar-shaped electrode has a first end portion connected to the first conductive portion, a second end portion opposite the first end portion, and a side portion connecting the first end portion and the second end portion, the sealing resin layer is formed to cover the side portion of the pillar-shaped electrode and the side portion of the first conductive portion so that the second end portion of the pillar-shaped electrode is exposed, and a second conductive portion is formed on a second surface opposite the first surface of the chip substrate and on the exposed surface of the second end portion of the pillar-shaped electrode.

[0011] (2) The semiconductor package according to (1), wherein the first conductive portion has a lower elastic modulus than the columnar electrode.

[0012] (3) The semiconductor package according to (1) or (2) above, wherein at least a portion of the sealing resin layer formed between the semiconductor chip and the transparent substrate is formed of an underfill layer.

[0013] (4) A semiconductor package described in any one of (1) to (3) above, wherein the second conductive portion is formed on the exposed surface of the second end of the columnar electrode, with an area equal to or larger than the exposed surface, and is formed to cover the entire second surface of the semiconductor chip.

[0014] (5) The semiconductor package according to any one of (1) to (4) above, wherein the columnar electrodes are formed of metal pins.

[0015] (6) The semiconductor package according to any one of (1) to (5) above, wherein the sealing resin layer contains a non-conductive filler.

[0016] (7) The semiconductor package according to any one of (1) to (6) above, wherein the sealing resin layer has a linear expansion coefficient equal to or greater than the linear expansion coefficient of the chip substrate of the semiconductor chip.

[0017] (8) The semiconductor package according to any one of (1) to (7) above, wherein the first conductive portion is formed of a conductive paste or solder.

[0018] (9) The semiconductor package according to any one of (1) to (8) above, wherein the second conductive portion is made of a material containing copper as a main component.

[0019] (10) The semiconductor package according to any one of (1) to (9) above, wherein the sealing resin layer has a groove formed in at least a part of the periphery of the columnar electrode.

[0020] (11) The semiconductor package according to any one of (1) to (10) above, wherein a connection terminal portion is provided on the exposed surface of the second end portion of the columnar electrode and / or the second conductive portion.

[0021] (12) The semiconductor package according to any one of (1) to (11) above, wherein the semiconductor chip is an image sensor.

[0022] (13) The semiconductor package according to (12), wherein the sealing resin layer has a light-shielding portion that blocks light having a wavelength sensitive to the image sensor. [Effects of the Invention]

[0023] A semiconductor package according to one embodiment of the present invention reduces solder stress caused by temperature changes during package mounting, thereby improving solder connection reliability and providing a package with excellent heat dissipation properties. [Brief explanation of the drawings]

[0024] [Figure 1] 1 is a cross-sectional view showing a state in which the semiconductor package according to the embodiment is mounted on a mounting substrate. [Figure 2] FIG. 1 is a cross-sectional view of a semiconductor package. [Figure 3A] FIG. 1 is a diagram showing step 1 of the method for manufacturing a semiconductor package. [Figure 3B] FIG. 10 is a diagram showing step 2 of the method for manufacturing a semiconductor package. [Figure 3C] FIG. 10 is a diagram showing step 3 of the method for manufacturing a semiconductor package. [Figure 3D] FIG. 10 is a diagram showing step 4 of the method for manufacturing a semiconductor package. [Figure 3E] FIG. 10 is a diagram showing step 5 of the method for manufacturing a semiconductor package. [Figure 3F] FIG. 10 is a diagram showing step 6 of the semiconductor package manufacturing method. [Figure 3G] FIG. 10 is a diagram showing step 7 of the semiconductor package manufacturing method. [Figure 3H] FIG. 10 is a diagram showing step 8 of the semiconductor package manufacturing method. [Figure 3I] FIG. 10 is a diagram showing step 9 of the semiconductor package manufacturing method. [Figure 3J] FIG. 1 is a diagram showing step 10 of the method for manufacturing a semiconductor package. [Figure 4] FIG. 10 is a cross-sectional view showing one form of a semiconductor package according to a first modified example. [Figure 5A] FIG. 10 is a cross-sectional view showing one form of a semiconductor package according to a second modified example. [Figure 5B] 10A and 10B are diagrams showing another form of the semiconductor package of the second modified example. [Figure 6] 10 is a graph showing the results of a solder life simulation for an example and a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience. Meanwhile, the embodiments described below are merely examples, and various modifications are possible from such embodiments.

[0026] Hereinafter, the terms "upper" and "above" may include not only what is directly above in contact with something, but also what is above without contact. Similarly, the terms "lower" and "below" may include not only what is directly below in contact with something, but also what is below without contact.

[0027] The singular expression includes the plural expression unless the context clearly dictates otherwise. Furthermore, when a part "includes," "comprises," or "has" a certain element, it does not mean that it excludes other elements, but that it may further include other elements, unless otherwise specified to the contrary.

[0028] Unless explicitly stated or stated to the contrary, steps constituting a method may be performed in any suitable order, and are not necessarily limited to the order of the steps described. The use of any examples or exemplary terms is merely for the purpose of illustrating the technical idea, and the scope of the invention is not limited by the examples or exemplary terms, except as limited by the scope of the claims.

[0029] In the following description, when ordinal numbers such as "first" and "second" are used, unless otherwise specified, they are used for convenience and do not stipulate any particular order.

[0030] The semiconductor package 1 according to this embodiment will be described. As shown in Figures 1 and 2, the semiconductor package 1 is a fan-out package in which the semiconductor chip 20 is configured as a solid-state imaging element (CMOS image sensor) and has wiring drawn out to an area larger than the size of the semiconductor chip.

[0031] 1, the semiconductor package 1 includes a transparent substrate 10, a semiconductor chip 20, a first conductive portion 30, columnar electrodes 40, and a sealing resin layer 50. The semiconductor package 1 can be mounted on a mounting substrate 200 via connection terminal portions 70, as shown in FIG.

[0032] The transparent substrate 10 is made of a transparent material having optical transparency, such as a glass material or a resin material such as polyimide. The planar size of the transparent substrate 10 is equal to or larger than the planar size of the chip substrate 21 of the semiconductor chip 20. As shown in FIG. 2, the transparent substrate 10 has a first surface 10a, which is a light incident surface, and a second surface 10b opposite the first surface 10a. The second surface 10b of the transparent substrate 10 and the first surface 21a of the chip substrate 21 of the semiconductor chip 20 are bonded together by a sealing resin layer 50 in a facing relationship. In FIG. 1, the first surface 10a of the transparent substrate 10 is the upper surface of the transparent substrate 10, and the second surface 10b of the transparent substrate 10 is the lower surface of the transparent substrate 10.

[0033] A wiring layer 11 is formed on the second surface 10b of the transparent substrate 10. The wiring layer 11 electrically connects the semiconductor chip 20 and the columnar electrodes 40. The wiring layer 11 can be formed by laminating a single layer or multiple layers of a metal material such as copper (Cu) or gold (Au) using a known wiring formation method such as photolithography. The wiring layer 11 can be formed, for example, by plating a copper (Cu) wiring with gold (Au).

[0034] The semiconductor chip 20 has a chip substrate 21 made of silicon or the like. An IC circuit pattern or the like is formed on a first surface 21a of the chip substrate 21. In Fig. 1, the first surface 21a of the chip substrate 21 of the semiconductor chip 20 is the upper surface (incident surface) of the chip substrate 21, and the second surface 21b of the chip substrate 21 is the lower surface of the chip substrate 21.

[0035] The semiconductor chip 20 has a light receiving area in which multiple pixels that convert incident light into electrical signals are arranged in rows and columns, and can be configured as a CMOS image sensor that is equipped with a microlens (on-chip lens) 22, as well as color filters, photodiodes, pixel circuits, etc. (not shown).

[0036] Electrodes 23 are formed on the first surface 21a of the semiconductor chip 20. The electrodes 23 are configured by forming stud bumps 23b made of gold (Au) or the like on bonding pads 23a. The electrodes 23 are formed at positions that allow electrical connection with the wiring layer 11 formed on the transparent substrate 10.

[0037] The first conductive portion 30 is interposed between the wiring layer 11 and the columnar electrode 40, and electrically connects the wiring layer 11 and the columnar electrode 40. The first conductive portion 30 can be formed of a conductive paste such as a conductive adhesive containing copper particles, or solder. The first conductive portion 30 can be formed by a known printing method such as screen printing or inkjet printing.

[0038] The elastic modulus of the first conductive part 30 is preferably lower than that of the columnar electrode 40. In other words, the relationship in magnitude between the elastic moduli of the first conductive part 30 and the columnar electrode 40 preferably satisfies the relationship "elastic modulus of first conductive part < elastic modulus of columnar electrode." When the semiconductor package 1 forms a first conductive part 30 having an elastic modulus lower than that of the columnar electrode 40 between the wiring layer 11 and the columnar electrode 40, the stress acting on the connection terminal part 70 due to the difference in thermal expansion can be effectively reduced.

[0039] The columnar electrode 40 is formed by being laminated on the first conductive portion 30. The columnar electrode 40 is an electrode member having a first end portion 41 connected to the first conductive portion 30, a second end portion 42 on the axially opposite side of the first end portion 41 where the connection terminal portion 70 and the like are formed, and a side surface 43 connecting the first end portion 41 and the second end portion. The columnar electrode 40 can be formed from a metal pin (copper pin) whose main component is copper, or a columnar member made of copper plating formed by a known plating method such as electroplating or chemical plating. By using a copper pin for the columnar electrode 40, it is possible to simply place the metal pin that functions as an electrode at the position where the first conductive portion 30 is formed, thereby improving assembly efficiency during manufacturing.

[0040] The sealing resin layer 50 is formed around at least the semiconductor chip 20 and covers the side surface 31 of the first conductive part 30 and the side surface 43 of the columnar electrode 40. As shown in Fig. 2, the sealing resin layer 50 is formed so as to cover the wiring layer 11 while exposing the second surface 21b of the semiconductor chip and the second end portion 42 of the columnar electrode 40.

[0041] In the semiconductor package 1, it is preferable that the exposed surface 42a of the second end 42 and the second surface 21b of the semiconductor chip 20 are positioned at approximately the same height in the thickness direction. This allows the second conductive portion 60 and the connection terminal portion 70 to be formed so that they have the same height in the thickness direction, thereby improving ease of manufacturing. Furthermore, in the semiconductor package 1, the connection terminal portion 70 stacked on the columnar electrode 40 and the connection terminal portion 70 stacked on the second surface 21b of the semiconductor chip 20 are positioned at the same height in the thickness direction, making package assembly easier.

[0042] The encapsulating resin layer 50 is made of an insulating resin such as an epoxy resin that can be used as a potting resin. The encapsulating resin layer 50 preferably contains a non-conductive filler such as a spherical or flat inorganic filler such as silica. The content of the non-conductive filler in the encapsulating resin layer 50 can be adjusted to maximize the solder connection reliability of the semiconductor package 1. By adjusting the filler content of the encapsulating resin layer 50, the linear expansion coefficient and elastic modulus of the encapsulating resin layer 50 itself can be adjusted. Therefore, by including an encapsulating resin layer 50 whose filler content is adjusted to maximize the solder connection reliability, the semiconductor package 1 becomes a package with excellent solder connection reliability.

[0043] The sealing resin layer 50 has a linear expansion coefficient equal to or greater than that of the chip substrate 21 of the semiconductor chip 20. The linear expansion coefficient of the sealing resin layer 50 is 5 to 15 ppm / °C, which is higher than that of the chip substrate 21 of the semiconductor chip 20 (up to 3 ppm / °C) and close to that of the mounting substrate 200 (15 to 20 ppm / °C). By being formed between the semiconductor chip 20 and the mounting substrate 200, the sealing resin layer 50 can function as a stress relaxation layer that significantly reduces stress on the connection terminal portions 70 due to temperature changes that may occur between the semiconductor chip 20 and the mounting substrate 200.

[0044] When the semiconductor chip 20 is configured as an image sensor, the encapsulating resin layer 50 preferably has a light-shielding portion 51 that blocks light of the wavelength to which the image sensor is sensitive. The encapsulating resin layer 50 may contain a light-shielding material such as carbon or a filler to achieve the above-mentioned light-shielding properties, allowing the entire layer to function as the light-shielding portion 51. Alternatively, the encapsulating resin layer 50 may be formed with a film material or layer that achieves the above-mentioned light-shielding properties, so as to cover part or all of the encapsulating resin layer 50 as the light-shielding portion 51. By forming the light-shielding portion 51 in the encapsulating resin layer 50, the semiconductor package 1 equipped with an image sensor can reduce the adverse effects on the sensor of stray light such as reflected light and scattered light.

[0045] The second conductive portion 60 is formed on the exposed surface 42a of the second end portion 42 of the columnar electrode 40 and on the second surface 21b of the semiconductor chip 20. The second conductive portion 60 is made of a conductive material, and is preferably formed of a material containing copper as a main component, such as copper paste or copper plating. The second conductive portion 60 can be formed by screen printing, inkjet printing, or the like, with a mask applied to areas other than the formation position.

[0046] The second conductive portion 60 functions as a conductive layer that electrically connects the columnar electrode 40 and the connection terminal portion 70. The second conductive portion 60 can be formed to have an area equal to or larger than the area of ​​the exposed surface 42a of the second end portion 42 of the columnar electrode 40. This allows the semiconductor package 1 to adjust the size of the connection terminal portion 70 in accordance with the area size of the second conductive portion 60 when forming the connection terminal portion 70 on the second conductive portion 60.

[0047] Furthermore, by forming the second conductive portion 60 on the second surface 21b of the semiconductor chip 20, the second conductive portion 60 functions as a die pad for the semiconductor chip 20, either alone or in combination with the connection terminal portion 70. This allows the semiconductor package 1 to dissipate heat generated by the semiconductor chip 20 to the mounting substrate 200 with high efficiency. Furthermore, by forming the second conductive portion 60 on the second surface 21b of the semiconductor chip 20, the second conductive portion 60 can also provide a shielding effect against electrical noise from the mounting substrate 200. In addition, the second conductive portion 60 also has the effect of reducing stress on the columnar electrodes 40 arranged around the semiconductor chip 20. Forming the second conductive portion 60 over the entire second surface 21b of the semiconductor chip 20 is preferable because it effectively achieves the above-mentioned effect. However, the second conductive portion 60 may also be formed on only a portion of the second surface 21b of the semiconductor chip 20.

[0048] The connection terminal portion 70 is formed on the exposed surface 42a of the second end portion 42 of the columnar electrode 40 or on the second conductive portion 60 formed on the second surface 21b of the semiconductor chip 20. The connection terminal portion 70 can be formed of a conductive material such as solder. In the configuration shown in FIG. 2, the connection terminal portion 70 is formed by stacking on the second conductive portion 60 formed on the columnar electrode 40 and the second conductive portion 60 formed on the second surface 21b of the semiconductor chip 20, but a configuration in which the connection terminal portion 70 is not formed on either or both of the second conductive portions 60 may also be used.

[0049] Next, a description will be given of a method for manufacturing the semiconductor package 1. The method for manufacturing the semiconductor package 1 includes the following steps 1 to 9. FIGS. 3A to 3I show configuration diagrams of each step (step 1 to step 9) included in the manufacturing process of the semiconductor package 1.

[0050] (Process 1) 3A, step 1 involves forming electrodes 23 on a first surface Wa of a semiconductor wafer W that will become a chip substrate 21 of a semiconductor chip 20. The electrodes 23 can be formed as stud bumps 23b made of gold (Au) or the like on bonding pads 23a.

[0051] (Process 2) 3B, in step 2, a process is performed to form a wiring layer 11 on a second surface Gb opposite to the first surface Ga of the glass substrate G that will become the transparent substrate 10. The wiring layer 11 is formed by forming copper (Cu) wiring and then plating the surface with gold (Au).

[0052] (Step 3) In step 3, as shown in FIG. 3C , a conductive paste is applied to the wiring layer 11 formed on the glass substrate G so as to be laminated thereon, thereby forming the first conductive portion 30. The first conductive portion 30 is formed on the wiring layer 11 corresponding to the position where the columnar electrode 40 is to be formed. The formation process of the first conductive portion 30 can be performed by screen printing, inkjet printing, or the like, with a mask applied to areas other than the formation position.

[0053] (Step 4) In step 4, as shown in FIG. 3D, a columnar electrode 40 is disposed on the first conductive portion 30. The process of disposing the columnar electrode 40 is similar to the ball mounting method and can be performed by applying a mask to the area other than the first conductive portion 30 so that the first conductive portion 30 shown in FIG. 3C is exposed; transporting multiple copper pins that will become the columnar electrodes 40 over the mask and disposing the copper pins through openings in the mask to contact each of the first conductive portions 30; and removing the mask and drying, baking, and hardening the first conductive portion 30. The end of the columnar electrode 40 that contacts the first conductive portion 30 is the first end 41.

[0054] (Step 5) 3E, in step 5, the semiconductor chip 20 on which the electrodes 23 have been formed in step 1 is flip-chip mounted on the transparent substrate 10. The semiconductor chip 20 is electrically connected to the wiring layer 11 of the transparent substrate 10 via the electrodes 23.

[0055] (Step 6) In step 6, as shown in FIG. 3F, a process for forming the encapsulating resin layer 50 is performed. The encapsulating resin layer 50 is formed by applying a resin containing a non-conductive filler such as epoxy resin, followed by a grinding process so that the exposed surfaces 42a of the second ends 42 of the columnar electrodes 40 are exposed. The grinding process involves back-grinding the second surface Wb of the semiconductor wafer W to a thickness corresponding to a predetermined chip size, and also back-grinding so that the second ends 42 of the columnar electrodes 40 are exposed from the surface of the encapsulating resin layer 50. As a result, the encapsulating resin layer 50 is formed to cover the first conductive parts 30, the side surfaces 43 of the columnar electrodes 40, and the wiring layer 11, with the second ends 42 of the columnar electrodes 40 exposed.

[0056] (Step 7) 3G, step 7 involves forming the second conductive portion 60 on the exposed surface 42a of the second end 42 of the columnar electrode 40 and on the second surface 21b of the semiconductor chip 20. The process of forming the second conductive portion 60 can be performed by screen printing, inkjet printing, or the like, with a mask applied to areas other than the formation position.

[0057] (Step 8) 3H, step 8 involves forming connection terminal portions 70 on the second conductive portions 60 formed on the columnar electrodes 40 and the semiconductor chip 20. The connection terminal portions 70 can be formed on the second ends 42 of the columnar electrodes 40 or the second surface 21b of the semiconductor chip 20 by a ball mounting method, a screen printing method, or the like. In step 8, from the viewpoint of ease of mounting, it is preferable to form the height positions of the contact surfaces of the connection terminal portions 70 relative to the mounting substrate 200 so that they are at approximately the same position in the thickness direction of the semiconductor package 1.

[0058] (Step 9) In step 9, as shown in Fig. 3I, a process is performed in which the glass substrate G is cut at predetermined locations to singulate the semiconductor packages 1. Through the above steps, the semiconductor package 1 shown in Fig. 3J is manufactured.

[0059] The above-described method for manufacturing the semiconductor package 1 may include, as necessary, a step of carrying out a process other than steps 1 to 9 (such as a step of carrying out a cleaning process). Furthermore, in the method for manufacturing the semiconductor package 1, the order of the steps may be appropriately changed as long as the configuration and function of the manufactured semiconductor package 1 do not deviate from the gist of the present invention.

[0060] In the above-described manufacturing method, the semiconductor package 1 may be configured such that the connection terminal portions 70 are not formed on the second ends 42 of the columnar electrodes 40 or the second conductive portions 60 formed on the second surface 21b of the semiconductor chip 20. In this case, the processing in step 8 is omitted.

[0061] The semiconductor package 1 of the present invention can be implemented by appropriately modifying it as shown in the following modified examples. Note that the following description of each modified example mainly focuses on the differences from the above-described embodiment, and components having equivalent functions to those of other embodiments are denoted by the same or related reference numerals, and detailed description thereof is omitted, and no particular mention is made. Furthermore, the configuration, members, and usage method may be the same as those of each embodiment. Furthermore, each modified example can be implemented in combination with other embodiments by appropriately selecting necessary components from those shown in each modified example, within the scope of the gist of the present invention.

[0062] A semiconductor package 1A according to the first modified example will be described.

[0063] 4 shows a configuration diagram of a semiconductor package 1A of Modified Example 1. The semiconductor package 1A differs from other types of packages in that at least a portion of the sealing resin layer 50 between the transparent substrate 10 and the semiconductor chip 20 is formed by an underfill layer 80.

[0064] The encapsulating resin layer 50 is formed to cover the periphery of the semiconductor chip 20 after the semiconductor chip 20 is mounted on the transparent substrate 10, but it is difficult to make it extend to the chip surface. For this reason, the semiconductor package 1A can easily achieve the desired encapsulation by forming an underfill layer 80 made of an underfill material mainly made of epoxy resin or the like in at least a portion between the transparent substrate 10 and the semiconductor chip 20, and then forming the encapsulating resin layer 50. The underfill layer 80 can be formed of a resin that is an insulator having insulating properties.

[0065] In the method for manufacturing the semiconductor package 1A, the step of forming the underfill layer 80 can be performed between step 5 shown in Fig. 3E and step 6 shown in Fig. 3F. That is, after the semiconductor chip 20 is mounted on the transparent substrate 10 in step 5, an underfill material is inserted between the transparent substrate 10 and the semiconductor chip 20 to form the underfill layer 80. Thereafter, step 6 is performed to form the sealing resin layer 50.

[0066] Next, a semiconductor package 1B according to a second modified example will be described.

[0067] 5 shows a configuration diagram of a semiconductor package 1B. The semiconductor package 1B differs from other packages in that a groove 52 is formed in the sealing resin layer 50.

[0068] The sealing resin layer 50 has grooves 52. The grooves 52 have the effect of significantly reducing deformation (warping, etc.) of the package itself due to stress when the sealing resin layer 50 is soldered and temperature changes.

[0069] As shown in Fig. 5A, the groove 52 can be formed between adjacent columnar electrodes 40 in a direction intersecting the thickness direction of the semiconductor package 1B (the left-right direction in the figure). As shown in Fig. 5B, the groove 52 can have a shape in which a portion of the periphery of the semiconductor package 1B is removed. The groove 52 shown in Figs. 5A and 5B may be formed in advance by forming the sealing resin layer 50 into the shape shown in the figure, or may be shaped by removing a portion from the shape shown in Fig. 2, etc.

[0070] Note that the groove portion 52 is not limited to the shape or the position shown in Figures 5A and 5B, as long as it is formed at a position where the stress applied to the sealing resin layer 50 can be alleviated and has a shape that provides a stress alleviation effect.

[0071] In the method for manufacturing the semiconductor package 1B, the step of forming the groove 52 can be performed between step 10 shown in Fig. 3J and step 11 shown in Fig. 3K. That is, after the encapsulating resin layer 50 is formed in step 10, the groove 52 can be formed by removing a portion of the encapsulating resin layer 50. Note that if the encapsulating resin layer 50 is formed with the groove 52 already formed, the above-mentioned removal step is unnecessary.

[0072] As described above, the semiconductor packages 1, 1A, and 1B according to the present invention include a semiconductor chip 20 having electrodes 23 formed on a first surface 21a of a chip substrate 21, which is a surface on which light is incident, a transparent substrate 10 having a wiring layer 11, columnar electrodes 40 electrically connected to the electrodes 23 via the wiring layer 11, and a sealing resin layer 50 formed around the semiconductor chip 20 and on the wiring layer 11 side of the transparent substrate 10, and the columnar electrodes 40 are connected to the wiring layer 11 via first conductive portions 30. The columnar electrode 40 has a first end 41 connected to the first conductive portion 30, a second end 42 opposite the first end 41, and a side surface 43 connecting the first end 41 and the second end 42, the sealing resin layer 50 is formed to cover the side surface 43 of the columnar electrode 40 and the side surface 31 of the first conductive portion 30 so that the second end of the columnar electrode 40 is exposed, and a second conductive portion 60 is formed on the second surface 21b opposite the first surface 21a of the chip substrate 21 and on the exposed surface 42a of the second end 42 of the columnar electrode 40.

[0073] The semiconductor package 1 includes a first conductive portion 30 interposed between the wiring layer 11 and the columnar electrode 40, and a sealing resin layer 50 formed to cover the side surface 31 of the first conductive portion 30 and the side surface 43 of the columnar electrode 40. This significantly reduces solder stress caused by temperature changes when the semiconductor package 1 is mounted on a mounting substrate 200. Furthermore, by providing a second conductive portion 60 on the exposed surface 42a of the second end 42 of the columnar electrode 40 and the second surface 21b of the semiconductor chip 20, stress on the connection terminal portion 70 formed on the columnar electrode 40 can be more effectively reduced. Furthermore, the second conductive portion 60 formed on the second surface 21b of the semiconductor chip 20 functions as a die pad, allowing for efficient heat dissipation from the semiconductor chip 20 to the mounting substrate 200 and providing effective shielding against electrical noise from the mounting substrate 200. Therefore, the semiconductor package 1 significantly improves solder connection reliability, package mounting heat dissipation, and electromagnetic shielding. [Example]

[0074] The effects of the present invention will be explained using the following examples and comparative examples, although the technical scope of the present invention is not limited to the following examples.

[0075] In the following evaluation test, the solder connection reliability of the semiconductor package according to the present invention was evaluated based on the results of a simulation of solder life.

[0076] <Test Overview> The evaluation test was carried out as follows. The structural analysis software used in the evaluation test was "Marc2023 (manufactured by MSC Software Co., Ltd.)." The solder life simulation can be carried out by a known method such as the method described in a prior art document ("Thermal Fatigue Life Prediction of Lead-Free Solder Joints," Technical Report, Technology Introduction, 2013-12, No. 49, by Tetsuya Ima, Yamaha Motor Co., Ltd.).

[0077] The following conditions were set for the simulation. The example model was a model simulating the semiconductor package of the present invention, as shown in Figure 2, while the comparative example model was a model simulating a typical fan-out semiconductor package. A quarter-size model was used for each model, taking symmetry into consideration. This "quarter-size model" refers to a simulation modeling that targets only a quarter of the package, with left-right and top-bottom symmetry, rather than the entire package. The element class was a hexahedron with 20 nodes. The boundary conditions included symmetry constraints and time-dependent temperature for all nodes. The temperature-dependent test conditions were as follows: the initial temperature was 175°C, the curing temperature of the stress relief layer, and after cooling to room temperature (25°C), 10 cycles of temperature cycling from -55°C to 125°C were performed. Temperature-independent elastic properties were defined for the substrate, semiconductor chip, transparent substrate, wiring layer, first conductive layer, and DAM agent, while viscoelasticity was set for the potting resin. Plasticity was also set for the solder.

[0078] In order to determine the solder life, the test obtained the time-plastic strain history of the node with the maximum total plastic strain from the simulation results, and from this, the plastic strain at the 10th cycle was extracted and used as the plastic strain amplitude. The number of solder life cycles was calculated from the obtained plastic strain amplitude and the Coffin-Manson law. It is known that the number of solder fatigue life cycles follows the Coffin-Manson law.

[0079] <Evaluation results> The evaluation results are shown in Figure 6. The evaluation results shown in Figure 6 show the predicted results for the number of temperature cycles for the example and comparative example. The predicted results in Figure 6 show that the greater the number of temperature cycles, the longer the solder life, indicating higher solder connection reliability.

[0080] As shown in Figure 6, the number of temperature cycles in the comparative example was 182. In contrast, the number in the working example was 741. From these results, it was confirmed that the solder life was increased by approximately four times when the structure of the present invention was adopted.

[0081] As described above, the semiconductor package of the present invention comprises a first conductive portion interposed between the wiring layer of the semiconductor chip and the columnar electrode electrically connected thereto, a sealing resin layer formed around the semiconductor chip and on the wiring layer side of the transparent substrate so as to cover the side surfaces of the columnar electrode and the first conductive portion, and a second conductive portion formed at the second end of the columnar electrode, and therefore can be said to be able to reduce solder stress caused by temperature changes during package assembly and improve solder connection reliability. [Explanation of symbols]

[0082] 1, 1A, 1B semiconductor packages, 10 transparent substrate, 10a: a first surface of a transparent substrate; 10b: a second surface of the transparent substrate; 11 wiring layer, 20 semiconductor chips, 21 chip substrate, 21a: a first surface of the chip substrate; 21b a second surface of the chip substrate; 22 microlenses, 23 electrodes, 23a Bonding pad, 23b stud bump, 30 first conductive part, 31 side surface of the first conductive part, 40 columnar electrodes, 41 first end; 42 second end; 42a Exposed surface, 43 Side of the columnar electrode, 50 Sealing resin layer, 51 light-shielding part, 52 groove portion, 60 second conductive portion, 70 connection terminal part, 80 underfill layer, 200 mounting boards.

Claims

1. a semiconductor chip having an electrode formed on a first surface of a chip substrate, the first surface being a surface on which light is incident; a transparent substrate having a wiring layer; columnar electrodes electrically connected to the electrodes via the wiring layer; and a sealing resin layer formed around the semiconductor chip and on the wiring layer side of the transparent substrate; the pillar-shaped electrode is connected to the wiring layer via a first conductive portion; the pillar-shaped electrode has a first end connected to the first conductive portion, a second end opposite to the first end, and a side surface connecting the first end and the second end, the sealing resin layer is formed to cover the side surface of the pillar-shaped electrode and the side surface of the first conductive portion so that the second end of the pillar-shaped electrode is exposed; a second conductive portion formed on a second surface of the chip substrate opposite the first surface and on an exposed surface of the second end of the columnar electrode;

2. The semiconductor package according to claim 1 , wherein the first conductive portion has a lower elastic modulus than the columnar electrode.

3. The semiconductor package according to claim 1 , wherein at least a portion of the sealing resin layer formed between the semiconductor chip and the transparent substrate is formed of an underfill layer.

4. 2. The semiconductor package of claim 1, wherein the second conductive portion is formed on the exposed surface of the second end of the columnar electrode, with an area equal to or greater than the exposed surface, and is formed to cover the entire second surface of the semiconductor chip.

5. The semiconductor package according to claim 1 , wherein the pillar-shaped electrodes are formed of metal pins.

6. The semiconductor package according to claim 1 , wherein the sealing resin layer contains a non-conductive filler.

7. 2. The semiconductor package according to claim 1, wherein the coefficient of linear expansion of the sealing resin layer is equal to or greater than the coefficient of linear expansion of the chip substrate of the semiconductor chip.

8. The semiconductor package according to claim 1 , wherein the first conductive portion is formed of a conductive paste or a solder.

9. The semiconductor package according to claim 3 , wherein the second conductive portion is formed of a material containing copper as a main component.

10. The semiconductor package according to claim 1 , wherein the sealing resin layer has a groove formed in at least a part of the periphery of the columnar electrode.

11. The semiconductor package according to claim 4 , wherein a connection terminal portion is provided on the exposed surface of the second end portion of the columnar electrode and / or the second conductive portion.

12. The semiconductor package according to claim 1 , wherein the semiconductor chip is an image sensor.

13. The semiconductor package according to claim 12 , wherein the sealing resin layer has a light-shielding portion that blocks light having a sensitivity wavelength of the image sensor.

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