Circuit board and power device

Abstract

To provide a circuit board and a power device that can enhance resistance to cold-heat cycles and improve reliability.SOLUTION: A circuit board 50 includes a ceramic substrate 10, a bonding layer 20 formed on one main surface 12 of the ceramic substrate 10, and a conductor layer 30 made of metal bonded to the ceramic substrate 10 via the bonding layer 20, and the ceramic substrate 10 has microcracks 14 that open on the interface with the bonding layer 20 and are composed of voids.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a circuit board and a power device. [Background technology]

[0002] Silicon nitride, with its high thermal conductivity and strength, is attracting attention as an insulating heat dissipation substrate for inverter power modules installed in electric vehicles (EVs) and hybrid vehicles (HVs). Traditionally, aluminum nitride has been widely used as an insulating heat dissipation substrate material. However, in the case of high-current power modules such as those used in EVs, temperatures reach approximately 250°C, and the difference in thermal expansion between the substrate and the copper or other metals to which it is bonded generates significant thermal stress, causing the aluminum nitride, which has low strength, to crack and break. Therefore, silicon nitride, which has a higher thermal conductivity than common insulating ceramics and is even stronger, is increasingly being adopted, although its thermal conductivity is inferior to that of aluminum nitride. The bonding of silicon nitride heat dissipation substrates to conductor layers is generally performed using a brazing method involving the use of a brazing filler metal containing metal.

[0003] Patent Document 1 discloses a copper / ceramic joined body comprising a copper member made of copper or a copper alloy and a ceramic member, the copper member and the ceramic member being joined together, an active metal compound layer made of an active metal compound being formed on the ceramic member side at the joining interface between the ceramic member and the copper member, microcracks existing in the ceramic member that propagate from the joining interface toward the interior of the ceramic member, and the active metal compound being filled in at least a portion of the microcracks. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2023-086688 Summary of the Invention [Problem to be solved by the invention]

[0005] Patent Document 1 describes that filling at least a portion of the microcracks with an active metal compound can suppress the occurrence of ceramic cracks originating from the microcracks, thereby suppressing the occurrence of cracks in the ceramic member during thermal cycling. Furthermore, the anchoring effect of the active metal compound filled in the microcracks can improve the bonding strength between the ceramic member and the copper member. However, the copper / ceramic bonded body described in Patent Document 1 has a thick Ag-Cu alloy layer derived from the bonding material, which may act as a thermal barrier between the ceramic substrate and the circuit layer. Furthermore, under more severe thermal cycling conditions, the difference in thermal expansion coefficient between the ceramic member and the active metal compound filled in the microcracks can cause the microcracks to propagate, resulting in insufficient resistance to thermal cycling.

[0006] For these reasons, when a circuit board in which a ceramic heat dissipation substrate and a conductor layer are bonded together is used as a circuit board for a power device, there has been a demand for a circuit board with improved resistance to thermal cycles.

[0007] The present invention has been made in view of the above circumstances, and has an object to provide a circuit board and a power device that can enhance resistance to thermal cycles and improve reliability. [Means for solving the problem]

[0008] (1) In order to achieve the above object, the circuit board of the present invention employs the following measures: That is, a circuit board according to an application example of the present invention includes a ceramic substrate, a bonding layer formed on one main surface of the ceramic substrate, and a conductor layer made of metal bonded to the ceramic substrate via the bonding layer, and the ceramic substrate has microcracks that open to the interface with the bonding layer and are voids.

[0009] (2) In addition, in the circuit board of the application example of (1) above, the microcracks include those having a length of 1 μm or more and 3 μm or less, and the average angle of the microcracks having a length of 1 μm or more and 3 μm or less with respect to the direction perpendicular to the interface is 0° or more and 80° or less.

[0010] (3) In the circuit board according to the application example of (1) or (2) above, the bonding layer contains titanium as a main component.

[0011] (4) Furthermore, in the circuit board of any of the application examples (1) to (3) above, the circuit board further comprises a second bonding layer containing titanium formed on the other main surface opposite the one main surface of the ceramic substrate, and a second conductor layer containing copper bonded to the ceramic substrate via the second bonding layer, wherein the bonding layer contains titanium, the conductor layer contains copper, and the thermal conductivity in a direction perpendicular to the one main surface of the circuit board is 150 W / mK or more.

[0012] (5) A power device according to an application example of the present invention includes the circuit board according to any one of (1) to (4) above, and a power semiconductor mounted on the conductor layer. [Effects of the Invention]

[0013] According to the circuit board or power device of the present invention, it is possible to improve the resistance to thermal cycles, and it is possible to provide a circuit board or power device with improved reliability. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating an example of a circuit board according to an embodiment. [Figure 2] FIG. 2 is a schematic plan view illustrating an example of a circuit board according to an embodiment. [Figure 3] FIG. 2 is a schematic enlarged partial cross-sectional view showing an example of a circuit board according to an embodiment. [Figure 4] 1(a) to 1(c) are schematic diagrams each showing an example of a microcrack in a circuit board according to an embodiment. [Figure 5] FIG. 10 is a schematic cross-sectional view showing a modified example of the circuit board according to the embodiment. [Figure 6] FIG. 10 is a schematic bottom view showing a modified example of the circuit board according to the embodiment. [Figure 7] 1 is a schematic cross-sectional view showing an example of a power device according to an embodiment. [Figure 8] 1 is a table showing polishing conditions, metal layer formation methods, and various test results for circuit boards of Examples and Comparative Examples. DETAILED DESCRIPTION OF THE INVENTION

[0015] Next, an embodiment of the present invention will be described with reference to the drawings. To facilitate understanding of the description, the same reference numerals are used to designate the same components in the drawings, and duplicated descriptions will be omitted. Note that in the configuration diagrams, the size of each component is shown conceptually and does not necessarily represent the actual dimensional ratio.

[0016] [Circuit board configuration] (Embodiment) First, a circuit board according to an embodiment of the present invention will be described. FIG. 1 is a schematic cross-sectional view showing an example of a circuit board 50 according to an embodiment of the present invention. FIG. 2 is a schematic plan view showing an example of a circuit board 50 according to an embodiment of the present invention. FIG. 3 is a schematic partially enlarged cross-sectional view showing an example of a circuit board according to an embodiment of the present invention. The circuit board 50 according to an embodiment of the present invention includes a ceramic substrate 10, a bonding layer 20, and a conductor layer 30.

[0017] The ceramic substrate 10 is made of ceramic. The ceramic substrate 10 can be formed of ceramics containing, for example, silicon nitride, aluminum nitride, aluminum oxide, etc. The ceramic substrate 10 is preferably made of a material containing silicon nitride as a main component. "Containing silicon nitride as a main component" means that the ceramic substrate 10 contains 86 wt% or more of silicon nitride. When the ceramic substrate 10 is made of a material containing silicon nitride as a main component, the ceramic substrate 10 may also contain sialon. The ceramic substrate 10 is formed, for example, in the shape of a flat plate.

[0018] The thickness of the ceramic substrate 10 in the direction perpendicular to one main surface 12 is preferably 220 μm or more and 690 μm or less. This allows a good balance between the strength and heat dissipation of the ceramic substrate 10. If the thickness is smaller than this range, the strength of the ceramic substrate 10 may be reduced. On the other hand, if the thickness is larger than this range, the heat dissipation properties may be reduced.

[0019] The ceramic substrate 10 has microcracks 14 formed from voids that open at the interface (one of the main surfaces 12) with the bonding layer 20, which will be described later. Cracks that occur in the ceramic substrate 10 due to the difference in thermal expansion coefficient between the conductor layer 30 and the ceramic substrate 10 extend in a direction generally parallel to the bonding interface. The circuit board 50 of the present invention has microcracks 14 in the thickness direction of the ceramic substrate 10, which can suppress the extension of cracks in the ceramic substrate 10. Furthermore, even if a crack extends beyond the microcracks 14, the direction of the crack can be changed, preventing the crack from extending linearly. As a result, resistance to thermal cycles can be increased, and the reliability of the circuit board 50 can be improved.

[0020] The microcracks 14 being voids means that 90% or more of the line segment defining the length of the microcracks 14, as described below, is void. This also means that the material forming the bonding layer 20 is not substantially filled into the microcracks 14. This is because if the material forming the bonding layer 20 penetrates into the microcracks 14, the microcracks 14 themselves may extend during severe thermal cycling. Ten randomly selected locations on the polished surface of a cross section perpendicular to one of the main surfaces 12 of the ceramic substrate 10 are observed at 5000x magnification in a 16 μm × 20 μm field of view. The average number of microcracks 14 at these 10 locations is preferably between one and five. However, microcracks with a length of less than 0.1 μm, as measured by the method described below, are not included in the microcracks 14 of the present invention.

[0021] The length of the microcracks 14 is preferably 1 μm or more and 3 μm or less. This is because microcracks with a length of less than 1 μm have a reduced effect of suppressing crack extension. Furthermore, microcracks with a length of more than 3 μm may themselves extend. Therefore, it is preferable that the microcracks 14 do not include any microcracks with a length of more than 3 μm. "Not including any microcracks 14 with a length of more than 3 μm" means that no microcracks 14 with a length of more than 3 μm are observed in the SEM images of 10 locations described below. The average angle of the microcracks 14 with respect to the direction perpendicular to the interface is preferably 0° or more and 80° or less. The average angle of the microcracks 14 is the average angle measured for microcracks with a length of more than 1 μm and less than 3 μm. If the average angle exceeds 80°, it will generally coincide with the crack extension direction, and peeling may not be suppressed. When the average angle is 80° or less, the direction of crack propagation can be changed, and peeling can be suppressed. This can further increase resistance to thermal cycles and improve the reliability of the circuit board 50. The average angle of the microcracks 14 is more preferably 0° or more and 70° or less, and even more preferably 0° or more and 60° or less. Furthermore, the aspect ratio of the microcracks is preferably 3 or more, more preferably 4 or more, and even more preferably 5 or more.

[0022] 4(a) to 4(c) are schematic diagrams showing examples of microcracks 14 in a circuit board 50 according to an embodiment of the present invention. The length and angle of the microcracks 14 can be determined by SEM (Scanning Electron Microscope) observation. Specifically, 10 locations are randomly selected on the polished surface of a cross section perpendicular to one main surface 12 of the ceramic substrate 10, and a 16 μm × 20 μm field of view is observed at 5000x magnification. The length or angle of the microcracks 14 that are entirely within the observed field of view is determined according to the following criteria. The fact that the microcracks 14 are voids can be confirmed from the EPMA results described below for the same screen as the SEM image.

[0023] 4(a), when the microcrack 14 is linear, the length of the microcrack 14 is the distance between P and Q, where P is the midpoint of the opening P1P2 at the interface between the ceramic substrate 10 and the bonding layer 20, and Q is the point of the microcrack 14 that is deepest in the direction perpendicular to the reference interface. Furthermore, when the intersections of the perpendicular bisector M of PQ with P1Q and P2Q are P3 and P4, respectively, the aspect ratio is PQ / P3P4. Note that if the actual interface on the SEM image is not linear, the reference interface is the same as the reference line described below.

[0024] As shown in FIG. 4(b), when the microcrack 14 is a broken line, the length of the microcrack 14 is defined as PR+RQ, where P is the midpoint of the opening P1P2 at the interface between the ceramic substrate 10 and the bonding layer 20, R is the midpoint of the line connecting the corners R1 and R2 of the broken line, and Q is the point of the microcrack 14 that is deepest in the direction perpendicular to the reference interface. Also, T is the midpoint of PR+RQ, and M is the perpendicular line of PR or RQ that passes through T (PR⊥M in FIG. 4(b)). Furthermore, P3 is the intersection point of M with P1R1 or R1Q, and P4 is the intersection point of M with P2R2 or R2Q. The same applies when one microcrack 14 is broken two or more times. In addition, when the microcrack 14 is curved, the total length is the sum of the line segments drawn for each short section that can be regarded as a straight line in an SEM image at a magnification of less than 5000 times.

[0025] As shown in Figure 4(c), when a microcrack 14 splits into two, the length of the microcrack 14 is calculated by dividing the length of the first microcrack 14 and the second microcrack 14. In Figure 4(c), the length of the microcrack 14 on the right side, which is considered to have split first, is PR+RQ. The length of the microcrack 14 on the left side, which is considered to have split later, is P'R'. R' is the midpoint of the boundary line dividing the microcrack 14 into two. The aspect ratio is calculated as described above for each split microcrack. The same applies when the microcrack splits into three or more parts. Note that if the actual interface in the SEM image is not parallel to the reference interface, microcracks with a 90° angle may exist. The length of such a microcrack is the distance from end to end of only the 90° portion.

[0026] The distance P1P2 between the openings of the microcracks 14 is preferably 0.5 μm or less, because if the openings are larger than this, the material that forms the bonding layer 20 will easily get into the microcracks 14.

[0027] The angle of the microcrack 14 with respect to the direction perpendicular to the interface is defined as the angle θ between a line L that passes through the midpoint P of the opening and is perpendicular to the interface, and a line segment closer to the interface, as shown in Figures 4(a) to 4(c).

[0028] The bonding layer 20 is formed on one main surface 12 of the ceramic substrate 10. The bonding layer 20 preferably contains titanium, and more preferably has titanium as its main component. This increases the bonding strength between the ceramic substrate 10 and the conductor layer 30 while maintaining the heat transfer between the ceramic substrate 10 and the conductor layer 30. The bonding layer 20 may also include a layer other than the layer containing titanium as its main component (a layer that can be distinguished from the layer containing titanium as its main component by SEM imaging or EPMA).

[0029] The thickness of the bonding layer 20 is preferably 0.1 μm or more and 5 μm or less. The thickness of the bonding layer 20 can be determined by SEM observation. Specifically, 10 random locations are selected on the polished surface of a cross section perpendicular to one of the main surfaces 12 of the ceramic substrate 10, and a 16 μm × 20 μm field of view is observed at 5000x magnification. Next, 10 lines are drawn at equal intervals perpendicular to a 10 μm line drawn at the interface between the ceramic substrate 10 and the bonding layer 20, and the lengths between the interfaces of each layer are determined. The average of these values ​​is then used as the thickness of the bonding layer 20. Note that if the interface between the ceramic substrate 10 and the bonding layer 20 is not a straight line in the SEM image, a line drawn at the interface in a lower magnification SEM image where the interface between the ceramic substrate 10 and the bonding layer 20 can be considered a straight line is used as the reference line. Furthermore, the interfaces of each layer can be distinguished because each layer has a different color tone in the SEM image.

[0030] The types and proportions of elements contained in the ceramic substrate 10, the bonding layer 20, and the conductor layer 30 can be measured by performing qualitative and quantitative analysis using an EPMA (Electron Probe Micro Analyzer) on a polished surface of a cut surface perpendicular to one main surface 12 of the ceramic substrate 10 of the circuit board 50.

[0031] The conductor layer 30 is made of a metal and is bonded to the ceramic substrate 10 via the bonding layer 20. The conductor layer 30 is preferably made of a metal containing copper, more preferably a metal containing copper as its main component, and even more preferably oxygen-free copper. A metal containing copper as its main component refers to a metal containing 99 wt% or more of copper. The thickness of the conductor layer 30 is preferably 0.2 mm or more and 1.5 mm or less.

[0032] (Variation) Fig. 5 is a schematic cross-sectional view showing a modified example of a circuit board 50 according to an embodiment of the present invention. Fig. 6 is a schematic bottom view showing a modified example of a circuit board 50 according to an embodiment of the present invention. The circuit board 50 according to an embodiment of the present invention includes a ceramic substrate 10, a bonding layer 20, a conductor layer 30, a second bonding layer 26, and a second conductor layer 32. The configurations of the ceramic substrate 10, the bonding layer 20, and the conductor layer 30 are the same as those of the circuit board 50 described above.

[0033] Ceramic substrate 10 may have microcracks 14 that open at the interface with second bonding layer 26 (the other main surface 16 opposite one main surface 12) and that are not filled with the material that forms second bonding layer 26. This can increase the resistance to thermal cycles on the second bonding layer 26 side as well, improving reliability. It is preferable that microcracks 14 that open on the other main surface 16 side also have the above-mentioned characteristics.

[0034] Second bonding layer 26 is formed on the other main surface 16 of ceramic substrate 10. Second bonding layer 26 preferably contains titanium, and more preferably has titanium as its main component. This increases the bonding strength between ceramic substrate 10 and second conductor layer 32 while maintaining the heat transfer between ceramic substrate 10 and second conductor layer 32. When second bonding layer 26 includes a layer containing titanium as its main component, second bonding layer 26 may also include a layer other than the layer containing titanium as its main component (a layer that can be distinguished from the layer containing titanium as its main component by SEM imaging or EPMA).

[0035] The thickness of the second bonding layer 26 is preferably 0.1 μm or more and 5 μm or less. The thickness of the second bonding layer 26 may be the same as or different from the thickness of the bonding layer 20.

[0036] The second conductor layer 32 is made of a metal and is bonded to the ceramic substrate 10 via the second bonding layer 26. The second conductor layer 32 is preferably made of a metal containing copper, more preferably made of a metal primarily composed of copper, and even more preferably made of oxygen-free copper. The material of the second conductor layer 32 may be different from the material of the conductor layer 30, but is preferably the same. The thickness of the second conductor layer 32 is preferably 0.2 mm or more and 1.5 mm or less. The thickness of the second conductor layer 32 may be the same as or different from the thickness of the conductor layer 30.

[0037] 5, the second conductor layer 32 is preferably bonded to an area that occupies 75% or more of the area of ​​the other main surface 16 of the ceramic substrate 10. This allows heat to be dissipated efficiently from the second conductor layer 32, improving the heat dissipation performance of the circuit board 50.

[0038] The thermal conductivity of the circuit board 50 in the direction perpendicular to the one main surface 12 is preferably 150 W / mK or more. This sufficiently improves the heat dissipation properties of the circuit board 50. Note that the thermal conductivity in the direction perpendicular to the one main surface 12 of the circuit board 50 is measured for a circuit board 50 that includes a conductor layer 30 and a second conductor layer 32, such as the circuit board 50 of the modified example.

[0039] The thermal conductivity in the direction perpendicular to one main surface 12 of the circuit board 50 can be measured and calculated by a laser flash method.

[0040] These features can enhance the resistance to thermal cycles and improve the reliability of the circuit board 50. In addition, the bonding strength between the ceramic substrate 10 and the conductor layer 30 can be increased while maintaining the heat transfer between the ceramic substrate 10 and the conductor layer 30.

[0041] [Power device configuration] 7 is a schematic cross-sectional view showing an example of a power device according to an embodiment of the present invention. The power device 100 includes a circuit board 50 and a power semiconductor 60. In FIG. 7, the bonding layer 20, the second bonding layer 26, etc. of the circuit board 50 are omitted.

[0042] The circuit board 50 is the above-described circuit board 50. The circuit board 50 has a conductor layer 30 formed on at least one main surface 12 of the ceramic substrate 10. The circuit board 50 may have a second conductor layer 32 formed on the other main surface 16 opposite the one main surface 12.

[0043] A power semiconductor 60 is mounted on the upper side of the conductor layer 30 of the circuit board 50. The power semiconductor 60 and the conductor layer 30 may be joined using solder 52 or the like. The power semiconductor 60 may be, for example, a semiconductor for an EV that flows a large current and is prone to high temperatures. The circuit board 50 of the present invention has increased bonding strength while maintaining heat dissipation properties, and therefore has high resistance to thermal cycles. Therefore, even if a large thermal stress is generated in the ceramic substrate 10 due to the difference in thermal expansion between the ceramic substrate 10 and the joined metal due to high temperatures, cracks or breakage are unlikely to occur.

[0044] When the circuit board 50 includes the second conductor layer 32, the heat sink 70 may be bonded to the underside of the second conductor layer 32. The heat sink 70 and the second conductor layer 32 may be bonded using solder 52 or the like.

[0045] The surface of the heat sink 70 opposite to the surface bonded to the second conductor layer 32 may be in contact with the heat dissipation member 80 via grease 72 or the like. The heat sink 70 is preferably made of metal, more preferably made of a metal containing copper as its main component, and even more preferably made of oxygen-free copper. The heat dissipation member 80 preferably has heat dissipation fins formed thereon. The heat dissipation member 80 is preferably made of metal, more preferably made of a metal containing copper or aluminum as its main component.

[0046] [Circuit board manufacturing method] An example of a method for manufacturing the above-mentioned circuit board is shown below. A general silicon nitride sintered body can be used as the ceramic substrate. The silicon nitride sintered body can be manufactured, for example, by the following method. First, raw material powder for the silicon nitride sintered body is weighed. The raw material powder for the silicon nitride sintered body may be an oxide, carbonate, hydroxide, nitride, etc. of each element contained in the silicon nitride sintered body. In addition to silicon nitride, examples of raw material powder for the silicon nitride sintered body include magnesium carbonate, calcium carbonate, and yttrium oxide.

[0047] Ethanol is added to these raw material powders, and the mixture is wet mixed and pulverized in a ball mill at, for example, 60 rpm for 6 to 60 hours to obtain a slurry. The slurry is dried in a hot water bath or spray dryer to obtain a mixed powder.

[0048] Next, the mixed powder is filled into a mold and pressed uniaxially at a pressure of, for example, 30 MPa to form it into the desired shape. After that, a CIP (cold isostatic pressing) process is performed at a pressure of, for example, 150 MPa to obtain a green body. The obtained green body (CIP pressed body) is placed in a silicon carbide mold with the inside coated with BN, and sintered at a maximum temperature of 1800°C to 1900°C for 5 to 30 hours in a nitrogen atmosphere at 9 atmospheres to obtain a silicon nitride sintered body.

[0049] The resulting silicon nitride sintered body is processed to a predetermined shape and thickness to produce a ceramic substrate. Processing can be performed by, for example, cutting, grinding, polishing, etc. The main surface of the ceramic substrate on which the conductor layer or second conductor layer is bonded is preferably polished to a surface roughness Ra of 0.5 μm or less. At this time, grinding and polishing are performed so that microcracks with lengths of 1 μm to 3 μm are formed on at least one of the main surfaces. The length, number, and angle of the microcracks formed can be adjusted by adjusting the amount and speed of grinding and polishing.

[0050] Separately from the production of the ceramic substrate, a plate made of a metal with a predetermined thickness is prepared to serve as the conductor layer or second conductor layer. The plate is preferably made of a metal containing copper, more preferably made of a metal primarily composed of copper, and even more preferably made of oxygen-free copper. Next, a metal film primarily composed of Ti to serve as a bonding layer is formed on one main surface of the plate or ceramic substrate. The metal film can be formed by sputtering, vapor deposition, or the like. The thickness of the metal film is preferably 0.1 μm or more and 5 μm or less. A metal film to serve as a second bonding layer may be formed on the other main surface.

[0051] Next, the ceramic substrate and the plate material are stacked so that the metal film is sandwiched between them. Then, HP (hot pressing) or HIP (hot isostatic pressing) can be performed to bond the plate material and the ceramic substrate. The HP treatment conditions can be, for example, a pressure of 5 MPa to 30 MPa, a maximum temperature of 700°C to 980°C, and a maximum temperature holding time of 10 minutes to 2 hours. By bonding the ceramic substrate and the plate material with microcracks via a thin metal film formed by sputtering or the like, it is possible to prevent the material of the metal film from penetrating into the microcracks.

[0052] By using this manufacturing method, it is possible to manufacture a circuit board that has improved resistance to thermal cycles and improved reliability.

[0053] [Examples and Comparative Examples] Example 1 The raw material powders were weighed out to a total of 94 wt% silicon nitride powder (average particle size 1.4 μm), 3 wt% magnesium carbonate powder (average particle size 2.5 μm), and 3 wt% yttrium oxide powder (average particle size 1.0 μm). Next, the weighed raw material powders were ball milled to obtain a mixed slurry. For ball milling, the raw material powders and ethanol were placed in a resin pot and milled and mixed at 60 rpm for 24 hours using silicon nitride balls. The resulting mixed slurry was dried in a hot water bath to obtain a mixed powder.

[0054] The resulting mixed powder was subjected to powder press molding using uniaxial pressing and CIP to produce a compact. First, the mixed powder was filled into a dedicated mold and then preformed using uniaxial pressing at a pressure of 30 MPa. Next, the preform was placed in a dedicated bag via vacuum suction and subjected to CIP molding at a pressure of 150 MPa. The resulting compact was then fired. The sintering method involved atmospheric firing under a nitrogen gas pressure of 9 atmospheres, with the maximum temperature held at 1900°C for 10 hours. A silicon carbide mold with a BN-coated interior was used. The fired silicon nitride sintered compact was cut into pieces measuring 100 mm x 100 mm x 0.32 mm, and the surface roughness Ra of one and the other main surfaces of the ceramic substrate, which would serve as the bonding surfaces for the conductor layer and the second conductor layer, was polished to a value of 0.5 μm or less. The polishing amount was 5 μm, and the polishing speed was 10 mm / sec. In this manner, a ceramic substrate was prepared.

[0055] Separately, two oxygen-free copper plates (conductor layer, second conductor layer) measuring 100 mm × 100 mm × 0.5 mm were prepared. Next, a Ti-containing metal film was sputtered to a thickness of 0.1 μm to 5 μm on one main surface and the other main surface (the bonding surface with the plate) of a ceramic substrate with a thermal conductivity of 70 W / mK or more and a thickness of 0.32 mm. The conductor layer, ceramic substrate, and conductor layer (second conductor layer) were then stacked in this order and bonded by HP treatment (hot pressing). The pressure was 10 MPa, the maximum temperature was 900°C, and the maximum temperature was maintained for 30 minutes. In this way, the circuit board of Example 1 was produced.

[0056] Example 2 The circuit board of Example 2 was produced under the same conditions as the circuit board of Example 1, except that the polishing conditions for one and the other main surfaces of the ceramic substrate were changed to a polishing amount of 5 μm and a polishing speed of 14 mm / sec.

[0057] Example 3 The circuit board of Example 3 was produced under the same conditions as the circuit board of Example 1, except that the polishing conditions for one and the other main surfaces of the ceramic substrate were changed to a polishing amount of 5 μm and a polishing speed of 18 mm / sec.

[0058] Example 4 The circuit board of Example 4 was produced under the same conditions as the circuit board of Example 1, except that the polishing conditions for one and the other main surfaces of the ceramic substrate were changed to a polishing amount of 5 μm and a polishing speed of 20 mm / sec.

[0059] Example 5 The circuit board of Example 5 was produced under the same conditions as the circuit board of Example 1, except that the polishing conditions for one and the other main surfaces of the ceramic substrate were changed to a polishing amount of 10 μm and a polishing speed of 10 mm / sec.

[0060] (Comparative Example 1) The circuit board of Comparative Example 1 was produced under the same conditions as the circuit board of Example 1, except that instead of sputtering Ti onto the plate material, a brazing filler metal containing Ti, Cu, and Ag was applied to a thickness of 15 μm and heated to 800°C to bond the plate material.

[0061] (Comparative Example 2) The circuit board of Comparative Example 2 was produced under the same conditions as the circuit board of Example 1, except that the polishing conditions for one and the other main surfaces of the ceramic substrate were changed to a polishing amount of 10 μm and a polishing speed of 20 mm / sec.

[0062] [Various measurements] The obtained circuit boards of the examples and comparative examples were evaluated by the following measurements.

[0063] (Calculation of thermal conductivity) The thermal conductivity of the circuit boards of the examples and comparative examples was determined by a laser flash method at room temperature.

[0064] (Measurement of porosity, length and angle of microcracks) The circuit boards of the examples and comparative examples were cut perpendicular to one main surface of the ceramic substrate and polished. Next, SEM images of the cross sections were taken at 5000x magnification at 10 randomly selected locations. The elements contained in the same images were measured using an EPMA, and element mapping was performed. The porosity within the microcracks was measured based on the element mapping results. The length and angle of the microcracks in each SEM image were also measured. Microcracks that opened at the interface and were entirely contained within the SEM image were the subject of measurement. If the porosity of all microcracks was 90% or greater, the porosity standard was evaluated as "good." If even one microcrack had a porosity below 90%, the porosity standard was evaluated as "not good." Furthermore, if there were microcracks of 1 μm or greater and all microcracks had a length of 3 μm or less, the length standard was evaluated as "good." If even one microcrack had a length greater than 3 μm, the length standard was evaluated as "not good." In addition, if the average angle of microcracks between 1 μm and 3 μm was between 0° and 80°, the angle criteria was met (◯), and if the average angle was over 80°, the angle criteria was not met (×).

[0065] (Cold-heat cycle test) The circuit boards of the examples and comparative examples were placed in a thermal cycle tester, and a maximum of 2000 thermal cycles were performed, with one cycle consisting of -40°C for 5 minutes, 250°C for 5 minutes, and then cooling to -40°C. SAT testing (ultrasonic flaw detection) was performed every 100 cycles to check for cracks at the edge of the bonding layer. If a crack was detected, its length was measured, and if it was 1 mm or greater, it was determined that a crack preventing continued use had occurred. A test piece that developed a crack preventing continued use after less than 500 cycles was deemed a failure (×), while a test piece that developed a crack preventing continued use after 500 cycles or more was deemed a pass. Among the pass tests, a test piece that completed fewer than 1000 cycles was deemed a good (◯), and a test piece that completed 1000 cycles or more was deemed an excellent (◎).

[0066] (result) FIG. 8 is a table showing the polishing conditions, metal layer formation methods, and test results for the circuit boards of the examples and comparative examples. Examples 1 to 5, which passed the thermal cycle test, met the porosity criteria. In contrast, Comparative Examples 1 and 2, which failed the thermal cycle test, did not meet the porosity criteria. The reason for the failure in Comparative Example 1 is thought to be that a large portion of the brazing material penetrated into the microcracks during joining, causing the microcracks to extend due to the thermal cycle. Furthermore, the amount of polishing in Comparative Example 2 was large and the polishing rate was fast, which led to the opening of the microcracks becoming larger. Even with sputtering, Ti penetrated the microcracks. Furthermore, the microcracks were long and had poor angles, which led to the microcracks extending further due to the thermal cycle. This demonstrates that the presence of microcracks that meet the porosity criteria can enhance resistance to thermal cycles.

[0067] Examples 1 to 3, which satisfied the criteria for the length and angle of the microcracks, showed better results in the thermal cycling test than Examples 4 and 5, which did not satisfy either criterion. It was also found that the average angle is preferably 70° or less, and even more preferably 60° or less. These findings demonstrate that microcracks that satisfy the porosity criteria can further increase resistance to thermal cycling and enhance reliability by satisfying the length and angle criteria.

[0068] As described above, it has been confirmed that the circuit board or power device of the present invention can improve the heat transfer between the ceramic substrate and the conductor layer, while also improving resistance to thermal cycles, thereby increasing reliability.

[0069] The present invention is not limited to the above-described embodiments, and it goes without saying that various modifications and equivalents are included within the spirit and scope of the present invention. Furthermore, the structure, shape, number, position, size, etc. of the components shown in each drawing are for the convenience of explanation and may be changed as appropriate. [Explanation of symbols]

[0070] 10 Ceramic substrate 12 One main surface 14 Microcracks 16 Other main surface 20 Bonding layer 26 Second bonding layer 30 Conductor Layer 32 Second conductor layer 50 Circuit Board 52 Solder 60 Power Semiconductors 70 Heat sink 72 Grease 80 Heat dissipation material 100 Power Devices

Claims

1. a ceramic substrate; a bonding layer formed on one main surface of the ceramic substrate; a conductor layer made of metal bonded to the ceramic substrate via the bonding layer, The ceramic substrate has microcracks formed by voids that open at the interface with the bonding layer.

2. 2. The circuit board according to claim 1, wherein the microcracks include those having a length of 1 μm or more and 3 μm or less, and the average angle of the microcracks having a length of 1 μm or more and 3 μm or less with respect to a direction perpendicular to the interface is 0° or more and 80° or less.

3. 3. The circuit board according to claim 1, wherein the bonding layer is mainly composed of titanium.

4. a second bonding layer including titanium formed on the other main surface opposite to the one main surface of the ceramic substrate; a second conductor layer including copper bonded to the ceramic substrate via the second bonding layer, the bonding layer comprises titanium; the conductor layer comprises copper; 3. The circuit board according to claim 1, wherein the thermal conductivity of the circuit board in a direction perpendicular to the one main surface is 150 W / mK or more.

5. The circuit board according to claim 1 or 2; a power semiconductor mounted on the conductor layer.

Images